6124 results about "Passivation" patented technology

Improved methods and systems for passivating a surface of a high-mobility semiconductor and structures and devices formed using the methods are disclosed. The method includes providing a high-mobility semiconductor surface to a chamber of a reactor and exposing the high-mobility semiconductor surface to a gas-phase chalcogen precursor to passivate the high-mobility semiconductor surface.

A chamber passivation method particularly useful for hydrogen plasma cleaning of low-k dielectrics prior to coating a barrier layer into a via hole with hydrogen radicals are provided from a remote plasma source. For each wafer, the chamber is passivated with water vapor (or other gas even more chemabsorbed on plasma facing walls) passed through the remote plasma source prior to the ignition of the hydrogen plasma. The water vapor is absorbed on walls, such as alumina and quartz parts of the remote plasma source, and forms a protective mono-layer that endures sufficiently long to protect the walls during the generation of the hydrogen plasma. Thereby, the plasma facing walls, particularly of a dielectric such as alumina, are protected from etching.

PCT No. PCT/US95/13325 Sec. 371 Date Sep. 28, 1997 Sec. 102(e) Date Sep. 28, 1997 PCT Filed Oct. 10, 1995 PCT Pub. No. WO96/12316 PCT Pub. Date Apr. 25, 1996Fuel cell stacks comprising stacked separator/membrane electrode assembly fuel cells in which the separators comprise a series of thin sheet platelets, having individually configured serpentine micro-channel reactant gas humidification active areas and cooling fields therein. The individual platelets are stacked with coordinate features aligned in contact with adjacent platelets and bonded to form a monolithic separator. Post-bonding processing includes passivation, such as nitriding. Preferred platelet material is 4-25 mil Ti, in which the features, serpentine channels, tabs, lands, vias, manifolds and holes, are formed by chemical and laser etching, cutting, pressing or embossing, with combinations of depth and through etching preferred. The platelet manufacturing process is continuous and fast. By employing CAD based platelet design and photolithography, rapid change in feature design can accommodate a wide range of thermal management and humidification techniques. One hundred H2-O2/PEM fuel cell stacks of this IFMT platelet design will exhibit outputs on the order of 0.75 kW/kg, some 3-6 times greater than the current graphite plate PEM stacks.

Methods for selectively forming a target film on a substrate comprising a first dielectric surface and a second metallic surface are disclosed. The methods may include: contacting the substrate with a plasma generated from a hydrogen containing gas, selectively forming a passivation film from vapor phase reactants on the first dielectric surface while leaving the second metallic surface free from the passivation film, and selectively depositing the target film from vapor phase reactants on the second metallic surface relative to the passivation film.

Fabrication methods using Ion Beam Etching (IBE) for MRAM cell memory elements are described. In embodiments of the invention the top electrode and MTJ main body are etched with one mask using reactive etching such as RIE or magnetized inductively coupled plasma (MICP) for improved selectivity, then the bottom electrode is etched using IBE as specified in various alternative embodiments which include selection of incident angles, wafer rotational rate profiles and optional passivation layer deposited prior to the IBE. The IBE according to the invention etches the bottom electrode without the need for an additional mask by using the layer stack created by the first etching phase as the mask. This makes the bottom electrode self-aligned to MTJ. The IBE also achieves MTJ sidewall cleaning without the need for an additional step.

A bumped wafer for use in making a chip device. The bumped wafer includes two titanium layers sputtered alternatingly with two copper layers over a non-passivated die. The bumped wafer further includes under bump material under solder bumps contained thereon.

A microbolometer includes a micro-bridge structure for uncooling infrared or terahertz detectors. The thermistor and light absorbing materials of the micro-bridge structure are the vanadium oxide-carbon nanotube composite film formed by one-dimensional carbon nanotubes and two-dimensional vanadium oxide film. The micro-bridge is a three-layer sandwich structure consisting of a layer of amorphous silicon nitride base film as the supporting and insulating layer of the micro-bridge, a layer or multi-layer of vanadium oxide-carbon nanotube composite film in the middle of the micro-bridge as the heat sensitive and light absorbing layer of the microbolometer, and a layer of amorphous silicon nitride top film as the stress control layer and passivation of the heat sensitive film. The microbolometer and method for manufacturing the same can overcome the shortcomings of the prior art, improve the performance of the device, reduce the cost of raw materials and is suitable for large-scale industrial production.

Backside illuminated photosensitive devices and associated methods are provided. In one aspect, for example, a backside-illuminated photosensitive imager device can include a semiconductor substrate having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation, and a passivation region positioned between the textured region and the at least one junction. The passivation region is positioned to isolate the at least one junction from the textured region, and the semiconductor substrate and the textured region are positioned such that incoming electromagnetic radiation passes through the semiconductor substrate before contacting the textured region. Additionally, the device includes an electrical transfer element coupled to the semiconductor substrate to transfer an electrical signal from the at least one junction.

In the manufacture of a semiconductor device having a high-performance and high-reliability, a silicon nitride film 17 for self alignment, which film is formed to cover the gate electrode of a MISFET, is formed at a substrate temperature of 400° C. or greater by plasma CVD using a raw material gas including monosilane and nitrogen. A silicon nitride film 44 constituting a passivation film is formed at a substrate temperature of about 350° C. by plasma CVD using a raw material gas including monosilane, ammonia and nitrogen. The hydrogen content contained in the silicon nitride film 17 is smaller than that contained in the silicon nitride film 44, making it possible to suppress hydrogen release from the silicon nitride film 17.

Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

The invention belongs to the technical field of nanometer biological materials, and particularly relates to an 800nm excitation-based up/down conversion dual-mode fluorescent nanomaterial for Nd<3+> sensitization and a synthesis method thereof. The synthetic up/down conversion dual-mode fluorescent nanomaterial for Nd<3+>sensitization designed by the invention has a multi-layer core-shell structure, and comprises a down conversion luminous layer, an up conversion luminous layer, an isolation layer and a passivation layer. Different layers of the material synergistically play respective different roles, and meanwhile, the dual-mode fluorescent probe with up conversion fluorescence and down conversion fluorescence is finally achieved under an 800nm of excitation light with a low-heat effect. The up conversion excitation light is expanded to about 800nm from 980nm by Nd<3+>, Yb<3+> and Er<3+>-doped NaGdF4:Nd, Yb, Er up conversion layer due to introduction of Nd<3+>, and the fluorescent process from a near infrared light to a visible light is achieved. The process meets the requirements of an in-vitro fluorescent probe. In addition, the typical down conversion fluorescence from the near infrared light to a far infrared light is also achieved in one nanoparticle due to the synergistic effect of the NaGdF4:Nd core.

A process for fabricating an electronic device structure on or in a substrate. A storage and dispensing vessel is provided, containing a solid-phase physical sorbent medium having physically adsorbed thereon a fluid for fabrication of the electronic device structure, e.g., a source fluid for a material constituent of the electronic device structure, or a reagent such as an etchant or mask material which is utilized in the fabrication of the electronic device structure but does not compose or form a material constituent of the electronic device structure. In the process, the source fluid is desorbed from the physical sorbent medium and dispensing source fluid from the storage and dispensing vessel, and contacted with the substrate, under conditions effective to utilize the material constituent on or in the substrate. The contacting step of the process may include process steps such as ion implantation; epitaxial growth; plasma etching; reactive ion etching; metallization; physical vapor deposition; chemical vapor deposition; cleaning; doping; etc. The process of the invention may be employed to fabricate electronic device structures such as transistors; capacitors; resistors; memory cells; dielectric material; buried doped substrate regions; metallization layers; channel stop layers; source layers; gate layers; drain layers; oxide layers; field emitter elements; passivation layers; interconnects; polycides; electrodes; trench structures; ion implanted material layers; via plugs; precursor structures for the foregoing electronic device structures; and device assemblies comprising more than one of the foregoing electronic device structures. The electronic device structure fabricated by such process may in turn may be employed as a component of an electronic product such as a telecommunications device or electronic appliance.

The invention discloses a multilayer silicon nitride antireflection film of a crystalline silicon solar cell and a preparation method of the multilayer silicon nitride antireflection film, belonging to the technical field of manufacturing of semiconductor crystalline silicon and solar cells. The multilayer silicon nitride antireflection film comprises at least three silicon nitride films which are deposited on a silicon substrate, the refraction indexes of all the silicon nitride films are sequentially reduced from bottom to top, and the thicknesses of all the silicon nitride films are sequentially increased from bottom to top. According to the invention, the passivation effect of a coating film is effectively improved, the antireflection effect of the antireflection film is improved, thepassivation effect of the antireflection film is enhanced, and the photoelectric conversion efficiency of the solar cell is increased.

The present invention relates to the physical or chemical specific purification of natural mineral graphite. This purification is preferably applied to the surface of natural graphite in order to allow the formation of a passivation film during the first electrical discharge or the insertion of lithium in the graphite when the latter is used in a lithium-ion cell. The grinding to a small size before purification allows the optimization of the distribution of the particles, resulting in a more uniform electrode. This grinding is carried out in the presence of the natural impurities of the graphite that play the role of a micro-abrasive and result in a hardness of the graphite that increases its mechanical properties.

The invention discloses a solar cell with a composite dielectric passivation layer structure and a preparation process thereof. A silicon oxide film, an alumina film and a silicon nitride or silicon oxynitride film are deposited in turn on the front, back and sides of a p-type silicon substrate to form a composite dielectric film on the whole surface, and windows are opened locally to lead electrodes out. Through aluminum oxide, silicon dioxide, silicon oxynitride, silicon nitride with different refractive indexes and a back surface passivation layer with a laminated structure of the materials, the back surface recombination rate is greatly reduced, the back reflectivity is improved, the CTM of a module is reduced, and the light attenuation and heat-assisted light attenuation and the anti-PID performance of the cell are improved. The structure can be made on a boron/gallium-doped p-type monocrystalline silicon, p-type polycrystalline silicon or p-type monocrystalline-silicon-like substrate, and a passivation method based on the composite dielectric film passivation structure can be used to manufacture PERC cells, double-sided PERC+ cells and imbricate PERC cells. Based on the preparation process steps and sequence, the corresponding preparation mode and the process parameter range of the laminated structure, the making of the cell can be well completed.

A solid state light emitting device comprises one or more active layers comprising semiconductor nano-particles in a host matrix, e.g. silicon nano-particles in silicon dioxide or silicon nitride. The incorporation of carbon in the active layers provides a great improvement in performance through shortened decay time and enhance emission spectra, as well as reliability and lifetime. The emission wavelengths from the nano-particles can be made to correspond to the quantization energy of the semiconductor nano-particles, which allows the entire visible range of the spectrum be covered. Ideally an engineered structure of alternating active and buffer material layers are disposed between AC or DC electrodes, which generate an electric field. The buffer layers are comprised of a wide bandgap semiconductor or dielectric material, and are designed with a thickness, in the direction of an applied electric field, that ensures that electrons passing therethrough picks up enough energy to excite the nano-particles in the adjacent active layer at a sufficient excitation energy to emit light efficiently at a desired wavelength.

An array substrate includes a switching element, a signal transmission line, a passivation layer and a pixel electrode. The switching element is disposed on an insulating substrate. The signal transmission line is connected to the switching element and includes a barrier layer, a conductive line, and a copper nitride layer. The barrier layer is disposed on the insulating substrate. The conductive line is disposed on the barrier layer and includes copper or copper alloy. The copper nitride layer covers the conductive line. The passivation layer covers the switching element and the signal transmission line and has a contact hole through which a drain electrode of the switching element is partially exposed. The pixel electrode is disposed on the insulating substrate, and is connected to the drain electrode of the switching element through the contact hole.

The invention discloses a passivation contact structure of a selective polycrystalline silicon thin film. A preparation method comprises the following steps: preparing one silicon dioxide layer with the thickness of less than 2nm on the surface of crystalline silicon, preparing a doped polycrystalline silicon thin film on the surface of the silicon dioxide layer, wherein the doped polycrystalline silicon thin film has a first thickness in a nonmetallic contact region and a second thickness in a metallic contact region, and the first thickness is less than the second thickness, and then forming a metal electrode on the surface of the second thickness region of the polycrystalline silicon thin film. Meanwhile, the invention also discloses a method for preparing the passivation contact structure of the selective polycrystalline silicon thin film. The passivation contact structure of the selective polycrystalline silicon thin film has the advantages that the traditional screen printing technology can be effectively combined with a passivation contact technology, the passivation contact technology can be beneficially popularized to mass production, and efficiency of a solar cell is effectively improved.

The invention provides a flexible organic light-emitting diode display and a method for manufacturing the same. The flexible organic light-emitting diode display comprises a first flexible substrate and a second flexible substrate opposite to the first flexible substrate. A thin film transistor, a first passivation layer, a first electrode, an organic light-emitting layer and a second electrode are sequentially manufactured on the first flexible substrate, and the cathode, the anode, the thin film transistor (TFT) and the second flexible substrate are sequentially positioned on the first flexible substrate. The flexible organic light-emitting diode display is characterized in that a stress absorbing layer is further arranged between the second electrode and the second flexible substrate and is made of resin materials. The flexible organic light-emitting diode display and the method have the advantage that stress generated by the flexible organic light-emitting diode display in a bending procedure can be absorbed, so that breakage of the electrodes of the flexible organic light-emitting diode display and the influence on the display quality due to the effect of the stress can be prevented.

The invention discloses a capacitive relative humidity sensor based on graphene oxide. The humidity sensor is characterized by comprising a substrate (1), an oxide layer (2), a heating strip (3) and an insulating layer (4) that are successively arranged on the substrate (1) from bottom to up. The humidity sensor also comprises a first capacitance electrode (5), a second capacitance electrode (6), passivation layers (7) and humidity sensitive mediums (8). The first capacitance electrode (5) and the second capacitance electrode (6) are arranged on the insulating layer (4) respectively and are equipped with a passivation layer (7) respectively; and the sensitive mediums (8) are arranged between the first capacitance electrode (5) and the second capacitance electrode (6), and also arranged above the first capacitance electrode (5) and the second capacitance electrode (6). According to the invention, sensor reliability is increased; technology steps are simple; and graphene oxide is employed as the humidity sensitive medium. Therefore, the sensor has advantages of high sensitivity, fast response speed and low hysteresis.