406 results about "Self alignment" patented technology

The invention discloses a preparation method of a vertical comb-driven MEMS (Micro Electro Mechanical System) micromirror, which comprises the following steps of: forming a through alignment mark and a pre-etched comb structure on a device layer by using a first composite mask, and forming the through alignment mark and the pre-etched comb structure on the back surface of the device layer on a first substrate through a composite mask process, after the first substrate and the second substrate are bonded, the self-alignment composite mask of the comb tooth structure is aligned with the back face pre-etched comb tooth structure through the through alignment mark, high-precision alignment of the comb tooth structure is achieved, accumulated errors are avoided, and the yield of device preparation is improved.

A nanosheet semiconductor structure including a self-aligned backside contact, and a gate cut contact structure extending between two stacks stack of semiconducting layers and in electrical contact with the self-aligned backside contact and a source drain contact on a frontside, wherein a lateral dimension of the gate cut contact structure is less than a lateral dimension of the self-aligned backside contact.

A semiconductor structure includes a field effect transistor having a plurality of source / drain regions and a metal gate structure. A dielectric layer is in contact with a first surface of each of the plurality of source / drain regions, while a bottom dielectric isolation layer is in contact with a first surface of the metal gate structure. The bottom dielectric isolation layer is coplanar with the dielectric layer. The semiconductor structure further includes a backside metal contact that extends through a backside interlevel dielectric and the dielectric layer until an uppermost surface of at least one source / drain region of the plurality of source / drain regions. The backside interlevel dielectric is disposed above the dielectric layer and above the bottom dielectric isolation layer. The backside metal contact electrically connects the at least one source / drain region to a backside interconnect structure disposed above the backside interlevel dielectric.

A method for making a semiconductor structure, including: forming a conductive layer; forming a patterned mask layer on the conductive layer; patterning the conductive layer to form a recess and a conductive feature; forming a first dielectric layer over the patterned mask layer and filling the recess with the first dielectric layer; patterning the first dielectric layer to form an opening; selectively forming a blocking layer in the opening; forming an etch stop layer to cover the first dielectric layer and exposing the blocking layer; forming on the etch stop layer a second dielectric layer; forming a second dielectric layer on the etch stop layer; patterning the second dielectric layer to form a through hole and exposing the conductive feature; and filling the through hole with an electrically conductive material to form an interconnect electrically connected to the conductive feature.

A semiconductor structure including a first stack of semiconducting layers in a first region, a second stack of semiconducting layers in a second region, where the second stack of semiconducting layers in the second region has at least one fewer layer than the first stack of semiconducting layers in the first region, a backside channel plug directly beneath the first stack of semiconducting layers in the first region, and a gate cut contact structure extending between a backside contact structure and a source drain contact on a frontside.

Spacer self-aligned via structures for gate contact or trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. The integrated circuit structure also includes a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers between adjacent ones of the plurality of gate structures and the plurality of conductive trench contact structures, wherein the plurality of dielectric spacers protrudes above the plurality of gate structures and above the plurality of conductive trench contact structures. Individual ones of the plurality of dielectric spacers have an upper spacer portion on a lower spacer portion, with an interface between the upper spacer portion and the lower spacer portion.

The present application discloses a chip, a preparation method, and an electronic device. The chip comprises VFETs. Each VFET comprises a vertical channel, a stack structure, a groove structure, and a first electrode. The vertical channel extends in a direction perpendicular to a substrate. The stack structure comprises a gate structure and a first isolating dielectric layer, and the first isolating dielectric layer is provided on the side of the gate structure facing away from the substrate. The groove structure is provided on the side of the stack structure facing away from the substrate. The formed first electrode completely fills the bottom of the groove structure. A polycrystalline area is formed at the edges and corners on the side of the first electrode facing the substrate, so as to fill air gaps in the prior art with the part of the first electrode where the polycrystalline area is formed, thereby reducing the presence of air gaps; and the part of the first electrode where the polycrystalline area is formed is used as a support, thereby improving the stability and reliability of the structure of the corresponding VFET. In addition, the use of the first electrode having a regular shape as a mask is conducive to a subsequent process of using a self-alignment process to form a gate structure, thereby improving the accuracy of a subsequent self-alignment process.

Photonics integrated circuit (PIC) dies bonded to photonics substrates, related apparatuses, systems, and methods of fabrication are disclosed. A photonics substrate and a PIC die include corresponding optical bonding regions one or both of which are surrounded by hydrophobic structures. A liquid droplet is applied to the PIC die or photonics substrate optical bonding region and the PIC die is placed on the optical bonding region of the photonics substrate. Capillary forces cause the PIC die to self-align to the optical bonding region, and an optical bond is formed by evaporating the liquid and subsequent anneal.

A die placement system provides a tip body and a die placement head to ensure planarity of a die to a substrate without the need for calibration before each pick and place operation. A self-aligning tip incorporated into the tip body aids in die placement / attachment. This tip provides a global correction for planarity errors that exist between the die and the substrate, whether these errors are due to gantry misalignment (i.e., die side misalignment) or machine deck tool misalignment (i.e., substrate side misalignment).

Methods of filling a gap in a semiconductor structure are presented. A titanium nitride and sacrificial silicon nitride spacer is deposited onto a line pattern comprising a trench between two lines of the line pattern. The titanium nitride and sacrificial silicon nitride spacer is etched to leave titanium nitride and sacrificial silicon nitride spacer covering sides of the two lines within the trench. An organic planarization layer is applied over the line pattern and the titanium nitride and sacrificial silicon nitride spacer. A pillar cut is cut through the organic planarization layer and into the trench to form a gap within the trench. The gap is filled with silicon oxide.

The invention relates to a preparation process of a deep ultraviolet micro LED (light-emitting diode) array with self-aligned electrodes. According to the process, a metal barrier layer is deposited, a mesa shape is formed through wet etching, a mesa is formed through etching, a passivation layer is filled to protect the side wall, the CMP technology is combined, the surface is polished to be flat, ICP etching is carried out, the metal barrier layer is exposed, the metal barrier layer is washed away, the mesa can be exposed, and then a long electrode does not need to be aligned with the process in a high-precision mode. Complex procedures are not needed, the alignment difficulty is overcome and the chip yield is improved by combining the planarization of the filling thick passivation layer and the ICP dry etching technology, and industrialization of micro-LED array preparation is facilitated.

A method of manufacturing a silicon carbide power device includes performing a first ion implantation process to form a JFET region in an epitaxial layer over a substrate. A patterned mask layer is formed on the epitaxial layer above the JFET region. A second ion implantation process is performed to form well regions at both sides of the JFET region. A first spacer is formed on sidewalls of the patterned mask layer. A third ion implantation process is performed to form a self-aligned heavily doped region in the well regions. A second spacer is formed on a side of the first spacer to shield a portion of the heavily doped region. A fourth ion implantation process is performed to form another self-aligned heavily doped region in the heavily doped region. A gate structure is formed after removing the patterned mask layer, the first spacer, and the second spacer.

The embodiment of the invention provides a preparation method of an inner side wall, which comprises the following steps: before forming a first dielectric layer, firstly removing false side walls at two sides of a false gate structure and forming cavities at two sides of a sacrificial layer, and then forming a first part covering the side wall of the false gate structure and a second part filling the cavities and covering the side wall of a stack structure, the first part exposes at least part of the surface, facing the dummy gate structure, of the target channel layer, so that a step structure of which the second part protrudes towards two sides is formed on one side, facing the dummy gate structure, of the first channel layer; and finally, when the inner side wall is formed, anisotropic etching can be performed on the first dielectric layer and the stacked structure by taking the first part as a self-alignment structure so as to form the inner side wall and the outer side wall, and the first part is taken as the self-alignment structure, so that transverse undercutting of the inner side wall is avoided, and the over-etching problem of the inner side wall is improved.

The present disclosure relates to a 2T memory cell, and more particularly to a technology including a first transistor that performs data write and erase operations and a second transistor that performs a data read operation. The first transistor is formed vertically above the second transistor, and the first drain of the first transistor serves as the second gate of the second transistor. The channel of the first transistor has a longer effective channel length than the channel of the second transistor. High-density integration is possible by forming the first transistor through a self-aligned process, and data retention characteristics are improved by forming the channel of the first transistor with a semiconductor material having a wide bandgap such as polysilicon or IGZO. The 2T memory cell according to the present disclosure can simultaneously achieve high-speed operation and high integration density.

The present disclosure discloses a method for fabricating an integrated structure of a metal-gate MOS transistor, which defines a high-resistance MOS device gate structure region in the high-resistance device area and a high-voltage MOS device gate structure region in the high-voltage device area through photolithography, wherein during gate polysilicon etching, the entire high-voltage MOS device gate structure region is retained without forming slots in the MOS device gate structure regions; spacers are formed through self-aligned etching, eliminating the need for a spacers process mask; and the same mask layer is used for both the high-resistance layer etching and the slot etching in the high-voltage MOS device gate structure region. This fabricating method offers several advantages: reduced number of required masks, healthier high-voltage MOS device gate structures, larger process windows, improved device electrical characteristics, enhanced reliability, and simplified contact hole etching process with lower contact resistance.

The invention relates to the technical field of semiconductor processing, in particular to a self-alignment double patterning method and a semiconductor device. The self-alignment double patterning method comprises the steps that a substrate is provided, a hard mask layer and an initial side wall layer are formed on the substrate, the initial side wall layer comprises an asymmetric part, and the asymmetric part comprises a first side face and a second side face which are arranged oppositely and have asymmetry; forming a dielectric layer, wherein the dielectric layer covers the hard mask layer and the initial side wall layer; etching a part of the dielectric layer to expose an asymmetric part; the asymmetric part is removed, so that the top surface of the initial side wall layer is flush with the top surface of the dielectric layer; the remaining dielectric layer is etched to form a side wall layer, and the side wall layer comprises a first side face and a second side face which are arranged oppositely and have symmetry; and sequentially etching the hard mask layer and the substrate to form a required pattern in the substrate. According to the invention, the problem of asymmetry of the left and right shapes of the side wall in the current self-alignment double patterning method can be relieved.

A process includes forming, over a dielectric layer, a hardmask stack including a first layer below a second layer below a third layer below a fourth layer. The first and third layers include a different hardmask material from the second and fourth layers. A trench pattern including sidewall spacer structures is formed over the hardmask stack. The fourth layer is etched in a first region. The fourth and third layers are etched in a second region. The fourth and third layers are etched in a third region. The fourth layer is etched in a fourth region. The second and first layers are etched in the second and third regions. The third layer is etched in the first and fourth regions. In the dielectric layer, trenches are formed in the first and fourth regions, and via openings, deeper than the trenches, are formed in the second and third regions.

The invention relates to an MEMS micromirror, in particular to a self-alignment MEMS micromirror based on electrostatic driving, which comprises an inner layer structure and an outer layer structure, the inner layer structure comprises a rectangular mirror surface, a rectangular inner frame and a rectangular outer frame, the left side surface and the right side surface of the rectangular mirror surface are respectively provided with a mirror surface boss in an extending manner, and the side surface of each mirror surface boss is provided with two comb tooth beams A in an extending manner; the inner side face of the rectangular inner frame is provided with four rows of driving comb teeth A in an extending mode, the front outer side face and the rear outer side face of the rectangular inner frame are each provided with an inner frame boss in an extending mode, the side face of each inner frame boss is provided with two comb tooth beams B in an extending mode, and the inner side face of the rectangular outer frame is provided with four rows of driving comb teeth B. The outer layer structure comprises four comb tooth beams C and a rectangular bottom frame. A rectangular anchor block is fixed to the upper surface of each frame edge of the rectangular bottom frame, and a row of driving comb teeth C are arranged on the inner side face of each rectangular anchor block in an extending mode. The MEMS micro-mirror solves the problem that an existing MEMS micro-mirror is low in light source utilization rate, and is suitable for the fields of projection display, laser radar, optical communication and the like.

The application discloses a PIN type back incidence germanium-silicon photodiode based on inductance peaking, and the photodiode structure sequentially comprises a back incidence area, an absorption area and a collection area from top to bottom; the back incidence area comprises a silicon substrate and silicon microlenses formed by etching on the back surface of the silicon substrate; the absorption area comprises a doped area and a germanium absorption layer, the built-in electric field is formed by P-type and N-type doping of the doped area, and the germanium absorption layer is used for absorbing incident photons and generating photo-generated carriers; the collection area comprises a self-alignment resistance layer, an interlayer dielectric layer, a coplanar waveguide electrode and a metal bump, and the geometric parameters of the coplanar waveguide electrode are optimized to introduce a compensation inductance L p The inductance peaking is realized, so that the bandwidth of the photodiode is optimized; the metal bump is arranged on the surface of the coplanar waveguide electrode to realize flip-chip bonding of the photodiode and an external circuit. p The bandwidth of the device can be significantly improved under the premise of ensuring high responsivity and low dark current.

Self-aligned direct backside contacts by an epitaxy everywhere under source / drain region approach are provided. In one aspect, a semiconductor device includes: a field-effect transistor(s) on a backside interlayer dielectric; an epitaxial contact placeholder in the backside interlayer dielectric that directly contacts a first source / drain region of the field-effect transistor(s); and a self-aligned direct backside contact in the backside interlayer dielectric that directly contacts a second source / drain region of the field-effect transistor(s). The epitaxial contact placeholder extends a distance d1 into the backside interlayer dielectric from the first source / drain region, and the self-aligned direct backside contact extends a distance d2 into the backside interlayer dielectric from the second source / drain region, where d2>d1. The field-effect transistor(s) can include a stack of active layers surrounded by a gate, and the first / second source / drain regions on opposite sides thereof. A method of fabricating the present semiconductor device is also provided.

Aspects of the subject disclosure may include, for example, splicing optical fibers using a self-aligning optical fiber insertion connector. An optical fiber is supported between an optical fiber tool and a fiber aligning cavity, and the optical fiber tool is translated towards the fiber aligning cavity to engage the optical fiber. The optical fiber is separated into a first optical fiber segment and a second optical fiber segment by translation of the optical fiber tool. The first and second optical fiber segments are aligned with respective first and second optical waveguides by further translation of the optical fiber tool to obtain splices of the first and second optical fiber segments to the respective first and second optical waveguides. Other embodiments are disclosed.

According to some embodiments of the present disclosure, methods of forming a semiconductor device on a semiconductor layer having opposing first and second surfaces are disclosed. An n-type doped region including an n-type dopant may be formed at the first surface of the semiconductor layer. A p-type dopant source layer including a p-type dopant may be formed on the n-type doped region. The p-type dopant may be diffused from the p-type dopant source layer through the n-type doped region into the semiconductor layer to form a p-type doped region of the semiconductor layer, and the p-type doped region of the semiconductor layer may be between the n-type doped region and the second surface of the semiconductor layer. After diffusing the p-type dopant, the p-type dopant source layer may be removed.

Disclosed are methods and apparatuses for performing spacer on spacer multiple patterning schemes using an exhumable first spacer material and a complementary second spacer material. Certain embodiments involve using a tin oxide spacer material for one of the spacer materials in spacer on spacer self aligned multiple patterning.

The invention relates to an ESD device with a self-aligned trigger region. A method of forming a semiconductor device includes forming rows of n-type wells and p-type wells in an upper surface of a semiconductor body, the p-type wells and the n-type wells being alternately arranged; a trigger region is formed between the n-type well and the p-type well, the trigger region including a lightly doped partition of the semiconductor body configured to induce a current between the p-type well and the n-type well via avalanche breakdown, where the p-type well and the n-type well are formed by implanting dopant atoms into an upper surface of the semiconductor body, and wherein the lowly doped partitions of the semiconductor body are formed by a hard mask that prevents dopant atoms from penetrating an upper surface of the semiconductor body during implantation of the dopant atoms.

Techniques of integrating lateral HBT devices into a silicon on insulator (SOI) CMOS process. Similar approaches could also be applied to Fin Field-Effect Transistors (FinFETs). A first technique makes use of a CMOS replacement gate process that is typically associated with a partially depleted SOI (PDSOI) or fully depleted SOI (FDSOI) process. A second technique is independent of the CMOS process. Both techniques can accommodate silicon germanium (SiGe) and / or III-V materials, include a self-aligned base contact, and can be used to construct both NPN and PNP transistors with varied peak fT and breakdown voltages.

A method of forming a phase change switching device is disclosed, the method comprising: providing a substrate; forming first and second RF terminals on the substrate; forming a strip of phase change material connected between the first and second RF terminals on the substrate; forming a heating element adjacent to the strip of phase change material such that the heating element is configured to control a conductive state of the strip of phase change material. The first and second RF terminals and the heating element are formed by a photolithography process that self-aligns the heating element with the first and second RF terminals.

A method for forming a semiconductor structure includes: providing a substrate, including a target layer for forming a target pattern; forming a core layer on the substrate, the core layer extending along a first direction, and a second direction perpendicular to the first direction; forming a first mask sidewall on a sidewall of the core layer; forming a self-aligned sacrificial sidewall on a sidewall of the first mask sidewall; forming an etch-resistant layer on the substrate exposed by the core layer, the self-aligned sacrificial sidewall, and the first mask sidewall; removing the self-aligned sacrificial sidewall to form a first groove; removing the core layer so that the first mask sidewall surrounds a second groove; and etching the target layer along the first groove and the second groove using the first mask sidewall and the etch-resistant layer as masks to form the target pattern. Embodiments of the present invention are advantageous in improving the dimensional accuracy of the target pattern and the matching degree between the target pattern and the design pattern.

A method for manufacturing a semiconductor memory device includes: sequentially forming a lower oxide layer, a word line metal layer, and an upper oxide layer over at least a portion of a memory cell; forming a via through the upper oxide layer, the word line metal layer, and the lower oxide layer to expose a portion of the memory cell; forming a sacrificial pillar in the via; removing the upper oxide layer to expose the top of the sacrificial pillar; sequentially forming a first oxide sidewall, a nitride sidewall, and a second oxide sidewall on the sidewall of the top of the sacrificial pillar; removing the nitride sidewall to form a void; and etching the word line metal layer through the void to form individual word lines. An enhanced self-aligned word line process utilizes different material spacers to precisely pattern the word line metal layer to form multiple word lines with balanced widths.

A semiconductor structure including a nanosheet stack comprising a series of channel nanosheets, a gate structure, first inner spacers, second inner spacers, and a self-aligned backside cap, where the self-aligned backside cap is immediately below the gate structure and between the second inner spacers.

The application provides a multi-pose measuring device relative installation error calibration and compensation method and system, and relates to the technical field of spaceflight. The application comprises the following steps: S1, measuring a star sensor pose and converting coordinates; S2, calibrating high-precision inertial navigation and star sensor relative installation errors; S3, calibrating high-precision inertial navigation and low-precision inertial navigation self-alignment relative installation errors; and S4, compensating for the relative installation errors. The application calibrates and compensates for the relative installation errors among the high-precision inertial measurement combination, the low-precision inertial measurement combination and the star sensor by using the inertial navigation static self-alignment and the star sensor static pose measurement in the static state, so as to realize the consistency of the space pose reference in the dynamic multi-source combined navigation information fusion.