1194 results about "Self alignment" patented technology

The invention relates to the technical field of silicon waveguide and optical fiber coupling, and particularly provides an AI-based silicon waveguide-optical fiber mode field self-alignment coupling method and system, and the method comprises the steps: monitoring the strain distribution of a chip in real time through an integrated distributed fiber bragg grating array, and obtaining the light field intensity distribution of a coupling region through cooperation with a near-field optical probe array; constructing a deep space-time convolutional network, and generating a deformation compensation vector and a waveguide reconstruction parameter by an output layer; a nanofluid channel is integrated on the side wall of the waveguide, and the refractive index of liquid is adjusted through an electrowetting effect to realize dynamic broadening of a mode field; and the electrostatic driving micro-beam embedded below the waveguide adjusts the spatial pose of the waveguide according to an instruction of an output layer of the depth space-time convolutional network. The system comprises a light field intensity acquisition module, a convolutional network construction module and a spatial pose adjustment module. According to the method, real-time analysis and prediction are performed, so that system parameters are actively adjusted, and alignment precision and stability are improved.

The invention discloses a preparation method of a vertical comb-driven MEMS (Micro Electro Mechanical System) micromirror, which comprises the following steps of: forming a through alignment mark and a pre-etched comb structure on a device layer by using a first composite mask, and forming the through alignment mark and the pre-etched comb structure on the back surface of the device layer on a first substrate through a composite mask process, after the first substrate and the second substrate are bonded, the self-alignment composite mask of the comb tooth structure is aligned with the back face pre-etched comb tooth structure through the through alignment mark, high-precision alignment of the comb tooth structure is achieved, accumulated errors are avoided, and the yield of device preparation is improved.

Integrated circuit structures with through substrate vias (TSVs) processed by self-aligned contact modules are disclosed. Thus, much smaller and / or much densified TSVs are formed with low mechanical stresses. The denser TSVs allow for more flexible routing options.

A nanosheet semiconductor structure including a self-aligned backside contact, and a gate cut contact structure extending between two stacks stack of semiconducting layers and in electrical contact with the self-aligned backside contact and a source drain contact on a frontside, wherein a lateral dimension of the gate cut contact structure is less than a lateral dimension of the self-aligned backside contact.

A method is provided for forming a light-shielding layer to block irradiation of light onto a light-sensitive storage region. The light-sensitive storage region is formed in a semiconductor substrate to store electric charges. A storage gate feature is formed over the light-sensitive storage region, and includes a polysilicon gate electrode that is disposed over the light-sensitive storage region. A metal layer is formed over the storage gate feature. A silicidation process is performed to transform a part of the metal layer that is in contact with the polysilicon gate electrode into a silicide light-shielding layer. A thermal process is performed to induce lateral growth of the silicide light-shielding layer to make the silicide light-shielding layer extend to cover a lateral surface of the storage gate feature. A process temperature of the thermal process is higher than that of the silicidation process.

A self-aligning window mounted communication apparatus is discussed herein. In some examples, a wireless gateway may comprise a first unit to be mounted outside a window and a second unit to be mounted inside the window. A first unit and a second unit may each include an optical unit, a coupling unit, and a housing unit. A first optical unit may include a magnetic array with polarities of the magnetic elements configured to orient with a second optical unit in a single orientation. The optical unit(s) may be movably coupled with the respective coupling unit(s) so that the optical unit may move with various degrees of freedom and thus, when the first and second units are mounted on a window, the optical units can self-align based on the respective magnetic arrays and the degrees of freedom afforded by the movable coupling with the coupling unit.

Embodiments of the present disclosure provide a method for forming backside gate contacts and semiconductor fabricated thereof. A semiconductor device includes both signal outputs, such as source / drain contacts, and signal inputs, such as gate contacts, formed on a backside of the substrate. The backside gate contacts and backside source / drain contacts are formed in a self-aligned manner.

The invention relates to a backside illuminated image sensor preparation method and a backside illuminated image sensor, and relates to the technical field of integrated circuits, and the method comprises the steps: providing a substrate which comprises a plurality of trench isolation parts distributed at intervals in a first direction; self-aligning the plurality of trench isolation parts to form a first type bottom semiconductor layer comprising a plurality of first target patterns which are distributed at intervals along the first direction, the first target patterns comprising a first type second semiconductor part, a first semiconductor part and a second semiconductor part which are sequentially distributed along the first direction; forming a second type photosensitive lamination layer on the surface, deviating from the substrate, of the bottom semiconductor layer; self-aligning the first semiconductor part, and forming a plurality of first type semiconductor columns which penetrate through the photosensitive lamination layer along a second direction and extend to the first semiconductor part; and forming a first type top semiconductor layer by adopting the same preparation process as the bottom semiconductor layer. The electron concentration of a photosensitive area can be increased at least, and the photosensitive performance of the BSI image sensor is improved.

The invention provides a high-density photoelectric common connection pinboard based on a low-loss silicon nitride grating coupler. The invention aims to overcome the difficulty that the existing photoelectric heterogeneous chip is difficult to integrate, stack and package, and realizes high-density interconnection between the chip and the interposer by using a grating coupling structure and a silicon through hole technology, thereby realizing high-integration low-loss packaging of the heterogeneous chip on the interposer. According to the invention, high-efficiency optical interconnection between the heterogeneous chip and the photoelectric co-connection intermediate layer is realized through the high-efficiency grating coupler, and high-density electrical interconnection between the chip and the photoelectric co-connection intermediate layer is realized through the TSV technology and the RDL technology. Meanwhile, the optical interconnection efficiency between the interposer and the chip is improved by utilizing the electrode patterning advantage of the RDL technology, and the self-alignment between the chip and the interposer is realized. The method has extremely high compatibility to the packaging scene of the existing photoelectric heterogeneous chip, so that the method has great significance in improving the integration density and reducing the interconnection loss of a photoelectric heterogeneous integrated system and promoting the practicability of the photoelectric heterogeneous integrated system.

The invention provides a process integration method of a high-voltage CMOS (Complementary Metal Oxide Semiconductor) device in a flash memory device, which comprises the following steps of: before a grid electrode of a high-voltage MOS (Metal Oxide Semiconductor) device region is prepared, by virtue of a mask plate of threshold voltage ion implantation of a flash memory device region, adopting a non-self-alignment mode and taking a patterned sacrificial layer as a mask, forming a high-voltage MOS device region; and performing threshold voltage ion implantation (CVT ion implantation) on the substrate in the flash memory device region and the high-voltage MOS device region to form a first threshold voltage ion implantation region in the first well region and form a second threshold voltage ion implantation region in the second well region at two sides of the patterned sacrificial layer, and replacing traditional LDD implantation in the MOS device region with the threshold voltage ion implantation to form a second threshold voltage ion implantation region in the second well region at two sides of the patterned sacrificial layer. Therefore, a low-doped expansion region can be formed between the lower part of the grid boundary of the high-voltage MOS device region and the source / drain, and an independent high-voltage LDD ion implantation process of the traditional high-voltage CMOS device region can be omitted, so that the process manufacturing cost is reduced.

The invention discloses a semiconductor device and a preparation method thereof. According to the invention, on the basis of not adding a new manufacturing process, a plurality of lightly doped drain regions with different doping concentration gradients in the transverse direction are formed by utilizing a multi-layer structure side wall, taking self-alignment as a barrier layer of ion implantation and performing multi-section ion implantation, and the doping concentration of the lightly doped drain structure jointly formed by the plurality of lightly doped drain regions is gradually distributed; buffer of hot carriers can be effectively increased, a peak electric field is further reduced, and therefore the purpose of further improving the hot carrier injection effect is achieved.

The invention discloses a Micro-LED (Light Emitting Diode) device self-alignment groove filling and passivating method, which comprises the following steps that a Micro-LED device is provided, and the Micro-LED device comprises array units and grooves between the array units; preparing a dielectric layer on the Micro-LED device, wherein the dielectric layer fills the groove and covers all the array units; curing the dielectric layer; and thinning the whole surface of the dielectric layer by using a mask-free dry etching back etching method until the upper surfaces of all the array units are exposed, and forming a patterned passivation layer at the groove. The whole surface of the dielectric layer is thinned by using a mask-free dry etching back etching method, mask preparation and photoetching are not needed, the height of the dielectric layer can be accurately regulated and controlled through an etching process, and the process is simple; meanwhile, due to the fact that the register step and the developing solution corrosion step are avoided, the technological method can eliminate the problems of interface gaps and table top residues caused by register errors, the graphical passivation layer which is tightly connected can be formed without being restrained by the shape and the size, the etching resistance of the passivation structure is improved, and the device manufacturing yield is improved.

The invention relates to the technical field of communication power connection, in particular to a magnetic coupling connector assembly for deep sea wet plugging, which comprises a socket component and a plug component, wireless power supply coils and communication modules are arranged at the front ends of the socket component and the plug component, and a first annular magnet array is arranged at the front end of the socket component. A second annular magnet array is arranged at the front end of the plug component, and magnetic poles at the same position of the first annular magnet array and the second annular magnet array are oppositely arranged; and a rotary locking mechanism is arranged between the socket component and the plug component and is used for realizing mechanical locking through relative rotation after the socket component and the plug component are magnetically adsorbed. By adopting the design that the annular multi-pole magnet array and the mechanical rotary locking mechanism cooperate with each other, magnetic force provides adsorption force during butt joint and is converted into locking force after locking, self-alignment and high-reliability locking in the butt joint process are completed, and the technical effect of environment interference resistance is achieved.

The invention discloses a deep learning assisted variational Bayesian group filtering self-alignment method for a low-precision SINS (Strapdown Inertial Navigation System), which comprises the following steps of: firstly, regarding gyroscope data obtained by the low-precision SINS as a time sequence by utilizing the principle and the characteristic of sensor measurement; a neural network model adopting a gated cycle unit (GRU) is designed and is used for calibrating and compensating the measurement error of the low-precision SINS. Secondly, a novel variational Bayesian Lie group filtering method is developed to process various errors in the Lie group alignment model, especially state dependent noise. A variational Bayesian method is expanded to a Lie group space to adaptively estimate a measurement noise covariance matrix in real time. And finally, performing an experiment on rotary table equipment to verify and test the performance and advantages of the proposed method. Experimental results show that the initial self-alignment method provided by the invention is obviously superior to the existing method in the aspects of alignment precision and time. According to the method, the real-time requirement in practical application is completely met, and extra equipment and cost are not needed.

The invention discloses a self-alignment and equivalent confrontation training simulation method based on scene driving, and belongs to the technical field of radar confrontation, and the method specifically comprises the steps: obtaining and analyzing a confrontation training task, obtaining training information, and generating a test scene according to training; real-time position information of the tested electronic countermeasure equipment and the countermeasure training equipment is acquired in real time, the countermeasure training equipment is controlled to generate a radiation radar signal according to the real-time position information, and the radiation radar signal is wirelessly transmitted to the tested electronic countermeasure equipment; after a radiation radar signal is received, an interference signal is generated, power detection is performed on the interference signal, the received interference signal is modulated and superposed with the radiation radar signal to obtain test data, and the interference confrontation performance of confrontation training equipment is determined based on the test data. According to the invention, radar targets and interference signals can be flexibly simulated according to complex combat scenes, and a highly vivid electromagnetic training environment is provided for electronic countermeasure equipment.

Techniques are provided herein to form semiconductor devices that include one or more gate cuts that are self-aligned within the gate trench between adjacent devices. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure includes a gate dielectric and a gate electrode. The gate structure may be interrupted with a gate cut that extends through an entire thickness of the gate structure and includes dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. In an example, the gate cut is confined within the gate trench such that it does not extend beyond the walls of the gate trench as defined by gate spacer structures. Additionally, the gate dielectric does not form on any surface of the gate cut, such that the gate cut directly contacts the gate electrode.

A semiconductor device according to some embodiments of the disclosure may include a fin type active pattern extending in a first direction, a plurality of gate structures on the fin type active pattern and extending in a second direction different from the first direction, a plurality of inter-contact insulation patterns on respective ones of the plurality of gate structures, a plurality of interlayer insulation layers on side surfaces of the plurality of gate structures, and a plurality of contact plugs respectively between pairs of the plurality of gate structures. The fin type active pattern may include a plurality of source / drains. Lower ends of the plurality of contact plugs may contact the plurality of source / drains. The plurality of gate structures may each include a first gate metal, a second gate metal, a gate capping layer, a gate insulation layer, a first spacer, and a second spacer.

Methods of forming a metal gate structure of a stacked multi-gate device are provided. A method according to the present disclosure includes depositing a titanium nitride (TiN) layer over a channel region that includes bottom channel layers and top channel layers, depositing a dummy fill layer to cover sidewalls of the bottom channel layers, after the depositing of the dummy fill layer, selectively forming a blocking layer over the TiN layer along sidewalls of the top channel layers, selectively removing the dummy fill layer to release the bottom channel layers, selectively depositing a first work function metal layer to wrap around each of the bottom channel layers, forming a gate isolation layer over a top surface of the first work function metal layer, removing the blocking layer, releasing the top channel layers, and selectively depositing a second work function metal layer to wrap around each of the top channel layers.

A semiconductor structure includes a field effect transistor having a plurality of source / drain regions and a metal gate structure. A dielectric layer is in contact with a first surface of each of the plurality of source / drain regions, while a bottom dielectric isolation layer is in contact with a first surface of the metal gate structure. The bottom dielectric isolation layer is coplanar with the dielectric layer. The semiconductor structure further includes a backside metal contact that extends through a backside interlevel dielectric and the dielectric layer until an uppermost surface of at least one source / drain region of the plurality of source / drain regions. The backside interlevel dielectric is disposed above the dielectric layer and above the bottom dielectric isolation layer. The backside metal contact electrically connects the at least one source / drain region to a backside interconnect structure disposed above the backside interlevel dielectric.

A backside contact structure is provided that directly connects a first electrode (52) of the MRAM located at the backside of the wafer to a source / drain structure (36) of the transistor. The backside contact is self-aligned with a source / drain structure (36) of the transistor and a first electrode (52) of the MRAM. The close proximity between the MRAM and the source / drain structure (36) increases the speed of the device. The MRAM yield is not compromised because re-sputtering of the back side contact metal onto the MRAM does not occur.

The invention relates to a preparation method of an LDMOS device and the LDMOS device, and relates to the technical field of semiconductors, in the preparation method, a first etching machine table is adopted for a self-aligned polycrystalline silicon material layer, a second etching machine table is adopted for a shielding material layer, and special etching machine tables are adopted for different materials, so that the etching precision can be improved, and the manufacturing cost is reduced. Therefore, the material loss caused by incomplete etching of the material needing to be etched or over-etching during etching is avoided, and the yield of the product is improved. In addition, according to the formed LDMOS device, the metal silicide covering the shielding layer serves as a supplementary grid electrode of the grid electrode of the LDMOS device, so that the length of a conducting channel is increased, and the LDMOS device has better high voltage resistance.

A semiconductor structure includes a first transistor including a first placeholder and a first gate pitch, and a second transistor including a second placeholder and a second gate pitch, where the first gate pitch is less than the second gate pitch, and where the first placeholder is less than the second placeholder.

Techniques are provided herein to form semiconductor devices that include one or more gate cuts that are self-aligned within the gate trench between adjacent devices. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure includes a gate dielectric and a gate electrode. The gate structure may be interrupted, for example, between two transistors with a gate cut that extends through at least a portion of the entire thickness of the gate structure and includes dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. A dielectric plug contacts a top surface of the gate cut to separate the gate structure on either side of the dielectric plug. The gate cut is self-aligned between the adjacent semiconductor devices such that it is substantially equidistant between the semiconductor devices along the gate trench.

The invention discloses a flexible substrate material doped with a two-dimensional material and a preparation method of a sensor of the flexible substrate material, and belongs to the technical field of array sensors. The electrode material comprises a two-dimensional material substrate, a composite doping atom layer and an insulation isolation layer, high-density defect sites are formed through H2 plasma processing, uniform distribution of doping atoms is achieved in combination with atomic layer deposition, and an electrode and a temperature-sensitive layer are precisely integrated through the self-alignment photoetching technology. According to the scheme, the electronic structure of the two-dimensional material is optimized through the composite doping synergistic effect, the multi-layer heterojunction design and the high-precision preparation process are combined, the response capacity of the electrode to weak pressure signals is remarkably improved, and high resolution and stability of the sensor in pressure and temperature detection are achieved. The method has a wide application prospect in the fields of wearable equipment, medical monitoring, robot tactile perception and the like.

A surgical robotic system includes a control tower and a robotic system component. The control tower includes a tower Li-Fi transceiver configured to communicate on a first communication data channel. The robotic system component includes a robotic system component Li-Fi transceiver configured to communicate first data, and a self-aligning mechanism. The self aligning mechanism includes an imaging device configured to capture images configured to allow detection of a detected a geospatial location of the tower Li-Fi transceiver, and an actuatable base configured for aligning the imaging device with the detected geospatial location of the tower Li-Fi transceiver. The robotic system component Li-Fi transceiver is mounted to the actuatable base.

A method of making a semiconductor device includes providing semiconductor region of a first conductivity type. A first region comprising the first conductivity type and a second dopant concentration greater than the first dopant concentration is provided within the region. The first region provides a JFET channel region for a JFET device. A second region comprising a second conductivity type is provided within the first region. The second region provides a body region for a MOSFET device and a gate region for the JFET device. The second region comprises a first portion and a second portion below the first portion. The second portion has a higher peak dopant concentration than the first portion. A third region comprising the first conductivity type is provided within and self-aligned to the second region. The third region provides a JFET source for the JFET device.

Disclosed in the present application are a split-gate floating-gate flash memory device and a manufacturing method therefor. The method comprises: S1: providing a flash memory device, the flash memory device comprising a substrate and gate structures grown on the substrate, select gate protection layers being formed at the tops of the gate structures, third spacer dielectric layers being formed on both sides of each gate structure, and source-drain regions being formed in the substrate located on both sides of each gate structure; S2: using the select gate protection layers and the third spacer dielectric layer as hard masks to perform self-aligned etching on the source-drain regions, so as to form shallow trench contact holes; and S3, depositing metal silicide in the shallow trench contact holes. The solution of the present application can solve the problem of interference in related technologies between adjacent units during programming processes.

A method for making a semiconductor structure, including: forming a conductive layer; forming a patterned mask layer on the conductive layer; patterning the conductive layer to form a recess and a conductive feature; forming a first dielectric layer over the patterned mask layer and filling the recess with the first dielectric layer; patterning the first dielectric layer to form an opening; selectively forming a blocking layer in the opening; forming an etch stop layer to cover the first dielectric layer and exposing the blocking layer; forming on the etch stop layer a second dielectric layer; forming a second dielectric layer on the etch stop layer; patterning the second dielectric layer to form a through hole and exposing the conductive feature; and filling the through hole with an electrically conductive material to form an interconnect electrically connected to the conductive feature.

A semiconductor structure with self-aligned backside trench epitaxy includes a channel fin extending vertically from a bottom source / drain region of a field effect transistor. The bottom source / drain region includes a trench epitaxial layer below the bottommost surface of the channel fin. A high-k metal gate stack is disposed along sidewalls of the channel fin. The high-k metal gate is separated from the bottom source / drain region by a bottom spacer. A top source / drain region is over the topmost surface of the channel fin. The top source / drain region is separated from the high-k metal gate by a top spacer. The semiconductor structure also includes a backside metal contact within the backside interlayer dielectric. The backside metal contact is electrically connected to and vertically aligned with the bottom source / drain region.

An optical phased array device, and method of fabricating an optical phased array device, where the optical phased array device has a plurality of self-aligned waveguides having an on-chip edge coupler at which a single mode optical fiber is coupled to each of the plurality of self-aligned waveguides; and / or has a fiber coupling interface and a plurality of waveguide layers sharing a common edge at the fiber coupling interface, wherein the fiber coupling interface is configured to couple a single mode optical fiber to each of the plurality of waveguide layers at the common edge. The method includes fabricating an optical phased array according to a layer thickness for one or more waveguide layers, wherein the layer thickness is determined based on mode matching data derived from a mode profile at an input coupling interface.