1059 results about "Self alignment" patented technology

The invention relates to the technical field of silicon waveguide and optical fiber coupling, and particularly provides an AI-based silicon waveguide-optical fiber mode field self-alignment coupling method and system, and the method comprises the steps: monitoring the strain distribution of a chip in real time through an integrated distributed fiber bragg grating array, and obtaining the light field intensity distribution of a coupling region through cooperation with a near-field optical probe array; constructing a deep space-time convolutional network, and generating a deformation compensation vector and a waveguide reconstruction parameter by an output layer; a nanofluid channel is integrated on the side wall of the waveguide, and the refractive index of liquid is adjusted through an electrowetting effect to realize dynamic broadening of a mode field; and the electrostatic driving micro-beam embedded below the waveguide adjusts the spatial pose of the waveguide according to an instruction of an output layer of the depth space-time convolutional network. The system comprises a light field intensity acquisition module, a convolutional network construction module and a spatial pose adjustment module. According to the method, real-time analysis and prediction are performed, so that system parameters are actively adjusted, and alignment precision and stability are improved.

The invention discloses a preparation method of a vertical comb-driven MEMS (Micro Electro Mechanical System) micromirror, which comprises the following steps of: forming a through alignment mark and a pre-etched comb structure on a device layer by using a first composite mask, and forming the through alignment mark and the pre-etched comb structure on the back surface of the device layer on a first substrate through a composite mask process, after the first substrate and the second substrate are bonded, the self-alignment composite mask of the comb tooth structure is aligned with the back face pre-etched comb tooth structure through the through alignment mark, high-precision alignment of the comb tooth structure is achieved, accumulated errors are avoided, and the yield of device preparation is improved.

A nanosheet semiconductor structure including a self-aligned backside contact, and a gate cut contact structure extending between two stacks stack of semiconducting layers and in electrical contact with the self-aligned backside contact and a source drain contact on a frontside, wherein a lateral dimension of the gate cut contact structure is less than a lateral dimension of the self-aligned backside contact.

A method is provided for forming a light-shielding layer to block irradiation of light onto a light-sensitive storage region. The light-sensitive storage region is formed in a semiconductor substrate to store electric charges. A storage gate feature is formed over the light-sensitive storage region, and includes a polysilicon gate electrode that is disposed over the light-sensitive storage region. A metal layer is formed over the storage gate feature. A silicidation process is performed to transform a part of the metal layer that is in contact with the polysilicon gate electrode into a silicide light-shielding layer. A thermal process is performed to induce lateral growth of the silicide light-shielding layer to make the silicide light-shielding layer extend to cover a lateral surface of the storage gate feature. A process temperature of the thermal process is higher than that of the silicidation process.

A self-aligning window mounted communication apparatus is discussed herein. In some examples, a wireless gateway may comprise a first unit to be mounted outside a window and a second unit to be mounted inside the window. A first unit and a second unit may each include an optical unit, a coupling unit, and a housing unit. A first optical unit may include a magnetic array with polarities of the magnetic elements configured to orient with a second optical unit in a single orientation. The optical unit(s) may be movably coupled with the respective coupling unit(s) so that the optical unit may move with various degrees of freedom and thus, when the first and second units are mounted on a window, the optical units can self-align based on the respective magnetic arrays and the degrees of freedom afforded by the movable coupling with the coupling unit.

Embodiments of the present disclosure provide a method for forming backside gate contacts and semiconductor fabricated thereof. A semiconductor device includes both signal outputs, such as source / drain contacts, and signal inputs, such as gate contacts, formed on a backside of the substrate. The backside gate contacts and backside source / drain contacts are formed in a self-aligned manner.

The invention relates to a backside illuminated image sensor preparation method and a backside illuminated image sensor, and relates to the technical field of integrated circuits, and the method comprises the steps: providing a substrate which comprises a plurality of trench isolation parts distributed at intervals in a first direction; self-aligning the plurality of trench isolation parts to form a first type bottom semiconductor layer comprising a plurality of first target patterns which are distributed at intervals along the first direction, the first target patterns comprising a first type second semiconductor part, a first semiconductor part and a second semiconductor part which are sequentially distributed along the first direction; forming a second type photosensitive lamination layer on the surface, deviating from the substrate, of the bottom semiconductor layer; self-aligning the first semiconductor part, and forming a plurality of first type semiconductor columns which penetrate through the photosensitive lamination layer along a second direction and extend to the first semiconductor part; and forming a first type top semiconductor layer by adopting the same preparation process as the bottom semiconductor layer. The electron concentration of a photosensitive area can be increased at least, and the photosensitive performance of the BSI image sensor is improved.

The invention provides a high-density photoelectric common connection pinboard based on a low-loss silicon nitride grating coupler. The invention aims to overcome the difficulty that the existing photoelectric heterogeneous chip is difficult to integrate, stack and package, and realizes high-density interconnection between the chip and the interposer by using a grating coupling structure and a silicon through hole technology, thereby realizing high-integration low-loss packaging of the heterogeneous chip on the interposer. According to the invention, high-efficiency optical interconnection between the heterogeneous chip and the photoelectric co-connection intermediate layer is realized through the high-efficiency grating coupler, and high-density electrical interconnection between the chip and the photoelectric co-connection intermediate layer is realized through the TSV technology and the RDL technology. Meanwhile, the optical interconnection efficiency between the interposer and the chip is improved by utilizing the electrode patterning advantage of the RDL technology, and the self-alignment between the chip and the interposer is realized. The method has extremely high compatibility to the packaging scene of the existing photoelectric heterogeneous chip, so that the method has great significance in improving the integration density and reducing the interconnection loss of a photoelectric heterogeneous integrated system and promoting the practicability of the photoelectric heterogeneous integrated system.

The invention provides a process integration method of a high-voltage CMOS (Complementary Metal Oxide Semiconductor) device in a flash memory device, which comprises the following steps of: before a grid electrode of a high-voltage MOS (Metal Oxide Semiconductor) device region is prepared, by virtue of a mask plate of threshold voltage ion implantation of a flash memory device region, adopting a non-self-alignment mode and taking a patterned sacrificial layer as a mask, forming a high-voltage MOS device region; and performing threshold voltage ion implantation (CVT ion implantation) on the substrate in the flash memory device region and the high-voltage MOS device region to form a first threshold voltage ion implantation region in the first well region and form a second threshold voltage ion implantation region in the second well region at two sides of the patterned sacrificial layer, and replacing traditional LDD implantation in the MOS device region with the threshold voltage ion implantation to form a second threshold voltage ion implantation region in the second well region at two sides of the patterned sacrificial layer. Therefore, a low-doped expansion region can be formed between the lower part of the grid boundary of the high-voltage MOS device region and the source / drain, and an independent high-voltage LDD ion implantation process of the traditional high-voltage CMOS device region can be omitted, so that the process manufacturing cost is reduced.

The invention relates to the technical field of communication power connection, in particular to a magnetic coupling connector assembly for deep sea wet plugging, which comprises a socket component and a plug component, wireless power supply coils and communication modules are arranged at the front ends of the socket component and the plug component, and a first annular magnet array is arranged at the front end of the socket component. A second annular magnet array is arranged at the front end of the plug component, and magnetic poles at the same position of the first annular magnet array and the second annular magnet array are oppositely arranged; and a rotary locking mechanism is arranged between the socket component and the plug component and is used for realizing mechanical locking through relative rotation after the socket component and the plug component are magnetically adsorbed. By adopting the design that the annular multi-pole magnet array and the mechanical rotary locking mechanism cooperate with each other, magnetic force provides adsorption force during butt joint and is converted into locking force after locking, self-alignment and high-reliability locking in the butt joint process are completed, and the technical effect of environment interference resistance is achieved.

Techniques are provided herein to form semiconductor devices that include one or more gate cuts that are self-aligned within the gate trench between adjacent devices. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure includes a gate dielectric and a gate electrode. The gate structure may be interrupted with a gate cut that extends through an entire thickness of the gate structure and includes dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. In an example, the gate cut is confined within the gate trench such that it does not extend beyond the walls of the gate trench as defined by gate spacer structures. Additionally, the gate dielectric does not form on any surface of the gate cut, such that the gate cut directly contacts the gate electrode.

A semiconductor device according to some embodiments of the disclosure may include a fin type active pattern extending in a first direction, a plurality of gate structures on the fin type active pattern and extending in a second direction different from the first direction, a plurality of inter-contact insulation patterns on respective ones of the plurality of gate structures, a plurality of interlayer insulation layers on side surfaces of the plurality of gate structures, and a plurality of contact plugs respectively between pairs of the plurality of gate structures. The fin type active pattern may include a plurality of source / drains. Lower ends of the plurality of contact plugs may contact the plurality of source / drains. The plurality of gate structures may each include a first gate metal, a second gate metal, a gate capping layer, a gate insulation layer, a first spacer, and a second spacer.

Methods of forming a metal gate structure of a stacked multi-gate device are provided. A method according to the present disclosure includes depositing a titanium nitride (TiN) layer over a channel region that includes bottom channel layers and top channel layers, depositing a dummy fill layer to cover sidewalls of the bottom channel layers, after the depositing of the dummy fill layer, selectively forming a blocking layer over the TiN layer along sidewalls of the top channel layers, selectively removing the dummy fill layer to release the bottom channel layers, selectively depositing a first work function metal layer to wrap around each of the bottom channel layers, forming a gate isolation layer over a top surface of the first work function metal layer, removing the blocking layer, releasing the top channel layers, and selectively depositing a second work function metal layer to wrap around each of the top channel layers.

A semiconductor structure includes a field effect transistor having a plurality of source / drain regions and a metal gate structure. A dielectric layer is in contact with a first surface of each of the plurality of source / drain regions, while a bottom dielectric isolation layer is in contact with a first surface of the metal gate structure. The bottom dielectric isolation layer is coplanar with the dielectric layer. The semiconductor structure further includes a backside metal contact that extends through a backside interlevel dielectric and the dielectric layer until an uppermost surface of at least one source / drain region of the plurality of source / drain regions. The backside interlevel dielectric is disposed above the dielectric layer and above the bottom dielectric isolation layer. The backside metal contact electrically connects the at least one source / drain region to a backside interconnect structure disposed above the backside interlevel dielectric.

A semiconductor structure includes a first transistor including a first placeholder and a first gate pitch, and a second transistor including a second placeholder and a second gate pitch, where the first gate pitch is less than the second gate pitch, and where the first placeholder is less than the second placeholder.

Techniques are provided herein to form semiconductor devices that include one or more gate cuts that are self-aligned within the gate trench between adjacent devices. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure includes a gate dielectric and a gate electrode. The gate structure may be interrupted, for example, between two transistors with a gate cut that extends through at least a portion of the entire thickness of the gate structure and includes dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. A dielectric plug contacts a top surface of the gate cut to separate the gate structure on either side of the dielectric plug. The gate cut is self-aligned between the adjacent semiconductor devices such that it is substantially equidistant between the semiconductor devices along the gate trench.

The invention discloses a flexible substrate material doped with a two-dimensional material and a preparation method of a sensor of the flexible substrate material, and belongs to the technical field of array sensors. The electrode material comprises a two-dimensional material substrate, a composite doping atom layer and an insulation isolation layer, high-density defect sites are formed through H2 plasma processing, uniform distribution of doping atoms is achieved in combination with atomic layer deposition, and an electrode and a temperature-sensitive layer are precisely integrated through the self-alignment photoetching technology. According to the scheme, the electronic structure of the two-dimensional material is optimized through the composite doping synergistic effect, the multi-layer heterojunction design and the high-precision preparation process are combined, the response capacity of the electrode to weak pressure signals is remarkably improved, and high resolution and stability of the sensor in pressure and temperature detection are achieved. The method has a wide application prospect in the fields of wearable equipment, medical monitoring, robot tactile perception and the like.

A surgical robotic system includes a control tower and a robotic system component. The control tower includes a tower Li-Fi transceiver configured to communicate on a first communication data channel. The robotic system component includes a robotic system component Li-Fi transceiver configured to communicate first data, and a self-aligning mechanism. The self aligning mechanism includes an imaging device configured to capture images configured to allow detection of a detected a geospatial location of the tower Li-Fi transceiver, and an actuatable base configured for aligning the imaging device with the detected geospatial location of the tower Li-Fi transceiver. The robotic system component Li-Fi transceiver is mounted to the actuatable base.

A method of making a semiconductor device includes providing semiconductor region of a first conductivity type. A first region comprising the first conductivity type and a second dopant concentration greater than the first dopant concentration is provided within the region. The first region provides a JFET channel region for a JFET device. A second region comprising a second conductivity type is provided within the first region. The second region provides a body region for a MOSFET device and a gate region for the JFET device. The second region comprises a first portion and a second portion below the first portion. The second portion has a higher peak dopant concentration than the first portion. A third region comprising the first conductivity type is provided within and self-aligned to the second region. The third region provides a JFET source for the JFET device.

A method for making a semiconductor structure, including: forming a conductive layer; forming a patterned mask layer on the conductive layer; patterning the conductive layer to form a recess and a conductive feature; forming a first dielectric layer over the patterned mask layer and filling the recess with the first dielectric layer; patterning the first dielectric layer to form an opening; selectively forming a blocking layer in the opening; forming an etch stop layer to cover the first dielectric layer and exposing the blocking layer; forming on the etch stop layer a second dielectric layer; forming a second dielectric layer on the etch stop layer; patterning the second dielectric layer to form a through hole and exposing the conductive feature; and filling the through hole with an electrically conductive material to form an interconnect electrically connected to the conductive feature.

A semiconductor structure with self-aligned backside trench epitaxy includes a channel fin extending vertically from a bottom source / drain region of a field effect transistor. The bottom source / drain region includes a trench epitaxial layer below the bottommost surface of the channel fin. A high-k metal gate stack is disposed along sidewalls of the channel fin. The high-k metal gate is separated from the bottom source / drain region by a bottom spacer. A top source / drain region is over the topmost surface of the channel fin. The top source / drain region is separated from the high-k metal gate by a top spacer. The semiconductor structure also includes a backside metal contact within the backside interlayer dielectric. The backside metal contact is electrically connected to and vertically aligned with the bottom source / drain region.

A semiconductor structure and method of manufacturing a semiconductor structure having a front side and an opposing backside. An early power delivery network (EBPDN) of wires is built above a substrate layer. Buried power rails (BPRs) are built above levels of the PDN and connected to the EBPDN by short length via connections that can be self-aligned to the back side buried power rails. Both BPRs and vias connections have a common metallization. A front side level of transistor devices are built at the front side of the structure above the BPRs. The resulting formed buried power rail structure has an aspect ratio of height:width greater than 4:1, a height >3 times a height of the formed via structure; and a via structure having a length greater than a height of the formed conductive power rail structure.

The invention provides a microelectronic device and a preparation method thereof, and belongs to the technical field of microelectronic manufacturing. The method comprises the following steps: depositing a dielectric film layer on a substrate; forming a first photoetching pattern on the film layer by using first photoresist, performing first etching on the dielectric film layer by taking the pattern as a mask to obtain a first pattern structure, and stripping the first photoresist; depositing a reflective film layer on the first pattern structure; and forming a second photoetching pattern on the reflecting film layer by using a second photoresist, performing second etching on the reflecting film layer by using the pattern as a mask to obtain a second pattern structure, and stripping the second photoresist to obtain the microelectronic device. The first photoetching pattern and the second photoetching pattern are formed by the same photomask, and the size of the first pattern structure is different from that of the second pattern structure. According to the method, a new photomask and an additional alignment step are not needed, multi-layer patterning and self-alignment transfer of the microelectronic device are realized, the number of photomasks and the alignment frequency are reduced, the cost is reduced, and the pattern consistency is improved.

Described are methods for forming complementary field-effect transistor (CFET), or other vertically aligned semiconductor structures, utilizing a sequential self-aligning process. In one example, a method of forming a complementary field-effect transistor (CFET) is provide. The method includes replacing top sacrificial layers interleaved between channel layers in a top superlattice of a top device structure with top replacement metal gate layers, the top device structure disposed on a bottom device structure, the bottom device structure disposed on a first substrate layer; securing a second substrate layer to the top device structure and removing the first substrate layer from the bottom device structure; and replacing bottom sacrificial layers interleaved between channel layers in a bottom superlattice of the bottom device structure with bottom replacement metal gate layers.

A semiconductor structure including a first stack of semiconducting layers in a first region, a second stack of semiconducting layers in a second region, where the second stack of semiconducting layers in the second region has at least one fewer layer than the first stack of semiconducting layers in the first region, a backside channel plug directly beneath the first stack of semiconducting layers in the first region, and a gate cut contact structure extending between a backside contact structure and a source drain contact on a frontside.

A self-aligning jamb jack apparatus with a cylindrical threaded adjustment component that has adjustment component threads on the exterior wall and smooth surface on the interior walls, the cylindrical threaded adjustment component extending through a cylinder with a smooth exterior to a ball (or cut-off sphere), the smooth surface extending through the cylinder and the ball (or cut-off sphere). The jamb jack apparatus also has a platform base with a socket configured to encompass the ball (or cut-off sphere) such that the platform base pivots around the ball (or cut-off sphere). The self-aligning jamb jack apparatus is installed in a door or window jamb (or any other appliance) to connect and regulate the space between the jamb and the rough framing.

The present techniques include vertical cell dynamic random access memory (DRAM) arrays with improved bit line and storage node contact resistivity and self-alignment, and methods of making such arrays. The array includes a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. The array includes a plurality of channels extending in a vertical direction substantially orthogonal to the first direction and the second horizontal direction such that a plurality of bit lines intersect source / drain regions of the plurality of channels and a plurality of word lines intersect gate regions of the plurality of channels. Further, the array includes where the bit lines, the storage node contacts, or both are formed of metallized material.

Spacer self-aligned via structures for gate contact or trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. The integrated circuit structure also includes a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers between adjacent ones of the plurality of gate structures and the plurality of conductive trench contact structures, wherein the plurality of dielectric spacers protrudes above the plurality of gate structures and above the plurality of conductive trench contact structures. Individual ones of the plurality of dielectric spacers have an upper spacer portion on a lower spacer portion, with an interface between the upper spacer portion and the lower spacer portion.

Techniques to form semiconductor devices that include forksheet transistors with a self-aligned dielectric spine. In an example, first and second semiconductor devices have first and second semiconductor regions, respectively, extending in a first direction between corresponding source or drain regions. The first and second semiconductor regions may include any number of nanosheets with first and second gate structures extending around three sides of each of the first and second semiconductor regions, respectively. A dielectric spine extends in the first direction directly between the first and second semiconductor regions. In an example, the gate dielectric of each of the first and second gate structures is still present between the first and second semiconductor regions and the dielectric spine. An uppermost width of the dielectric spine may be smaller (e.g., 5 nm or more smaller) than a lower width of the dielectric spine that is between the first and second gate structures.