782 results about "Self alignment" patented technology

The invention discloses a preparation method of a vertical comb-driven MEMS (Micro Electro Mechanical System) micromirror, which comprises the following steps of: forming a through alignment mark and a pre-etched comb structure on a device layer by using a first composite mask, and forming the through alignment mark and the pre-etched comb structure on the back surface of the device layer on a first substrate through a composite mask process, after the first substrate and the second substrate are bonded, the self-alignment composite mask of the comb tooth structure is aligned with the back face pre-etched comb tooth structure through the through alignment mark, high-precision alignment of the comb tooth structure is achieved, accumulated errors are avoided, and the yield of device preparation is improved.

A nanosheet semiconductor structure including a self-aligned backside contact, and a gate cut contact structure extending between two stacks stack of semiconducting layers and in electrical contact with the self-aligned backside contact and a source drain contact on a frontside, wherein a lateral dimension of the gate cut contact structure is less than a lateral dimension of the self-aligned backside contact.

Embodiments of the present disclosure provide a method for forming backside gate contacts and semiconductor fabricated thereof. A semiconductor device includes both signal outputs, such as source / drain contacts, and signal inputs, such as gate contacts, formed on a backside of the substrate. The backside gate contacts and backside source / drain contacts are formed in a self-aligned manner.

The invention relates to a backside illuminated image sensor preparation method and a backside illuminated image sensor, and relates to the technical field of integrated circuits, and the method comprises the steps: providing a substrate which comprises a plurality of trench isolation parts distributed at intervals in a first direction; self-aligning the plurality of trench isolation parts to form a first type bottom semiconductor layer comprising a plurality of first target patterns which are distributed at intervals along the first direction, the first target patterns comprising a first type second semiconductor part, a first semiconductor part and a second semiconductor part which are sequentially distributed along the first direction; forming a second type photosensitive lamination layer on the surface, deviating from the substrate, of the bottom semiconductor layer; self-aligning the first semiconductor part, and forming a plurality of first type semiconductor columns which penetrate through the photosensitive lamination layer along a second direction and extend to the first semiconductor part; and forming a first type top semiconductor layer by adopting the same preparation process as the bottom semiconductor layer. The electron concentration of a photosensitive area can be increased at least, and the photosensitive performance of the BSI image sensor is improved.

The invention provides a high-density photoelectric common connection pinboard based on a low-loss silicon nitride grating coupler. The invention aims to overcome the difficulty that the existing photoelectric heterogeneous chip is difficult to integrate, stack and package, and realizes high-density interconnection between the chip and the interposer by using a grating coupling structure and a silicon through hole technology, thereby realizing high-integration low-loss packaging of the heterogeneous chip on the interposer. According to the invention, high-efficiency optical interconnection between the heterogeneous chip and the photoelectric co-connection intermediate layer is realized through the high-efficiency grating coupler, and high-density electrical interconnection between the chip and the photoelectric co-connection intermediate layer is realized through the TSV technology and the RDL technology. Meanwhile, the optical interconnection efficiency between the interposer and the chip is improved by utilizing the electrode patterning advantage of the RDL technology, and the self-alignment between the chip and the interposer is realized. The method has extremely high compatibility to the packaging scene of the existing photoelectric heterogeneous chip, so that the method has great significance in improving the integration density and reducing the interconnection loss of a photoelectric heterogeneous integrated system and promoting the practicability of the photoelectric heterogeneous integrated system.

The invention relates to the technical field of communication power connection, in particular to a magnetic coupling connector assembly for deep sea wet plugging, which comprises a socket component and a plug component, wireless power supply coils and communication modules are arranged at the front ends of the socket component and the plug component, and a first annular magnet array is arranged at the front end of the socket component. A second annular magnet array is arranged at the front end of the plug component, and magnetic poles at the same position of the first annular magnet array and the second annular magnet array are oppositely arranged; and a rotary locking mechanism is arranged between the socket component and the plug component and is used for realizing mechanical locking through relative rotation after the socket component and the plug component are magnetically adsorbed. By adopting the design that the annular multi-pole magnet array and the mechanical rotary locking mechanism cooperate with each other, magnetic force provides adsorption force during butt joint and is converted into locking force after locking, self-alignment and high-reliability locking in the butt joint process are completed, and the technical effect of environment interference resistance is achieved.

A semiconductor device according to some embodiments of the disclosure may include a fin type active pattern extending in a first direction, a plurality of gate structures on the fin type active pattern and extending in a second direction different from the first direction, a plurality of inter-contact insulation patterns on respective ones of the plurality of gate structures, a plurality of interlayer insulation layers on side surfaces of the plurality of gate structures, and a plurality of contact plugs respectively between pairs of the plurality of gate structures. The fin type active pattern may include a plurality of source / drains. Lower ends of the plurality of contact plugs may contact the plurality of source / drains. The plurality of gate structures may each include a first gate metal, a second gate metal, a gate capping layer, a gate insulation layer, a first spacer, and a second spacer.

Methods of forming a metal gate structure of a stacked multi-gate device are provided. A method according to the present disclosure includes depositing a titanium nitride (TiN) layer over a channel region that includes bottom channel layers and top channel layers, depositing a dummy fill layer to cover sidewalls of the bottom channel layers, after the depositing of the dummy fill layer, selectively forming a blocking layer over the TiN layer along sidewalls of the top channel layers, selectively removing the dummy fill layer to release the bottom channel layers, selectively depositing a first work function metal layer to wrap around each of the bottom channel layers, forming a gate isolation layer over a top surface of the first work function metal layer, removing the blocking layer, releasing the top channel layers, and selectively depositing a second work function metal layer to wrap around each of the top channel layers.

A semiconductor structure includes a field effect transistor having a plurality of source / drain regions and a metal gate structure. A dielectric layer is in contact with a first surface of each of the plurality of source / drain regions, while a bottom dielectric isolation layer is in contact with a first surface of the metal gate structure. The bottom dielectric isolation layer is coplanar with the dielectric layer. The semiconductor structure further includes a backside metal contact that extends through a backside interlevel dielectric and the dielectric layer until an uppermost surface of at least one source / drain region of the plurality of source / drain regions. The backside interlevel dielectric is disposed above the dielectric layer and above the bottom dielectric isolation layer. The backside metal contact electrically connects the at least one source / drain region to a backside interconnect structure disposed above the backside interlevel dielectric.

A semiconductor structure includes a first transistor including a first placeholder and a first gate pitch, and a second transistor including a second placeholder and a second gate pitch, where the first gate pitch is less than the second gate pitch, and where the first placeholder is less than the second placeholder.

Techniques are provided herein to form semiconductor devices that include one or more gate cuts that are self-aligned within the gate trench between adjacent devices. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure includes a gate dielectric and a gate electrode. The gate structure may be interrupted, for example, between two transistors with a gate cut that extends through at least a portion of the entire thickness of the gate structure and includes dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. A dielectric plug contacts a top surface of the gate cut to separate the gate structure on either side of the dielectric plug. The gate cut is self-aligned between the adjacent semiconductor devices such that it is substantially equidistant between the semiconductor devices along the gate trench.

The invention discloses a flexible substrate material doped with a two-dimensional material and a preparation method of a sensor of the flexible substrate material, and belongs to the technical field of array sensors. The electrode material comprises a two-dimensional material substrate, a composite doping atom layer and an insulation isolation layer, high-density defect sites are formed through H2 plasma processing, uniform distribution of doping atoms is achieved in combination with atomic layer deposition, and an electrode and a temperature-sensitive layer are precisely integrated through the self-alignment photoetching technology. According to the scheme, the electronic structure of the two-dimensional material is optimized through the composite doping synergistic effect, the multi-layer heterojunction design and the high-precision preparation process are combined, the response capacity of the electrode to weak pressure signals is remarkably improved, and high resolution and stability of the sensor in pressure and temperature detection are achieved. The method has a wide application prospect in the fields of wearable equipment, medical monitoring, robot tactile perception and the like.

A method of making a semiconductor device includes providing semiconductor region of a first conductivity type. A first region comprising the first conductivity type and a second dopant concentration greater than the first dopant concentration is provided within the region. The first region provides a JFET channel region for a JFET device. A second region comprising a second conductivity type is provided within the first region. The second region provides a body region for a MOSFET device and a gate region for the JFET device. The second region comprises a first portion and a second portion below the first portion. The second portion has a higher peak dopant concentration than the first portion. A third region comprising the first conductivity type is provided within and self-aligned to the second region. The third region provides a JFET source for the JFET device.

A method for making a semiconductor structure, including: forming a conductive layer; forming a patterned mask layer on the conductive layer; patterning the conductive layer to form a recess and a conductive feature; forming a first dielectric layer over the patterned mask layer and filling the recess with the first dielectric layer; patterning the first dielectric layer to form an opening; selectively forming a blocking layer in the opening; forming an etch stop layer to cover the first dielectric layer and exposing the blocking layer; forming on the etch stop layer a second dielectric layer; forming a second dielectric layer on the etch stop layer; patterning the second dielectric layer to form a through hole and exposing the conductive feature; and filling the through hole with an electrically conductive material to form an interconnect electrically connected to the conductive feature.

A semiconductor structure and method of manufacturing a semiconductor structure having a front side and an opposing backside. An early power delivery network (EBPDN) of wires is built above a substrate layer. Buried power rails (BPRs) are built above levels of the PDN and connected to the EBPDN by short length via connections that can be self-aligned to the back side buried power rails. Both BPRs and vias connections have a common metallization. A front side level of transistor devices are built at the front side of the structure above the BPRs. The resulting formed buried power rail structure has an aspect ratio of height:width greater than 4:1, a height >3 times a height of the formed via structure; and a via structure having a length greater than a height of the formed conductive power rail structure.

The invention provides a microelectronic device and a preparation method thereof, and belongs to the technical field of microelectronic manufacturing. The method comprises the following steps: depositing a dielectric film layer on a substrate; forming a first photoetching pattern on the film layer by using first photoresist, performing first etching on the dielectric film layer by taking the pattern as a mask to obtain a first pattern structure, and stripping the first photoresist; depositing a reflective film layer on the first pattern structure; and forming a second photoetching pattern on the reflecting film layer by using a second photoresist, performing second etching on the reflecting film layer by using the pattern as a mask to obtain a second pattern structure, and stripping the second photoresist to obtain the microelectronic device. The first photoetching pattern and the second photoetching pattern are formed by the same photomask, and the size of the first pattern structure is different from that of the second pattern structure. According to the method, a new photomask and an additional alignment step are not needed, multi-layer patterning and self-alignment transfer of the microelectronic device are realized, the number of photomasks and the alignment frequency are reduced, the cost is reduced, and the pattern consistency is improved.

Described are methods for forming complementary field-effect transistor (CFET), or other vertically aligned semiconductor structures, utilizing a sequential self-aligning process. In one example, a method of forming a complementary field-effect transistor (CFET) is provide. The method includes replacing top sacrificial layers interleaved between channel layers in a top superlattice of a top device structure with top replacement metal gate layers, the top device structure disposed on a bottom device structure, the bottom device structure disposed on a first substrate layer; securing a second substrate layer to the top device structure and removing the first substrate layer from the bottom device structure; and replacing bottom sacrificial layers interleaved between channel layers in a bottom superlattice of the bottom device structure with bottom replacement metal gate layers.

A semiconductor structure including a first stack of semiconducting layers in a first region, a second stack of semiconducting layers in a second region, where the second stack of semiconducting layers in the second region has at least one fewer layer than the first stack of semiconducting layers in the first region, a backside channel plug directly beneath the first stack of semiconducting layers in the first region, and a gate cut contact structure extending between a backside contact structure and a source drain contact on a frontside.

The present techniques include vertical cell dynamic random access memory (DRAM) arrays with improved bit line and storage node contact resistivity and self-alignment, and methods of making such arrays. The array includes a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. The array includes a plurality of channels extending in a vertical direction substantially orthogonal to the first direction and the second horizontal direction such that a plurality of bit lines intersect source / drain regions of the plurality of channels and a plurality of word lines intersect gate regions of the plurality of channels. Further, the array includes where the bit lines, the storage node contacts, or both are formed of metallized material.

Spacer self-aligned via structures for gate contact or trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. The integrated circuit structure also includes a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers between adjacent ones of the plurality of gate structures and the plurality of conductive trench contact structures, wherein the plurality of dielectric spacers protrudes above the plurality of gate structures and above the plurality of conductive trench contact structures. Individual ones of the plurality of dielectric spacers have an upper spacer portion on a lower spacer portion, with an interface between the upper spacer portion and the lower spacer portion.

Techniques to form semiconductor devices that include forksheet transistors with a self-aligned dielectric spine. In an example, first and second semiconductor devices have first and second semiconductor regions, respectively, extending in a first direction between corresponding source or drain regions. The first and second semiconductor regions may include any number of nanosheets with first and second gate structures extending around three sides of each of the first and second semiconductor regions, respectively. A dielectric spine extends in the first direction directly between the first and second semiconductor regions. In an example, the gate dielectric of each of the first and second gate structures is still present between the first and second semiconductor regions and the dielectric spine. An uppermost width of the dielectric spine may be smaller (e.g., 5 nm or more smaller) than a lower width of the dielectric spine that is between the first and second gate structures.

A semiconductor device is provided. The semiconductor device includes first transistors positioned over a substrate and arranged along a first row in a first direction substantially parallel to a working surface of the substrate. Second transistors are positioned over the substrate and arranged along a second row in the first direction. Each first transistor is aligned with a respective second transistor in a second direction substantially parallel to the working surface of the substrate. An isolation wall structure is positioned between the first transistors and the second transistors.

The present application discloses a chip, a preparation method, and an electronic device. The chip comprises VFETs. Each VFET comprises a vertical channel, a stack structure, a groove structure, and a first electrode. The vertical channel extends in a direction perpendicular to a substrate. The stack structure comprises a gate structure and a first isolating dielectric layer, and the first isolating dielectric layer is provided on the side of the gate structure facing away from the substrate. The groove structure is provided on the side of the stack structure facing away from the substrate. The formed first electrode completely fills the bottom of the groove structure. A polycrystalline area is formed at the edges and corners on the side of the first electrode facing the substrate, so as to fill air gaps in the prior art with the part of the first electrode where the polycrystalline area is formed, thereby reducing the presence of air gaps; and the part of the first electrode where the polycrystalline area is formed is used as a support, thereby improving the stability and reliability of the structure of the corresponding VFET. In addition, the use of the first electrode having a regular shape as a mask is conducive to a subsequent process of using a self-alignment process to form a gate structure, thereby improving the accuracy of a subsequent self-alignment process.

The invention relates to the technical field of AI glasses packaging, in particular to an FPC micro-optical module packaging system and method for AI glasses, and the system comprises at least one first optical element, at least one second optical element, an optical tweezers array generation system, an in-situ monitoring and feedback system and a curing system. The invention aims to solve the problems of low alignment precision and poor yield of optical module packaging in the prior art, and provides a micro-optical module precise packaging system and method capable of realizing active, real-time feedback and in-situ self-alignment.

A method of fabricating a transistor includes: forming a dummy gate and gate spacers; forming an ILD layer alongside the gate spacers; forming a trench having a lower portion and an upper portion wider than the lower portion, forming the trench including: removing the dummy gate and part of the gate spacers; forming a gate structure in the trench; and forming a SAC layer in the trench on the gate structure, wherein: the gate structure has a lower portion and a wider upper portion, a first gate spacer has a first inner sidewall that faces a first side of the lower portion, and a second gate spacer has a second inner sidewall that faces a second side of the lower portion, the first inner sidewall being spaced from the second inner sidewall by a first distance, and the self-aligned contact layer is wider than the first distance.

Photonics integrated circuit (PIC) dies bonded to photonics substrates, related apparatuses, systems, and methods of fabrication are disclosed. A photonics substrate and a PIC die include corresponding optical bonding regions one or both of which are surrounded by hydrophobic structures. A liquid droplet is applied to the PIC die or photonics substrate optical bonding region and the PIC die is placed on the optical bonding region of the photonics substrate. Capillary forces cause the PIC die to self-align to the optical bonding region, and an optical bond is formed by evaporating the liquid and subsequent anneal.

The present invention discloses a method and structure for integrating CMOS and self-aligned silicon-germanium (SGe) HBTs. The method comprises: forming multiple shallow trench isolation regions on a silicon substrate; forming polysilicon gates, gate silicon oxide, and lightly doped regions in the CMOS active region; opening a base window in the HBT region and forming a selective ion implantation region; forming a SiGe base region; forming a sacrificial emitter region; etching to expose the surface of the outer region of the SiGe base region and forming an extrinsic base region; forming an emitter window and exposing the SiGe surface of the underlying SiGe base region; forming a silicon emitter region in the emitter window, and photolithographically patterning the emitter region and the extrinsic base region. The present invention utilizes a novel sacrificial emitter process, combined with a method for self-aligning the raised extrinsic base region and the emitter region, effectively reducing process complexity and making the device process compatible with standard CMOS and other passive device processes.

A photonic device includes a substrate, a P-type doped component disposed over the substrate, an N-type doped component disposed over the substrate, an optical absorption layer disposed over the substrate, and a charging layer disposed over the substrate. The optical absorption layer is disposed between the P-type doped component and the N-type doped component. The optical absorption layer and the substrate have different material compositions. A charging layer is disposed between the P-type doped component and the N-type doped component. The charging layer has a first side surface that is substantially linear. The first side surface is in direct contact with the optical absorption layer.

A die placement system provides a tip body and a die placement head to ensure planarity of a die to a substrate without the need for calibration before each pick and place operation. A self-aligning tip incorporated into the tip body aids in die placement / attachment. This tip provides a global correction for planarity errors that exist between the die and the substrate, whether these errors are due to gantry misalignment (i.e., die side misalignment) or machine deck tool misalignment (i.e., substrate side misalignment).

The techniques include a semiconductor element having improved stress in a channel region. The semiconductor element includes a substrate, a source region, a drain region, a channel region including at least one channel between the source and the drain, a first gate region, and a second gate region. The first gate region includes a self-aligned single diffused break, and the second gate region includes a first gate surrounding the channel between the source region and the drain region. The self-aligned single diffused fracture also includes a dielectric liner and a stress metal filler, wherein the stress metal filler exhibits a stress of about 350 MPa or greater.