390 results about "Non-volatile memory" patented technology

The invention relates to the technical field of DRAM (Dynamic Random Access Memory) dynamic repair, in particular to a DRAM dynamic repair method based on unit damage trend identification. The method comprises the following steps: receiving a logic address request sent by a CPU (Central Processing Unit), sending a reading command to a DRAM (Dynamic Random Access Memory), and obtaining return data and ECC (Error Correction Code When a single-bit error is detected, the error is corrected according to ECC verification data, correct data is returned, meanwhile, the damage trend of a surrounding area is pre-judged based on physical correlation of DRAM unit damage, a DRAM address and the surrounding area are marked as isolation addresses, and the data are moved to an SRAM; establishing a repair mapping table in the SRAM, and writing the repair mapping table into the nonvolatile memory through the bus interface; reading the mapping table during cold start of the system, judging whether the address is an isolation address or not according to the mapping table in subsequent access, and if yes, accessing the SRAM to obtain data. According to the invention, a single-bit error is prevented from being evolved into a multi-bit error, and the system reliability is improved.

The invention provides a quick start and security verification method and equipment for an embedded device, a medium and a program product, in the method, firmware is divided into a core start module and a non-core function module in advance, and the core start module and the non-core function module are respectively stored in a high-speed access area and a common storage area of a nonvolatile memory; after the embedded device is powered on, initialization of the key peripheral is completed; when firmware is started or updated for the first time, security verification based on a digital signature is executed on the core starting module, if verification is passed, a mirror image of the core starting module is written into a running cache partition of the nonvolatile memory, and an integrity label is generated; in the subsequent starting process, the mirror image is loaded from the running cache partition, and the integrity label is used for executing rapid verification; after loading of the core starting module is completed, the non-core function module is loaded, and lightweight check is executed. According to the method, the security of the core module is ensured, the performance and security requirements of the non-core module are considered, and the calculation and storage overhead is reduced.

The invention relates to the technical field of system security, and discloses a firmware package generation method, a secure starting method, a verification method, a device and a medium, the starting method is suitable for a vehicle-mounted SoC system without OTP / eFuse and with a BootROM unmodifiable, and complementary building of a trusted root is achieved in a software mode. In response to the starting instruction, the BootROM loads a security bootstrap program; during first deployment, a secure storage area is created in a nonvolatile memory, and an initial root public key and an abstract thereof are written in to complete initialization of a trust chain. In the subsequent starting process, after the security bootstrap program verifies the integrity of the root public key, the mirror image public key, the abstract and the signature of the mirror image to be started are verified, and it is ensured that the source is legal and the data is complete. On-line updating of a root public key through a chain signature mechanism is supported, that is, a current effective root private key is used for carrying out abstract signature on a new public key, and the new public key can be replaced after the signature verification of an old public key is passed, so that key rotation and trust anchor migration without hardware modification are realized.

Method (100) for operating a field device (1) comprising an adjustable clock (2), at least one non-volatile CA memory (3) containing a public key certificate (3a) of a trusted certification authority, CA, at least one non-volatile time memory (4) for recording a date and / or time (4a) and at least one interface (5), comprising the steps: • A current date and / or time (7a) is received via the interface (5) (170); • this current date or time (7a) is compared with the date or time (4a) in the time memory (4) (180); and • In response to the fact that the current date or time (7a) is later (190) than the date or time (4a) in the time memory (4), the adjustable clock (2) of the field device (1) is set to the current date or time (7a) (200).

A processing system includes one or more memories and one or more processors coupled to the one or more memories. The processing system is configured to obtain first data associated with a vehicle and to obtain second data associated with the vehicle. The first data is associated with a first priority level, and the second data is associated with a second priority level. The processing system is further configured to store the first data to a nonvolatile memory of the vehicle in accordance with detection of a data migration trigger event and further in accordance with a prioritization scheme that prioritizes the first data over the second data upon occurrence of the data migration trigger event.

A method of operating a nonvolatile memory device is provided. The method includes: performing a program operation on a selected word-line of a plurality of cell strings during a program execution period of a program loop by applying a program voltage to the selected word-line; and performing a program verification operation during a program verification period of the program loop by applying a program verification voltage to the selected word-line and by applying a first verification pass voltage to a first zone of unselected word-lines among and a second verification pass voltage to a second zone of the unselected word-lines. A voltage level of the second verification pass voltage is lower than a voltage level of the first verification pass voltage.

A memory controller configured to write, read, and erase data for a nonvolatile memory device storing first meta data and first journal data indicating first changes of the first meta data, the memory controller comprising: a buffer memory circuit including a buffer memory and a buffer controller, wherein the buffer memory stores second meta data and second journal data indicating second changes of the second meta data, and wherein the buffer controller controls the buffer memory; and an accelerator managing the first meta data, the second meta data, the first journal data, and the second journal data, wherein the buffer controller includes: a first error correction code (a first ECC) engine configured to correct a first error of first data that includes the second meta data; and a second error correction code (a second ECC) engine configured to correct a second error of second data including the second journal data.

The invention discloses a portable wireless radio frequency switching method and system, a medium and a program product, and relates to the field of transmission, in the method, a switching device obtains a radio frequency signal strength value of a device to be switched; the switching device sends an awakening instruction and a handshake request to a to-be-switched device which is in a deep sleep state and keeps low-power-consumption monitoring; executing the handshake request to establish a secure communication connection; the switching device sends the encrypted radio frequency configuration data to a device to be switched, and the device to be switched writes the encrypted radio frequency configuration data into a nonvolatile memory; after the equipment to be switched completes writing of the encrypted radio frequency configuration data, a confirmation signal is sent to the switching equipment, the deep sleep state is automatically switched to, and low-power-consumption monitoring is kept. On the basis of keeping certain power to monitor the configuration request, low-power-consumption standby is realized, so that energy waste is reduced, and the use cost of equipment is reduced.

The invention provides a calibration method for an analog quantity acquisition module of a ship automation system, and the method comprises the steps: enabling the analog quantity acquisition module to be in an automatic calibration state, and enabling an output channel of standard signal generation equipment to be connected with a to-be-calibrated input channel of the analog quantity acquisition module; applying at least two different standard analog quantity signal values to the to-be-calibrated input channel through the standard signal generation equipment; the analog quantity acquisition module automatically acquires and records an actual measurement value corresponding to each standard analog quantity signal value; calculating calibration parameters k and b through linear fitting based on the at least two standard analog quantity signal values and the corresponding actual measurement values; and storing the calculated calibration parameters k and b into a nonvolatile memory of the analog quantity acquisition module for real-time calibration during subsequent data acquisition. According to the invention, the calibration of errors floating along with actual signals is realized, and the efficiency of field debugging and calibration work can be improved through an automatic calibration process.

The invention relates to a data acquisition unit and method based on an industrial internet unique identifier, and belongs to the technical field of industrial internet and data acquisition, the data acquisition unit comprises a main control module, a communication module and a data acquisition interface module, after equipment is powered on, the main control module firstly automatically initiates a unique identifier registration request to an identifier registration center; the successfully registered identification code is stored in a nonvolatile memory; then, based on the unique identification code, an authentication connection with an industrial internet platform is established through a communication module, and an acquisition configuration instruction issued by the industrial internet platform is received; and generating an acquisition rule according to the acquisition configuration instruction, performing data acquisition through the data acquisition interface module, binding the acquired data with the unique identification code, and reporting the bound data to the platform. According to the invention, global identifiability and credible authentication of the device identity are realized, and dependence on an edge gateway is reduced; the method realizes traceable data source and traceable destination, effectively gets through data islands, and supports cross-domain collaborative application.

The invention discloses a nonvolatile memory device based on CrMoGe2S6 / Ga2O3 heterostructure tensile strain and a construction method, and belongs to the technical field of nonvolatile memory devices. Comprising the following steps: vertically stacking a single layer of Ga2O3 and a single layer of CrMoGe2S6, and constructing two kinds of CrMoGe2S6 / Ga2O3 heterostructures; performing biaxial tensile strain on the CrMoGe2S6 / Ga2O3 heterostructure, calculating a magnetic ground state and an energy band of the CrMoGe2S6 / Ga2O3 heterostructure under different strains, and screening out the CrMoGe2S6 / Ga2O3 heterostructure which is represented as a ferromagnetic state; and on the basis of the screened CrMoGe2S6 / Ga2O3 heterostructures, two CrMoGe2S6 / Ga2O3 heterostructures with the same tensile strain are selected to construct the nonvolatile memory device. Ferroelectric Ga2O3 is introduced to serve as a switch, the electronic property of CrMoGe2S6 is controlled by the polarization state of Ga2O3, the Ga2O3 which is electrically polarized upward P does not change the semiconductor characteristic of CrMoGe2S6, and the Ga2O3 which is electrically polarized downward P enables the CrMoGe2S6 to present semimetallic property; therefore, the non-volatile electric control of the CrMoGe2S6 between the antiferromagnetic semiconductor and the semimetal is indirectly realized; the characteristic is especially important for a memory device, and can significantly reduce energy consumption and improve data stability.

The invention provides an ONU (Optical Network Unit) management mode and port state switching method based on a hardware button, and relates to the technical field of communication, the method comprises the following steps: acquiring the triggering duration of an MOD (Modulation of Delay) button in ONU equipment, the triggering duration comprising a first triggering duration in a first time period and a second triggering duration in a second time period, the first time period is longer than the second time period; when the triggering duration of the MOD button is a first triggering duration, enabling the ONU equipment to execute a management mode switching operation, and performing switching between a remote management mode and a local management mode; and when the triggering duration of the MOD button is a second triggering duration, enabling the ONU equipment to execute switching between a port isolation state and a port intercommunication state in a local management mode, and directly writing a switching result into a nonvolatile memory. According to the invention, the reliability of the ONU equipment can be improved.

An example nonvolatile memory device includes page buffer circuits, compression engines, local clock controllers, a data input / output (I / O) circuit, and a control circuit. Each compression engine is connected with a respective page buffer circuit through respective local data lines. The control circuit controls each compression engine to perform an encoding operation based on receiving soft decision data from target cache latches corresponding to an output address, based on compressing the received soft decision data, and based on overwriting the compressed soft decision data in the target cache latches based on an input address. The control circuit controls one or more page buffer circuits among the plurality of page buffer circuits to perform an output operation based on outputting the compressed soft decision data through the data I / O circuit, the output operation performed in parallel with the encoding operation or independently from the encoding operation.

A method for data transmission is provided. The method includes, at an initiator computing device, receiving a data payload to be transmitted to a target computing device for storage using the nonvolatile memory express over fabric (NVMe-oF) protocol, wherein the data payload is represented as a plurality of logical blocks. Using a compression engine, the data payload is compressed into a plurality of physical blocks having a smaller total data size than the plurality of logical blocks. A write request is transmitted to the target computing device, the write request including the plurality of physical blocks, and metadata specifying a correspondence between each logical block of the plurality of logical blocks and one or more corresponding physical blocks of the plurality of physical blocks.

The invention relates to the technical field of wireless detonators. The parameter configuration method for the through-the-earth type wireless detonator comprises the following steps: before the wireless detonator is put into a hole, transmitting parameter configuration data to the wireless detonator by using a circuit, and storing the parameter configuration data in a nonvolatile memory of the wireless detonator to obtain data for verification; after the wireless detonator is put into the hole, a detonating instruction is sent to the wireless detonator, and the detonating instruction comprises a detonating instruction identifier and target equipment identification and verification information; and receiving the data used for verification, carrying out format verification, verification and verification and anti-replay attack detection on the detonation instruction by the wireless detonator, forming a feedback result, and determining an execution state and a detonation result of the wireless detonator. According to the method, the reliability of parameter configuration and the adaptability in a complex geological environment are remarkably improved, the deployment time is shortened, meanwhile, the system complexity is reduced through a function separation framework, and maintenance is more convenient.

A memory device is provided. The memory device includes a nonvolatile memory including a memory cell array, and a controller configured to control the nonvolatile memory. The memory cell array includes: a memory cell including a first magnetic tunnel junction element, an OTP (One-Time-Programmable) cell including a second magnetic tunnel junction element, and a reference cell connected to a first reference resistor for reading data for the memory cell or a second reference resistor for reading data from the OTP cell, wherein the controller is configured to set the second reference resistance, based on a first edge resistance value detected from a resistance distribution of OTP cells comprising the OTP cell or based on the first reference resistance.

The invention discloses an automatic testing method and device for a water meter module, a medium and a product. In the method, a manipulator is controlled to grab a to-be-tested water meter module and place the to-be-tested water meter module at a test station, and start power consumption characteristic data, sleep power consumption characteristic data and valve control response characteristic data of the to-be-tested water meter module are collected; processing the starting power consumption characteristic data, the dormancy power consumption characteristic data and the valve control response characteristic data to construct an electrical reference portrait; writing a module identity into a nonvolatile memory of the water meter module to be tested; performing function verification on the to-be-tested water meter module to obtain a dynamic function data set; obtaining dynamic power consumption characteristic data, and verifying the dynamic function data set and the dynamic power consumption characteristic data to obtain a consistency verification result; and generating a quality judgment conclusion, and moving the to-be-detected water meter module to a preset area according to the quality judgment conclusion. By implementing the technical scheme provided by the invention, the limitation that a traditional quality inspection method only depends on independent parameter threshold judgment is effectively overcome.

A system and method for validating that all functions within a time-critical task are resident in RAM is disclosed. This ensures that time-critical tasks are not impacted by having to access slow nonvolatile memory (NVM). The method comprises generating an exception for each transition between RAM-based instruction execution and NVM-based instruction execution, determining whether the transition is acceptable, and saving a fault address if the transition is not acceptable. A transition is deemed to be acceptable if it does not impact the execution of a time-critical function.

The embodiment of the invention provides a memory system, an operation method thereof and electronic equipment. The memory system includes: a nonvolatile memory device including a plurality of pages; the preset number of pages form a storage group; the memory controller is coupled with the nonvolatile memory device and is configured to determine a reading voltage of the to-be-read data according to a first duration of a target storage group where the to-be-read data is located in a process of performing a reading operation on the nonvolatile memory device; the first duration is the time difference between the moment when the last write-in is completed in the target storage group and the reading operation starting moment.

The invention relates to a portable WiFi (Wireless Fidelity) self-adaptive endurance optimization system, which comprises a data acquisition module used for acquiring terminal information for establishing Wi-Fi connection, byte receiving and transmitting total quantity, data packet processing quantity and physical state information of equipment, adding a timestamp label to acquired real-time data, storing the data in a nonvolatile memory of the equipment, and storing the acquired real-time data in the nonvolatile memory of the equipment; the method comprises the following steps: generating a historical log, performing periodic aggregation calculation on the historical log, generating feature data representing user behavior habits, compressing and encrypting the feature data and the historical log, and reporting the feature data and the historical log to a cloud server; the behavior prediction module is used for receiving the baseline prediction model issued by the cloud server and the data acquired by the data acquisition module, and performing real-time behavior prediction of the equipment side and incremental training and fine tuning optimization of the model according to the data; the intelligent decision engine is used for dynamically generating a power consumption control strategy; and the feedback learning module collects actual operation effect data, updates a local model and synchronizes the local model to the cloud.

A method is described. The method includes constructing a bitmap having a first dimension organized into bins of logical block addresses (LBA bins) and a second dimension organized into bins of physical block addresses (PBA bins). Coordinates of the bitmap indicate whether respective physical blocks of non volatile memory within one or more SSDs that fall within a particular PBA bin are being mapped to by an LBA that falls within a particular one of the LBA bins. The method includes using the bitmap during a rebuild of an LBA bin of an LBA / PBA table to avoid reading meta data for physical blocks that are not mapped to by an LBA that falls within the LBA bin.

According to an embodiment, a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a first memory cell configured to nonvolatilely store data of a plurality of bits including a first bit and a second bit, and a second memory cell configured to nonvolatilely store data of at least one bit. The memory controller is configured to execute a save operation in accordance with reception of a command from a host, in the save operation, write first bit data to the second memory cell in a case where the first memory cell stores the first bit data as the first bit and does not store data as the second bit, and transmit, to the host, a completion response to the command after the first bit data has been written to the second memory cell.

According to one embodiment, a controller of a memory system provides a host with logical address spaces. A plurality of queues of the host include one or more queues allocated to each of the logical address spaces. The controller calculates first use amounts of a nonvolatile memory corresponding to the logical address spaces, respectively, selects a queue from which a command is to be fetched among the plurality of queues, based on the first use amounts, fetches a command from the queue, calculates a predicted use amount of the nonvolatile memory in accordance with the command, and updates a second use amount corresponding to a first logical address space to which the first queue is allocated among the first use amounts by using the predicted use amount.

One embodiment provides a storage system capable of enhancing security of access to a storage. According to the embodiment, the storage system includes a nonvolatile memory and a controller. The controller activates first access right to at least a part of a storage area of the nonvolatile memory, i.e., a first storage area, which is given to first user identification information, and sets a first period until the first access right becomes invalid. The controller deactivates the first access right in correspondence with the current time exceeding the first period.

The invention provides a map anti-loss cache and application method and device, a processor and a medium, and belongs to the technical field of machine mapping. The method comprises the following steps: continuously monitoring the area and duration of a map during mapping; after a preset condition is met, the current map is used as a cache to be stored in the nonvolatile memory, and the updating process is cycled; after the equipment is abnormally restarted, the final cache map is read, and the available index of the final cache map is calculated; and determining whether to directly apply map recovery work or reconstruct the map according to the available index. According to the method, the map caching mechanism is introduced, and the decision is adaptively made according to the available index calculated for the cached map after the abnormal restart, so that the cleaning efficiency and the operation safety are improved, and the user experience is also improved.

A memory controller generates Mi codewords each including a parity with a size Ni, divides each of the parities of the Mi codewords into K partial parities, determines K×A codewords from Mi codewords for Mi write information and the K or less partial parities of the K×A codewords, selects partial parities from the K×A codewords, generates Mi write information including the selected partial parities, and allocates continuous addresses of the nonvolatile memory to the K or less partial parities included in each of the Mi write information. A number of write information with sizes of the included partial parities matched becomes larger.

According to one embodiment, a controller of a memory system performs a first operation a plurality of times for each of a plurality of first blocks. The first operation includes a write operation for writing data in a first write mode for writing m-bit data per memory cell and a data erase operation. While a second block is not a defective block, the controller performs a second operation a plurality of times for the second block. The second operation includes a write operation for writing data in a second write mode for writing n-bit data per memory cell and a data erase operation. When the second block is a defective block, the controller selects a first block from the plurality of first blocks, and writes second write data to the selected first block in the second write mode.

To provide an ECU for a vehicle which can be used for a long time.SOLUTION: The processor of the vehicular ECU verifies falsification of the program stored in the normal storage area of the nonvolatile memory, executes the program stored in the normal storage area when the program stored in the normal storage area is not falsified, verifies falsification of the program stored in the backup storage area when the program stored in the normal storage area is falsified, and executes the program stored in the backup storage area when the program stored in the backup storage area is not falsified. The check disk of the normal storage area is operated, and when any defective part is detected in the normal storage area, the defective part is disconnected, and the normal storage area is formatted.SELECTED DRAWING: Figure 7

A vertical nonvolatile memory device includes a stack including gate patterns and interlayer insulation patterns stacked in a stacking direction, the stack having a through-hole extending in the stacking direction in the gate pattern and in the interlayer insulation pattern; a semiconductor pillar in the through-hole and extending in the stacking direction; a data storage structure between the gate pattern and the semiconductor pillar in the through-hole, the data storage structure including a charge storage layer; and a dummy charge storage layer in the through-hole on a sidewall of the interlayer insulation pattern toward the semiconductor pillar.

The invention discloses a method, a device and equipment for collecting in-band and out-of-band logs of a server and a medium, relates to the technical field of computers, and is applied to a server side comprising a substrate management controller, a basic input and output system, an operating system and a serial port data recorder. The output ends of the substrate management controller, the basic input and output system and the operating system are connected with the input end of the serial port data recorder; the method comprises the following steps: starting a basic input / output system, controlling initialization of the basic input / output system and loading of a bootstrap program, and generating a first out-of-band log of the basic input / output system; controlling the operation system to run, and generating an in-band log of the operation system; controlling the baseboard management controller to start, and generating a second out-of-band log of the baseboard management controller; and collecting each out-of-band log and each in-band log by using each preset transmission channel, sending the out-of-band logs and the in-band logs in parallel, and storing the out-of-band logs and the in-band logs in a nonvolatile memory of the serial port data recorder. And full coverage collection of in-band and out-of-band logs of the server is realized.