724 results about "Non-volatile memory" patented technology

According to an embodiment, it is a system comprising, a sensor, a communication module, and a processor, wherein the processor storing instructions in a non-transitory memory that, when executed, cause the processor to scan, via the sensor of a host vehicle at a first frequency to observe surroundings for an erratic behavior, determine an erratic vehicle by analyzing for the erratic behavior, scan via the sensor at a second frequency to determine an identity of the erratic vehicle and analyze a traffic condition around the erratic vehicle, determine a possibility of a collision, alert via the communication module a nearby vehicle by sending a message, and determine an evasive action to avoid the collision.

According to an embodiment, it is a system comprising, a communication module, and a processor; wherein the processor storing instructions in a non-transitory memory that, when executed, cause the processor to receive, a first message by a host vehicle via the communication module from a source, wherein the first message comprises information on an erratic vehicle, wherein the information comprises one or more of a license plate number, a make and model, a color, a first contact zone, a location of the erratic vehicle, and a direction of travel of the erratic vehicle; and transmit a second message, via the communication module, to alert a second vehicle, wherein the second message comprises a part of the first message, a second contact zone, and an evasive action for the second vehicle.

This disclosure provides techniques for managing memory which match per-data metrics to those of other data or to memory destination. In one embodiment, wear data is tracked for at least one tier of nonvolatile memory (e.g., flash memory) and a measure of data persistence (e.g., age, write frequency, etc.) is generated or tracked for each data item. Memory wear management based on these individually-generated or tracked metrics is enhanced by storing or migrating data in a manner where persistent data is stored in relatively worn memory locations (e.g., relatively more-worn flash memory) while temporary data is stored in memory that is less worn or is less susceptible to wear. Other data placement or migration techniques are also disclosed.

The invention discloses a dynamic neutral position and boundary self-calibration method and system of a joystick, and belongs to the technical field of engineering machinery and mining equipment control, and the method comprises the following steps: S1, electrifying equipment, and selecting a mode; s2, calibrating a dead zone; s3, setting a threshold value; s4, data storage; and S5, exiting and applying. According to the dynamic median and boundary self-calibration method and system of the joystick, when the joystick works, a physical manipulated variable is converted into an original electric signal through a joystick sensing unit, then the original electric signal is received through a signal processing module and subjected to signal conditioning, and an analog signal is converted into a digital signal which can be processed by a microprocessor; all logical judgments are executed through the main control unit, a user issues an instruction through a user configuration interface and directly inputs the instruction to the main control unit, the main control unit and the nonvolatile memory carry out bidirectional data interaction to realize permanent storage and calling of dead zone parameters, and the main control unit generates a final control instruction to be output after processing all information. And the actuating mechanism is driven.

The invention provides a multifunctional floating gate transistor based on a two-dimensional material heterojunction and a preparation method thereof, and relates to the technical field of semiconductors, and the multifunctional floating gate transistor comprises a substrate which comprises a back gate and a gate dielectric layer which are stacked from bottom to top; the floating gate layer is located on the surface, away from the back gate, of the gate dielectric layer; the tunneling dielectric layers are located on the surfaces, away from the back gate, of the floating gate layer and the gate dielectric layer respectively, and the floating gate layer is covered with the tunneling dielectric layers; the channel layer is located on the surface, away from the substrate, of the tunneling dielectric layer, and the first orthographic projection of the channel layer on the substrate and the second orthographic projection of the floating gate layer on the substrate are at least partially overlapped; the channel layer is also provided with a source electrode and a drain electrode, and a channel region is formed between the source electrode and the drain electrode. The multifunctional floating gate transistor based on the two-dimensional material heterojunction can be used as a nonvolatile memory and has excellent storage capability.

Disclosed is a binarized neural network circuitry using a quasi-nonvolatile memory device. More particularly, the binarized neural network circuitry according to an embodiment of the present disclosure is characterized in that a diode structure is positioned in a channel region between a drain terminal and a source terminal, a gate terminal is positioned on the diode structure, an operation state is determined by occurrence of a latch-up or latch-down phenomenon due to a positive feedback loop in the channel region based on different voltages applied to the drain terminal and the gate terminal, respectively, and a plurality of quasi-nonvolatile memory devices that implement memory characteristics of remembering a memory state are included as holes or electrons in a potential well in the channel region due to the positive feedback loop are accumulated, and the plural quasi-nonvolatile memory devices are a pair of two quasi-nonvolatile memory devices that operate as a single synaptic cell and are connected in parallel to form an array circuit, memory states of the two quasi-nonvolatile memory devices are determined and stored based on an input line applied from an input line processor connected to the array circuit and a weight update signal applied from a synaptic line processor connected to the array circuit, and a MAC (multiply-accumulate) operation result is output using a combination of the memory states.

According to one embodiment, a controller of the memory system manages a plurality of zones using first information indicating (i) a correspondence between the zones and storage areas of a nonvolatile memory and (ii) a status of each of the zones. The status includes a first status indicating that data is written over an entire logical address range corresponding to a zone and a second status indicating that a zone is reset. In response to receiving a first command from a host device, the controller transmits to the host device a first list including information indicating a zone which is to be garbage collected. The zone is determined based on the first information.

According to an embodiment, it is a system comprising a communication module and a processor, wherein the processor storing instructions in a non-transitory memory that, when executed, cause the processor to determine an identity of an occupant; establish a first connection, by sending a first connection request via the communication module, to a first device;receive a first message from the first device, wherein the first message comprises an occupant profile comprising a vehicle setting; establish a second connection, by sending a second connection request via the communication module, to a second device; and receive a second message from the second device, wherein the second message comprises a limitation setting and a priority level.

The invention relates to the technical field of DRAM (Dynamic Random Access Memory) dynamic repair, in particular to a DRAM dynamic repair method based on unit damage trend identification. The method comprises the following steps: receiving a logic address request sent by a CPU (Central Processing Unit), sending a reading command to a DRAM (Dynamic Random Access Memory), and obtaining return data and ECC (Error Correction Code When a single-bit error is detected, the error is corrected according to ECC verification data, correct data is returned, meanwhile, the damage trend of a surrounding area is pre-judged based on physical correlation of DRAM unit damage, a DRAM address and the surrounding area are marked as isolation addresses, and the data are moved to an SRAM; establishing a repair mapping table in the SRAM, and writing the repair mapping table into the nonvolatile memory through the bus interface; reading the mapping table during cold start of the system, judging whether the address is an isolation address or not according to the mapping table in subsequent access, and if yes, accessing the SRAM to obtain data. According to the invention, a single-bit error is prevented from being evolved into a multi-bit error, and the system reliability is improved.

The invention provides a quick start and security verification method and equipment for an embedded device, a medium and a program product, in the method, firmware is divided into a core start module and a non-core function module in advance, and the core start module and the non-core function module are respectively stored in a high-speed access area and a common storage area of a nonvolatile memory; after the embedded device is powered on, initialization of the key peripheral is completed; when firmware is started or updated for the first time, security verification based on a digital signature is executed on the core starting module, if verification is passed, a mirror image of the core starting module is written into a running cache partition of the nonvolatile memory, and an integrity label is generated; in the subsequent starting process, the mirror image is loaded from the running cache partition, and the integrity label is used for executing rapid verification; after loading of the core starting module is completed, the non-core function module is loaded, and lightweight check is executed. According to the method, the security of the core module is ensured, the performance and security requirements of the non-core module are considered, and the calculation and storage overhead is reduced.

A zonal audio system for a vehicle may include a microcontroller unit (MCU), a non-volatile storage communicatively coupled with the MCU that stores audio files for different types of audio functions, and a digital signal processing (DSP) module communicatively coupled with the MCU. The DSP module may process multiple types of audio functions simultaneously through a layered architecture that consolidates and prioritizes different audio streams including emergency calls, acoustic vehicle alerts, chimes, and infotainment.

The invention discloses a method and a system for improving the control precision of a control lever based on a configurable dead zone, and relates to the field of electronic control and signal processing, and the method comprises the following steps: carrying out median calibration sampling, precisely obtaining an electrical median value, and temporarily storing a calculation result; boundary calibration sampling is carried out, a rocker is pushed to the limit position in sequence, and the maximum value and the minimum value of an original ADC are monitored and updated in real time; calculating and storing calibration parameters, calculating proportionality coefficients and offset key parameters of an X axis and a Y axis by utilizing the temporarily stored median value and boundary value in combination with a target output range, and generating and solidifying mapping parameters; and writing the parameters into FLASH: permanently storing the finally calculated calibration parameters into a nonvolatile memory FLASH. According to the control lever control precision improving method and system based on the configurable dead zone, the output data of the control lever caused by abrasion and aging can be stabilized within the range specified by a standard protocol again without disassembling equipment and special tools, the full-stroke control capability of the control lever is recovered, and control hidden dangers are eliminated.

A system can include a first memory device comprising a plurality of dynamic capacity devices, a second memory device, and a processing device, operatively coupled with the first and second memory devices. The processing device is configured to perform operations including receiving a host command to move first data associated with a first tag to the second memory device, wherein the first tag is associated with a first memory section of the plurality of dynamic capacity devices, and wherein the first memory section is allocated to a first host system to store the first data; responsive to receiving the host command to move, determining a second memory section of the second memory device, wherein the second memory section is associated with a namespace of the second memory device; and storing the first data in the second memory section associated with the namespace.

The invention relates to the technical field of system security, and discloses a firmware package generation method, a secure starting method, a verification method, a device and a medium, the starting method is suitable for a vehicle-mounted SoC system without OTP / eFuse and with a BootROM unmodifiable, and complementary building of a trusted root is achieved in a software mode. In response to the starting instruction, the BootROM loads a security bootstrap program; during first deployment, a secure storage area is created in a nonvolatile memory, and an initial root public key and an abstract thereof are written in to complete initialization of a trust chain. In the subsequent starting process, after the security bootstrap program verifies the integrity of the root public key, the mirror image public key, the abstract and the signature of the mirror image to be started are verified, and it is ensured that the source is legal and the data is complete. On-line updating of a root public key through a chain signature mechanism is supported, that is, a current effective root private key is used for carrying out abstract signature on a new public key, and the new public key can be replaced after the signature verification of an old public key is passed, so that key rotation and trust anchor migration without hardware modification are realized.

Some embodiments construct a set of build dependencies for a program without a full set of build instructions. The build dependency set is constructed without piggy-backing on a build process that would produce an executable version of the program. Representations of the program's structure, such as expression types, call targets, symbol tables, abstract syntax trees, and other internal compiler data structures, are emitted to persistent non-volatile storage instead of being used only as intermediate steps for executable code generation. Security analysis can then utilize the program representations. Licensing analysis can also utilize the dependency set to identify program components and their storage locations.

Method (100) for operating a field device (1) comprising an adjustable clock (2), at least one non-volatile CA memory (3) containing a public key certificate (3a) of a trusted certification authority, CA, at least one non-volatile time memory (4) for recording a date and / or time (4a) and at least one interface (5), comprising the steps: • A current date and / or time (7a) is received via the interface (5) (170); • this current date or time (7a) is compared with the date or time (4a) in the time memory (4) (180); and • In response to the fact that the current date or time (7a) is later (190) than the date or time (4a) in the time memory (4), the adjustable clock (2) of the field device (1) is set to the current date or time (7a) (200).

According to an embodiment, a memory system includes: a nonvolatile memory including a plurality of blocks; and a memory controller. The memory controller is configured to: make a comparison between a first erase voltage application accumulated time period and a first erase verify permission time period each corresponding to a first block targeted for erasure; cause the nonvolatile memory to execute a erase voltage application operation in a case where the first erase voltage application accumulated time period is less than the first erase verify permission time period; and cause the nonvolatile memory to execute a erase verify operation in a case where the first erase voltage application accumulated time period is equal to or greater than the first erase verify permission time period.

According to one embodiment, a memory system includes a nonvolatile memory, and a memory controller including first and second caches and a first controller. The first cache includes a first memory unit and a first control unit. The second cache includes a second memory unit and a second control unit. The first memory unit includes a plurality of entries each having a cache tag including a first field and a cache line. Upon receiving a first prefetch request for first data of a first logical address, the first control unit stores the first data in the cache line of a first entry included in the first memory unit, and stores a first value in the first field of the first entry. The first control unit maintains the first entry until receiving a read request or a write request for the first logical address from the host.

According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller manages first account information to be used for authentication of a first account and second account information to be used for authentication of a second account. The controller receives third account information from a host device. When the third account information matches the first account information, the controller permits access to at least a partial storage area of the nonvolatile memory based on a request from the host device and transmits first data that includes the second account information to a first memory system.

An apparatus includes control circuits configured to connect to a plurality of nonvolatile memory cells. The one or more control circuits are configured to apply read voltages on a plurality of word lines connected to the nonvolatile memory cells, ramp down from the read voltages to subsequent voltages such that voltage on a word line transitions through a voltage that is below a subsequent voltage by a negative kick voltage. The one or more control circuits are further configured to apply a first negative kick voltage to ramp down from a read voltage on a first word line and apply a second negative kick voltage to ramp down from the read voltage on a second word line.

A memory system that can effectively use resources includes a nonvolatile memory that includes a plurality of physical blocks and a controller. The controller manages a plurality of superblocks that each include one or more physical blocks among the plurality of physical blocks, and notifies a host of a maximum size among data sizes writable in each of the superblocks, as a first size that is a size of a reclaim unit. Upon receipt of one or more write commands from the host, the one or more write commands designating a first reclaim unit having the first size, the controller writes a first data portion of the first reclaim unit into the first superblock to fill the entire first superblock and then a second data portion of the first reclaim unit into the second superblock.

A processing system includes one or more memories and one or more processors coupled to the one or more memories. The processing system is configured to obtain first data associated with a vehicle and to obtain second data associated with the vehicle. The first data is associated with a first priority level, and the second data is associated with a second priority level. The processing system is further configured to store the first data to a nonvolatile memory of the vehicle in accordance with detection of a data migration trigger event and further in accordance with a prioritization scheme that prioritizes the first data over the second data upon occurrence of the data migration trigger event.

Various implementations disclosed herein include devices, systems, and methods for capturing a new media content item. In various implementations, a device includes a display, one or more processors and a non-transitory memory. In some implementations, a method includes determining a plot template for generating a media content item based on other media content items that are distributed temporally. In some implementations, the plot template is defined by a set of one or more conditional triggers for capturing the other media content items. In some implementations, the method includes determining that a condition associated with a first conditional trigger of the set of one or more conditional triggers is satisfied. In some implementations, the method includes in response to the condition associated with the first conditional trigger being satisfied, displaying, on the display, a notification to capture a new media content item for populating the plot template.

An electronic device comprising a rechargeable battery and a circuit and a method for monitoring the charge level of the battery is provided. An example device comprises: a rechargeable battery; a first circuit comprising a processor, and a voltage comparator configured to compare the voltage of the rechargeable battery with a limiting voltage; and a second circuit, coupled to the first circuit, comprising a memory of non-volatile type and configured to initialize the processor of the first circuit if the voltage of the rechargeable battery is higher than the limiting voltage.

A method of operating a nonvolatile memory device is provided. The method includes: performing a program operation on a selected word-line of a plurality of cell strings during a program execution period of a program loop by applying a program voltage to the selected word-line; and performing a program verification operation during a program verification period of the program loop by applying a program verification voltage to the selected word-line and by applying a first verification pass voltage to a first zone of unselected word-lines among and a second verification pass voltage to a second zone of the unselected word-lines. A voltage level of the second verification pass voltage is lower than a voltage level of the first verification pass voltage.

A memory controller configured to write, read, and erase data for a nonvolatile memory device storing first meta data and first journal data indicating first changes of the first meta data, the memory controller comprising: a buffer memory circuit including a buffer memory and a buffer controller, wherein the buffer memory stores second meta data and second journal data indicating second changes of the second meta data, and wherein the buffer controller controls the buffer memory; and an accelerator managing the first meta data, the second meta data, the first journal data, and the second journal data, wherein the buffer controller includes: a first error correction code (a first ECC) engine configured to correct a first error of first data that includes the second meta data; and a second error correction code (a second ECC) engine configured to correct a second error of second data including the second journal data.

The invention discloses a portable wireless radio frequency switching method and system, a medium and a program product, and relates to the field of transmission, in the method, a switching device obtains a radio frequency signal strength value of a device to be switched; the switching device sends an awakening instruction and a handshake request to a to-be-switched device which is in a deep sleep state and keeps low-power-consumption monitoring; executing the handshake request to establish a secure communication connection; the switching device sends the encrypted radio frequency configuration data to a device to be switched, and the device to be switched writes the encrypted radio frequency configuration data into a nonvolatile memory; after the equipment to be switched completes writing of the encrypted radio frequency configuration data, a confirmation signal is sent to the switching equipment, the deep sleep state is automatically switched to, and low-power-consumption monitoring is kept. On the basis of keeping certain power to monitor the configuration request, low-power-consumption standby is realized, so that energy waste is reduced, and the use cost of equipment is reduced.

The invention discloses an SOT-MRAM differential storage unit and a working method thereof, and belongs to the field of nonvolatile memories. The SOT-MTJ unit comprises an SOT-MTJ unit, a bidirectional selector, a transistor, a diode, a source line, a word line and two complementary bit lines, each SOT-MTJ unit is provided with a magnetic tunnel junction (MTJ) structure and a spin-orbit torque (SOT) layer; the two spin-orbit torque SOT layers are connected through the bidirectional selector, the other end of one spin-orbit torque SOT layer is connected with a first port of the transistor, a second port of the transistor is connected with one bit line, a third port of the transistor is connected with the word line, and the other end of the other spin-orbit torque SOT layer is connected with the other bit line; the tops of the two MTJ structures are connected and then connected with the anode of the diode, and the cathode of the diode is connected with the source line. The present invention is applicable to high-reliability storage and cache applications.

An example nonvolatile memory device includes page buffer circuits, compression engines, local clock controllers, a data input / output (I / O) circuit, and a control circuit. Each compression engines is connected with a respective page buffer circuit through respective local data lines. The control circuit controls each compression engine to perform an encoding operation based on receiving soft decision data from target cache latches corresponding to an output address, based on compressing the received soft decision data, and based on overwriting the compressed soft decision data in the target cache latches based on an input address, The control circuit controls one or more page buffer circuits among the plurality of page buffer circuits to perform an output operation based on outputting the compressed soft decision data through the data I / O circuit, the output operation performed in parallel with the encoding operation or independently from the encoding operation.