1244 results about "Non-volatile memory" patented technology

According to an embodiment, it is a system comprising, a sensor, a communication module, and a processor, wherein the processor storing instructions in a non-transitory memory that, when executed, cause the processor to scan, via the sensor of a host vehicle at a first frequency to observe surroundings for an erratic behavior, determine an erratic vehicle by analyzing for the erratic behavior, scan via the sensor at a second frequency to determine an identity of the erratic vehicle and analyze a traffic condition around the erratic vehicle, determine a possibility of a collision, alert via the communication module a nearby vehicle by sending a message, and determine an evasive action to avoid the collision.

In at least one embodiment, processing can include: receiving write operations; persistently recording, in a write cache or log, the write operations using page descriptors (PDESCs) of a PDESC pool and page buffers (PBs) of a PB pool; selecting, in accordance with criteria, write data pages stored in the PB pool for demotion to a physical large block (PLB) pool included in backend non-volatile storage, wherein each write data page selected denotes content written by a corresponding one of the write operations; responsive to the selecting, persistently storing the write data pages of the PB pool in the PLB pool; and updating PDESCs associated with the write data pages to reference corresponding storage locations in the PLB pool rather than in the PB pool.

According to an embodiment, it is a system comprising, a communication module, and a processor; wherein the processor storing instructions in a non-transitory memory that, when executed, cause the processor to receive, a first message by a host vehicle via the communication module from a source, wherein the first message comprises information on an erratic vehicle, wherein the information comprises one or more of a license plate number, a make and model, a color, a first contact zone, a location of the erratic vehicle, and a direction of travel of the erratic vehicle; and transmit a second message, via the communication module, to alert a second vehicle, wherein the second message comprises a part of the first message, a second contact zone, and an evasive action for the second vehicle.

This disclosure provides techniques for managing memory which match per-data metrics to those of other data or to memory destination. In one embodiment, wear data is tracked for at least one tier of nonvolatile memory (e.g., flash memory) and a measure of data persistence (e.g., age, write frequency, etc.) is generated or tracked for each data item. Memory wear management based on these individually-generated or tracked metrics is enhanced by storing or migrating data in a manner where persistent data is stored in relatively worn memory locations (e.g., relatively more-worn flash memory) while temporary data is stored in memory that is less worn or is less susceptible to wear. Other data placement or migration techniques are also disclosed.

The invention discloses a dynamic neutral position and boundary self-calibration method and system of a joystick, and belongs to the technical field of engineering machinery and mining equipment control, and the method comprises the following steps: S1, electrifying equipment, and selecting a mode; s2, calibrating a dead zone; s3, setting a threshold value; s4, data storage; and S5, exiting and applying. According to the dynamic median and boundary self-calibration method and system of the joystick, when the joystick works, a physical manipulated variable is converted into an original electric signal through a joystick sensing unit, then the original electric signal is received through a signal processing module and subjected to signal conditioning, and an analog signal is converted into a digital signal which can be processed by a microprocessor; all logical judgments are executed through the main control unit, a user issues an instruction through a user configuration interface and directly inputs the instruction to the main control unit, the main control unit and the nonvolatile memory carry out bidirectional data interaction to realize permanent storage and calling of dead zone parameters, and the main control unit generates a final control instruction to be output after processing all information. And the actuating mechanism is driven.

The invention discloses an artificial intelligence acceleration system based on vertical integration of a nonvolatile memory and a logic chip, and belongs to the field of chip integration, one layer or multiple layers of nonvolatile memory chips are vertically integrated on the logic chip, and the multiple layers of nonvolatile memory chips are vertically integrated through bumps, micro bumps or a hybrid bonding process. The multi-layer nonvolatile storage chip is used for storing model data, and the physical distance between the position where the model data is stored and the position where the model data is used in the logic chip is as short as possible. The error correction code (ECC) function in the invention can be put on the NVM and also can be put on the logic chip; when the ECC is placed on the NVM chip, the transmission path is long, and when the ECC is placed on the logic chip, the delay is shorter, and the bandwidth is higher.

The invention discloses a server security management method and device, equipment and a medium, and belongs to the technical field of servers, and the method comprises the steps: generating a key pair through a key generation platform; storing a public key of the key pair to a nonvolatile memory of the substrate management controller; obtaining customer product feature information, and generating a target license file according to the customer product feature information and the private key; performing signature verification on the target license file according to a public key of the key pair and a hash algorithm; obtaining product feature information of the target license file, and performing matching verification on the product feature information of the target license file; and in response to that all the product feature information of the target license file is matched successfully, security verification of the target license file is successful. According to the method, the BMC chip of the server is used for carrying out security management on the license file, additional hardware does not need to be added, and the security management cost of the server is reduced.

The invention provides a multifunctional floating gate transistor based on a two-dimensional material heterojunction and a preparation method thereof, and relates to the technical field of semiconductors, and the multifunctional floating gate transistor comprises a substrate which comprises a back gate and a gate dielectric layer which are stacked from bottom to top; the floating gate layer is located on the surface, away from the back gate, of the gate dielectric layer; the tunneling dielectric layers are located on the surfaces, away from the back gate, of the floating gate layer and the gate dielectric layer respectively, and the floating gate layer is covered with the tunneling dielectric layers; the channel layer is located on the surface, away from the substrate, of the tunneling dielectric layer, and the first orthographic projection of the channel layer on the substrate and the second orthographic projection of the floating gate layer on the substrate are at least partially overlapped; the channel layer is also provided with a source electrode and a drain electrode, and a channel region is formed between the source electrode and the drain electrode. The multifunctional floating gate transistor based on the two-dimensional material heterojunction can be used as a nonvolatile memory and has excellent storage capability.

The invention provides a data writing method and a memory controller, which are suitable for a rewritable nonvolatile memory module with a plurality of memory units. The method comprises the following steps: acquiring original data from a host system; executing a plurality of randomization operations on the original data to obtain a plurality of write-in data; based on a plurality of directions of a three-dimensional circuit architecture of the rewritable nonvolatile memory module, executing randomization verification operation on each piece of write-in data to verify the data uniformity of each piece of write-in data in each direction so as to obtain target write-in data in the plurality of pieces of write-in data, wherein the randomized quality of the target write data is determined to be qualified; and storing the target write data to a plurality of target memory cells among the plurality of memory cells. Through multiple randomization operations and verification processes, the randomness and reliability of data storage are effectively improved, so that the overall performance and data security of a storage system are enhanced.

The embodiment of the invention discloses a test control method and device of a memory, a chip, equipment and a storage medium, the method is applied to a system control processor SCP, and the method comprises the following steps: responding to a starting operation of a system on chip of the chip, and starting the SCP; after a second-level boot loader of the SCP is executed, if it is detected that the power-on state register information is power-on starting information, whether memory self-test MBIST needs to be carried out in current starting or not is determined on the basis of test running field information in the nonvolatile memory; if MBIST needs to be carried out on the current starting, locking configuration of the test clock frequency is carried out on the phase-locked loop, and when locking succeeds, based on configured test link information, the MBIST device is controlled to carry out self-test on a target memory of the chip. Through the technical scheme of the embodiment of the invention, the memory test in the chip can be effectively controlled, so that the test resources are saved, and the memory test flexibility is improved.

The invention provides a firmware set updating method, which is executed in a BMS (Baseboard Management Controller), and comprises the following steps: acquiring a firmware set and storing the firmware set in a nonvolatile memory, the firmware set comprising more than one firmware, and each firmware comprising more than one version; identifying the firmware type and the firmware version of each firmware in the firmware set; according to a preset firmware adaptation table and the firmware type and the firmware version of each firmware in the firmware set, generating a recommended update combination formed by each firmware in the firmware set; and according to a user instruction, reading the firmware selected by the user from the nonvolatile memory for automatic updating or reading the firmware corresponding to the recommended updating combination from the nonvolatile memory for automatic updating. According to the firmware set updating method provided by the invention, the recommended updating combination in the firmware set can be automatically identified and the firmware updating process can be automatically executed, so that the operation and maintenance cost can be saved.

Disclosed is a binarized neural network circuitry using a quasi-nonvolatile memory device. More particularly, the binarized neural network circuitry according to an embodiment of the present disclosure is characterized in that a diode structure is positioned in a channel region between a drain terminal and a source terminal, a gate terminal is positioned on the diode structure, an operation state is determined by occurrence of a latch-up or latch-down phenomenon due to a positive feedback loop in the channel region based on different voltages applied to the drain terminal and the gate terminal, respectively, and a plurality of quasi-nonvolatile memory devices that implement memory characteristics of remembering a memory state are included as holes or electrons in a potential well in the channel region due to the positive feedback loop are accumulated, and the plural quasi-nonvolatile memory devices are a pair of two quasi-nonvolatile memory devices that operate as a single synaptic cell and are connected in parallel to form an array circuit, memory states of the two quasi-nonvolatile memory devices are determined and stored based on an input line applied from an input line processor connected to the array circuit and a weight update signal applied from a synaptic line processor connected to the array circuit, and a MAC (multiply-accumulate) operation result is output using a combination of the memory states.

According to one embodiment, a controller of the memory system manages a plurality of zones using first information indicating (i) a correspondence between the zones and storage areas of a nonvolatile memory and (ii) a status of each of the zones. The status includes a first status indicating that data is written over an entire logical address range corresponding to a zone and a second status indicating that a zone is reset. In response to receiving a first command from a host device, the controller transmits to the host device a first list including information indicating a zone which is to be garbage collected. The zone is determined based on the first information.

The invention provides a memory management method and a memory controller. The method comprises the following steps: acquiring block use conditions of a plurality of physical blocks of a rewritable nonvolatile memory module and a working state of storage equipment; when the working state is a busy state, whether garbage collection operation is executed or not is judged according to the block use condition and the host write-in requirement; and dynamically adjusting the write-in speed of the write-in operation of the host according to the number of the plurality of residual blocks when executing the garbage collection operation during the write-in operation of the host. According to the method, the use condition of the physical block and the write-in behavior of the host are monitored in real time, and a dynamic write-in speed adjusting mechanism is combined, so that the execution efficiency of garbage collection operation is obviously improved, and the write-in performance of the storage equipment under the high-load condition is effectively improved.

A data storage apparatus includes a nonvolatile memory device including a dump region configured to temporarily store data according to a state of applied power; and a controller configured to monitor health information of the dump region of the nonvolatile memory device, generate environmental information corresponding to a power loss protection (PLP) operation based on the health information, and share the environmental information with an external device.

The invention provides a power failure keeping method and system for a control system. The method comprises the steps that the power supply state of the control system is monitored, and when the voltage of a power supply of the control system is lower than a preset voltage threshold value, a power failure event signal is generated; in response to the power failure event signal, switching a power supply of the control system into a power failure protection circuit, and temporarily supplying power to the control system by using a super capacitor in the power failure protection circuit; and in the power-down protection time of the temporary power supply, storing the power-down retention data and the running log file of the control system into the nonvolatile memory. According to the invention, the storage capacity of the power-down holding data is improved, the cost of power-down holding is reduced, and the manufacturing requirements of a control system can be greatly met.

A computing system is provided, including non-volatile storage storing a reactive database including a plurality of database entities. The computing system may further include a processor configured to, via a reactive database application program interface (API), receive a first standing query registration input including a first standing query. The first standing query may include a first update condition and may be associated with a first database entity. The processor may be further configured to store the first standing query in the non-volatile storage. The processor may be further configured to write data to the reactive database and determine that the first update condition is satisfied by the written data. In response to determining that the first update condition is satisfied, the processor may be further configured to execute the first standing query to perform a first state change at the first database entity of the plurality of database entities.

The invention relates to the field of nonvolatile memories, in particular to an SOT-MRAM circuit unit based on a 2T2M differential structure and a storage array circuit of the SOT-MRAM circuit unit. The SOT-MRAM unit comprises a first magnetic tunnel junction, a second magnetic tunnel junction, a first field effect transistor, a second field effect transistor, a first phase inverter, a second phase inverter, a write line, a read line, an input line and an output line which have a specific connection relation. According to the SOT-MRAM circuit unit, through the special 2T2M differential structure design and in combination with the excellent performance of a spin-orbit moment magnetic tunnel junction, the storage and operation performance and efficiency of a 2T2MSOT-MRAM differential circuit unit array are integrally improved, the dependence on the performance of the MTJ is reduced, the SOT-MRAM circuit unit has the better energy efficiency ratio and the more stable read-write speed and precision, and the SOT-MRAM circuit unit has the advantages of being simple in structure, low in cost and high in reliability. And the reliability and the stability are excellent.

The invention discloses a single event upset reinforced magnetic random access memory reading circuit, and belongs to the field of nonvolatile memories. Interlocked transistors are added on the basis of a traditional 6T reading circuit, meanwhile, a PMOS tube and an NMOS tube are introduced, and errors caused by the single event upset effect can be effectively corrected. The method has the following advantages that single event effect sensitive nodes are considered, zero upset nodes do not exist in the reinforcement method, meanwhile, 1 upset can be rapidly corrected, the single event upset resistance is higher, and the method can be used for reliable storage of data in the space radiation environment.

The invention provides a data writing method and a memory controller, which are suitable for a rewritable nonvolatile memory module with a plurality of memory units. The method comprises the following steps: firstly, obtaining original data from a host system; then, a plurality of randomization operations are performed on the original data to obtain a plurality of write-in data. Next, a first randomization verification operation is performed on each write data, by which target write data among the plurality of write data is acquired, where the randomization quality of the target write data is determined to be qualified. Finally, the target write data is stored in a plurality of target memory cells of the plurality of memory cells. Through multiple randomization operations and verification processes, the randomness and reliability of data storage are effectively improved, so that the overall performance and data security of a storage system are enhanced.

The invention provides USB (Universal Serial Bus) extension safety real-time bus network card equipment and a terminal networking method, which are applied to the technical field of network data safety. The network card device comprises a USB interface, a nonvolatile memory, a device ID comparison module, a fingerprint authentication module and an SRB bus module. According to the invention, the secure data transmission of the sensitive equipment is ensured by storing and comparing the equipment ID, identifying the equipment type and using fingerprint authentication, and the sensitive data can be selectively transmitted on the secure real-time bus channel according to the data sensitivity, so that the usability of the network card equipment is improved while the data security is ensured.

According to an embodiment, it is a system comprising a communication module and a processor, wherein the processor storing instructions in a non-transitory memory that, when executed, cause the processor to determine an identity of an occupant; establish a first connection, by sending a first connection request via the communication module, to a first device;receive a first message from the first device, wherein the first message comprises an occupant profile comprising a vehicle setting; establish a second connection, by sending a second connection request via the communication module, to a second device; and receive a second message from the second device, wherein the second message comprises a limitation setting and a priority level.

In some examples, a security processor detects a potential attack in a system. In response to detecting the potential attack in the system, the security processor issues a command block indication to block processing of commands to access a nonvolatile memory. The security processor determines, based on monitored information, a likelihood of the potential attack being a real attack, and in response to the determined likelihood, triggers an erase of the nonvolatile memory.

The invention discloses an Internet of Things gas meter abnormal data real-time storage and intelligent alarm method and device, and relates to the technical field of gas safety monitoring and intelligent alarm. According to the main technical scheme, real-time state data corresponding to a target gas meter are collected, wherein the real-time state data comprise a real-time flow value, a real-time temperature value and a real-time pressure value; based on the instant state data, whether the target gas meter meets an abnormal alarm condition or not is judged, the abnormal alarm condition is used for representing that at least one of an instant flow value, an instant temperature value and an instant pressure value exceeds respective target threshold values, and the target threshold values are dynamic self-adaptive threshold values for conducting geographical environment-seasonal coupling compensation on the target gas meter; and if yes, storing the instant state data as abnormal data in real time to a nonvolatile memory and uploading the abnormal data to a cloud, and executing corresponding intelligent alarm operation according to the abnormal alarm level. The invention aims to improve the accuracy of abnormal alarm so as to ensure that related abnormal data is instantly stored and uploaded to the cloud.

The invention relates to the technical field of DRAM (Dynamic Random Access Memory) dynamic repair, in particular to a DRAM dynamic repair method based on unit damage trend identification. The method comprises the following steps: receiving a logic address request sent by a CPU (Central Processing Unit), sending a reading command to a DRAM (Dynamic Random Access Memory), and obtaining return data and ECC (Error Correction Code When a single-bit error is detected, the error is corrected according to ECC verification data, correct data is returned, meanwhile, the damage trend of a surrounding area is pre-judged based on physical correlation of DRAM unit damage, a DRAM address and the surrounding area are marked as isolation addresses, and the data are moved to an SRAM; establishing a repair mapping table in the SRAM, and writing the repair mapping table into the nonvolatile memory through the bus interface; reading the mapping table during cold start of the system, judging whether the address is an isolation address or not according to the mapping table in subsequent access, and if yes, accessing the SRAM to obtain data. According to the invention, a single-bit error is prevented from being evolved into a multi-bit error, and the system reliability is improved.

A data transfer circuit in a nonvolatile memory device includes first repeaters, second repeaters and signal lines. The signal lines connect the first repeaters and the second repeaters, and include a first group of signal lines and a second group of signal lines alternatingly arranged. The first repeaters include a first group of repeaters activated in a first operation mode and a second group of repeaters activated in a second operation mode. The second repeaters include a third group of repeaters activated in the first operation mode and are connected to the first group of repeaters through the first group of signal lines floated in the second operation mode, and a fourth group of repeaters activated in the second operation mode and are connected to the second group of repeaters through the second group of signal lines floated in the first operation mode.

An example brake monitoring system for bicycles comprises at least one force sensing element (FSE) for detecting brake pressure. The FSE may be attached to either a brake lever or a brake pad. A component connects to the FSE and reads force data, and includes a custom PCB, a connector, a battery connector, and resistors for logging and storing brake pressure data in non-volatile storage, or relaying it to a remote system using wireless or wired communication. The system also includes a display device to receive and display brake pressure data. The FSE for brake levers, FSE for brake pads, components, and display devices work together to monitor and display brake pressure data. This system has numerous applications in cycling, including training, safety research, bike design improvement, event organization, bike rental monitoring, and city planning.

The invention provides a quick start and security verification method and equipment for an embedded device, a medium and a program product, in the method, firmware is divided into a core start module and a non-core function module in advance, and the core start module and the non-core function module are respectively stored in a high-speed access area and a common storage area of a nonvolatile memory; after the embedded device is powered on, initialization of the key peripheral is completed; when firmware is started or updated for the first time, security verification based on a digital signature is executed on the core starting module, if verification is passed, a mirror image of the core starting module is written into a running cache partition of the nonvolatile memory, and an integrity label is generated; in the subsequent starting process, the mirror image is loaded from the running cache partition, and the integrity label is used for executing rapid verification; after loading of the core starting module is completed, the non-core function module is loaded, and lightweight check is executed. According to the method, the security of the core module is ensured, the performance and security requirements of the non-core module are considered, and the calculation and storage overhead is reduced.