76 results about "Vertical channel" patented technology

A three-dimensional semiconductor memory device may include a stack including gate electrodes and insulating layers, which are alternatingly stacked on a substrate, vertical channel structures penetrating the stack, and data storage patterns between the stack and the vertical channel structures. The data storage patterns may be spaced apart from each other in a direction perpendicular to a top surface of the substrate, and each of the data storage patterns may include a ferroelectric pattern, an anti-ferroelectric pattern, and a first insulating pattern.

The invention belongs to the technical field of gravity energy storage, and particularly relates to a high-channel-utilization-rate gravity energy storage system based on vertical circulation operation, which comprises at least one energy conversion shaft, at least one empty return shaft, a top shaft transfer section and a bottom shaft transfer section, the top hoistway transfer section is communicated with the upper part of the energy conversion hoistway or the empty return hoistway through reciprocating translational motion, and the bottom hoistway transfer section is communicated with the lower part of the energy conversion hoistway or the empty return hoistway through reciprocating translational motion; racks are arranged on the inner walls of the hoistways, gears are arranged on the elevator, and the racks and the gears are meshed to achieve movement of the elevator in the circulating hoistways. Compared with an existing steel wire rope or chain annular conveying chain scheme, the conveying load is transferred to different heights of the vertical channel well wall in a distributed mode, the bottom and top horizontal transverse moving mechanism and the vertical load are transferred to a horizontal wheel rail, the conveying capacity is higher, the service life is longer and more reliable compared with a traditional circulating conveying chain cable, and the later operation and maintenance cost is reduced.

A plurality of supporting layers are arranged on a supporting assembly in a sole buffering supporting structure in the vertical direction, an arrangement direction and a channel direction which are perpendicular to each other are defined for each supporting layer, and each supporting layer is provided with a plurality of supporting channels which are sequentially arranged in the arrangement direction. The supporting channels located in the same supporting layer extend in the channel direction. The adjacent supporting layers are communicated with each other, the corresponding arrangement directions of the supporting layers are perpendicular to each other, and the channel directions are also perpendicular to each other; a protruding supporting platform is formed in the middle of the top of the supporting assembly through a supporting layer, and a cushioning table top lower than the supporting platform is formed on the peripheral side of the supporting platform. The outer wall covers the periphery of the supporting assembly so as to seal the supporting assembly to form a closed air cavity. The sole buffering and supporting structure can provide a better buffering effect and improve the wearing comfort.

Disclosed are a semiconductor device, a manufacturing method therefor, and an electronic equipment, the semiconductor device includes: at least one vertical channel transistor disposed on a base substrate, and a bit line; the transistor includes a semiconductor pillar extending along a direction perpendicular to the base substrate, the semiconductor pillar includes a channel region, and a first region and a second region respectively disposed on two sides of the channel region, the second region is disposed between the base substrate and the first region, the bit line is in contact with the second region, and a plasma dopant concentration of a contact surface between the second region and the bit line is greater than or equal to 1e14 atoms / square centimeter.

The invention relates to a deep foundation pit assembly type ladder cage system which comprises a deep foundation pit, an inner supporting beam, a supporting piece and an assembly type ladder cage. A plurality of layers of inner supporting beams are arranged and fixed to the inner wall of the deep foundation pit, the supporting pieces are fixedly installed on the multiple inner supporting beams on the same layer, and the assembly type ladder cage located on the inner supporting beams is fixedly connected with the supporting pieces. A plurality of assembly type ladder cages are fixedly spliced between the upper and lower adjacent layers of inner supporting beams; a plurality of assembled ladder cages are also fixedly spliced between the bottom surface of the deep foundation pit and the lowermost inner supporting beam; the assembly type ladder cage system is erected while being excavated in the excavation process of the deep foundation pit, and all the assembly type ladder cages form a vertical channel after being erected. The invention further relates to a construction method of the deep foundation pit fabricated ladder cage system, the fabricated ladder cage serves as a vertical channel, an auxiliary installation tool does not need to be erected, erecting in the deep foundation pit excavation process is achieved, the installation speed is increased, and the construction method belongs to the technical field of deep foundation pit construction.

The invention provides a multichannel SIW filtering jumper and a communication device, and belongs to the technical field of filtering jumpers. The multichannel SIW filtering jumper comprises m * n SIW rectangular dual-mode resonant cavities which are arranged in m rows and n columns and work in a TE102 and TE201 orthogonal degenerate mode, m > 0, and n > 0; each row of SIW rectangular dual-mode resonant cavities corresponds to a horizontal channel, each column of SIW rectangular dual-mode resonant cavities corresponds to a vertical channel, two adjacent SIW rectangular dual-mode resonant cavities are coupled through a common wall, and a coupling window is located in a weakest electric field area of any one of the SIW rectangular dual-mode resonant cavities. According to the multichannel SIW filtering jumper, the number of channels and the working center frequency, the working bandwidth, the working order and the transmission zero point of each channel can be independently set.

A semiconductor device includes: a mold insulating pattern positioned on a substrate; an upper conductive line extending in a first horizontal direction on the substrate; a channel structure including a vertical channel portion that faces a side surface of the upper conductive line, and is in contact with a first side wall of the mold insulating pattern, wherein the vertical channel portion extends in a vertical direction; a first gate dielectric layer at least partially surround a surface of the channel structure; and a second gate dielectric layer positioned between the upper conductive line and the first gate dielectric layer on the channel structure, wherein the mold insulating pattern includes a body and protrusion, wherein the body extends in the first horizontal direction, and the protrusion protrude in a second horizontal direction that intersects with the first horizontal direction.

The disclosure provides a kind of high viscosity microdroplet generation device and method based on three-dimensional microchannel structure, which is T-shaped, including first straight channel, vertical channel, second straight channel and third straight channel in turn;A group of boss structures are symmetrically provided inside the second straight channel near the two sides of the inner wall of the main channel, and the outer end face of the microtube can abut with the outer end face of the boss structure after extending into the vertical channel, so that high viscosity microdroplet generation channel is formed between the two boss structures;The connecting part of high viscosity microdroplet generation channel and third straight channel also forms a tapered channel, and high viscosity microdroplets are stably output from the third straight channel through the tapered channel;The present application designs a new tip mode, realizes the high monodispersity and uniformity of high viscosity microdroplets, size controllable, improves the stability of high viscosity microdroplet generation, and can be repeatedly used based on the detachable design of three-dimensional microchannel structure, which expands the application range of the technology.

The present disclosure is directed to semiconductor packages incorporating composite or hybrid bridges that include first and second interconnect bridges positioned on a substrate and a power corridor with a plurality of vertical channels positioned on the substrate between the first and second interconnect bridges, wherein the power corridor integrally joins the first interconnect bridge to the second interconnect bridge.

Semiconductor device (200), comprising: a first plurality of GAA devices (250), gate-all-around devices, in a first device surface (10), each of the first plurality of GAA devices (250) comprising: a first vertical stack of channel elements (239-1) extending along a first direction, and a first plurality of inner spacers (230) which are nested with the first vertical stack of channel elements (239-1), a first gate structure (224A, 244B) above and around the first vertical stack of channel elements (239-1); and a second plurality of GAA devices (260) in a second device surface (20), each of the second plurality of GAA devices (260) comprising: a second vertical stack of channel elements (239-2) extending along a second direction, and a second plurality of inner spacers (230) which are nested with the second vertical stack of channel elements (239-2), a second gate structure (224C, 244D) above and around the second vertical stack of channel elements (239-2), wherein each of the first plurality of GAA devices (250) has a first channel length, wherein each of the second set of GAA devices (260) has a second channel length that is smaller than the first channel length, wherein the first plurality of inner spacers (230) and the second plurality of inner spacers (230) extend inwards to substantially the same extent; where each of the first gate structures (224A, 244B) has: a first upper gate feature (244A) arranged above a topmost channel element (239) of the first vertical stack of channel elements (239-1), and a plurality of first lower gate features (244B) arranged between two adjacent channel elements (239) of the first vertical stack of channel elements (239-1), where each of the second gate structures (224C, 244D) has: a second upper gate feature (244C) arranged above a topmost channel element (239) of the second vertical stack of channel elements (239-2), and a plurality of second lower gate features (244D) arranged between two adjacent channel elements (239) of the second vertical stack of channel elements (239-2), wherein the first upper gate feature (244A) has a first length (L1) along the first direction, wherein the second upper gate feature (244C) has a second length (L3) along the second direction, where the first length (L1) and the second length (L3) are essentially identical.

A semiconductor device includes: a first stacked structure including a first lower dielectric layer, a first horizontal gate structure, and a first upper dielectric layer stacked vertically; a second stacked structure including a second lower dielectric layer, a second horizontal gate structure, and a second upper dielectric layer stacked vertically, and having a first side facing a first side of the first stacked structure; a first channel layer formed on the first side of the first stacked structure; a second channel layer formed on the first side of the second stacked structure; a lower electrode layer commonly coupled to lower ends of the first and second channel layers between the first and second stacked structures; a first upper electrode layer coupled to an upper end of the first channel layer; and a second upper electrode layer coupled to an upper end of the second channel layer.

A retention substrate includes: a plate-shaped member having a first surface and a second surface and containing a ceramic material as a main component, the first surface for retaining an object, the second surface disposed opposite to the first surface; a gas channel formed in the plate-shaped member; and a gas-permeable porous body filling part of the gas channel and containing a ceramic material as a main component. The gas channel including a vertical channel section and a horizontal channel section. The vertical channel section having a gas outlet opening in the first surface and extending from the gas outlet toward the second surface. The horizontal channel section connected to the vertical channel section and extending parallel to the first surface. The porous body filling the vertical channel section and forming a space adjacent to the second surface and inside the horizontal channel section.

A microelectronic device includes a memory array structure, an additional memory array structure, and a control circuitry structure. The memory array structure includes memory cells respectively including a vertical channel access device and a storage node device coupled to the vertical channel access device. The additional memory array structure vertically overlies the memory array structure and includes additional memory cells respectively including an additional vertical channel access device and an additional storage node device coupled to the additional vertical channel access device. The control circuitry structure vertically overlies and is bonded to one or more of the memory array structure and the additional memory array structure. The control circuitry structure includes control logic circuitry coupled to the memory cells of the memory array structure and the additional memory cells of the additional memory array structure. Related memory devices and electronic systems are also described.

The utility model discloses a winding chuck and clamping equipment. The winding chuck comprises a base, a pushing assembly, a jacking head assembly and a limiting piece. The base is provided with a channel penetrating through the two opposite ends of the base and a sliding way in the axial direction perpendicular to the channel, and the sliding way is communicated with the channel and penetrates through the side wall of the base. The propelling assembly is assembled in the channel and is in sliding connection with the base; the ejector head assembly is assembled in the slide way, slidably connected with the base and contacted with the propelling assembly, and the propelling assembly is used for pushing the ejector head assembly to slide and extend out of the slide way; the limiting piece is connected with the base and blocks the end, close to the ejector head assembly, of the channel. The pushing assembly does not need to be broken due to the fact that the pushing force of the driving piece is too large. The pushing assembly and the top head assembly are in direct contact pushing and are convenient to replace and maintain. The limiting piece at the bottom of the base can limit further movement of the propelling assembly, and therefore the situation that the propelling assembly breaks away from the channel, and the clamping function of the winding chuck fails is prevented.

A frame structure for an electronic equipment enclosure includes vertical frame members and horizontal frame members arranged to form rear and front frames connected together via horizontal front-to-back members. At least one of the vertical frame members includes a closed profile and a vertical channel extending a length thereof for providing access to an adjustment assembly of a leveling foot. The adjustment assembly is positioned within the vertical channel and outside of the closed profile. At least one of the horizontal frame or front-to-back members is a structural member having a closed profile that includes at least one T-slot channel and at least one recessed groove extending a length thereof. The at least one recessed groove includes a row of mounting apertures arranged therein.

The present invention discloses a semiconductor structure. The semiconductor structure includes a channel element. The channel element includes a substrate portion and a vertical channel portion. The vertical channel portion is adjacent to the substrate portion. Both the substrate portion and the vertical channel portion include single crystal silicon.

The invention discloses a control method, a base station, a storage medium and a computer program product, the base station comprises an active antenna unit (AAU), the AAU comprises a first antenna array plane used for communication and perceptual emission and a second antenna array plane used for perceptual reception, the first antenna array plane and the second antenna array plane are respectively provided with a plurality of vertical channels, and the vertical channels are communicated with the AAU. The arrangement number of the vertical channels is set based on a communication scene demand and / or a perception control demand, and the method comprises the step of controlling the opening number of the vertical channels in the first antenna array plane and the second antenna array plane based on a perception receiving signal-to-noise ratio when working in a perception continuous wave mode.

The invention provides a laser radar satellite inversion method and system for optical parameters of background aerosol, and the method comprises the steps: carrying out the preprocessing of satellite-borne laser radar calibration data, and obtaining a vertical channel signal, a parallel channel signal and a hyperspectral channel signal of the background aerosol; performing day and night backscattering coefficient inversion on the vertical channel signal, the parallel channel signal and the hyperspectral channel signal by adopting different denoising strategies to obtain a night backscattering coefficient and a final backscattering coefficient; performing noise reduction processing on the accumulated atmospheric optical thickness corresponding to the night signal to obtain a night extinction coefficient; constructing a laser radar ratio climate field according to the night backscattering coefficient and the night extinction coefficient; and multiplying the climate field by the final backscattering coefficient through the laser radar to obtain a final extinction coefficient. By introducing an innovative multi-scale denoising and systematic deviation correction technology, the low signal-to-noise ratio challenge is effectively overcome, and the inversion precision is remarkably improved.

The invention provides a semiconductor element and a preparation method thereof. The semiconductor device includes a bit line extending along a first direction; the first word line extends along a second direction and is arranged above the bit line; and a second word line extending along the second direction and disposed over the bit line. The semiconductor device also includes a first pillar structure overlapping the first word line and the second word line.

This invention provides a memory device including a stacked structure, a vertical channel post, a first plug, and a second plug. The stacked structure includes multiple insulating layers and multiple conductive layers stacked alternately. The vertical channel post extends vertically through the stacked structure, and each vertical channel post includes an insulating post, a channel layer surrounding the insulating post, and a charge storage structure surrounding the channel layer. The first plug and the second plug are disposed on opposite sides of the insulating post and are connected to the channel layer. In a top view, the distance between the center of the first plug and the center of the second plug is greater than the radius of the vertical channel post.

The invention discloses a freezing crystallization system, relates to the technical field of freezing crystallization, and aims to solve the technical problem that seed crystal sinks to the bottom during freezing crystallization. Seed crystal is input into a sowing sheet through a transmission assembly and a torsion assembly, and is thrown out by an inclined ramp through a vertical channel due to centrifugal force; in this way, the seed crystal can be more uniformly dispersed in the solution, and the contact area between the seed crystal and a solute in the solution is greatly increased, so that the nucleation process of crystallization is effectively promoted, and the crystallization efficiency is remarkably improved. Meanwhile, when the sowing sheet is immersed into a solution, the floating ball in the ball cavity floats upwards, the floating ball is firstly thrown into the inclined ramp by centrifugal force, and the narrow opening is blocked by the floating ball, so that seed crystal is prevented from sinking to the bottom. The seed crystal is ensured to be always located at a proper position in the solution, the effect of promoting crystallization is continuously exerted, the stability of the crystallization process is ensured, and the product quality is further improved.

A system of the present disclosure has a housing that has at least one vertical channel for housing a plurality of medicine bottles laterally stacked in the channel, the channel has a first gate positioned above a trough and positioned such that when open, the first gate is beneath a first of the plurality of medicine bottles. Further, the channel has a second gate positioned above the first gate and positioned such that when open, the second gate is beneath a second of the plurality of medicine bottles, the second of the plurality of medicine bottles atop the first of the plurality of medicine bottles. The housing further comprising a trough for catching falling medicine bottles. The system further has a processor that sends a signal to a first servo motor coupled to the first gate at a predetermined time, the servo motor opening the first gate and allowing the first of the plurality of medicine bottles to fall into the trough. The processor further sends a signal to a second servo motor coupled to the second gate, the second servo motor opening the second gate and allowing the second of the plurality of medicine bottles to fall into a position where the first of the plurality of medicine bottles was held before the first of the plurality of medicine bottles fell into the trough.

A temporary building or structure includes one or more wall segments. The one or more wall segments include a first upright post, a second upright post, a first channel member on the first upright post and defining a first vertical channel, and a second channel member on the second upright post and defining a second vertical channel. The wall segment additionally includes a first horizontal row extending between the first and second vertical channels and including a first wall panel and a plenum. The wall segment includes a second horizontal row above or below the first horizontal row and extending between the first and second vertical channels. The second horizontal row includes a second wall panel.

The present disclosure describes an illustrative semiconductor IC device that includes a integrated logic microdevice and a memory microdevice that share the same vertical channel. By utilizing the same vertical channel, the overall footprint area of the integrated logic microdevice and the memory microdevice is relatively reduced and allows for further scaling of the associated semiconductor IC device.

The invention provides a vertical channel isolation device for a low-voltage drawer cabinet, and relates to the technical field of isolation devices, and the vertical channel isolation device is structurally composed of two parts: a drawer body and an interlayer partition plate are installed on a cabinet assembly. Wherein the curtain picking push plates are made of ABS flame-retardant materials and are integrally formed through a mold, and the two groups of curtain picking push plates are symmetrically installed on the left rear portion of the drawer body. Wherein the vertical channel lifting curtain is made of an ABS flame-retardant material and is integrally formed through a mold, and arc guides are arranged on the left side and the right side of the vertical channel lifting curtain. According to the drawer cabinet, the problem that in the prior art, after a drawer is pulled out, an electrified copper bar is not subjected to insulation protection during overhauling is solved, the protection grade is IP20 after a cabinet door is opened in the overhauling state, the electrified copper bar is completely shielded by an insulating part, the safety of equipment during overhauling under the electrified condition is guaranteed, and then the use reliability and safety of the drawer cabinet are improved.

A semiconductor device includes a substrate that includes a cell array region, a peripheral region, and a scribe lane region. A stack structure is disposed on the cell array region of the substrate and includes electrodes that are vertically stacked and spaced apart from each other. A dummy structure extends from the peripheral region to the scribe lane region of the substrate and includes first dielectric layers and second dielectric layers that are alternately and repeatedly stacked. A vertical channel structure penetrates the stack structure, and a slit in the dummy structure on the scribe lane region. The slit extends in a direction that is perpendicular to a top surface of the substrate and penetrates at least a portion of the dummy structure. The slit includes a void.

Three-dimensional, 3D, semiconductor device comprising: a stack structure (ST1, ST2) extending in a first direction and having electrodes (EL) stacked vertically on a substrate (10); a channel structure (CHS) coupled to the electrodes (EL) to form a plurality of memory cells arranged three-dimensionally on the substrate (10), the channel structure (CHS) comprising: first vertical channels (VS1) and second vertical channels (VS2) penetrating the stack structure (ST1, ST2); and a first horizontal channel (HS1) which is below the stack structure (ST1, ST2) and which laterally connects the first vertical channels (VS1) and the second vertical channels (VS2), the first horizontal channel (HS1) having an upper horizontal section (HP1), a lower horizontal section (HP2) and wall sections (VP), one of the wall sections (VP) being connected between one end of the upper horizontal section (HP1) and one end of the lower horizontal section (HP2), and the other of the wall sections (VP) being connected between another end of the upper horizontal section (HP1) and another end of the lower horizontal section (HP2); a second horizontal channel (HS2) connected to a sidewall of the first horizontal channel (HS1) of the channel structure and a top surface of the substrate (10), the second horizontal channel (HS2) having a first conductivity type; conductive plugs located at upper ends of the second vertical channels (VS2), the conductive plugs having a second conductivity type; a conductive line extending in a first direction on the stack structure (ST1, ST2) and connected to the second vertical channels (VS2), the first direction being parallel to a top surface of the substrate; and a bit line (BL1, BL2) extending in a second direction perpendicular to the first direction on the conductive line, the bit line (BL1, BL2) being connected to the vertical channels (VS1, VS2), the second direction being parallel to a top surface of the substrate.

A semiconductor memory device may be provided. The semiconductor memory device may include a bit line, a channel pattern on the bit line, the channel pattern including a horizontal channel portion, which is provided on the bit line, and a vertical channel portion, which is vertically extended from the horizontal channel portion, a word line provided on the channel pattern to cross the bit line, the word line including a horizontal portion, which is provided on the horizontal channel portion, and a vertical portion, which is vertically extended from the horizontal portion to face the vertical channel portion, and a gate insulating pattern provided between the channel pattern and the word line.

The invention discloses a vertical channel structure of a magnetic suspension rail transit bridge, and relates to the technical field of magnetic suspension bridge accessory engineering, the vertical channel structure comprises a channel foundation, a curtain board and an evacuation staircase, the channel foundation comprises a plurality of pile foundations and a foundation, and the pile foundations are jointly connected with the foundation; the foundation is connected with two symmetrically-distributed separating type stand columns in the transverse bridge direction through embedded steel bars, embedded parts are arranged in the separating type stand columns, a space is reserved between the two separating type stand columns in advance, evacuation stairs are installed in the reserved space, and a magnetic levitation uplink and a magnetic levitation downlink are arranged at the top ends of the two separating type stand columns respectively. Rail structures are arranged in the maglev ascending line and the maglev descending line, under the daily condition, maintainers can reach the bridge floor through the evacuation stairs to conduct maintenance operation, passengers can reach the vertical channel from the interval evacuation platform to rapidly get off the bridge in the emergency condition, and on the basis that passenger evacuation and maintainer passing are met, the maintenance efficiency is greatly improved. And the arrangement requirements of maglev trains and equipment can also be met.

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having vertically oriented access devices having a first source / drain region and a second source drain region vertically separated by a channel region, and gates opposing the channel region, vertically oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the first source / drain region and horizontally oriented digit lines coupled to the second source / drain regions.