780 results about "Contact formation" patented technology

Methods of wiring to a transistor and a related transistor are disclosed. In one embodiment, the method includes a method of forming wiring to a transistor, the method comprising: forming a transistor on a semiconductor-on-insulator (SOI) substrate using masks that are mirror images of an intended layout, the forming including forming a gate and a source / drain region for each and a channel, the SOI substrate including a semiconductor-on-insulator (SOI) layer, a buried insulator layer and a silicon substrate; forming a dielectric layer over the transistor; bonding the dielectric layer to another substrate; removing the silicon substrate from the SOI substrate to the buried insulator layer; forming a contact to each of the source / drain region and the gate from a channel side of the gate; and forming at least one wiring to the contacts on the channel side of the gate.

There is provided a nitride semiconductor light emitting device including: an n-type semiconductor region; an active layer formed on the n-type semiconductor region; a p-type semiconductor region formed on the active layer; an n-electrode disposed in contact with the n-type semiconductor region; a p-electrode formed on the p-type semiconductor region; and at least one intermediate layer formed in at least one of the n-type semiconductor region and the p-type semiconductor region, the intermediate layer disposed above the n-electrode, wherein the intermediate layer is formed of a multi-layer structure where at least three layers with different band gaps from one another are deposited, wherein the multi-layer structure includes one of an AlGaN layer / GaN layer / InGaN layer stack and an InGaN layer / GaN layer / AlGaN layer stack.

A rotary manipulation type electronic component includes a space formed by a case. A base houses a rotating body holding a resilient contact as a movable element. A comb-like contact is formed as a fixed element. A first bushing in the case and a second bushing in the base rotatably support a rotating shaft that rotates together with the rotating body. An inner bottom face of a cap-shaped knob is secured onto an end of the rotating shaft so that the knob receives a barrel portion, which supports the rotating shaft as a portion of the case.

In a semiconductor device including a MIS transistor with a FUSI gate electrode and a polysilicon resistor, a portion of the polysilicon resistor provided in a contact formation region is silicided simultaneously with the gate electrode or an impurity diffusion region.

A storage device is provided with a sliding lid slidably contacting guide rails formed at both side ends of an opening of the storage device, and when the sliding lid is stored in an accommodating section formed continuously to a rear end of the opening, the sliding lid opens at the storage device. In the storage device, in sliding sections where the guide rails and sliding lid slidably contact each other, there are formed buffer sections for allowing the sliding lid to be displaced toward a direction orthogonal to a sliding direction. Therefore, the buffer sections are deformed during the opening and covering movements, so a play can be eliminated.

A universal logic gate apparatus is disclosed, which include a plurality of self-assembling chains of nanoparticles having a plurality of resistive connections, wherein the plurality of self-assembling chains of nanoparticles comprise resistive elements. A plasticity mechanism is also provided, which is based on a plasticity rule for creating stable connections from the plurality of self-assembling chains of nanoparticles for use with the universal, reconfigurable logic gate. In addition, the universal logic gate can be configured with a cross-bar architecture, where nanoconnections are formed from a columbic-educed mechanical stress contact.

The present invention provides a low-resistance magnetoresistive element of a spin-injection write type. A crystallization promoting layer that promotes crystallization is formed in contact with an interfacial magnetic layer having an amorphous structure, so that crystallization is promoted from the side of a tunnel barrier layer, and the interface between the tunnel barrier layer and the interfacial magnetic layer is adjusted. With this arrangement, it is possible to form a magnetoresistive element that has a low resistance so as to obtain a desired current value, and has a high TMR ratio.

According to one aspect of the invention, an electronic assembly is provided. The electronic assembly includes a microelectronic die having an integrated circuit formed therein. Carbon nanotubes are grown on the microelectronic die and are electrically connected to the integrated circuit. The carbon nanotubes form a plurality of contact formations to connect the die, and the integrated circuit therein, to a package substrate. The package substrate may then be attached to a printed circuit board and installed in a computing system. According to another aspect of the present invention, a first conductive layer is formed on a semiconductor substrate having a plurality of transistors formed thereon. Then a second conductive layer is formed on the first conductive layer. A hole is created at least partially through both the first and second conductive layers. Carbon nanotubes are grown within the hole to electrically interconnect the two conductive layers.

A pressure regulating reservoir is structured such that a major diameter portion of a shaft contacts a bottom surface of a valve seat, whereas a top surface of a piston does not contact an upper end surface of a wall forming a reservoir chamber in a housing. Therefore, a lift amount of a ball valve can be set using a portion above the major diameter portion of the shaft that contacts the bottom surface of the valve seat. That is, the lift amount can be set using only a dimension in the axial direction of a minor diameter portion of the shaft.

A non-volatile semiconductor memory device according to the present invention includes a substrate; a first word-line provided above the substrate surface, the first word-line having a plate shape in an area where a memory cell is formed; a second word-line provided above the first word-line surface, the second word-line having a plate shape; a plurality of metal wirings connecting the first and second word-lines with a driver circuit; and a plurality of contacts connecting the first and second word-lines with the metal wirings. The contact of the first word-line is formed in a first word-line contact area. The contact of the second word-line is formed in a second word-line contact area. The first word-line contact area is provided on a surface of the first word-line that is drawn to the second word-line contact area.

A method for forming a CMOS device in a manner so as to avoid dielectric layer undercut during a pre-silicide cleaning step is described. During formation of CMOS device comprising a gate stack on a semiconductor substrate surface, the patterned gate stack including gate dielectric below a conductor with vertical sidewalls, a dielectric layer is formed thereover and over the substrate surfaces. Respective nitride spacer elements overlying the dielectric layer are formed at each vertical sidewall. The dielectric layer on the substrate surface is removed using an etch process such that a portion of the dielectric layer underlying each spacer remains. Then, a nitride layer is deposited over the entire sample (the gate stack, the spacer elements at each gate sidewall, and substrate surfaces) and subsequently removed by an etch process such that only a portion of said nitride film (the “plug”) remains. The plug seals and encapsulates the dielectric layer underlying each said spacer, thus preventing the dielectric material from being undercut during the subsequent pre-silicide clean process. By preventing undercut, this invention also prevents the etch-stop film (deposited prior to contact formation) from coming into contact with the gate oxide. Thus, the integration of thin-spacer transistor geometries, which are required for improving transistor drive current, is enabled.