99results about How to "Reduce step height" patented technology

An integrated circuit having composite gate structures and a method of forming the same are provided. The integrated circuit includes a first MOS device, a second MOS device and a third MOS device. The gate stack of the first MOS device includes a high-k gate dielectric and a first metal gate on the high-k gate dielectric. The gate stack of the second MOS device includes a second metal gate on a high-k gate dielectric. The first metal gate and the second metal gate have different work functions. The gate stack of the third MOS device includes a silicon gate over a gate dielectric. The silicon gate is preferably formed over the gate stacks of the first MOS device and the second MOS device.

A SOI MOSFET structure having a reduced step height between the various semiconductor layers without adversely affecting the junction capacitance of the semiconductor device formed on the uppermost semiconductor layer as well as a method of fabricating the same are provided. The structure of the present invention includes an elevated device region having at least one semiconductor device located on a second semiconductor layer. The elevated device region further includes a source / drain junction that extends from the second semiconductor layer down to a first buried insulator layer that is located on an upper surface of the semiconductor substrate. The structure also includes a recessed device region having at least one semiconductor device located atop a first semiconductor layer which is located on an upper surface of the first buried insulator. An isolation region separates the elevated device region from the recessed device region.

An organic light emitting display which is constructed with a TFT substrate having an insulating substrate and a TFT that has at least a source electrode and a drain electrode, a lower electrode formed on the TFT substrate and connected to one of source / drain electrodes, an insulating layer having an opening that exposes a portion of the lower electrode, an organic thin film layer formed on the exposed portion of the lower electrode and the insulating layer, and an upper electrode formed on the organic thin film layer, wherein the insulating layer has a taper angle less than 40° at an edge of the opening, and a step less than or equal to 3,000 Å is formed between the lower electrode and the organic thin film layer. The organic light emitting display can prevent device failure.

An active organic electroluminescence panel display and a fabricating method thereof are disclosed. A thin film transistor array comprising a plurality of thin film transistors, a plurality of datalines and a plurality of scanlines are formed on a substrate. A passivation layer is formed on the substrate, covering the thin film transistor array. A contact opening is formed in the passivation layer for exposing a prescribed area of the array. An anode layer is formed on the passivation layer and fills into the contact opening. A blank layer is formed on the anode, covering the contact opening. A shadow mask is disposed on the blank layer. Then, a sputtering process is performed to form an organic luminescent layer. The shadow mask is then removed, and a cathode layer is formed on the organic luminescent layer for forming an active organic electroluminescence panel display.

A method is provided for fabrication of a semiconductor substrate having regions isolated from each other by shallow trench isolation (STI) structures protruding above a surface of the substrate by a step height. The method includes the steps of forming a bottom antireflective coating (BARC) layer overlying the surface of a semiconductor substrate and the surface of STI structures; etching back a portion of the BARC layer overlying at least one of the STI structures, and partially etching back the at least one of the STI structures, to reduce the step height by which the STI structure protrudes above the surface of the substrate; and removing a remaining portion of the BARC layer between adjacent STI structures. The method may be used to fabricate semiconductor devices including memory cells that have improved reliability.

A radially segmented apodized diffractive multifocal IOL for ocular implant is provided. The ocular implant can comprise a radially segmented apodized diffractive multifocal intraocular lens optic and a number of haptics. The radially segmented apodized diffractive multifocal IOL may pass optical energy in both photopic and mesopic conditions. The radially segmented apodized diffractive multifocal IOL includes a number of radially segmented apodization zones, each radially segmented apodization zones having a unique focal length. The haptics mechanically couple to the apodized diffractive multifocal IOL optic in order to position and secure the apodized diffractive multifocal IOL within the eye. The radially segmented apodized diffractive multifocal IOL may include both a diffractive region and a refractive region.

An exercise apparatus includes a housing, a pair of pivoting foot treadles and a pair of reciprocating bellows that support the foot treadles. A sealed air system including a conduit interconnects the bellows and is operable for reciprocating transfer of air from bellow to bellow. Each of the foot treadles is pivotably movable between upper and lower positions, and has a resting position between the upper and lower positions. The resting position of the foot treadles defines a resting position of the bellows while the upper and lower positions of the foot treadles respectively define elongated and compressed positions of the bellows. In use, the elongated and compressed positions of the bellows are each no more than 5 degrees off the center resting position thereby reducing stress on the bellows.

To ensure sealing ability of a resealable can container formed of a welded can body between a curled portion of container mouth and a resin sealing liner, without degrading productivity and easiness to open the closure.The can body 2 is prepared by rolling a steel sheet and welding overlapped longitudinal edges of the steel sheet. In order to achieve the above-mentioned objective, a level difference of a welded portion 2a on the surface of a curled portion 21a is reduced smaller than that on the trunk portion 22, specifically, kept within the range of 15 to 100 μm, and a durometer hardness of the resin sealing liner is kept within the range of HDA 30 to 70 according to ISO 868 (or JIS-K7215).