357results about How to "Large capacitance" patented technology

A pixel structure comprises a photo-sensitive element for generating charge in response to incident light. A first transfer gate is connected between the photo-sensitive element and a first charge conversion element. A second transfer gate is connected between the photo-sensitive element and a second charge conversion element. An output stage outputs a first value related to charge at the first charge conversion element and outputs a second value related to charge at the second charge conversion element. A controller controls operation of the pixel structures and causes a pixel structure. The controller causes the pixel structure to: acquire charges on the photo-sensitive element during an exposure period; transfer a first portion of the charges acquired during the exposure period from the photo-sensitive element to the first charge conversion element via the first transfer gate; and transfer a second portion of the charges acquired during the exposure period from the photo-sensitive element to the second charge conversion element via the second transfer gate.

An active matrix driven electro-optical device, such as a liquid crystal device, is provided which is able to add sufficient storage capacitance to pixel electrodes and to decrease the diameter of contact holes connecting with pixel electrodes, even when a fine pixel pitch is employed. The liquid crystal device has TFTs, data lines, scanning lines, storage capacitor lines, and pixel electrodes provided on a TFT array substrate. Each of the pixel electrodes is electrically connected to one of the TFTs by two contact holes through a barrier layer. A part of a semiconductor layer and each of the capacitor lines sandwich a first dielectric film and constitute a first storage capacitor, while a part of the barrier layer and each of the capacitor lines sandwich a second dielectric film and constitute a second storage capacitor.

An integrated circuit device comprises a memory cell well formed with a flash memory device, first and second well of opposite conductivity types for formation of high voltage transistors, and third and fourth wells of opposite conductivity types for low voltage transistors, wherein at least one of the fist and second wells and at least one of the third and fourth wells have an impurity distribution profile steeper than the memory cell well.

Optical plasmon-wave attenuator and modulator structures for controlling the amount of coupling between an guided optical signal and a surface plasmon wave. Optical power coupled to the plasmon wave mode is dissipated in varying amounts producing an intensity modulation effect on the optical signal. For electrical modulation, an additional dielectric (or polymer) layer with variable refractive index in optical contact with a metal layer supporting at least one plasmon wave mode is used to perturb or vary the propagation constant of plasmon wave. Propagation constant variation results in the power coupling variation between the surface plasmon wave and the optical wave. The refractive index variation of the dielectric (or polymer) layer can be accomplished via an electro-optic traveling-wave, a lump-element, or any other integrated optics modulator configuration situated to affect the layer, thereby permitting data rates into tens of GHz. Because of the extremely small interaction lengths needed, the optical plasmon-wave modulator is a very compact device which can be implemented on the top of a fiber or as an integrated optical planar structure.

Embodiments of the present invention are directed to apparatuses and methods of making a micromachined resonator gyroscope, e.g. a disc resonator gyro (DRG), including one or more of the following novel features. Embodiments of the invention may comprise a triple-wafer stack gyroscope with an all fused quartz (or all silicon) construction for an electrical baseplate, resonator and vacuum cap. This can yield superior thermal stability over prior art designs. A typical resonator embodiment may include a centrally anchored disc with high aspect-ratio in-plane electrostatic drive and sense electrodes to create large capacitance. A silicon sacrificial layer may be employed for attaching a quartz resonator wafer to a quartz handle wafer for high aspect-ratio etching. In addition, embodiments of the invention may comprise a low thermal stress, wafer-level vacuum packaged gyroscope with on-chip getter. An ultra-thin conductive layer deposited on the quartz resonator may also be utilized for high Q.

The interposer includes a glass substrate 46 with first through-electrodes 47 buried in; a plurality of resin layers 68, 20, 32 supported by the glass substrate; thin film capacitors 18a, 18b buried between a first resin layer 68 of the plural resin layers and a second resin layer 20 of the plural resin layers and including the first capacitor electrodes 12a, 12b, the second capacitor electrodes 16 opposed to the first capacitor electrodes 12a, 12b, and a dielectric thin film 14 of a relative dielectric constant of 200 or above formed between the first capacitor electrode 12a, 12b and the second capacitor electrode 16, and the second through-electrodes 77a, 77b penetrating the plural resin layers 68, 20, 32, electrically connected to the first through-electrode 47 and electrically connected to the first capacitor electrode 12a, 12b or the second capacitor electrode 16.

A switching power supply device includes a full-bridge circuit, a transformer, a rectifier circuit, a filter circuit, a first series connection of a snubber capacitor and a first diode, and a second diode. The full-bridge circuit includes switching elements which are controlled to be driven under phase-shift control. The first series connection is connected in parallel with the smoothing reactor, where one terminal is connected to a terminal on positive side of the rectifier circuit, and the other terminal is connected to an anode of the first diode. A cathode of the first diode is connected to one terminal of the smoothing capacitor which is applied with positive voltage. The second diode is provided between a terminal on negative side of the rectifier circuit and a connecting point of the snubber capacitor and the first diode. A cathode of the second diode is connected to the connecting point.

A multilayer ceramic capacitor includes an element body of roughly rectangular solid shape which is constituted by dielectric layers alternately stacked with internal electrode layers having different polarities, with a pair of cover layers formed on it to cover the top and bottom faces in the direction of lamination of the foregoing, and which has a pair of principal faces, a pair of end faces, and a pair of side faces, wherein external electrodes are formed on the pair of end faces and at least one of the pair of principal faces of the element body, and Tt representing the thickness of the external electrode and Tc representing the thickness of the cover layer satisfy the relationship of Tt≦Tc. The multilayer ceramic capacitor has large capacitance and also exhibits excellent thermal shock resistance while sufficiently suppressing generation of cracks.

To provide a semiconductor device with a small circuit size and low power consumption or an electronic device including the semiconductor device and compressing a large volume of image data. A semiconductor device of a Hopfield neural network is formed using neuron circuits and synapse circuits. The synapse circuit includes an analog memory and a writing control circuit, and the writing control circuit is formed using a transistor including an oxide semiconductor in a channel formation region. Thus, data retention lifetime of the analog memory can be extended and refresh operation for data retention can be omitted, so that power consumption of the semiconductor device can be reduced. The semiconductor device enables judgement whether learned image data and arbitrary image data match, are similar, or mismatch by comparing video data. Thus, motion compensation prediction, which is one of data compression methods, can be employed for image data.

The invention provides a semiconductor device which is non-volatile, easily manufactured, and can be additionally written. A semiconductor device of the invention includes a plurality of transistors, a conductive layer which functions as a source wiring or a drain wiring of the transistors, and a memory element which overlaps one of the plurality of transistors, and a conductive layer which functions as an antenna. The memory element includes a first conductive layer, an organic compound layer and a phase change layer, and a second conductive layer stacked in this order. The conductive layer which functions as an antenna and a conductive layer which functions as a source wiring or a drain wiring of the plurality of transistors are provided on the same layer.

An apparatus and method provides a driver circuit that provides for power factor correction (PFC) to a load, such as a solid-state lighting (SSL) device, such as, for example, a light emitting diode (LED) or an array or cluster of LEDs. A programmable reference is provided in the circuit to operate in a fixed frequency peak current mode control (FFPCMC) or in a fixed frequency average current mode control (FFACMC). A driver circuit is employed to operate the SSL device using power derived from a main power source which may be DC or AC. In a FFPCMC embodiment, a programmable power reference is programmed to be a fixed DC voltage. In a FFACMC embodiment, source input current to the circuit can be programmed to be proportional to the rectified AC voltage after a bridge rectifier.

Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus. a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.

A capacitive pressure sensor and method for its fabrication. The sensor is fabricated from first and second wafers to have a mechanical capacitor comprising a fixed electrode and a moving electrode defined by a conductive plate. The sensor further has a diaphragm on a surface of the first wafer that is mechanically coupled but electrically insulated from the conductive plate. A conductive layer on the surface of the first wafer is spaced apart from the conductive plate to define the fixed electrode. The second wafer is bonded to the first wafer and carries interface circuitry for the sensor, including the conductive plate and the fixed electrode which are between the first and second wafers and electrically connected to the interface circuitry. At least an opening is present in the first wafer and its first conductive layer by which the diaphragm is released and exposed to an environment surrounding the sensor.

An electrolytic capacitor includes a capacitor element, an electrolyte solution with which the capacitor element is impregnated, and an outer package enclosing the capacitor element and the electrolyte solution. The capacitor element includes an anode foil having a dielectric layer on a surface thereof, a cathode foil, a separator disposed between the anode foil and the cathode foil, and a solid electrolyte layer in contact with the dielectric layer of the anode foil and the cathode foil. The electrolyte solution contains a low-volatile solvent that is at least one of polyalkylene glycol and a derivative of polyalkylene glycol.

The present invention is to provide a metallized film capacitor having a compact size, a large capacitance and a low inductance whereas number of parts is reduced. The metallized film capacitor comprises: a plurality of capacitor elements (1) provided with metallized contact electrodes (2) on both ends in the width direction; a bus-bar (3) to connect each of a plurality of electrodes (2) on one end; and a capacitor case (5) to house a plurality of capacitor elements (1), wherein a plurality of capacitor elements (1) are arranged in the capacitor case such that one side of electrodes (2) faces the opening surface of capacitor case (1) and each electrode (2) of one of both ends of each capacitor element (1) are positioned generally coplanarly.

In a conventional DRAM, when the capacitance of a capacitor is reduced, an error of reading data easily occurs. A plurality of cells are connected to one bit line MBL_m. Each cell includes a sub bit line SBL_n_m and 4 to 64 memory cells (a memory cell CL_n_m_—1 or the like). Further, each cell includes selection transistors STr1_n_m and STr2_n_m and an amplifier circuit AMP_n_m that is a complementary inverter or the like is connected to the selection transistor STr2_n_m. Since parasitic capacitance of the sub bit line SBL_n_m is sufficiently small, potential change due to electric charge in a capacitor of each memory cell can be amplified by the amplifier circuit AMP_n_m without an error, and can be output to the bit line.