655 results about "Dielectric structure" patented technology

A broadband omni-directional bicone antenna. The antenna can comprise conductive surfaces of conical voids provided within a solid dielectric structure. The outside surface of the solid structure can support a radio frequency (RF) lens geometry operable for beam forming. The beam forming can modify the elevation pattern of the electromagnetic radiation from the bicone antenna. The solid dielectric structure may be machined or molded from a single piece of material. The conical voids provided within the solid structure can be metallized to provide conductive bicone radiators. The outer surface beam shaping lenses can be zoned or continuous and can provide elevation patterns with increased gain, cosecant squared falloff, or various other patterns. The beam shaping lens may be formed from any low-loss dielectric. Alternatively, the lens may be formed from a less dense material such as dielectric foam that can support radial conductive beam forming vanes.

The invention relates to a modeling and optimizing method for inter-layer signal crosstalk of a PCB (Printed Circuit Board). Frequency response data of all dielectric layers of the PCB under different temperature and humidity conditions are collected, and a mapping model with the temperature gradient and the humidity diffusion gradient as input and the dielectric constant as output is established. And calculating the dynamic distribution of mutual capacitance and mutual inductance under the environment change by combining the spatial layout parameters of the differential signal pair, and constructing a crosstalk sensitivity evaluation model with coupled frequency, environment and layout. And high-risk areas with crosstalk sensitivity caused by environment change are identified, and the crosstalk change rate of each area is quantified. For a sensitive area, a temperature and humidity compensation medium structure is introduced to stabilize local dielectric characteristics and reduce the influence of the environment on crosstalk. And according to the compensated medium distribution, adjusting a differential signal wiring path and impedance matching by adopting an optimization method with the aim of minimizing the crosstalk change rate, and generating a wiring layout with environmental robustness. According to the invention, the signal integrity and the transmission reliability of the multi-layer PCB in a temperature and humidity changing environment can be effectively improved.

The invention relates to an anti-ant large-core-number fiber ribbon cable comprising a cable core and an outer sheath. The cable core includes loose tubes; and fiber ribbons are sleeved inside the loose tubes. The outer sheath is an outer nylon sheath; and a non-metallic reinforcement layer is arranged between the outer sheath and the cable core. According to the anti-ant large-core-number fiber ribbon cable provided by the invention, with the outer nylon sheath, ants can not bite the sheath, so that the damages on the optical cable by ant biting in a pipe at an area with a serious anti problem are prevented, the normal state of the cable is ensured, and the application region of the cable is extended. The cable based on a simple and reasonable structure has advantages of small cable diameter, high fiber density, large fiber capacity, and low duty ratio and can be laid in a pipe conveniently; and the bending performance is good. During branched connection, 4 to 24 fibers can be melted once, so that the construction time is saved and the manpower cost is lowered, and the construction efficiency is improved. On the basis of the full drying type dielectric structure, branched connection is realized conveniently and usage becomes convenient.

The present application discloses a memory device and a method for fabricating the memory device. The memory device includes a substrate; a landing area positioned on the substrate; a bottom electrode positioned on the landing area, wherein the bottom electrode has a container-shaped profile; a support layer positioned over the substrate and laterally surrounded the bottom electrode; a dielectric structure including a dielectric layer conformally positioned on the bottom electrode and on a top surface of the support layer, and covering top corners of the support layer, and a plurality of dielectric portions conformally positioned on the dielectric layer and covering the top corners of the support layer; and a top electrode structure positioned on the dielectric structure. The dielectric portions are sandwiched by the top electrode structure and the dielectric layer. The top surface of the third support layer is higher than a top surface of the bottom electrode.

The invention discloses an all-dielectric structure type broadband wave-absorbing metamaterial and a design method thereof. The all-dielectric structure type broadband wave-absorbing metamaterial comprises a substrate and a plurality of resonators, the plurality of resonators are periodically and uniformly arrayed on the surface of the substrate, the adjacent resonators are connected with each other, each resonator comprises a pyramid structure unit and a grid structure unit, the pyramid structure units are nested in the grid structure units to form a pyramid-grid composite resonator, and the substrate and the resonators are both made of a high dielectric loss composite material. Based on the brand new design angle of wave absorbing performance complementation, the limitation of the wave absorbing performance of a single structure is broken through, the wave absorbing performance is improved from the microstructure level, meanwhile, efficient electromagnetic wave energy absorption is achieved in a wider frequency range, multi-stage dissipation and broadband impedance matching of incident electromagnetic waves are achieved, and the wave absorbing performance is improved. And the technical limitation of thickness constraint and narrow-band response of the traditional wave-absorbing material is broken through.

Integrated circuit structures having void-free internal spacers, and methods of fabricating integrated circuit structures having void-free internal spacers, are described. For example, an integrated circuit structure includes a stack of horizontal nanowires. A gate structure is vertically around the stack of horizontal nanowires, the stack of horizontal nanowires extending laterally beyond the gate structure. An internal gate spacer is between vertically adjacent nanowires of the stack of horizontal nanowires and laterally adjacent to the gate structure. An epitaxial source or drain structure is coupled to an end of the stack of horizontal nanowires and in contact with the internal gate spacer. A dielectric structure is beneath and in contact with the epitaxial source or drain structure, the dielectric structure including a same material as the internal gate spacer, and the dielectric structure not including a seam therein.

The invention discloses a band-pass type active frequency selective surface based on double-element composite loading. The band-pass type active frequency selective surface comprises at least one resonance unit which is periodically arranged, the resonance unit sequentially comprises a top metal frequency selection surface layer, a first dielectric structure layer, a middle metal feed layer, a second dielectric structure layer and a bottom metal frequency selection surface layer from top to bottom; the top metal layer and the bottom metal layer are composed of square ring aperture grooves subjected to deformation processing, and the middle feed layer is of a cross zigzag metal structure, plays a role in coupling an electromagnetic field and serves as a bias network of the AFSS. And the metal through holes penetrate through the resonance units in the vertical direction, so that the middle layer feeder line can respectively provide reverse bias voltage for independently regulating and controlling the resonance frequency for the PINs and the variable capacitance diodes on the top layer and the bottom layer. According to the invention, the functions of band switching and wide-range frequency tuning can be met, so that the problem of insertion loss increase caused by limited design frequency regulation and control range and element loading of the AFSS in the prior art can be solved.

The present application discloses a memory device and a method for fabricating the memory device. The memory device includes a substrate; a landing area positioned on the substrate; a bottom electrode positioned on the landing area, wherein the bottom electrode has a container-shaped profile; a support layer positioned over the substrate and laterally surrounded the bottom electrode; a dielectric structure including a dielectric layer conformally positioned on the bottom electrode and on a top surface of the support layer, and covering top corners of the support layer, and a plurality of dielectric portions conformally positioned on the dielectric layer and covering the top corners of the support layer; and a top electrode structure positioned on the dielectric structure. The dielectric portions are sandwiched by the top electrode structure and the dielectric layer. The top surface of the third support layer is higher than a top surface of the bottom electrode.

A semiconductor device structure and method for manufacturing the same are provided. The semiconductor device structure includes a substrate, a dielectric structure, a pad, a conductive structure, and a buffer structure. The dielectric structure is disposed on the substrate. The pad is embedded in the dielectric structure. The conductive structure is disposed on the pad. The buffer structure is disposed on the pad and separates the conductive structure from the dielectric structure. A coefficient of thermal expansion (CTE) of the buffer structure ranges between a CTE of the dielectric structure and a CTE of the conductive structure.

Various embodiments of the present disclosure are directed towards an integrated chip having an interconnect structure overlying a substrate. The interconnect structure includes a conductive wire disposed in a dielectric structure. The conductive wire comprises a body structure. A passivation structure overlies the interconnect structure. A bond pad overlies the passivation structure. The bond pad comprises an upper pad structure on the passivation structure and a plurality of lower bond structures extending through the passivation structure to the conductive wire. The lower bond structures respectively comprise a vertical bond structure and a diffusion barrier layer disposed along a lower surface and opposing sidewalls of the vertical bond structure. The upper pad structure comprises a first conductive layer vertically stacked with a second conductive layer

Various embodiments of the present disclosure are directed towards an integrated circuit (IC) device including a dielectric structure on a semiconductor substrate. A plurality of active bond pads are disposed in the dielectric structure. A plurality of auxiliary bond pads are disposed in the dielectric structure and are laterally offset from the plurality of active bond pads by a first distance greater than a pitch of the plurality of active bond pads. The active bond pads are respectively electrically coupled to a corresponding auxiliary bond pad in the plurality of auxiliary bond pads.

The invention relates to the technical field of antennas, in particular to a millimeter wave three-beam all-dielectric lens antenna, which comprises a group of 2 * 2 magnetoelectric dipole array antennas and an all-dielectric circular lens structure, the 2 * 2 magnetoelectric dipole array antenna is used as a feed source and is arranged on the plane side of the all-dielectric circular lens structure, and the feed source directly faces the geometric center of the all-dielectric circular lens structure; the all-dielectric circular lens structure has a direction-controllable three-beam radiation capability; through the reasonable medium structure layout, the multi-beam coverage and the frequency point adaptability are considered while high-gain output is ensured, and the contradiction between the performance and the practicability of the existing scheme is overcome.

The invention discloses a computing spectrum reconstruction method based on CS-Unet and a spectral imaging system. The calculation spectrum reconstruction method comprises two parts, namely TwIST pre-reconstruction and Unet coupling reconstruction, wherein the TwIST pre-reconstruction is used for preprocessing an initial coding spectrum image to generate a pre-reconstructed spectrum image; and the Unet part couples the pre-reconstructed image and the initial coding spectral image in the spectral dimension and inputs the coupled image and the initial coding spectral image into a network for fine reconstruction, and finally a target space-spectral image is recovered. The imaging system is composed of a spectral image coding module and a CS-Unet reconstruction module, a metasurface spectral modulator applied to the spectral image coding module is composed of 36 silicon-based all-dielectric structures, and rich spectral response is achieved by adjusting the period, the size and the direction angle of three basic C4 symmetric units, namely a round unit, a cross unit and a square unit. According to the method, high-robustness and high-imaging-quality spectrum reconstruction is realized in a visible light wave band (400-700 nm), and the method has relatively high engineering applicability.

The invention provides a magnetically soft alloy-based wave-absorbing composite material as well as a preparation method and application thereof, and belongs to the technical field of electromagnetic wave absorbing materials. The wave-absorbing composite material provided by the invention comprises various magnetically soft alloy substrates prepared from elements such as iron, cobalt, nickel and the like and nitrogen-doped carbon coating the surfaces of the magnetically soft alloy substrates. The coercive force of the soft magnetic alloy is relatively low, so that the magnetic domain wall movement and magnetic moment rotation resistance in the material are reduced, the magnetic conductivity is relatively high, and the nitrogen-doped carbon with high dielectricity is combined to construct a magnetic-dielectric structure, so that the impedance matching between the composite material and the space is improved, and the efficient absorption of electromagnetic waves is promoted. The magnetically soft alloy-based wave-absorbing composite material has the characteristics of strong electromagnetic wave absorption performance and wide absorption frequency band, and is simple in preparation technology and easy for large-scale production.

Disclosed is a semiconductor device comprising a first channel region, a first dielectric structure on the first channel region, a first metal pattern spaced apart from the first dielectric structure, and a first dipole structure between the first metal pattern and the first dielectric structure. The first dipole structure includes a first dipole layer and a second dipole layer. The first dipole layer includes a first dipole element. The second dipole layer includes a second dipole element different from the first dipole element. A maximum oxidation number of the first dipole element is different from a maximum oxidation number of the second dipole element.

Isolation structures between transistors in integrated circuit (IC) devices. An IC device includes transistors coupled to an interconnect network, and between the transistors a dielectric structure with a wider width away from the interconnect network and a narrower width nearer the interconnect network. Dielectric structures with wider back-side widths may separate gate electrodes and / or source and drain contacts of the transistors. The dielectric structures may be formed by etching an opening between metallization structures of the transistors from a back side of the device substrate and by depositing liner and fill dielectrics over the back-side opening.

The present disclosure relates to an integrated chip. The integrated chip includes a plurality of conductive interconnects arranged within a dielectric structure having a plurality of inter-level dielectric (ILD) layers stacked onto one another. A heat pipe vertically extends through the plurality of ILD layers. A high thermal conductivity layer is sandwiched between neighboring ones of the plurality of ILD layers. The high thermal conductivity layer laterally extends from over one or more of the plurality of conductive interconnects to the heat pipe.

A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a substrate, a word line structure, a dielectric structure, a contact plug, and a sidewall insulating layer. The substrate includes an active region. The word line structure is disposed in the substrate and in the active region. The dielectric structure is disposed on the word line structure. The contact plug is disposed on the substrate and in the active region. The contact plug includes a first conductive pillar disposed on the substrate and a second conductive pillar disposed on the first conductive pillar. The sidewall insulating layer is disposed on an upper portion of a sidewall of the contact plug. The sidewall insulating layer is in contact with the first conductive pillar, the second conductive pillar, and the dielectric structure.

The invention aims to provide a medium-loaded ultra-wideband miniaturized double-ridged horn antenna, and belongs to the technical field of double-ridged horn antennas. A dielectric structure loaded on a horn mouth surface in the antenna comprises a dielectric lens, a dielectric flat plate and a dielectric guide section with a specific shape, and through loading of an integrated dielectric structure formed by the dielectric lens, the dielectric flat plate and the dielectric guide section, impedance mutation from a metal waveguide to a free space can be optimized, and reflection is reduced; electromagnetic waves are guided to converge, beam divergence is reduced, and the directivity and gain of a main lobe are improved; meanwhile, the wavefront of the horn mouth electromagnetic wave can be corrected to be a plane wave, phase distortion is reduced, and the far-field directivity is improved; focused electromagnetic waves are refracted, side lobes are reduced, and main lobe gain is improved. The ultra-wide-band miniaturized double-ridge horn antenna has excellent comprehensive performance of ultra wide band, miniaturization, high gain and low side lobe.

Integrated circuit structures having uniform grid metal gate and trench contact placeholder cut and non-selective fin trim isolation (FTI) are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires or a fin. A gate structure is over the vertical stack of horizontal nanowires or the fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure. A dielectric gate cut plug is laterally between and in contact with the gate structure and the dielectric structure. The dielectric structure has an uppermost surface above an uppermost surface of the dielectric gate cut plug.

A method for forming a semiconductor structure includes following operations. An interconnect structure is formed over a substrate. The interconnect structure includes a top conductive layer. A dielectric structure is formed over the interconnect structure. The dielectric structure is patterned to simultaneously form a cavity and a protrusion in the cavity. A MEMS substrate is bonded to the dielectric structure to seal the cavity. The protrusion is separated from the MEMS substrate.

A semiconductor device (100) comprising: an interconnect structure (114) disposed over a semiconductor substrate (104); a dielectric structure (130) disposed over the interconnect structure (114); a plurality of cavities (148) disposed in the dielectric structure (130) and arranged in an array (502) having rows (504) and columns (506); a MEMS substrate (136) disposed over the dielectric structure (130), the MEMS substrate (136) defining upper surfaces of the cavities (148), the MEMS substrate (136) comprising a plurality of movable membranes (150), the movable membranes (150) overlying the respective cavity (148); and a plurality of flow connection channels (152) arranged in the dielectric structure (130), wherein the upper surfaces of the flow connection channels (152) are defined by the MEMS substrate (136),and wherein each of the flow connection channels (152) extends laterally between two adjacent cavities (148) of the cavities (148) such that all cavities (148) are in flow communication with one another, wherein the semiconductor device (100) comprises a buffer tank (1002) arranged in the dielectric structure (130) and arranged vertically between the semiconductor substrate (104) and the MEMS substrate (136), wherein the dielectric structure (130) at least partially defines side walls of the buffer tank (1004), wherein the semiconductor device (100) comprises a buffer tank channel (1004) extending laterally from the buffer tank (1004) to one of the cavities (146), wherein the semiconductor device (100) comprises a sealing structure (1006) extending vertically through the MEMS substrate (136) and into the buffer tank channel (1004), wherein the Sealing structure (1006) seals the buffer tank (1002) against the cavity (148),so that the buffer tank (1002) is not in flow connection with the cavity (148).,

Embodiments of the present application provide a semiconductor structure manufacturing method and a semiconductor structure. The manufacturing method comprises: providing a substrate; the substrate comprises a substrate, a dielectric structure on the substrate, and a blocking material layer on the dielectric structure; the dielectric structure comprises at least one dielectric layer; forming a first mask layer on the blocking material layer; the first mask layer comprises a first opening exposing a top surface of the blocking material layer; forming a second mask layer in the first opening, and removing the first mask layer; the second mask layer comprises a second opening exposing a top surface of the blocking material layer; using the second mask layer as a mask to pattern the blocking material layer, to form a blocking layer for patterning the dielectric structure; the blocking layer comprises a third opening exposing a top surface of the dielectric structure; the third opening has a size greater than that of the second opening.

A semiconductor structure includes multi-tier layer stacks laterally spaced apart by lateral isolation structures. Each multi-tier layer stack includes a first-tier alternating stack of first insulating layers and first electrically conductive layers, and a second-tier alternating stack of second insulating layers and second electrically conductive layers overlying the first-tier alternating stack. The semiconductor structure also includes a first memory array region and a second memory array region laterally spaced apart by an inter-array region. Memory opening fill structures vertically extend through the multi-tier layer stacks in the memory array regions. One of the lateral isolation structures may include a combination of a dielectric wall structure and at least one second-tier dielectric pillar structure. Alternatively, one of the lateral isolation structures may include a combination of dielectric wall structures, a first-tier retro-stepped dielectric material portion, and a second-tier dielectric material portion.

In an embodiment, a semiconductor device includes a semiconductor substrate having a first major surface, a trench extending from the first major surface into the semiconductor substrate and having a base and a side wall extending from the base to the first major surface. A conductive member is arranged in the trench and spaced apart from the side wall of the trench by a dielectric structure that is located in the trench. The dielectric structure includes a first chamber located at the base of the trench. The conductive member has a side wall having an inner surface and an outer surface. The inner surface surrounds a second chamber that is in fluid communication with the first chamber.

In one example, an electronic device includes an electronic component including a first side, a second side opposite to the first side, a lateral side connecting the first side to the second side, bond pads adjacent to the first side, and a passivation layer over the first side and including openings exposing the bond pads. A redistribution structure is over the passivation layer and the bond pads. The redistribution structure includes a conductive structure coupled to the bond pads and a dielectric structure. The conductive structure includes outward terminals. External interconnects are coupled to the outward terminals and a protection layer covers the lateral side of the electronic component. Other examples and related methods are also disclosed herein.

A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor structure laterally spaced apart from a second semiconductor structure and a dielectric structure laterally between the first semiconductor structure and the second semiconductor structure. The dielectric structure has an inner portion and an outer layer extending along a sidewall of the inner portion. Average grain sizes of the outer layer and the inner portion are different. A topmost surface of the inner portion is vertically spaced apart from a topmost surface of the outer layer.

A semiconductor device includes a semiconductor substrate, at least two source / drain features, at least two source / drain features, one or more channel layers, a gate structure, a first conductive feature, a second conductive feature, and an alignment mark. The semiconductor substrate has a first region and a second region next to the first region. The at least two source / drain features are disposed in the second region and are laterally arranged to each other. The one or more channel layers are disposed in the second region and connect the at least two source / drain features. The gate structure is disposed in the second region and engages the one or more channel layers and interposes the at least two source / drain features. The first conductive feature is disposed in the second region and is electrically coupled to the at least two source / drain features. The second conductive feature is disposed in the second region and is electrically coupled to the at least two source / drain features through the first conductive feature. The alignment mark is disposed in the first region and includes a first dielectric feature and a third conductive feature lining a bottom and a sidewall of the first dielectric feature.

The invention relates to a method for producing an electronic component. The method comprises: forming a first semiconductor layer of a first material on a substrate of a second material, wherein the first material differs from the second material; forming a dielectric structure on the first semiconductor layer, wherein the dielectric structure has a plurality of openings, and in the openings the first semiconductor layer is exposed; epitaxially forming a second semiconductor layer on the first semiconductor layer, which in the openings is exposed, and at least in a region above the dielectric structure, wherein the second semiconductor layer comprises or is formed from the first material; and forming a third semiconductor layer on or above the second semiconductor layer in a first region above the openings of the dielectric structure and in a second region above the dielectric structure. The method also comprises: forming a sacrificial structure on the second semiconductor layer; forming the third semiconductor layer on the sacrificial structure; and removing the sacrificial structure such that the third semiconductor layer is separated from the second semiconductor layer.

Integrated circuit structures having uniform grid metal gate and trench contact placeholder cut and non-selective fin trim isolation (FTI) are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires or a fin. A gate structure is over the vertical stack of horizontal nanowires or the fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure. A dielectric gate cut plug is laterally between and in contact with the gate structure and the dielectric structure. The dielectric structure has an uppermost surface above an uppermost surface of the dielectric gate cut plug.