419 results about "Dielectric structure" patented technology

A broadband omni-directional bicone antenna. The antenna can comprise conductive surfaces of conical voids provided within a solid dielectric structure. The outside surface of the solid structure can support a radio frequency (RF) lens geometry operable for beam forming. The beam forming can modify the elevation pattern of the electromagnetic radiation from the bicone antenna. The solid dielectric structure may be machined or molded from a single piece of material. The conical voids provided within the solid structure can be metallized to provide conductive bicone radiators. The outer surface beam shaping lenses can be zoned or continuous and can provide elevation patterns with increased gain, cosecant squared falloff, or various other patterns. The beam shaping lens may be formed from any low-loss dielectric. Alternatively, the lens may be formed from a less dense material such as dielectric foam that can support radial conductive beam forming vanes.

The invention relates to an anti-ant large-core-number fiber ribbon cable comprising a cable core and an outer sheath. The cable core includes loose tubes; and fiber ribbons are sleeved inside the loose tubes. The outer sheath is an outer nylon sheath; and a non-metallic reinforcement layer is arranged between the outer sheath and the cable core. According to the anti-ant large-core-number fiber ribbon cable provided by the invention, with the outer nylon sheath, ants can not bite the sheath, so that the damages on the optical cable by ant biting in a pipe at an area with a serious anti problem are prevented, the normal state of the cable is ensured, and the application region of the cable is extended. The cable based on a simple and reasonable structure has advantages of small cable diameter, high fiber density, large fiber capacity, and low duty ratio and can be laid in a pipe conveniently; and the bending performance is good. During branched connection, 4 to 24 fibers can be melted once, so that the construction time is saved and the manpower cost is lowered, and the construction efficiency is improved. On the basis of the full drying type dielectric structure, branched connection is realized conveniently and usage becomes convenient.

Various embodiments of the present disclosure are directed towards an integrated circuit (IC) device including a dielectric structure on a semiconductor substrate. A plurality of active bond pads are disposed in the dielectric structure. A plurality of auxiliary bond pads are disposed in the dielectric structure and are laterally offset from the plurality of active bond pads by a first distance greater than a pitch of the plurality of active bond pads. The active bond pads are respectively electrically coupled to a corresponding auxiliary bond pad in the plurality of auxiliary bond pads.

The invention relates to the technical field of antennas, in particular to a millimeter wave three-beam all-dielectric lens antenna, which comprises a group of 2 * 2 magnetoelectric dipole array antennas and an all-dielectric circular lens structure, the 2 * 2 magnetoelectric dipole array antenna is used as a feed source and is arranged on the plane side of the all-dielectric circular lens structure, and the feed source directly faces the geometric center of the all-dielectric circular lens structure; the all-dielectric circular lens structure has a direction-controllable three-beam radiation capability; through the reasonable medium structure layout, the multi-beam coverage and the frequency point adaptability are considered while high-gain output is ensured, and the contradiction between the performance and the practicability of the existing scheme is overcome.

The invention discloses a computing spectrum reconstruction method based on CS-Unet and a spectral imaging system. The calculation spectrum reconstruction method comprises two parts, namely TwIST pre-reconstruction and Unet coupling reconstruction, wherein the TwIST pre-reconstruction is used for preprocessing an initial coding spectrum image to generate a pre-reconstructed spectrum image; and the Unet part couples the pre-reconstructed image and the initial coding spectral image in the spectral dimension and inputs the coupled image and the initial coding spectral image into a network for fine reconstruction, and finally a target space-spectral image is recovered. The imaging system is composed of a spectral image coding module and a CS-Unet reconstruction module, a metasurface spectral modulator applied to the spectral image coding module is composed of 36 silicon-based all-dielectric structures, and rich spectral response is achieved by adjusting the period, the size and the direction angle of three basic C4 symmetric units, namely a round unit, a cross unit and a square unit. According to the method, high-robustness and high-imaging-quality spectrum reconstruction is realized in a visible light wave band (400-700 nm), and the method has relatively high engineering applicability.

Isolation structures between transistors in integrated circuit (IC) devices. An IC device includes transistors coupled to an interconnect network, and between the transistors a dielectric structure with a wider width away from the interconnect network and a narrower width nearer the interconnect network. Dielectric structures with wider back-side widths may separate gate electrodes and / or source and drain contacts of the transistors. The dielectric structures may be formed by etching an opening between metallization structures of the transistors from a back side of the device substrate and by depositing liner and fill dielectrics over the back-side opening.

A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a substrate, a word line structure, a dielectric structure, a contact plug, and a sidewall insulating layer. The substrate includes an active region. The word line structure is disposed in the substrate and in the active region. The dielectric structure is disposed on the word line structure. The contact plug is disposed on the substrate and in the active region. The contact plug includes a first conductive pillar disposed on the substrate and a second conductive pillar disposed on the first conductive pillar. The sidewall insulating layer is disposed on an upper portion of a sidewall of the contact plug. The sidewall insulating layer is in contact with the first conductive pillar, the second conductive pillar, and the dielectric structure.

Integrated circuit structures having uniform grid metal gate and trench contact placeholder cut and non-selective fin trim isolation (FTI) are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires or a fin. A gate structure is over the vertical stack of horizontal nanowires or the fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure. A dielectric gate cut plug is laterally between and in contact with the gate structure and the dielectric structure. The dielectric structure has an uppermost surface above an uppermost surface of the dielectric gate cut plug.

A method for forming a semiconductor structure includes following operations. An interconnect structure is formed over a substrate. The interconnect structure includes a top conductive layer. A dielectric structure is formed over the interconnect structure. The dielectric structure is patterned to simultaneously form a cavity and a protrusion in the cavity. A MEMS substrate is bonded to the dielectric structure to seal the cavity. The protrusion is separated from the MEMS substrate.

Embodiments of the present application provide a semiconductor structure manufacturing method and a semiconductor structure. The manufacturing method comprises: providing a substrate; the substrate comprises a substrate, a dielectric structure on the substrate, and a blocking material layer on the dielectric structure; the dielectric structure comprises at least one dielectric layer; forming a first mask layer on the blocking material layer; the first mask layer comprises a first opening exposing a top surface of the blocking material layer; forming a second mask layer in the first opening, and removing the first mask layer; the second mask layer comprises a second opening exposing a top surface of the blocking material layer; using the second mask layer as a mask to pattern the blocking material layer, to form a blocking layer for patterning the dielectric structure; the blocking layer comprises a third opening exposing a top surface of the dielectric structure; the third opening has a size greater than that of the second opening.

A semiconductor structure includes multi-tier layer stacks laterally spaced apart by lateral isolation structures. Each multi-tier layer stack includes a first-tier alternating stack of first insulating layers and first electrically conductive layers, and a second-tier alternating stack of second insulating layers and second electrically conductive layers overlying the first-tier alternating stack. The semiconductor structure also includes a first memory array region and a second memory array region laterally spaced apart by an inter-array region. Memory opening fill structures vertically extend through the multi-tier layer stacks in the memory array regions. One of the lateral isolation structures may include a combination of a dielectric wall structure and at least one second-tier dielectric pillar structure. Alternatively, one of the lateral isolation structures may include a combination of dielectric wall structures, a first-tier retro-stepped dielectric material portion, and a second-tier dielectric material portion.

In an embodiment, a semiconductor device includes a semiconductor substrate having a first major surface, a trench extending from the first major surface into the semiconductor substrate and having a base and a side wall extending from the base to the first major surface. A conductive member is arranged in the trench and spaced apart from the side wall of the trench by a dielectric structure that is located in the trench. The dielectric structure includes a first chamber located at the base of the trench. The conductive member has a side wall having an inner surface and an outer surface. The inner surface surrounds a second chamber that is in fluid communication with the first chamber.

In one example, an electronic device includes an electronic component including a first side, a second side opposite to the first side, a lateral side connecting the first side to the second side, bond pads adjacent to the first side, and a passivation layer over the first side and including openings exposing the bond pads. A redistribution structure is over the passivation layer and the bond pads. The redistribution structure includes a conductive structure coupled to the bond pads and a dielectric structure. The conductive structure includes outward terminals. External interconnects are coupled to the outward terminals and a protection layer covers the lateral side of the electronic component. Other examples and related methods are also disclosed herein.

A semiconductor device includes a semiconductor substrate, at least two source / drain features, at least two source / drain features, one or more channel layers, a gate structure, a first conductive feature, a second conductive feature, and an alignment mark. The semiconductor substrate has a first region and a second region next to the first region. The at least two source / drain features are disposed in the second region and are laterally arranged to each other. The one or more channel layers are disposed in the second region and connect the at least two source / drain features. The gate structure is disposed in the second region and engages the one or more channel layers and interposes the at least two source / drain features. The first conductive feature is disposed in the second region and is electrically coupled to the at least two source / drain features. The second conductive feature is disposed in the second region and is electrically coupled to the at least two source / drain features through the first conductive feature. The alignment mark is disposed in the first region and includes a first dielectric feature and a third conductive feature lining a bottom and a sidewall of the first dielectric feature.

Integrated circuit structures having uniform grid metal gate and trench contact placeholder cut and non-selective fin trim isolation (FTI) are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires or a fin. A gate structure is over the vertical stack of horizontal nanowires or the fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure. A dielectric gate cut plug is laterally between and in contact with the gate structure and the dielectric structure. The dielectric structure has an uppermost surface above an uppermost surface of the dielectric gate cut plug.

The method of forming the semiconductor device includes the following steps. An isolation structure is formed between a plurality of active areas. Semiconductor structures are formed over the active areas, and a portion of each semiconductor structure is embedded in the isolation structure. Sacrificial structures are formed on the semiconductor structures. An ion implantation process is performed to form implanted regions between the portions of the semiconductor structures embedded in the isolation structure. The sacrificial structures are removed to form patterned semiconductor structures. A dielectric structure is formed on the patterned semiconductor structure. A control structure is formed on the dielectric structure.

The integrated circuit comprises a semiconductor substrate (SUB) having a front face (FA) with insulation structures (STI) extending vertically into the substrate from the front face to a first depth (P1), and an interconnect portion (BE) comprising metal layers incorporating at least one passive component (LHQ), located above the front face (FA) of the substrate. The integrated circuit further comprises a dielectric structure (BLMN) aligned vertically with the position of said at least one passive component (LHQ), and extending vertically into the substrate from the front face to a second depth (P2) greater than the first depth (P1). (See Figure 8 for abbreviations.)

Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly contact structures in LED chips for reducing voiding of bonding metals are disclosed. LED chips include active LED structures on carrier submounts and contact structures arranged to receive external electrical connections adjacent the active LED structures. Exemplary contact structures include contacts electrically coupled to active LED structures and dielectric structures beneath the contacts. Dielectric structures are arranged beneath portions of the contacts while still allowing electrical connections therethrough. Such dielectric structures may be provided as regions of dielectric material with spacings that control topography of underlying bonding metals to reduce voiding.

Techniques are provided herein to form semiconductor devices with gate structures that do not extend below a top surface of dielectric subregions. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. A lower end of the fin of semiconductor material includes a subfin adjacent to a dielectric fill. A sacrificial material layer is deposited before the formation of the gate structure to prevent the gate structure from forming along the sides of the subfin. This sacrificial layer may then be removed from the backside of the structure along with the semiconductor material of the subfin. The subfin area may be replaced with one or more dielectric materials formed on the backside. As a result, the device performance is improved by lowering the parasitic capacitance caused by having the gate structure on either side of the dielectric structure replacing the subfin region.

A method of fabricating a semiconductor device includes forming a first active region and a second active region over a substrate, depositing an isolation structure between the first and second active regions, forming a gate structure across the first active region and the second active region, forming a trench dividing the gate structure into a first segment and a second segment, depositing a dielectric feature in the trench, thinning the substrate and the isolation structure to expose a bottom surface of the dielectric feature, selectively removing a surface layer of the dielectric feature to form an air gap, and depositing a seal layer capping the air gap.

The application discloses a gallium nitride transistor and a preparation method thereof, and relates to the technical field of semiconductor devices. The gallium nitride transistor comprises a substrate, a plurality of superlattice structures arranged in sequence on one side of the substrate, and interval cavities between adjacent two superlattice structures. The superlattice structure comprises a channel layer and a barrier layer arranged in a stack. The channel layer and the barrier layer of each second superlattice structure, the barrier layer of a first superlattice structure, and a first groove and a second groove located on opposite sides of each superlattice structure are penetrated. A source and a drain are respectively located in the first groove and the second groove and are in contact with each superlattice structure. A dielectric structure is located between the source and the drain, is located in each interval cavity, and covers the surface of each superlattice structure. A gate is located between the source and the drain and is arranged around the dielectric structure. According to the technical scheme, the gate around the dielectric structure covering the surface of each superlattice structure is arranged, and the control effect of the gate on the conductive channel layer is improved.

Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate; semiconductor layers over the substrate, wherein the semiconductor layers are separate from each other and are stacked up along a direction generally perpendicular to a top surface of the substrate; a dielectric feature over and separate from the semiconductor layers; and a gate structure wrapping around each of the semiconductor layers, the gate structure having a gate dielectric layer and a gate electrode layer, wherein the gate dielectric layer interposes between the gate electrode layer and the dielectric feature and the dielectric feature is disposed over at least a part of the gate electrode layer.

The present application relates to the technical field of memories. Disclosed are a three-dimensional dynamic random access memory and a manufacturing method therefor, which are used for increasing the storage density of dynamic random access memories, and increasing the contact area between a source region of a transistor and a contact structure or a capacitor as well as between a drain region of a transistor and a contact structure or a capacitor, thereby reducing contact resistance, and ameliorating electric leakage. The three-dimensional dynamic random access memory comprises a plurality of memory cells distributed in a three-dimensional array and a dielectric structure used for isolating different memory cells; each memory cell comprises a transistor and a capacitor, the transistor comprising a gate, a gate dielectric layer, a channel region, a source region and a drain region; the length direction of each channel region is parallel to a second direction, and two sidewalls of each channel region in the length direction are recessed inward with respect to sidewalls of a corresponding first dielectric portion, so as to form recesses; the source regions and the drain regions cover inner walls of the recesses. The manufacturing method for a three-dimensional dynamic random access memory is used for manufacturing the described three-dimensional dynamic random access memory.

In one example, an electronic device comprises a substrate comprising a first side, a second side opposite to the first side, a dielectric structure, and a conductive structure, a first electronic component over the first side of the substrate, wherein the first electronic component comprises an image component at a first side of the first electronic component facing away from the substrate, and an encapsulant over the first side of the substrate and over the first side of the first electronic component. The encapsulant defines a cavity over the first side of the first electronic component, and the image component is exposed in the cavity. The electronic device further comprises an interconnect in the encapsulant and coupled with the first electronic component and the conductive structure, and a lid over the cavity and covering the image component. Other examples and related methods are also disclosed herein.

The invention provides a long-wave infrared laser reflector with a three-medium structure. The long-wave infrared laser reflector structurally comprises a substrate Sub, a transition layer B, a metal layer G, a medium film system C and an air layer A from bottom to top. The dielectric film system C is structurally characterized by being formed by alternately stacking one or more groups of materials with high, medium and low refractive indexes. The invention aims to realize high reflection of a long-wave infrared band. Through meticulous design, three kinds of materials with high, medium and low refractive indexes are reasonably distributed in the reflector. According to the strategy, the absorption of the reflector is effectively reduced by balancing the low absorption of the chalcogenide and the low refractive index of the fluoride, the temperature rise caused by heat absorption is remarkably reduced, and meanwhile, the reflectivity is improved. Therefore, the continuous laser damage threshold value of the reflecting mirror is greatly enhanced theoretically, and the reflecting mirror shows higher stability and tolerance when facing continuous laser irradiation.

Some embodiments relate to an integrated circuit device having an IC layer including a plurality of pixel cell groups. Each pixel cell group includes a plurality of pixel cells arranged in a 2-by-2 configuration. Each pixel cell includes a photodetector in a substrate, and a transfer transistor electrically coupled to the photodetector and configured to transfer electrical charge collected at the photodetector across a first surface of the substrate. The IC layer further includes at least one dielectric structure extending from the first surface to a second surface of the substrate and separating each pixel cell from neighboring pixel cells. The dielectric structure includes a first gap disposed at a common corner of the pixel cells. A conductive structure is electrically connected to at least one of the photodetector or the transfer transistor of each of the pixel cells and is disposed in the first gap over the first surface.

A memory device includes a plurality of memory cells, each of the plurality of memory cells configured to store a data bit; a first interconnect structure operatively configured as a bit line and coupled to each of the plurality of memory cells; and a second interconnect structure operatively configured to carry a supply voltage and coupled to each of the plurality of memory cells. The data bit stored by a first one of the plurality of memory cells presents a first logic state when the first memory cell includes a first channel structure, with a first end and a second end of the first channel structure connected to a first epitaxial structure and a second epitaxial structure, respectively, and wherein the first epitaxial structure is overlaid by a dielectric structure and the second epitaxial structure is overlaid by a first contact structure.

A mask layer is formed over the dielectric structure. The mask layer includes an opening exposing a portion of the dielectric structure. A protective layer is formed on the mask layer. The protective layer covers at least side surfaces of the opening. After the protective layer is formed, a directional etching process is performed on the mask layer. The directional etch process is performed in a first direction while the protective layer protects the mask layer from etching in a second direction different from the first direction, such that after the directional etch process has been performed, the opening expands in the first direction without being substantially affected in the second direction. After the opening is enlarged in the first direction, the opening extends vertically into the dielectric structure. A conductive via is formed in the opening. Embodiments of the invention relate to an integrated circuit device and a method of forming the same.

Systems, devices, and methods are provided for managing a capacitor capping layer in a semiconductor device. In one aspect, a semiconductor device includes a transistor having a semiconductor body extending in a first direction and a gate structure adjacent to the semiconductor body. A capacitor is coupled to the transistor. The capacitor extends in a first direction and includes a first electrode, a second electrode, and a dielectric structure. The isolation spacer layer is located between the transistor and the capacitor in the first direction. The first electrode includes a first portion extending between both ends of the isolation spacer layer in the first direction, and a second portion extending away from the transistor in the first direction from the first portion. A width of the first portion in a second direction perpendicular to the first direction is greater than an outer dimension of the second portion in the second direction.

Integrated circuit structures with voltage-inducing fin-trim isolation regions bounded by gate cuts are described. An example of such an integrated circuit structure is one with a vertical stack of horizontal nanowires or a fin above a first sub-fin. A gate structure is located above the vertical stack of horizontal nanowires or the fin. A dielectric structure is spaced laterally from the gate structure. The dielectric structure is not located above a channel structure but rather on a second sub-fin. The dielectric structure induces a voltage on the vertical stack of horizontal nanowires or the fin. A dielectric gate-cut plug is in contact with both the gate structure and the dielectric structure and extends through from the gate structure to the dielectric structure.