871 results about "Dielectric structure" patented technology

A broadband omni-directional bicone antenna. The antenna can comprise conductive surfaces of conical voids provided within a solid dielectric structure. The outside surface of the solid structure can support a radio frequency (RF) lens geometry operable for beam forming. The beam forming can modify the elevation pattern of the electromagnetic radiation from the bicone antenna. The solid dielectric structure may be machined or molded from a single piece of material. The conical voids provided within the solid structure can be metallized to provide conductive bicone radiators. The outer surface beam shaping lenses can be zoned or continuous and can provide elevation patterns with increased gain, cosecant squared falloff, or various other patterns. The beam shaping lens may be formed from any low-loss dielectric. Alternatively, the lens may be formed from a less dense material such as dielectric foam that can support radial conductive beam forming vanes.

The invention relates to a modeling and optimizing method for inter-layer signal crosstalk of a PCB (Printed Circuit Board). Frequency response data of all dielectric layers of the PCB under different temperature and humidity conditions are collected, and a mapping model with the temperature gradient and the humidity diffusion gradient as input and the dielectric constant as output is established. And calculating the dynamic distribution of mutual capacitance and mutual inductance under the environment change by combining the spatial layout parameters of the differential signal pair, and constructing a crosstalk sensitivity evaluation model with coupled frequency, environment and layout. And high-risk areas with crosstalk sensitivity caused by environment change are identified, and the crosstalk change rate of each area is quantified. For a sensitive area, a temperature and humidity compensation medium structure is introduced to stabilize local dielectric characteristics and reduce the influence of the environment on crosstalk. And according to the compensated medium distribution, adjusting a differential signal wiring path and impedance matching by adopting an optimization method with the aim of minimizing the crosstalk change rate, and generating a wiring layout with environmental robustness. According to the invention, the signal integrity and the transmission reliability of the multi-layer PCB in a temperature and humidity changing environment can be effectively improved.

The invention relates to an anti-ant large-core-number fiber ribbon cable comprising a cable core and an outer sheath. The cable core includes loose tubes; and fiber ribbons are sleeved inside the loose tubes. The outer sheath is an outer nylon sheath; and a non-metallic reinforcement layer is arranged between the outer sheath and the cable core. According to the anti-ant large-core-number fiber ribbon cable provided by the invention, with the outer nylon sheath, ants can not bite the sheath, so that the damages on the optical cable by ant biting in a pipe at an area with a serious anti problem are prevented, the normal state of the cable is ensured, and the application region of the cable is extended. The cable based on a simple and reasonable structure has advantages of small cable diameter, high fiber density, large fiber capacity, and low duty ratio and can be laid in a pipe conveniently; and the bending performance is good. During branched connection, 4 to 24 fibers can be melted once, so that the construction time is saved and the manpower cost is lowered, and the construction efficiency is improved. On the basis of the full drying type dielectric structure, branched connection is realized conveniently and usage becomes convenient.

A memory device includes a horizontal source layer which is laterally separated into laterally isolated portions located in adjacent memory blocks by a dielectric backside trench fill structure or a source isolation dielectric structure.

The present application discloses a memory device and a method for fabricating the memory device. The memory device includes a substrate; a landing area positioned on the substrate; a bottom electrode positioned on the landing area, wherein the bottom electrode has a container-shaped profile; a support layer positioned over the substrate and laterally surrounded the bottom electrode; a dielectric structure including a dielectric layer conformally positioned on the bottom electrode and on a top surface of the support layer, and covering top corners of the support layer, and a plurality of dielectric portions conformally positioned on the dielectric layer and covering the top corners of the support layer; and a top electrode structure positioned on the dielectric structure. The dielectric portions are sandwiched by the top electrode structure and the dielectric layer. The top surface of the third support layer is higher than a top surface of the bottom electrode.

The invention discloses a multi-pass optical filter and a preparation method thereof, and the method comprises the steps: selecting a main reference channel, and carrying out the difference frequency modulation excitation through narrow linewidth laser, and obtaining optical transmission coupling data; performing periodic disturbance detection on the observation channel to obtain spectrum drift associated data; modulating deposition power and air pressure according to the spectrum drift associated data to form a crosstalk suppression layer; forming a three-layer dielectric structure with increasing optical thickness and a periodically changing coupling regulation layer on the crosstalk suppression layer; and performing temperature modulation annealing treatment to form an inter-channel steady-state coupling structure, and establishing a spectrum drift compensation parameter. The technical scheme of the invention can systematically characterize the correlation drift of the multi-channel spectral characteristic along with the micro process or service disturbance, accurately quantify the coupling relationship between different passbands, and solve the technical problem that the correlation drift between the passbands cannot be completely captured in the existing discrete measurement mode. The phenomenon of'array misfocus' in a miniature multispectral system is effectively avoided, and the precision and stability of the multi-pass optical filter are improved.

The invention discloses an all-dielectric structure type broadband wave-absorbing metamaterial and a design method thereof. The all-dielectric structure type broadband wave-absorbing metamaterial comprises a substrate and a plurality of resonators, the plurality of resonators are periodically and uniformly arrayed on the surface of the substrate, the adjacent resonators are connected with each other, each resonator comprises a pyramid structure unit and a grid structure unit, the pyramid structure units are nested in the grid structure units to form a pyramid-grid composite resonator, and the substrate and the resonators are both made of a high dielectric loss composite material. Based on the brand new design angle of wave absorbing performance complementation, the limitation of the wave absorbing performance of a single structure is broken through, the wave absorbing performance is improved from the microstructure level, meanwhile, efficient electromagnetic wave energy absorption is achieved in a wider frequency range, multi-stage dissipation and broadband impedance matching of incident electromagnetic waves are achieved, and the wave absorbing performance is improved. And the technical limitation of thickness constraint and narrow-band response of the traditional wave-absorbing material is broken through.

Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions, and methods of fabricating neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions, are described. For example, a structure includes first and second vertical arrangements of nanowires, the nanowires of the second vertical arrangement of nanowires having a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires. First and second gate stacks are over the first and second vertical arrangements of nanowires, respectively. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires, and second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening dielectric structure is between neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures.

The invention relates to a semiconductor structure, a semiconductor device and a forming method thereof. The present disclosure describes a semiconductor device having a semiconductor seed layer on an S / D dielectric structure. The semiconductor structure comprises a channel structure on a substrate; a gate structure surrounding the channel structure; an internal spacer adjacent to ends of the gate structure and the channel structure; a dielectric structure on the substrate and adjacent to the internal spacer; an amorphous semiconductor material on the dielectric structure; and an epitaxial structure on top surfaces of the amorphous semiconductor material and the dielectric structure.

Integrated circuit structures having void-free internal spacers, and methods of fabricating integrated circuit structures having void-free internal spacers, are described. For example, an integrated circuit structure includes a stack of horizontal nanowires. A gate structure is vertically around the stack of horizontal nanowires, the stack of horizontal nanowires extending laterally beyond the gate structure. An internal gate spacer is between vertically adjacent nanowires of the stack of horizontal nanowires and laterally adjacent to the gate structure. An epitaxial source or drain structure is coupled to an end of the stack of horizontal nanowires and in contact with the internal gate spacer. A dielectric structure is beneath and in contact with the epitaxial source or drain structure, the dielectric structure including a same material as the internal gate spacer, and the dielectric structure not including a seam therein.

The present invention discloses a plasma generating device and an electrical device, which relate to the field of plasma technology, wherein the plasma generating device comprises a dielectric structure, a first electrode and a second electrode, the dielectric structure covers the second electrode, a part of the dielectric structure is arranged as a planar dielectric layer, and the first electrode is arranged on a side of the planar dielectric layer away from the second electrode. The technical solution of the present application can avoid the plasma generating device from being too large in size under the condition of safe use of the plasma generating device.

The invention discloses a band-pass type active frequency selective surface based on double-element composite loading. The band-pass type active frequency selective surface comprises at least one resonance unit which is periodically arranged, the resonance unit sequentially comprises a top metal frequency selection surface layer, a first dielectric structure layer, a middle metal feed layer, a second dielectric structure layer and a bottom metal frequency selection surface layer from top to bottom; the top metal layer and the bottom metal layer are composed of square ring aperture grooves subjected to deformation processing, and the middle feed layer is of a cross zigzag metal structure, plays a role in coupling an electromagnetic field and serves as a bias network of the AFSS. And the metal through holes penetrate through the resonance units in the vertical direction, so that the middle layer feeder line can respectively provide reverse bias voltage for independently regulating and controlling the resonance frequency for the PINs and the variable capacitance diodes on the top layer and the bottom layer. According to the invention, the functions of band switching and wide-range frequency tuning can be met, so that the problem of insertion loss increase caused by limited design frequency regulation and control range and element loading of the AFSS in the prior art can be solved.

The present application discloses a memory device and a method for fabricating the memory device. The memory device includes a substrate; a landing area positioned on the substrate; a bottom electrode positioned on the landing area, wherein the bottom electrode has a container-shaped profile; a support layer positioned over the substrate and laterally surrounded the bottom electrode; a dielectric structure including a dielectric layer conformally positioned on the bottom electrode and on a top surface of the support layer, and covering top corners of the support layer, and a plurality of dielectric portions conformally positioned on the dielectric layer and covering the top corners of the support layer; and a top electrode structure positioned on the dielectric structure. The dielectric portions are sandwiched by the top electrode structure and the dielectric layer. The top surface of the third support layer is higher than a top surface of the bottom electrode.

The present disclosure provides a semiconductor device and a method of forming the same. A method according to one embodiment of the present disclosure includes forming a plurality of semiconductor nanostructures vertically stacked above a substrate, forming a dielectric structure suspended above a topmost one of the semiconductor nanostructures, forming a plurality of inner spacers interleaving the semiconductor nanostructures, forming an epitaxial feature abutting the semiconductor nanostructures, and forming a gate structure wrapping around each of the semiconductor nanostructures and the dielectric structure.

A transistor structure includes a field plate structure and a plurality of dielectric structures through the field plate structure. The dielectric structures may be arranged in a grid in a top view of the transistor structure. The dielectric structures enable the field plate structure to be positioned closer to a gate structure of the transistor than without the dielectric structures, which enables the length of the field plate structure to be increased without increasing the overall length (or with minimal length increase) of the transistor.

A semiconductor device according to an embodiment of the present disclosure includes a substrate, a first epitaxial electrode layer disposed on the substrate, a ferroelectric epitaxial layer disposed on the first epitaxial electrode layer, a dielectric epitaxial layer disposed on the ferroelectric epitaxial layer, and a second epitaxial electrode layer disposed on the dielectric epitaxial layer. The ferroelectric epitaxial layer implements a negative capacitance. Each of the first and second epitaxial electrode layers includes conductive pyrochlore oxide. The ferroelectric epitaxial layer and the dielectric epitaxial layer are electrically connected in series is non-ferroelectric. A dielectric structure comprising the ferroelectric epitaxial layer and the dielectric epitaxial layer is non-ferroelectric.

A semiconductor device structure and method for manufacturing the same are provided. The semiconductor device structure includes a substrate, a dielectric structure, a pad, a conductive structure, and a buffer structure. The dielectric structure is disposed on the substrate. The pad is embedded in the dielectric structure. The conductive structure is disposed on the pad. The buffer structure is disposed on the pad and separates the conductive structure from the dielectric structure. A coefficient of thermal expansion (CTE) of the buffer structure ranges between a CTE of the dielectric structure and a CTE of the conductive structure.

A semiconductor structure and method of forming the same are provided. The semiconductor structure includes a circuit structure, an interlayer structure and a memory structure. The circuit structure includes a substrate having semiconductor devices formed thereon; a dielectric structure disposed over the semiconductor devices; and an interconnect layer embedded in the dielectric structure and connected to the semiconductor devices. The interlayer structure is disposed over the circuit structure. The memory structure is disposed over the interlayer structure and physically separated from the circuit structure by the interlayer structure.

Various embodiments of the present disclosure are directed towards an integrated chip having an interconnect structure overlying a substrate. The interconnect structure includes a conductive wire disposed in a dielectric structure. The conductive wire comprises a body structure. A passivation structure overlies the interconnect structure. A bond pad overlies the passivation structure. The bond pad comprises an upper pad structure on the passivation structure and a plurality of lower bond structures extending through the passivation structure to the conductive wire. The lower bond structures respectively comprise a vertical bond structure and a diffusion barrier layer disposed along a lower surface and opposing sidewalls of the vertical bond structure. The upper pad structure comprises a first conductive layer vertically stacked with a second conductive layer

In one example, an electronic device comprises a substrate comprising a dielectric structure and a conductive structure, a first electronic component over a top side of the substrate and coupled with the conductive structure, a lid over the first electronic component and coupled with a top side of the substrate, wherein the lid comprises a top plate having a plurality of holes, and a covering material covering a lateral side of the first electronic component and extending between the top side of the substrate and a bottom side of the top plate of the lid. Other examples and related methods are also disclosed herein.

A wrap-around dielectric structure prevents backside contacts shorting to gates in nanosheet field effect transistors (FETs). A method of making same includes providing a sacrificial layer under a nanosheet stack adjacent shallow trench isolation (STI) regions, recessing the STI regions' liner to from gaps in communication with the sacrificial layer, removing the sacrificial layer to form a cavity, and filling the cavity and gaps with a continuous dielectric material which wraps around a subsequently formed backside contact.

A diode is formed in an active region. The diode includes a P-type component embedded in a first portion of the active region, an N-type component embedded in a second portion of the active region, and an undoped component disposed between the P-type component and the N-type component. An interconnect structure is formed over a first side of the diode. Different portions of the interconnect structure are electrically coupled to the P-type component and the N-type component, respectively. One or more openings are etched through a dielectric structure disposed over a second side of the diode opposite the first side. A dopant material is implanted into the active region through the one or more openings. The one or more openings are filled with a conductive material.

Various embodiments of the present disclosure are directed towards an integrated circuit (IC) device including a dielectric structure on a semiconductor substrate. A plurality of active bond pads are disposed in the dielectric structure. A plurality of auxiliary bond pads are disposed in the dielectric structure and are laterally offset from the plurality of active bond pads by a first distance greater than a pitch of the plurality of active bond pads. The active bond pads are respectively electrically coupled to a corresponding auxiliary bond pad in the plurality of auxiliary bond pads.

Integrated circuit structures having front-side-cut backside source or drain contacts are described. In an example, an integrated circuit structure includes a first gate stack over a first plurality of horizontally stacked nanowires or fin, and a second gate stack over a second plurality of horizontally stacked nanowires or fin. A first epitaxial source or drain structure is at an end of the first plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure having a backside contact structure thereon. A second epitaxial source or drain structure is at an end of the second plurality of horizontally stacked nanowires or fin, the second epitaxial source or drain structure having a backside dielectric structure thereon, the backside dielectric structure laterally spaced apart from the backside contact structure. A dielectric gate cut plug is laterally between and in contact with the backside dielectric structure and the backside contact structure.

A die includes: a semiconductor substrate having a front side and an opposing back side; a dielectric structure including a substrate oxide layer disposed on the front side of the semiconductor substrate and interlayer dielectric (ILD) layers disposed on the substrate oxide layer; an interconnect structure disposed in the dielectric structure; a through-silicon via (TSV) structure extending in a vertical direction from the back side of the semiconductor substrate through the front side of the semiconductor substrate, such that a first end of the TSV structure is disposed in the interconnect structure; and a TSV barrier structure including a barrier line that contacts the first end of the TSV structure, and a first seal ring disposed in the substrate oxide layer and that surrounds the TSV structure in a lateral direction perpendicular to the vertical direction.

A method of forming an electrode with multi-dielectric layers includes: forming a metal pattern on a substrate, in which the metal pattern includes a first metal film on the substrate and a second metal film on a top surface of the first metal film, and the first and second metal films have different metal compositions; and anodizing the metal pattern in a liquid electrolyte to form a covering anodized portion which covers an unanodized portion, in which the covering anodized portion includes a sidewall oxide dielectric structure and a top oxide dielectric structure, the sidewall oxide dielectric structure is in contact with a side surface of the unanodized portion, the top oxide dielectric structure is in contact with top surfaces of the unanodized portion and the sidewall oxide dielectric structure, and the sidewall and top oxide dielectric structures have different effective permittivities.

The invention relates to the technical field of antennas, in particular to a millimeter wave three-beam all-dielectric lens antenna, which comprises a group of 2 * 2 magnetoelectric dipole array antennas and an all-dielectric circular lens structure, the 2 * 2 magnetoelectric dipole array antenna is used as a feed source and is arranged on the plane side of the all-dielectric circular lens structure, and the feed source directly faces the geometric center of the all-dielectric circular lens structure; the all-dielectric circular lens structure has a direction-controllable three-beam radiation capability; through the reasonable medium structure layout, the multi-beam coverage and the frequency point adaptability are considered while high-gain output is ensured, and the contradiction between the performance and the practicability of the existing scheme is overcome.

The invention discloses a computing spectrum reconstruction method based on CS-Unet and a spectral imaging system. The calculation spectrum reconstruction method comprises two parts, namely TwIST pre-reconstruction and Unet coupling reconstruction, wherein the TwIST pre-reconstruction is used for preprocessing an initial coding spectrum image to generate a pre-reconstructed spectrum image; and the Unet part couples the pre-reconstructed image and the initial coding spectral image in the spectral dimension and inputs the coupled image and the initial coding spectral image into a network for fine reconstruction, and finally a target space-spectral image is recovered. The imaging system is composed of a spectral image coding module and a CS-Unet reconstruction module, a metasurface spectral modulator applied to the spectral image coding module is composed of 36 silicon-based all-dielectric structures, and rich spectral response is achieved by adjusting the period, the size and the direction angle of three basic C4 symmetric units, namely a round unit, a cross unit and a square unit. According to the method, high-robustness and high-imaging-quality spectrum reconstruction is realized in a visible light wave band (400-700 nm), and the method has relatively high engineering applicability.

The invention provides a magnetically soft alloy-based wave-absorbing composite material as well as a preparation method and application thereof, and belongs to the technical field of electromagnetic wave absorbing materials. The wave-absorbing composite material provided by the invention comprises various magnetically soft alloy substrates prepared from elements such as iron, cobalt, nickel and the like and nitrogen-doped carbon coating the surfaces of the magnetically soft alloy substrates. The coercive force of the soft magnetic alloy is relatively low, so that the magnetic domain wall movement and magnetic moment rotation resistance in the material are reduced, the magnetic conductivity is relatively high, and the nitrogen-doped carbon with high dielectricity is combined to construct a magnetic-dielectric structure, so that the impedance matching between the composite material and the space is improved, and the efficient absorption of electromagnetic waves is promoted. The magnetically soft alloy-based wave-absorbing composite material has the characteristics of strong electromagnetic wave absorption performance and wide absorption frequency band, and is simple in preparation technology and easy for large-scale production.

Disclosed is a semiconductor device comprising a first channel region, a first dielectric structure on the first channel region, a first metal pattern spaced apart from the first dielectric structure, and a first dipole structure between the first metal pattern and the first dielectric structure. The first dipole structure includes a first dipole layer and a second dipole layer. The first dipole layer includes a first dipole element. The second dipole layer includes a second dipole element different from the first dipole element. A maximum oxidation number of the first dipole element is different from a maximum oxidation number of the second dipole element.