1142 results about "Dielectric structure" patented technology

A broadband omni-directional bicone antenna. The antenna can comprise conductive surfaces of conical voids provided within a solid dielectric structure. The outside surface of the solid structure can support a radio frequency (RF) lens geometry operable for beam forming. The beam forming can modify the elevation pattern of the electromagnetic radiation from the bicone antenna. The solid dielectric structure may be machined or molded from a single piece of material. The conical voids provided within the solid structure can be metallized to provide conductive bicone radiators. The outer surface beam shaping lenses can be zoned or continuous and can provide elevation patterns with increased gain, cosecant squared falloff, or various other patterns. The beam shaping lens may be formed from any low-loss dielectric. Alternatively, the lens may be formed from a less dense material such as dielectric foam that can support radial conductive beam forming vanes.

The invention relates to a modeling and optimizing method for inter-layer signal crosstalk of a PCB (Printed Circuit Board). Frequency response data of all dielectric layers of the PCB under different temperature and humidity conditions are collected, and a mapping model with the temperature gradient and the humidity diffusion gradient as input and the dielectric constant as output is established. And calculating the dynamic distribution of mutual capacitance and mutual inductance under the environment change by combining the spatial layout parameters of the differential signal pair, and constructing a crosstalk sensitivity evaluation model with coupled frequency, environment and layout. And high-risk areas with crosstalk sensitivity caused by environment change are identified, and the crosstalk change rate of each area is quantified. For a sensitive area, a temperature and humidity compensation medium structure is introduced to stabilize local dielectric characteristics and reduce the influence of the environment on crosstalk. And according to the compensated medium distribution, adjusting a differential signal wiring path and impedance matching by adopting an optimization method with the aim of minimizing the crosstalk change rate, and generating a wiring layout with environmental robustness. According to the invention, the signal integrity and the transmission reliability of the multi-layer PCB in a temperature and humidity changing environment can be effectively improved.

The invention relates to an anti-ant large-core-number fiber ribbon cable comprising a cable core and an outer sheath. The cable core includes loose tubes; and fiber ribbons are sleeved inside the loose tubes. The outer sheath is an outer nylon sheath; and a non-metallic reinforcement layer is arranged between the outer sheath and the cable core. According to the anti-ant large-core-number fiber ribbon cable provided by the invention, with the outer nylon sheath, ants can not bite the sheath, so that the damages on the optical cable by ant biting in a pipe at an area with a serious anti problem are prevented, the normal state of the cable is ensured, and the application region of the cable is extended. The cable based on a simple and reasonable structure has advantages of small cable diameter, high fiber density, large fiber capacity, and low duty ratio and can be laid in a pipe conveniently; and the bending performance is good. During branched connection, 4 to 24 fibers can be melted once, so that the construction time is saved and the manpower cost is lowered, and the construction efficiency is improved. On the basis of the full drying type dielectric structure, branched connection is realized conveniently and usage becomes convenient.

A memory device includes a horizontal source layer which is laterally separated into laterally isolated portions located in adjacent memory blocks by a dielectric backside trench fill structure or a source isolation dielectric structure.

The present application discloses a memory device and a method for fabricating the memory device. The memory device includes a substrate; a landing area positioned on the substrate; a bottom electrode positioned on the landing area, wherein the bottom electrode has a container-shaped profile; a support layer positioned over the substrate and laterally surrounded the bottom electrode; a dielectric structure including a dielectric layer conformally positioned on the bottom electrode and on a top surface of the support layer, and covering top corners of the support layer, and a plurality of dielectric portions conformally positioned on the dielectric layer and covering the top corners of the support layer; and a top electrode structure positioned on the dielectric structure. The dielectric portions are sandwiched by the top electrode structure and the dielectric layer. The top surface of the third support layer is higher than a top surface of the bottom electrode.

The invention discloses a multi-pass optical filter and a preparation method thereof, and the method comprises the steps: selecting a main reference channel, and carrying out the difference frequency modulation excitation through narrow linewidth laser, and obtaining optical transmission coupling data; performing periodic disturbance detection on the observation channel to obtain spectrum drift associated data; modulating deposition power and air pressure according to the spectrum drift associated data to form a crosstalk suppression layer; forming a three-layer dielectric structure with increasing optical thickness and a periodically changing coupling regulation layer on the crosstalk suppression layer; and performing temperature modulation annealing treatment to form an inter-channel steady-state coupling structure, and establishing a spectrum drift compensation parameter. The technical scheme of the invention can systematically characterize the correlation drift of the multi-channel spectral characteristic along with the micro process or service disturbance, accurately quantify the coupling relationship between different passbands, and solve the technical problem that the correlation drift between the passbands cannot be completely captured in the existing discrete measurement mode. The phenomenon of'array misfocus' in a miniature multispectral system is effectively avoided, and the precision and stability of the multi-pass optical filter are improved.

In one example, an electronic device includes a substrate including a substrate outer side, a substrate inner side, a dielectric structure, and a conductive structure. An electronic component includes an upper side, a lower side opposite to the upper side and coupled to the substrate inner side; a lateral side connecting the upper side to the lower side; and a conductor on the upper side. A cover structure includes sidewalls coupled to the substrate inner side and an upper wall coupled to the sidewalls and comprising an inner side spaced apart from the conductor. A thermal interface material (TIM) contacts and is interposed between the conductor and the inner side of the upper wall. The TIM covers the conductor and the lateral side of the electronic component. Other examples and related methods are also disclosed herein.

The invention discloses an all-dielectric structure type broadband wave-absorbing metamaterial and a design method thereof. The all-dielectric structure type broadband wave-absorbing metamaterial comprises a substrate and a plurality of resonators, the plurality of resonators are periodically and uniformly arrayed on the surface of the substrate, the adjacent resonators are connected with each other, each resonator comprises a pyramid structure unit and a grid structure unit, the pyramid structure units are nested in the grid structure units to form a pyramid-grid composite resonator, and the substrate and the resonators are both made of a high dielectric loss composite material. Based on the brand new design angle of wave absorbing performance complementation, the limitation of the wave absorbing performance of a single structure is broken through, the wave absorbing performance is improved from the microstructure level, meanwhile, efficient electromagnetic wave energy absorption is achieved in a wider frequency range, multi-stage dissipation and broadband impedance matching of incident electromagnetic waves are achieved, and the wave absorbing performance is improved. And the technical limitation of thickness constraint and narrow-band response of the traditional wave-absorbing material is broken through.

A method of forming a microelectronic device comprises forming a microelectronic device structure. The microelectronic device structure comprises a stack structure comprising insulative structures and additional insulative structures vertically alternating with the insulative structures, a dielectric structure vertically extending partially through the stack structure, and a dielectric material vertically overlying and horizontally extending across the stack structure and the dielectric structure. Portions of at least the dielectric material and the dielectric structure are removed to form a trench vertically overlying and at least partially horizontally overlapping a remaining portion of the dielectric structure. The trench is substantially filled with additional dielectric material. Microelectronic devices, memory devices, and electronic systems are also described.

Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions, and methods of fabricating neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions, are described. For example, a structure includes first and second vertical arrangements of nanowires, the nanowires of the second vertical arrangement of nanowires having a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires. First and second gate stacks are over the first and second vertical arrangements of nanowires, respectively. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires, and second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening dielectric structure is between neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures.

A memory device includes a horizontal source layer laterally separated into laterally isolated portions located in adjacent memory blocks by a dielectric backside trench filling structure or a source isolation dielectric structure.

Some embodiments relate to an integrated chip include a conductive structure disposed within a dielectric structure. A first dielectric layer overlies the dielectric structure. A dielectric capping layer on the conductive structure. Opposing sidewalls of the dielectric capping layer are aligned with opposing sidewalls of the conductive structure. A second dielectric layer overlies the first dielectric layer and the dielectric capping layer, wherein the second dielectric layer directly contacts the opposing sidewalls of the dielectric capping layer, the opposing sidewalls of the conductive structure, and a top surface of the first dielectric layer.

The invention relates to a semiconductor structure, a semiconductor device and a forming method thereof. The present disclosure describes a semiconductor device having a semiconductor seed layer on an S / D dielectric structure. The semiconductor structure comprises a channel structure on a substrate; a gate structure surrounding the channel structure; an internal spacer adjacent to ends of the gate structure and the channel structure; a dielectric structure on the substrate and adjacent to the internal spacer; an amorphous semiconductor material on the dielectric structure; and an epitaxial structure on top surfaces of the amorphous semiconductor material and the dielectric structure.

Integrated circuit structures having void-free internal spacers, and methods of fabricating integrated circuit structures having void-free internal spacers, are described. For example, an integrated circuit structure includes a stack of horizontal nanowires. A gate structure is vertically around the stack of horizontal nanowires, the stack of horizontal nanowires extending laterally beyond the gate structure. An internal gate spacer is between vertically adjacent nanowires of the stack of horizontal nanowires and laterally adjacent to the gate structure. An epitaxial source or drain structure is coupled to an end of the stack of horizontal nanowires and in contact with the internal gate spacer. A dielectric structure is beneath and in contact with the epitaxial source or drain structure, the dielectric structure including a same material as the internal gate spacer, and the dielectric structure not including a seam therein.

The present invention discloses a plasma generating device and an electrical device, which relate to the field of plasma technology, wherein the plasma generating device comprises a dielectric structure, a first electrode and a second electrode, the dielectric structure covers the second electrode, a part of the dielectric structure is arranged as a planar dielectric layer, and the first electrode is arranged on a side of the planar dielectric layer away from the second electrode. The technical solution of the present application can avoid the plasma generating device from being too large in size under the condition of safe use of the plasma generating device.

The invention discloses a band-pass type active frequency selective surface based on double-element composite loading. The band-pass type active frequency selective surface comprises at least one resonance unit which is periodically arranged, the resonance unit sequentially comprises a top metal frequency selection surface layer, a first dielectric structure layer, a middle metal feed layer, a second dielectric structure layer and a bottom metal frequency selection surface layer from top to bottom; the top metal layer and the bottom metal layer are composed of square ring aperture grooves subjected to deformation processing, and the middle feed layer is of a cross zigzag metal structure, plays a role in coupling an electromagnetic field and serves as a bias network of the AFSS. And the metal through holes penetrate through the resonance units in the vertical direction, so that the middle layer feeder line can respectively provide reverse bias voltage for independently regulating and controlling the resonance frequency for the PINs and the variable capacitance diodes on the top layer and the bottom layer. According to the invention, the functions of band switching and wide-range frequency tuning can be met, so that the problem of insertion loss increase caused by limited design frequency regulation and control range and element loading of the AFSS in the prior art can be solved.

The invention discloses an aircraft bearing retainer guide surface lubricating oil film thickness ultrasonic measurement method and system, and belongs to the technical field of bearing lubricating oil film thickness measurement. The invention aims to solve the problem that the existing method cannot accurately measure the thickness of the aircraft bearing retainer guide surface lubricating oil film. Comprising the following steps: transmitting ultrasonic waves to a bearing retainer guide surface through an ultrasonic transducer; initial reference signals and measurement signals are collected for linear frequency modulation Z transformation, and a retainer guide surface transfer function is obtained; obtaining a mapping relation between a lagging phase of the retainer coating and a transfer function by combining a multi-layer medium structure ultrasonic transfer model; setting an estimation range of the oil film thickness; on the basis of the mapping relation, the lagging phase of the cage coating corresponding to the oil film thickness estimation value in the estimation range is calculated; and linear fitting is carried out on all the cage coating lagging phases, and an oil film thickness estimation value corresponding to a minimum fitting error value is extracted as a final oil film thickness measurement value. The method is used for oil film thickness measurement.

Semiconductor devices including a high-k field relief dielectric structure are described. The microelectronic device comprises a substrate including a body region and a drain drift region on the substrate, a gate dielectric layer extending over the body region and the drift region, a drain drift trench is formed by removal of silicon dioxide from a LOCOS silicon region, a high-k field relief dielectric structure laterally abutting the gate dielectric layer at a location in the drift region, and a gate electrode on the gate dielectric layer and the field relief dielectric layer. Increasing the dielectric constant of the field relief dielectric structure may improve channel hot carrier performance, improve breakdown voltage, and reduce the specific on resistance. A drain drift trench formed in a trench left after removal of silicon dioxide in a LOCOS region provides improved trench depth uniformity.

The present application discloses a memory device and a method for fabricating the memory device. The memory device includes a substrate; a landing area positioned on the substrate; a bottom electrode positioned on the landing area, wherein the bottom electrode has a container-shaped profile; a support layer positioned over the substrate and laterally surrounded the bottom electrode; a dielectric structure including a dielectric layer conformally positioned on the bottom electrode and on a top surface of the support layer, and covering top corners of the support layer, and a plurality of dielectric portions conformally positioned on the dielectric layer and covering the top corners of the support layer; and a top electrode structure positioned on the dielectric structure. The dielectric portions are sandwiched by the top electrode structure and the dielectric layer. The top surface of the third support layer is higher than a top surface of the bottom electrode.

The present disclosure provides a semiconductor device and a method of forming the same. A method according to one embodiment of the present disclosure includes forming a plurality of semiconductor nanostructures vertically stacked above a substrate, forming a dielectric structure suspended above a topmost one of the semiconductor nanostructures, forming a plurality of inner spacers interleaving the semiconductor nanostructures, forming an epitaxial feature abutting the semiconductor nanostructures, and forming a gate structure wrapping around each of the semiconductor nanostructures and the dielectric structure.

A transistor structure includes a field plate structure and a plurality of dielectric structures through the field plate structure. The dielectric structures may be arranged in a grid in a top view of the transistor structure. The dielectric structures enable the field plate structure to be positioned closer to a gate structure of the transistor than without the dielectric structures, which enables the length of the field plate structure to be increased without increasing the overall length (or with minimal length increase) of the transistor.

A semiconductor device according to an embodiment of the present disclosure includes a substrate, a first epitaxial electrode layer disposed on the substrate, a ferroelectric epitaxial layer disposed on the first epitaxial electrode layer, a dielectric epitaxial layer disposed on the ferroelectric epitaxial layer, and a second epitaxial electrode layer disposed on the dielectric epitaxial layer. The ferroelectric epitaxial layer implements a negative capacitance. Each of the first and second epitaxial electrode layers includes conductive pyrochlore oxide. The ferroelectric epitaxial layer and the dielectric epitaxial layer are electrically connected in series is non-ferroelectric. A dielectric structure comprising the ferroelectric epitaxial layer and the dielectric epitaxial layer is non-ferroelectric.

A semiconductor device structure and method for manufacturing the same are provided. The semiconductor device structure includes a substrate, a dielectric structure, a pad, a conductive structure, and a buffer structure. The dielectric structure is disposed on the substrate. The pad is embedded in the dielectric structure. The conductive structure is disposed on the pad. The buffer structure is disposed on the pad and separates the conductive structure from the dielectric structure. A coefficient of thermal expansion (CTE) of the buffer structure ranges between a CTE of the dielectric structure and a CTE of the conductive structure.

A semiconductor structure and method of forming the same are provided. The semiconductor structure includes a circuit structure, an interlayer structure and a memory structure. The circuit structure includes a substrate having semiconductor devices formed thereon; a dielectric structure disposed over the semiconductor devices; and an interconnect layer embedded in the dielectric structure and connected to the semiconductor devices. The interlayer structure is disposed over the circuit structure. The memory structure is disposed over the interlayer structure and physically separated from the circuit structure by the interlayer structure.

The present disclosure provides a radio frequency apparatus, an antenna and an electronic device, and belongs to the field of communication technology. The radio frequency apparatus includes first and second dielectric substrates opposite to each other, first and second phase shifting structures between the first and second dielectric substrates; wherein the radio frequency apparatus further includes a first connection electrode and a second connection electrode; the first phase shifting structure and the second phase shifting structure each have a first end and a second end, the first ends of the first phase shifting structure and the second phase shifting structure are electrically connected to each other by the first connection electrode; the second ends of the first phase shifting structure and the second phase shifting structure are electrically connected to each other by the second connection electrode, to form a ring circuit structure.

Various embodiments of the present disclosure are directed towards an integrated chip having an interconnect structure overlying a substrate. The interconnect structure includes a conductive wire disposed in a dielectric structure. The conductive wire comprises a body structure. A passivation structure overlies the interconnect structure. A bond pad overlies the passivation structure. The bond pad comprises an upper pad structure on the passivation structure and a plurality of lower bond structures extending through the passivation structure to the conductive wire. The lower bond structures respectively comprise a vertical bond structure and a diffusion barrier layer disposed along a lower surface and opposing sidewalls of the vertical bond structure. The upper pad structure comprises a first conductive layer vertically stacked with a second conductive layer

In one example, an electronic device comprises a substrate comprising a dielectric structure and a conductive structure, a first electronic component over a top side of the substrate and coupled with the conductive structure, a lid over the first electronic component and coupled with a top side of the substrate, wherein the lid comprises a top plate having a plurality of holes, and a covering material covering a lateral side of the first electronic component and extending between the top side of the substrate and a bottom side of the top plate of the lid. Other examples and related methods are also disclosed herein.

A transistor and a manufacturing method. The transistor includes a semiconductor base substrate, an active structure, a dielectric structure, and a gate stack structure. The active structure is formed on the semiconductor base substrate. The active structure includes a source region, a drain region, and a channel region located between the source region and the drain region. The channel region includes at least two nanostructures stacked in a thickness direction of the semiconductor base substrate. In the channel region, a bottom nanostructure has a greater width than other nanostructures. The dielectric structure is formed between the semiconductor base substrate and the active structure. The dielectric structure is in contact with the bottom nanostructure. The gate stack structure is formed on a surface of the bottom nanostructure not in contact with the dielectric structure, and the gate stack surrounds a periphery of the other nanostructures.

A wrap-around dielectric structure prevents backside contacts shorting to gates in nanosheet field effect transistors (FETs). A method of making same includes providing a sacrificial layer under a nanosheet stack adjacent shallow trench isolation (STI) regions, recessing the STI regions' liner to from gaps in communication with the sacrificial layer, removing the sacrificial layer to form a cavity, and filling the cavity and gaps with a continuous dielectric material which wraps around a subsequently formed backside contact.

A diode is formed in an active region. The diode includes a P-type component embedded in a first portion of the active region, an N-type component embedded in a second portion of the active region, and an undoped component disposed between the P-type component and the N-type component. An interconnect structure is formed over a first side of the diode. Different portions of the interconnect structure are electrically coupled to the P-type component and the N-type component, respectively. One or more openings are etched through a dielectric structure disposed over a second side of the diode opposite the first side. A dopant material is implanted into the active region through the one or more openings. The one or more openings are filled with a conductive material.