84 results about "Dielectric structure" patented technology

A broadband omni-directional bicone antenna. The antenna can comprise conductive surfaces of conical voids provided within a solid dielectric structure. The outside surface of the solid structure can support a radio frequency (RF) lens geometry operable for beam forming. The beam forming can modify the elevation pattern of the electromagnetic radiation from the bicone antenna. The solid dielectric structure may be machined or molded from a single piece of material. The conical voids provided within the solid structure can be metallized to provide conductive bicone radiators. The outer surface beam shaping lenses can be zoned or continuous and can provide elevation patterns with increased gain, cosecant squared falloff, or various other patterns. The beam shaping lens may be formed from any low-loss dielectric. Alternatively, the lens may be formed from a less dense material such as dielectric foam that can support radial conductive beam forming vanes.

The invention relates to an anti-ant large-core-number fiber ribbon cable comprising a cable core and an outer sheath. The cable core includes loose tubes; and fiber ribbons are sleeved inside the loose tubes. The outer sheath is an outer nylon sheath; and a non-metallic reinforcement layer is arranged between the outer sheath and the cable core. According to the anti-ant large-core-number fiber ribbon cable provided by the invention, with the outer nylon sheath, ants can not bite the sheath, so that the damages on the optical cable by ant biting in a pipe at an area with a serious anti problem are prevented, the normal state of the cable is ensured, and the application region of the cable is extended. The cable based on a simple and reasonable structure has advantages of small cable diameter, high fiber density, large fiber capacity, and low duty ratio and can be laid in a pipe conveniently; and the bending performance is good. During branched connection, 4 to 24 fibers can be melted once, so that the construction time is saved and the manpower cost is lowered, and the construction efficiency is improved. On the basis of the full drying type dielectric structure, branched connection is realized conveniently and usage becomes convenient.

Integrated circuit structures having uniform grid metal gate and trench contact placeholder cut and non-selective fin trim isolation (FTI) are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires or a fin. A gate structure is over the vertical stack of horizontal nanowires or the fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure. A dielectric gate cut plug is laterally between and in contact with the gate structure and the dielectric structure. The dielectric structure has an uppermost surface above an uppermost surface of the dielectric gate cut plug.

A method for forming a semiconductor structure includes following operations. An interconnect structure is formed over a substrate. The interconnect structure includes a top conductive layer. A dielectric structure is formed over the interconnect structure. The dielectric structure is patterned to simultaneously form a cavity and a protrusion in the cavity. A MEMS substrate is bonded to the dielectric structure to seal the cavity. The protrusion is separated from the MEMS substrate.

Embodiments of the present application provide a semiconductor structure manufacturing method and a semiconductor structure. The manufacturing method comprises: providing a substrate; the substrate comprises a substrate, a dielectric structure on the substrate, and a blocking material layer on the dielectric structure; the dielectric structure comprises at least one dielectric layer; forming a first mask layer on the blocking material layer; the first mask layer comprises a first opening exposing a top surface of the blocking material layer; forming a second mask layer in the first opening, and removing the first mask layer; the second mask layer comprises a second opening exposing a top surface of the blocking material layer; using the second mask layer as a mask to pattern the blocking material layer, to form a blocking layer for patterning the dielectric structure; the blocking layer comprises a third opening exposing a top surface of the dielectric structure; the third opening has a size greater than that of the second opening.

Integrated circuit structures having uniform grid metal gate and trench contact placeholder cut and non-selective fin trim isolation (FTI) are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires or a fin. A gate structure is over the vertical stack of horizontal nanowires or the fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure. A dielectric gate cut plug is laterally between and in contact with the gate structure and the dielectric structure. The dielectric structure has an uppermost surface above an uppermost surface of the dielectric gate cut plug.

The method of forming the semiconductor device includes the following steps. An isolation structure is formed between a plurality of active areas. Semiconductor structures are formed over the active areas, and a portion of each semiconductor structure is embedded in the isolation structure. Sacrificial structures are formed on the semiconductor structures. An ion implantation process is performed to form implanted regions between the portions of the semiconductor structures embedded in the isolation structure. The sacrificial structures are removed to form patterned semiconductor structures. A dielectric structure is formed on the patterned semiconductor structure. A control structure is formed on the dielectric structure.

Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly contact structures in LED chips for reducing voiding of bonding metals are disclosed. LED chips include active LED structures on carrier submounts and contact structures arranged to receive external electrical connections adjacent the active LED structures. Exemplary contact structures include contacts electrically coupled to active LED structures and dielectric structures beneath the contacts. Dielectric structures are arranged beneath portions of the contacts while still allowing electrical connections therethrough. Such dielectric structures may be provided as regions of dielectric material with spacings that control topography of underlying bonding metals to reduce voiding.

A method of fabricating a semiconductor device includes forming a first active region and a second active region over a substrate, depositing an isolation structure between the first and second active regions, forming a gate structure across the first active region and the second active region, forming a trench dividing the gate structure into a first segment and a second segment, depositing a dielectric feature in the trench, thinning the substrate and the isolation structure to expose a bottom surface of the dielectric feature, selectively removing a surface layer of the dielectric feature to form an air gap, and depositing a seal layer capping the air gap.

The application discloses a gallium nitride transistor and a preparation method thereof, and relates to the technical field of semiconductor devices. The gallium nitride transistor comprises a substrate, a plurality of superlattice structures arranged in sequence on one side of the substrate, and interval cavities between adjacent two superlattice structures. The superlattice structure comprises a channel layer and a barrier layer arranged in a stack. The channel layer and the barrier layer of each second superlattice structure, the barrier layer of a first superlattice structure, and a first groove and a second groove located on opposite sides of each superlattice structure are penetrated. A source and a drain are respectively located in the first groove and the second groove and are in contact with each superlattice structure. A dielectric structure is located between the source and the drain, is located in each interval cavity, and covers the surface of each superlattice structure. A gate is located between the source and the drain and is arranged around the dielectric structure. According to the technical scheme, the gate around the dielectric structure covering the surface of each superlattice structure is arranged, and the control effect of the gate on the conductive channel layer is improved.

This disclosure provides a composite dielectric structure, a device having the same, and a fabrication method thereof. The fabrication method includes operations S1-S4. Operation S1: Depositing source and drain ohmic metals at designated locations on the surface of an epitaxial wafer; Operation S2: Using photoresist and electron beam lithography to create the required window for the gate structure; Operation S3: Etching a portion of the epitaxial wafer surface structure corresponding to the window and removing the photoresist to fabricate a gate trench; Operation S4: Growing AlN / SiN within the gate trench. X Composite dielectrics enable the fabrication of devices with composite dielectric structures.

In one example, an electronic device comprises a lower substrate comprising a lower dielectric structure and a lower conductive structure, an electronic component coupled with a bottom side of the lower substrate and coupled with the lower conductive structure, an upper substrate over a top side of the lower substrate and comprising an upper dielectric structure and an upper conductive structure, an internal interconnect between the upper substrate and the lower substrate and coupled with the upper conductive structure and the lower conductive structure, and a first antenna component between the upper substrate and the lower substrate and coupled with the upper conductive structure. Other examples and related methods are also disclosed herein.

This invention discloses a Ka-band focusing array dielectric lens based on impedance matching, comprising several dielectric lens units. Each dielectric lens unit has a three-layer dielectric structure, consisting of a front dielectric substrate, a middle phase modulator, and a rear dielectric substrate, arranged according to the electromagnetic wave incident direction. The dielectric constants of the three dielectric layers are set according to preset conditions. The thicknesses of the front and rear dielectric substrates are set based on the wavelength of the electromagnetic wave in their respective media. The thickness of the middle phase modulator is calculated based on the compensation phase of the lens unit. This invention reduces interface reflection loss by adjusting the thickness of the front and rear dielectric substrates and achieves phase compensation for different dielectric lens units by adjusting the thickness of the middle phase modulator, thereby improving the electromagnetic wave focusing performance.

A method of forming a semiconductor structure includes forming a fin over a semiconductor substrate, forming an isolation region on sidewalls of the fin, forming a metal gate over the fin and the isolation region, etching the metal gate to form a trench through the isolation region, passivating the top portion of the semiconductor substrate exposed in the trench to form a dielectric layer at a bottom of the trench, and depositing a dielectric material in the trench to form a dielectric structure. The dielectric structure divides the metal gate into two sections.

A semiconductor structure and forming method thereof are provided. The semiconductor structure includes a substrate, a gate dielectric, a gate electrode and dielectric structures. The gate dielectric has a top surface aligned with a top surface of the substrate. The gate electrode is disposed over the substrate and overlaps the gate dielectric. The gate electrode has first segments extending in parallel along a direction. The dielectric structures are disposed over the substrate, overlap the gate dielectric and extend in parallel along the direction. The dielectric structures and the first segments are arranged in an alternating pattern.

An integrated chip including a first conductive interconnect, a dielectric structure, and a trench capacitor. The first conductive interconnect is over a semiconductor substrate. The dielectric structure includes a plurality of dielectric layers over the first conductive interconnect. The trench capacitor is over the dielectric structure and extends between sidewalls of the dielectric structure to the first conductive interconnect. The trench capacitor includes a bottom electrode layer, a top electrode layer over the bottom electrode layer, and a first insulator layer between the bottom electrode layer and the top electrode layer. A lower surface of the first insulator layer is between the sidewalls of the dielectric structure and spaced over an upper surface of the first conductive interconnect. The bottom electrode layer includes a first metal compound which extends from the lower surface of the first insulator layer to the upper surface of the first conductive interconnect.

Various embodiments of the present application are directed toward an integrated chip (IC). The IC comprises a dielectric structure disposed over a substrate. A phase change material (PCM) structure is disposed over the dielectric structure. A first conductive structure and a second conductive structure are disposed over and electrically coupled to the PCM structure. A heating structure is disposed in the dielectric structure and laterally between the first conductive structure and the second conductive structure. The heating structure has a first surface and a second surface opposite the first surface. The first surface faces the PCM structure. The first surface has a first width and the second surface has a second width that is greater than the first width.

A method of forming a semiconductor structure includes a number of operations. A first cell and a second cell are formed over a substrate, wherein the first cell abuts the second cell at a first cell boundary. A first dielectric structure is formed along the first cell boundary between the first cell and second cell, wherein from a plan view, the first dielectric structure comprises a first elongated pattern extending in a first direction and separating longitudinal ends of first gate structures in the first cell from first longitudinal ends of second gate structures in the second cell, and a second elongated pattern extending in a second direction orthogonal to the first elongated pattern.

A semiconductor device comprises a first transistor including at least one first nanosheet channel region and a source region and a drain region opposite to the ends of at least one first nanosheet channel region, a second transistor including at least one second nanosheet channel region and a source region and a drain region opposite to the ends of at least one second nanosheet channel region, a common gate on at least one first nanosheet channel region and at least one second nanosheet channel region, and a dielectric layer embedded in the common gate.

This invention discloses an integrated ultra-wideband absorbing material. From top to bottom, the material comprises a first lossy dielectric substrate, multiple lightweight interlayers, five resistive frequency selective surfaces, a metal backplate, and a composite material frame penetrating between the layers. Through slots are formed between the square rings and concentric geometric patterns of each resistive frequency selective surface. The composite material frame is embedded in these slots and continuously arranged along the thickness direction, creating a non-uniform dielectric structure within the material composed of high-dielectric and low-dielectric regions. This structure jointly regulates the resonance conditions and equivalent impedance gradient of the multiple resistive frequency selective surfaces, shifting the low-frequency absorption initiation frequency towards lower frequencies without increasing the thickness, and maintaining stable absorption performance at large oblique incidence angles. Simultaneously, the composite material frame improves the overall structural mechanical stability. This invention achieves thinness, wide bandwidth, and wide-angle absorption characteristics, making it suitable for electromagnetic stealth and electromagnetic compatibility applications.

A method of forming a semiconductor structure and a semiconductor structure are provided. The method of forming the semiconductor structure includes: providing a base, where the base includes a first dielectric layer and pads arranged at intervals in the first dielectric layer; forming a dielectric structure, where the dielectric structure exposes the pad and part of the first dielectric layer; forming an insulating structure, where the insulating structure is formed on a sidewall of the dielectric structure, the insulating structure covers a first partial sidewall of the dielectric structure, and an air gap is formed between a second partial sidewall of the dielectric structure and the insulating structure; and forming a conductive structure, where the conductive structure covers an exposed pad and an outer sidewall surface of the insulating structure.

A display substrate and a display device. The display substrate includes a first display area (110) and a second display area (120), wherein the light transmittance of the second display area (120) is greater than that of the first display area (110). The display substrate includes: a first organic dielectric structure located in the first display area (110), wherein the first organic dielectric structure is provided with a first dielectric opening exposing at least a portion of the first anode (111), and the first dielectric opening has a first dielectric slope angle; and a second organic dielectric structure located in the second display area (120), wherein the second organic dielectric structure is provided with a second dielectric opening exposing at least a portion of the second anode (112), and the second dielectric opening has a second dielectric slope angle; wherein the second dielectric slope angle is greater than the first dielectric slope angle.

A semiconductor structure includes a fin protruding from a substrate, a first and a second metal gate stacks disposed over the fin, and a dielectric feature defining a sidewall of each of the first and the second metal gate stacks. Furthermore, the dielectric feature includes a two-layer structure, where sidewalls of the first layer are defined by the second layer, and where the first and the second layers have different compositions.

The present application relates to a kind of biochip and its manufacturing method and application.The biochip includes: substrate;Multiple pixel units are arranged on the substrate, and each pixel unit includes the microelectrode array with working electrode, counter electrode and dielectric structure;Wherein, the surface of the dielectric structure has surface modification layer, and the surface modification layer includes interlinked first surface modification structure and second surface modification structure;The first surface modification structure includes the alkoxysilane modification layer bonded with the surface of the dielectric structure and the functional modification layer connected with the alkoxysilane modification layer by sulfide bond;And the second surface modification structure includes the alkoxysilane modification layer bonded with the surface of the dielectric structure.The biochip surface has region-selective and functionally differentiated functional structure, and it is of great significance to promote the development of high-throughput, programmable and strong bio-compatible chip technology.

Some embodiments relate to an integrated circuit including a semiconductor substrate. A silicide structure is disposed over the semiconductor substrate in a cross-sectional view. A dielectric structure is in direct contact with an upper surface of the silicide structure in the cross-sectional view. A metal structure is in direct contact with an upper surface of the dielectric layer in the cross-sectional view, such that the silicide structure and the metal structure establish a bottom electrode and a top electrode, respectively, which are spaced apart from one another by the dielectric structure to establish a metal-insulator-silicide capacitor over the semiconductor substrate.

A semiconductor device includes a lower structure; a lower electrode on the lower structure; an upper electrode covering the lower electrode on the lower structure; and a dielectric structure disposed between the lower electrode and the upper electrode. The dielectric structure includes a first dielectric film including a first material and a second dielectric film including a second material different from the first material. The first dielectric film includes a first surface in contact with or facing the lower electrode and a second surface facing the first surface. The second dielectric film includes a first portion disposed in an opening of the first dielectric film and extending in a direction from the second surface toward the first surface.

A semiconductor structure and a forming method thereof, the semiconductor structure comprising: a substrate; a gate structure separated on the substrate, comprising a gate contact region for contacting a gate plug; a source-drain doped region, comprising a source-drain contact region and a source-drain connection region; a dielectric structure layer, located on the substrate at the side of the gate structure and covering the source-drain doped region and the gate structure; a source-drain contact structure, contacting the source-drain doped region, the source-drain contact structure being an integrated structure, comprising a source-drain plug penetrating through the dielectric structure layer at the source-drain contact region, and a source-drain contact layer in the dielectric structure at the source-drain connection region, the top surface of the source-drain contact layer being lower than the top surface of the source-drain plug, the source-drain contact structure and the dielectric structure layer surrounding a spacing opening; a spacing dielectric layer, filling in the spacing opening; and the gate plug, located on the top of the gate structure at the gate contact region and contacting the gate structure. The source-drain contact structure of the embodiment is an integrated structure, which improves the electrical connection performance between the source-drain plug and the source-drain contact layer.

This invention provides an integrated circuit device including a dielectric structure on a semiconductor substrate, a plurality of active bonding pads in the dielectric structure, and a plurality of auxiliary bonding pads in the dielectric structure and laterally offset from the active bonding pads by a first distance, the first distance being greater than the spacing of the active bonding pads. The active bonding pads are electrically coupled to corresponding auxiliary bonding pads in the auxiliary bonding pads, so that the spare bonding pads have good electrical coupling, thereby improving the performance, reliability and yield of the integrated circuit device.

An assembly structure includes a first electronic device, a second electronic device, a conductive portion, and a dielectric structure. The second electronic device is disposed above the first electronic device. The conductive portion connects the first electronic device and the second electronic device. The dielectric structure encapsulates the conductive portion and extends beyond side surfaces of the first electronic device and side surfaces of the second electronic device.

The application provides a dual-resonance dual-polarization high-efficiency reconfigurable reflectarray antenna for SWIPT application, relates to the technical field of reflectarray antennas, adopts a multilayer laminated integrated structure, and comprises a first dielectric substrate, a second dielectric substrate, a metal ground plate and a third dielectric substrate which are sequentially stacked from top to bottom. The application adopts a multilayer dielectric structure and a dual-resonance design, realizes extremely high aperture efficiency, and in the SWIPT application scene, the energy polarization direction aperture efficiency reaches 60.16%, the information polarization direction aperture efficiency reaches 55.63%, which is much higher than the level of less than 45% of the traditional passive reflectarray, and the wireless power transmission and information polarization coverage area can be effectively improved.