442 results about "LDMOS" patented technology

The invention relates to an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a manufacturing method thereof. The LDMOS device comprises a semiconductor substrate; the body region and the drift region are formed in the semiconductor substrate, the source region is located in the body region, and the drain region is located in the drift region; the at least two shallow trench isolation structures are formed in the drift region, the tops of the at least two shallow trench isolation structures are higher than the surface of the semiconductor substrate, and a dielectric layer is formed between the parts, higher than the surface of the semiconductor substrate, of the at least two shallow trench isolation structures; and the gate structure comprises a gate dielectric layer and a gate electrode layer located on the gate dielectric layer, and the gate structure transversely extends to the drift region from the body region and at least partially covers the shallow trench isolation structure. The LDMOS structure has a relatively high breakdown voltage.

An integrated circuit includes a nanosheet laterally-diffused metal oxide semiconductor (LDMOS) transistor. The transistor includes source and drain regions having a first conductivity type that extend into a semiconductor substrate. A nanosheet region including semiconducting nanosheets extends between the source region and the drain region. The nanosheets alternate with gate conductor layers that extend between the source region and the drain region. The nanosheets also alternate with field plate conductor layers that extend between the gate conductor layers and the drain region.

The invention provides an LDMOS (Laterally Diffused Metal Oxide Semiconductor) drift region LOCOS growth method. The LDMOS drift region LOCOS growth method comprises the following steps: providing a silicon substrate; defining an LOCOS region on the surface of the silicon substrate, wherein the region except the LOCOS region in the silicon substrate is a non-LOCOS region; surface modification is carried out on the silicon substrate in the LOCOS area, a lattice damage area is formed in the LOCOS area, and the area outside the lattice damage area in the silicon substrate is a non-lattice damage area; the oxide growing on the surface of the silicon substrate is consumed through a furnace tube, and the growth rate of the oxide in the lattice damage area is larger than that of the oxide in the non-lattice damage area; the oxide is etched, the oxide in the non-LOCOS area is removed, and the remaining oxide in the LOCOS area serves as LOCOS. According to the technical scheme, the LOCOS is generated through the difference formed by the silicon substrate by utilizing the characteristics that crystal lattices are damaged after the ions are injected into the silicon substrate and the speed of generating oxides during high-temperature oxidation is higher than that of generating oxides during high-temperature oxidation of the silicon substrate, and compared with a traditional mode, the proportion of beaks is reduced, so that the size of the device is reduced.

The disclosure provides a LDMOS device and a fabrication method. By arranging a first field oxide, a second field oxide, a third field oxide, a gate polysilicon, and a gate oxide layer in the trench and making the surface of the gate polysilicon away from the trench flush with the trench opening, the lateral dimension of the LDMOS device is reduced. Meanwhile, by setting the thickness of the first field oxide and the third field oxide to be greater than that of the second field oxide, setting the height of the first field oxide to be less than or equal to the distance from the bottom of the trench to the channel region, and making the surface of the third field oxide away from the trench flush with the opening of the trench, three independent field plates are formed in the trench. This improves breakdown voltage resistance of the LDMOS device.

The utility model provides a double-channel planar gate silicon carbide LDMOS. The double-channel planar gate silicon carbide LDMOS is characterized in that a first N-type source region is connected with a silicon carbide substrate; the first channel region is connected with the silicon carbide substrate and the first N-type source region; the isolation region is respectively connected with the first channel region, the first N-type source region and the second N-type source region; the second channel region is connected to the isolation region and the first N-type source region; the P-type well region is connected with the isolation region and the second channel region, and the P-type well region is connected to the first N-type source region; the second N-type source region is arranged in the first through hole, the second N-type source region is connected to the isolation region, the body diode metal layer is arranged in the second through hole, and the body diode metal layer is connected to the isolation region; the gate dielectric layer is connected with the P-type well region, the source metal layer is arranged in the third through hole, and the source metal layer is connected to the second N-type source region and the body diode metal layer; the gate metal layer is connected to the gate dielectric layer; the drain metal layer is connected to the first N-type source region; double-channel structure design is carried out in the transverse power device, so that the on-resistance of the device is reduced.

The utility model provides a semiconductor device. The semiconductor device comprises a semiconductor substrate of a first conductive type; the deep well of the second conduction type is located in the semiconductor substrate; the shallow well of the first conductive type is located in the semiconductor substrate on the outer side of the deep well of the second conductive type; the JFET source electrode region, the drain electrode region and the LDMOS source electrode region are arranged at intervals; a field oxide layer, a JFET polysilicon gate and an LDMOS polysilicon gate, the field oxide layer is located in the deep trap of the second conduction type, and the JFET polysilicon gate and the LDMOS polysilicon gate are located on the field oxide layer; and the high-voltage well of the first conduction type comprises a first part and a second part, the first part is located in the deep well of the second conduction type between the JFET source region and the drain region, the second part is located in the deep well of the second conduction type between the drain region and the LDMOS polysilicon gate, and the second part is distributed in a polygonal matrix. The semiconductor device provided by the utility model can meet the performance requirements of the LDMOS and the JFET at the same time.

The invention discloses a semiconductor device critical breakdown characteristic simulation method based on a hybrid finite volume method. The method comprises the following steps: firstly, carrying out geometric modeling on a device, and carrying out mesh generation; then, the quality of the grids is judged, an FBM method is adopted for the grids with the good quality, and a CVFEM method is adopted for the grids with the poor quality to discretize a drift-diffusion equation set; and then, solving the discrete drift-diffusion equation set system by adopting a full-coupling Newton iteration method, and realizing the optimization of the boost numerical simulation process by adopting an automatic boost strategy and an initial value extrapolation method. And finally, obtaining physical field information of a power semiconductor device (LDMOS) under different external bias voltages, calculating terminal current through a post-processing method, and obtaining an I-V characteristic curve of the device after the avalanche breakdown effect is considered. The method has good numerical calculation precision, numerical stability and grid adaptability, and the complete benchmarking with the solution precision of an international advanced semiconductor simulation tool Sentaur TCAD is realized.

Novel NEDMOS and / or LDMOS FET integrated circuit structures that reduce or eliminate the floating body effect by reducing the built-in voltage Vbi of the device. Reduction of Vbi includes adding a source-side structure that includes a “Vbi Reduction Material” (VRM) layer. VRM has a bandgap less than the bandgap of Si and, for an N-type device, a valence band that is higher than the valence band of the body material. The low Vbi of the VRM layer on the source-side of a MOSFET device that would otherwise exhibit a floating body effect allows significantly freer movement of holes from the body of the device towards the source region, thus increasing body hole collection efficiency, and significantly reduces the floating body effect.

The invention relates to the technical field of semiconductors, and discloses an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a preparation method thereof, and the LDMOS device comprises a substrate layer comprising a drift region, a field oxide layer and a gate oxide layer which are located on the surface of the substrate layer, a gate structure, a polycrystalline silicon structure at the side part, a first dielectric layer and a first conductive column, the metal field plate, the second conductive through hole and the field plate connecting structure are arranged at the side part of the gate metal layer; wherein the field oxide layer is located on the surface of the drift region, and the gate structure, the drift region and the field oxide layer between the gate structure and the drift region form a first field plate structure; the metal field plate, the polycrystalline silicon structure and the first dielectric layer therebetween form a first capacitor, the polycrystalline silicon structure, the drift region and the field oxide layer therebetween form a second capacitor, and the first capacitor and the second capacitor are coupled in series to form a second field plate structure; the first field plate structure and the second field plate structure are connected through the field plate connecting structure and the second conductive through hole to form a double-field-plate structure. According to the invention, the breakdown voltage of the device can be improved under the condition of low on-resistance.

A LDMOS including a semiconductor substrate, a gate oxide, a gate, field plate oxide layers and field plate barrier layers is disclosed. A first field plate oxide layer and a second field plate oxide layer are positioned atop the gate oxide with a spacing between them. A first field plate barrier layer and a second field plate barrier layer are positioned atop the first and the second field plate oxide layers, respectively. A third field plate barrier layer is positioned atop the first and the second field plate barrier layers and the spacing. A third field plate oxide layer is positioned atop the third field plate barrier layer. The third field plate oxide layer includes a first portion positioned atop the first field plate oxide layer and a second portion positioned atop the spacing. A fourth field plate barrier layer is positioned atop the third field plate oxide layer.

A number of MOSFET architectures provide high-voltage capability (both drain-source breakdown voltage BVDSS and ON-state breakdown voltage BVON), low current leakage, and extended linearity. Embodiments of the invention overcome the limitations of conventional NEDMOS and LDMOS device designs by providing a low-resistance path for hole collection and by purposefully exhibiting multiple voltage thresholds VTH in different segments of the device. Embodiments includes NEDMOS and LDMOS device designs having multiple body contact regions for improved hole collection, sub-gate doped stripes or segments for even better hole collection and linearity, and sub-gate doped edge regions for increased local VTH and thus decreased current leakage. P– hole-collection stripes and P+ body contact regions may be formed of a semiconductor material that includes germanium. The inventive MOSFETs may be arranged as multi-MOSFET array elements, and multiple array elements may be arranged in a larger array.

A new semiconductor structure is disclosed. The semiconductor structure includes patterned dielectric layers disposed between the field plates and the channel layer. These patterned dielectric layers serve to further shape the electric field in the channel layer. This structure is not only applicable to III-nitride semiconductor devices, such as transistors, diodes or any other devices, but also is applicable to other semiconductor devices, such as Si LDMOS, SiC transistors, GaAs transistors.

A number of MOSFET architectures provide high-voltage capability (both drain-source breakdown voltage BVDSS and ON-state breakdown voltage BVON), low current leakage, and extended linearity. Embodiments of the invention overcome the limitations of conventional NEDMOS and LDMOS device designs by providing a low-resistance path for hole collection and by purposefully exhibiting multiple voltage thresholds VTH in different segments of the device. Embodiments includes NEDMOS and LDMOS device designs having multiple body contact regions for improved hole collection, sub-gate doped stripes or segments for even better hole collection and linearity, and sub-gate doped edge regions for increased local VTH and thus decreased current leakage. P− hole-collection stripes and P+ body contact regions may be formed of a semiconductor material that includes germanium. The inventive MOSFETs may be arranged as multi-MOSFET array elements, and multiple array elements may be arranged in a larger array.

A microelectronic device including a substrate having a semiconductor material containing a laterally diffused metal oxide semiconductor (LDMOS) transistor, including a body region of a first conductivity type and a drift region of an opposite conductivity type. A gate dielectric layer over a channel region of the body, the gate dielectric extending over a junction between a body region and the drift region with a gate electrode on the gate dielectric and a drain contact in the drain drift region, having the second conductivity type. A field relief dielectric layer on the drain drift region extending from the drain region to the gate dielectric, having a thickness greater than the gate dielectric layer. A silicide-blocking layer extends from the drain region toward the gate, providing an unsilicided portion of the drift region at the substrate top surface between the drain region and the gate.

The invention provides a low-delay level shift circuit, and belongs to the technical field of analog integrated circuit power management, the circuit comprises a level shift core circuit and an edge detection logic circuit, the level shift core circuit adopts a high-voltage-resistant LDMOS to complete conversion of different voltage domain signals on the basis of a traditional cross coupling structure, and the edge detection logic circuit is connected with the edge detection logic circuit. The edge detection logic circuit detects a fast falling edge of the level shift core circuit, and an output signal only related to the fast edge is obtained after logic operation. The low-delay level shift circuit provided by the invention has no static power consumption, the delay of the level shift circuit can be reduced to below 1ns, the delay time of the low-delay level shift circuit is obviously reduced compared with the delay time of a traditional two-stage cross coupling level shift circuit, and the low-delay level shift circuit is suitable for the field of SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) driving with higher requirements on propagation delay.

The invention belongs to the field of electrostatic discharge (ESD) and electrical overstress (EOS) pulse protection of an integrated circuit, and particularly provides an electrostatic surge integrated protection circuit of a high-reliability high-voltage driving chip, which is used for solving the problems of easy latching, high trigger voltage, poor robustness, low starting speed and the like in a traditional high-voltage ESD / EOS protection scheme. The SCR structure, the Zener structure and the LDMOS structure are technically embedded, the voltage clamping capacity of the Zener diode, the high voltage endurance capacity of the LDMOS, the quick response characteristic of the composite transistor and the strong discharge capacity of the SCR are integrated, the electrostatic and surge integrated protection efficiency is achieved, and under the ESD / EOS electric stress effect, the electrostatic and surge integrated protection effect is achieved. The composite structure promotes orderly opening of the Zener structure, the SCR structure and the LDMOS structure under the action of positive feedback, so that ESD and EOS protection requirements of different pulse frequencies are met, the hysteresis effect and the trigger voltage are remarkably reduced, and the latch-up phenomenon is effectively avoided.

The invention relates to the technical field of semiconductor devices, and discloses an LDMOS device and a preparation method thereof.The LDMOS device comprises a silicon substrate, a source region, a drain region, a gate region, a groove structure, an N-type drift region and a P-type well region, and the source region, the drain region, the gate region, the groove structure and the P-type well region are arranged in the N-type drift region on the silicon substrate; the trench structure is located between the source region and the drain region; the source region comprises a P-type heavily doped region and a first N-type heavily doped region and is arranged between the gate region and the drain region; the drain region comprises a second N-type heavily doped region; the gate region comprises a polycrystal structure and a first high dielectric constant insulating layer wrapping the polycrystal structure; the P-type well region is in contact with a source region arranged right above the P-type well region and is in contact with a gate region arranged right on the left side of the P-type well region, and a conducting channel is formed in the P-type well region under the condition that gate-source voltage is higher than starting voltage, so that the technical problem of how to improve the breakdown voltage of the device and reduce on resistance at the same time is solved.

The invention discloses a preparation method of an LDMOS (Laterally Diffused Metal Oxide Semiconductor) and an LDMOS device, and the preparation method of the LDMOS comprises the steps: providing a semiconductor substrate, and forming an LDMOS device region on the semiconductor substrate; forming an oxide layer on the region where the LDMOS device is formed; forming a grid electrode on the oxidation layer corresponding to the area between the source electrode area and the drain electrode area, and forming a step-shaped field plate structure on the corresponding oxidation layer above the drift area; forming a first dielectric layer covering the grid electrode and the stepped field plate structure; forming a first through hole and a second through hole which are respectively communicated to the source region and the drain region in the first dielectric layer, and forming a plurality of third through holes which are respectively communicated to different steps of the stepped field plate structure; the at least one third through hole electrically connects a step of the stepped field plate structure with the drain region. By adopting the method, the drain-source breakdown voltage performance of the device in a conducting state is improved, and the high-voltage breakdown of the drain electrode is effectively prevented.

The invention provides an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a preparation method thereof. The LDMOS device comprises a substrate; the first conductive type drift region and the second conductive type body region adjacent to the first conductive type drift region are both located in the substrate; the grid electrode is located on the first conduction type drift region and extends to the second conduction type body region; the groove is positioned in the first conduction type drift region and is self-aligned with the edge of the grid electrode; the side walls are located on the side edges of the two sides of the grid electrode and extend to the side edges of the groove; and the barrier layer fills the groove and extends to a part of the upper surface of the grid electrode. According to the LDMOS device, breakdown voltage is maintained and even improved, on-resistance is reduced, the length of the drift region is reduced, and the size of the device is further reduced.

The invention discloses an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a preparation method thereof. The LDMOS device comprises a semiconductor layer of a first doping type; the body region and the drift region are located in the semiconductor layer, the body region is provided with a first doping type, the drift region is provided with a second doping type opposite to the first doping type, the drift region comprises a plurality of partitions arranged in the horizontal direction, and the partitions are separated from one another; the source region is positioned in the body region; the drain region is positioned in the drift region; the source region and the drain region have a second doping type; the gate conductor is positioned on the surface of the semiconductor layer between the source region and the drain region; the polycrystalline silicon field plates are positioned on the surface of the partition between the source region and the drain region; wherein the plurality of polycrystalline silicon field plates are electrically connected with one another and are externally connected with voltage.

The invention provides a thermal resistance model construction method of an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device, which is characterized in that a plurality of N-type doped isolation layers are formed on a substrate, an LDMOS structure is formed on each N-type doped isolation layer, all LDMOS structures are divided into different test groups according to different key sizes, and the key sizes at least comprise a total channel width and a cross index; measuring the thermal resistance of the LDMOS structure in each test group so as to respectively extract a thermal resistance value array of each group, and performing data fitting on the thermal resistance value array of each group so as to obtain a thermal resistance model of the relationship between the thermal resistance value of the LDMOS structure and the critical dimension; according to the method, the thermal resistance model of the full-size LDMOS device can be constructed by only utilizing a limited number of LDMOS structures in a primary tape, so that the thermal resistance of the LDMOS devices with different sizes can be predicted, the self-heating effect of the device can be accurately evaluated in the design stage, the device design is optimized, the development cost of the device is reduced, and the research and development period is shortened.

The invention provides an LDMOS device and a manufacturing method thereof, and relates to the technical field of semiconductors. The LDMOS device may include: a semiconductor substrate; the drift region is located on the semiconductor substrate and is provided with a first conduction type; the body region is located at one end of the drift region and has a second conductive type; the gate structure is positioned on the surface of the body region and partially extends to the drift region; the source region is located in the body region and is adjacent to one side of the gate structure, and the body contact region is adjacent to the source region and is of a second conduction type; the drain region is located at one end, away from the body region, of the drift region; and the plurality of strip-shaped current modulation units are arranged in the drift region in an interdigital alternate arrangement mode, and extend and are arranged in the direction from the body region to the drain region. The chip has the advantages of being low in cost, small in overall chip area and easier to manufacture.

A structure for a laterally diffused metal oxide semiconductor device and a method of forming a structure for a laterally diffused metal oxide semiconductor device. The structure includes a drain and a source in a semiconductor substrate. The source includes a source region having a first terminal, a second terminal, and a length between the first terminal and the second terminal. The structure also includes a shallow trench isolation region in the semiconductor substrate. The shallow trench isolation region surrounds the drain. The structure also includes a gate surrounding the shallow trench isolation region and the drain. The gate has a side portion between the drain and source regions, the side portion of the gate having a width, and the gate having a length in a direction transverse to the width. A length of the source region is substantially equal to a length of the gate.

The invention provides an LDMOS process TVS (Transient Voltage Suppressor) device and a manufacturing method thereof, and belongs to the technical field of TVS semiconductor preparation. Comprising a P-type silicon substrate, the surface of the P-type silicon substrate is provided with a deep N well, the deep N well is used for providing isolation for a source / drain high-voltage N + region and preventing punch-through or premature breakdown between the deep N well and the P-type substrate, the deep N well is used as a collector region of a parasitic NPN BJT, and a P-type body region is arranged in the deep N well. According to the invention, the inherent high-voltage capability of an LDMOS and a parasitic BJT structure are utilized to realize rapid triggering and low clamping, the manufacturing process is highly compatible with a standard CMOS / BCD process, key parameters such as breakdown voltage, clamping voltage, capacitance, surge capability and the like can be optimized by accurately designing a drift region, a P body region, a deep N well and layout, various harsh circuit protection requirements are met, and the reliability of the device is improved. The method is particularly applied to applications requiring low capacitance, high integration level and high reliability.

The present invention discloses a high-end power control circuit based on digital logic and an anti-interference method. The high-end power control circuit includes a digital trigger module, the output end of the digital trigger module is simultaneously connected to the gates of a first PMOS transistor and a second PMOS transistor, and the control end is connected to the output end of the output driving circuit. At this time, the digital trigger module will use the output signal of the output driving circuit as a clock control signal, so that the digital trigger module is triggered during the rising edge period of the output signal, and thus the output end of the digital trigger module is always in a low level state. The anti-interference method is based on the high-end power control circuit to raise the drain potential of the first LDMOS transistor when the output signal is in the rising edge stage, reducing the noise pulse width. The high-end power control circuit has the advantages of simple structure and small chip volume, and the high-end power control circuit and the anti-interference method more effectively eliminate noise interference.

The invention relates to a super junction LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a manufacturing method thereof, a shallow trench is arranged between a source region and a drain region of the super junction LDMOS device, a trench dielectric layer is arranged on the inner wall of the shallow trench, and the shallow trench is sequentially filled with a silicon dioxide layer and a low dielectric constant layer which is positioned on the surface of the silicon dioxide layer and is filled with the shallow trench. Due to the dielectric constant difference between the low dielectric constant layer and the silicon dioxide layer, electric field peaks can be caused on the two sides of the junction of the low dielectric constant layer and the silicon dioxide layer, and the electric field peaks can improve the voltage endurance capability and the doping concentration of the two sides of the shallow trench, so that the on resistance of the region is reduced at the same time.

The invention discloses an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device with asymmetric stepped field oxide. The field oxide structure of the LDMOS device is in an asymmetric step shape, asymmetric coordinated regulation and control of the STI thickness are achieved, the step side expands the field oxide boundary through the gradient, electric field concentration at the STI corner is weakened, breakdown voltage is improved, the inclination angle of the non-step side keeps a thick field oxide area, the electric field peak of the source side is restrained, avalanche breakdown is delayed, and the device performance is improved. And meanwhile, the hot carrier injection risk is reduced. The structure gives consideration to the collaborative optimization of the breakdown capability and the conduction efficiency, is especially suitable for a high-voltage BCD platform with low loss and high reliability requirements, and is a structural innovation scheme with high process compatibility and high design flexibility.

The invention relates to an LDMOS with a bias circuit for biasing a field plate. A semiconductor device (100) includes: a drain extension transistor (101) having: a semiconductor layer (104) including oppositely doped body and drain drift regions (104, 120); a gate dielectric layer (134) over the body region (104) and extending over a junction between the body region (104) and the drain drift region (120); a gate electrode (140) over the gate dielectric layer (134); a drain region (160) in the drain drift region (120) and having a dopant density greater than a dopant density of the drain drift region (120); and a field plate (142) between the gate electrode (140) and the drain region (160); and a bias circuit (190) including an output coupled to the field plate (142) and a bias input coupled to a gate drive circuit (192).

The embodiment of the invention provides a SiC LDMOS device, a manufacturing method and a chip. The SiC LDMOS device comprises a P-type substrate; the N-type buried layer is located in the P-type substrate; the N-type epitaxial layer is located on the surface of the P-type substrate and the surface of the N-type buried layer; the P-type injection layer is located in the N-type epitaxial layer, and the bottom of the P-type injection layer is connected with part of the surface of the N-type buried layer; the P-type body region is located in the N-type epitaxial layer and extends into the P-type substrate; and the N-type buffer layer is located in the P-type injection layer and extends into the N-type buried layer. When the device is in a reverse withstand voltage state, the drift region is depleted, ionization donors in the P-type injection layer and the P-type substrate emit power lines and point to ionization acceptors of the N-type buried layer and the N-type epitaxial layer, the N-type epitaxial layer and the N-type buried layer are mutually overlapped, electric field distribution in the drift region of the device can be effectively adjusted, an electric field peak is introduced to the surface of the drift region of the device, and the device is prevented from being damaged. And the overall electric field of the drift region is lifted, so that the voltage resistance of the device is improved.

A metal-oxide-semiconductor (MOS) transistor includes a substrate including a well region, an insulator layer coupled to the substrate, and a source including a source region, a source contact passing through the insulator layer and the source region, and an ohmic contact disposed in the well region. The MOS transistor also includes a gate region including a gate insulator layer and a gate contact and a drain including a drain region and a drain contact passing through the insulator layer to the drain region. The MOS transistor can be an LDMOS transistor, for example, an LNDMOS or LPDMOS transistor.