70 results about "LDMOS" patented technology

A metal-oxide-semiconductor (MOS) transistor includes a substrate including a well region, an insulator layer coupled to the substrate, and a source including a source region, a source contact passing through the insulator layer and the source region, and an ohmic contact disposed in the well region. The MOS transistor also includes a gate region including a gate insulator layer and a gate contact and a drain including a drain region and a drain contact passing through the insulator layer to the drain region. The MOS transistor can be an LDMOS transistor, for example, an LNDMOS or LPDMOS transistor.

Disclosed examples include microelectronic devices, e.g., integrated circuits and methods of making such devices. One example includes a microelectronic device including a nanosheet laterally-diffused metal oxide semiconductor (LDMOS) transistor. The LDMOS transistor may include a high-k gate dielectric and a metal gate. The (LDMOS) transistor includes source and drain regions having a first conductivity type that extend into a semiconductor substrate. A nanosheet region including semiconducting nanosheets extends between the source region and the drain region. The nanosheets alternate with gate conductor layers that extend between the source region towards the drain region and field plate conductor layers that extend from the drain region towards the source region with gate dielectric layers and field relief dielectric layers separating the gate conductor layers from the field plate conductor layers.

This invention provides a high-voltage LDMOS and its manufacturing method. The shallow region of the substrate has two mutually spaced-apart STI regions. The first STI region includes multiple mutually spaced-apart segmented structures. The deep region of the substrate has a drift region that encloses the first STI region. A shallow inversion region is located at the bottom of the multiple mutually spaced-apart segmented structures, formed by boron ion implantation. A first N+ region is located between the first and second STI regions. A second N+ region is located on the side of the second STI region away from the first STI region. A deep well is located on the side of the second STI region away from the first STI region, enclosing a portion of the second STI region. An N-well enclosing the second N+ region is located within the deep well. A P-well is located on the side of the first STI region away from the second STI region. A field plate is located on the upper surface of the substrate. A P+ region and a third N+ region are also located within the P-well. The LDMOS of this invention employs field plate STI segmentation and boron ion implantation after STI. The high-voltage NLDMOS structure can simultaneously improve low on-resistance and high breakdown voltage performance, thus improving device performance.

This disclosure relates to a high-k / metal-gate LDMOS nanosheet device. Examples of the disclosure include a microelectronic device (100) and a method of manufacturing such a device. One example includes a nanosheet laterally diffused metal-oxide-semiconductor (LDMOS) transistor (101). The LDMOS transistor (101) may include a gate dielectric (136) of a high-k material and a metal gate (137). The LDMOS transistor (101) includes a source (141) and a drain (151) extending into a semiconductor substrate (104). A nanosheet region (116) extends between the source (141) and the drain (151). A nanosheet channel layer (135c) alternates with a metal gate layer (137) extending from the source (141) to the drain (151). A nanosheet drain drift layer (138) alternates with a field plate conductor layer (147) extending from the drain (151) to the source (141).

This invention provides a fully isolated LDMOS structure and its fabrication method. A P-type buried layer is formed below the N-type drift region, and an STI layer is formed in the N-type drift region between the N-type drain region and the P-type body region. This facilitates the high voltage withstand capability of the device through the vertical P-type buried layer and the surface STI field plate. Furthermore, the distance between the N-type drift region and the N-type isolation ring is increased laterally, forming a P-type well region between them. The P-type buried layer and the P-type well region achieve isolation of the drain voltage, avoiding latch-up effects and other reliability issues caused by electron injection into the substrate. In addition, the P-type epitaxial layer is formed in stages, which allows for precise control of the depth, doping concentration, and implantation energy of the P-type buried layer. By adjusting the lateral layout size and the dosage and energy of the vertical ion implantation, a fully isolated LDMOS structure in the medium-high voltage range of 60V~100V can be achieved.

The utility model provides a kind of LDMOS device.The LDMOS device, the recess and the convex part defined by recess have on the top surface of base, drain region is located in convex part, drift region is located in the base below recess bottom surface and part is located below drain region, the side surface of drain region is located above the top surface of drift region and the top surface of drift region is connected with the bottom surface of drain region, body region is located in the base below recess bottom surface and is located on the side of drift region away from drain region, gate structure is located in recess and covers part body region and part drift region, source region is located on the side of gate structure away from drain region, in the base below recess bottom surface and is located above body region.In this way, by setting recess on the top surface of base to raise drain region, the drain curvature effect disappears, and better surface electric field reduction effect is achieved.

A semiconductor device includes one or more LDMOS transistors and a semiconductor substrate having an upper surface. Each of the one or more LDMOS transistors includes: a plurality of impurity diffusion layers formed in the semiconductor substrate at the upper surface; a plurality of drain layers formed in the semiconductor substrate at the upper surface; and a plurality of insulating films formed on the upper surface. Each of the plurality of impurity diffusion layers, each of the plurality of drain layers, and each of the plurality of insulating films extend along a first direction in plan view. The plurality of impurity diffusion layers are arranged along a second direction perpendicular to the first direction in plan view while interposing a gap between two adjacent impurity diffusion layers among the plurality of impurity diffusion layers.

A semiconductor structure and a forming method thereof, the semiconductor structure comprising: a gate structure on a substrate, extending parallel to a surface of the substrate and transversely to a direction of extension of the gate structure; a drain on one side of the gate structure; a first drift region on the same side of the gate structure as the drain, a projection of the first drift region in the substrate covering a projection of the drain in the substrate; and a second drift region on an end of the gate structure close to the drain, the first drift region and the second drift region being spaced apart in the transverse direction, the second drift region having a higher ion doping concentration than the first drift region. In the embodiment, the projection of the first drift region in the substrate covers the projection of the drain in the substrate, so the first drift region bears a higher voltage drop of the drain, making the breakdown voltage of the LDMOS higher; and because the second drift region has a higher ion doping concentration than the first drift region, the on-resistance of the first drift region is smaller, making the on-current of the LDMOS larger.

MOSFET-based IC architectures, including SOI-NEDMOS ICs and bulk semiconductor LDMOS ICs, mitigate or eliminate the problems of edge transistors. One IC implementation comprises endcap-body contact regions with angled implants to exhibit a first property (e.g., P+), a drift region, and a gate structure that partially covers the endcap-body contact regions and the drift region. It also includes a conductive layer with a third property (e.g., N+) and a first side with angled implants to exhibit the first property.Steps to fabricate such an IC include implanting a dopant at an angle in the range of approximately 5° to approximately 60° within the endcap-body contact regions and within the first side of the conductive layer in a region of the gate structure that lies above the endcap-body contact regions, the angled dopant resulting in the first property for the endcap-body contact regions and the first side of the conductive layer.

The present disclosure generally relates to semiconductor devices including a material having a wide bandgap energy, or simply bandgap, located in a drift well of the semiconductor device. In an example, a semiconductor device includes a laterally-diffused metal-oxide-semiconductor (LDMOS) transistor. The LDMOS transistor includes a drain region, a source region, and a drift well. The drain region is disposed in a semiconductor material of a semiconductor substrate. The source region is disposed in the semiconductor material of the semiconductor substrate. The drift well is disposed laterally between the drain region and the source region. The drift well includes a wide bandgap material, and the wide bandgap material has a bandgap energy that is larger than a bandgap energy of the semiconductor material of the semiconductor substrate.

This application relates to the field of semiconductor integrated circuit manufacturing technology, specifically to an SOI-LDMOS device and its fabrication method. The SOI-LDMOS device includes: a substrate layer, a buried oxide layer, and an epitaxial layer stacked sequentially from bottom to top; a drift region is formed in the epitaxial layer; a source region and a drain region are formed on both sides of the drift region; a doped polysilicon field plate is formed on the drift region, and a vertical heterojunction is formed between the doped polysilicon field plate and the drift region. When the device is in the off state, the vertical heterojunction is depleted; one end of the doped polysilicon field plate contacts and overlaps with the source region to form a vertical homojunction; the other end of the doped polysilicon field plate is doped with a first conductivity type impurity to form a first conductivity type doped region; the main body of the doped polysilicon field plate forms a lateral heterojunction with the first conductivity type doped region; the doped polysilicon field plate contacts the metal electrode of the drain region through the heterojunction. The fabrication method is used to fabricate the above-mentioned SOI-LDMOS device.

The application provides an LDMOS device and a forming method, which comprises the following steps: sequentially forming an N-type buried layer and a P-type epitaxial layer; forming a P-type body region in the P-type epitaxial layer; forming a first N-type drift region and a second N-type drift region in the P-type epitaxial layer; forming a first gate on part of the first N-type drift region and part of the P-type body region, forming a second gate on part of the second N-type drift region and part of the P-type body region, and forming a first dummy gate and a second dummy gate above the first N-type drift region and the second N-type drift region by using the same mask; forming a first N+ heavily doped source region and a second N+ heavily doped source region which are arranged at intervals in the P-type body region and are separated by a P-type heavily doped region, and the first gate and the first dummy gate are symmetrically arranged with the second gate and the second dummy gate along the P-type heavily doped region; and forming a first N+ heavily doped drain region and a second N+ heavily doped drain region in the first N-type drift region and the second N-type drift region respectively.

The present invention provides a semiconductor device that can linearly change the electrical characteristics of an LDMOS transistor with respect to the number of fingers. [Solution] The semiconductor device (DEV1, DEV2, DEV3) comprises at least one LDMOS transistor (Tr) and a semiconductor substrate (SUB) having a top surface (F1). Each of the at least one LDMOS transistor has a plurality of impurity diffusion layers (ILD) formed inside and on the top surface of the semiconductor substrate, a plurality of drain layers (DRA) formed inside and on the top surface of the semiconductor substrate, and a plurality of insulating films (IF) formed on the top surface. Each of the plurality of impurity diffusion layers, each of the plurality of drain layers, and each of the plurality of insulating films extends along a first direction (DR1) in a plan view. The plurality of impurity diffusion layers are arranged with a gap between two adjacent impurity diffusion layers along a second direction (DR2) perpendicular to the first direction in a plan view.

The application provides a power semiconductor device and a preparation method thereof, and relates to the technical field of semiconductors. In the application, a main power VDMOS cell array, a sampling power VDMOS cell and at least one discharge path control LDMOS cell are integrated on a SiC epitaxial layer. When the power semiconductor device is in a working state, the sampling power VDMOS cell is used to obtain a real-time electrical signal of a JFET region; each discharge path control LDMOS cell is used to receive the real-time electrical signal, and when the real-time electrical signal exceeds a preset short-circuit threshold value, a low-resistance discharge path is turned on to discharge the charge at the gate of the main power VDMOS cell array to the source of the main power VDMOS cell array. Based on this, the short-circuit resistance time of the application is improved by integrating a short-circuit protection structure, and the short-circuit reliability of the device is improved.

The invention relates to a laterally diffused metal oxide semiconductor device and a preparation method thereof. The laterally diffused metal oxide semiconductor device comprises a semiconductor substrate, the front surface of which is provided with a first groove and a second groove which are arranged at an interval; a drift region, a body region, a source region and a drain region are arranged in the semiconductor substrate; the body region is located at the bottom of the first groove; the source region is located in the body region; the drift region is positioned on one side of the body region close to the second groove; the drain region is located in the drift region and located on the side, away from the first groove, of the second groove; the first dielectric structure is arranged in the first groove and is positioned between the body region and the second groove; one side, deviating from the second groove, of the first dielectric structure is provided with a slope part, and the thickness of the slope part is gradually reduced in the direction from the second groove to the body region; the second dielectric structure is arranged in the second groove; at least part of the field plate structure is arranged on the slope part; the grid electrode is arranged on the bottom wall of the first groove. The reliability of the device can be improved.

A power transistor device includes an LDMOS transistor element and a control circuit. The LDMOS transistor element includes a drain terminal, a source terminal, a gate terminal and a field plate. The control circuit relates a field plate control voltage applied to the field plate to a gate control voltage applied to the gate terminal: when the LDMOS transistor element operates in a strong inversion region in response to the gate control voltage having an enable potential, the field plate control voltage applied to the field plate can increase a value of on-state current in a drift region and decrease a value of on-state resistance; when the LDMOS transistor element operates in a cutoff region in response to the gate control voltage having a disable potential, the field plate control voltage applied to the field plate can increase a value of on-state resistance and a value of breakdown voltage in the drift region.

This application discloses an LDMOS and LDMOS device in a BCD process platform. The LDMOS includes a P-type well region and an N-type drift region fabricated in a substrate. The source region is located in the P-type well region, and the drain region is located in the N-type drift region. The gate region includes a connected upper substrate region and a lower substrate region. The upper substrate region covers the substrate, and the lower substrate region is located between the P-type well region and the N-type drift region. The LDMOS also includes a trench region extending from the upper surface of the LDMOS to the substrate of the LDMOS. This trench region penetrates the drain region, and its drain connection terminal is located on the trench region. Due to the use of a trench structure for the drain, the contact area between the drain electrode and the N-type drift region is increased, thereby reducing the series resistance of the drift layer by increasing the effective conduction area. Furthermore, the simultaneous use of a trench structure for the gate optimizes the internal electric field distribution of the device. Since the peak electric field of the drift layer is still limited within a safe range, the breakdown voltage is not lost.

This invention relates to an LDMOS device and its manufacturing method. The LDMOS device includes: a source region; a drain region; a drift region; a field oxide layer; a gate extending from near the edge of the source region onto the field oxide layer; a first low-doped region located directly below the field oxide layer on the side near the source region; and a second low-doped region located directly below the gate on the side near the drain region. The region between the first and second low-doped regions has a first conductivity type. The first and second low-doped regions have the first conductivity type, and their doping concentration is lower than that of the region between them; or the first and second low-doped regions have a second conductivity type. This invention introduces low-doped or inverted regions into areas of concentrated electric field, making the potential line distribution sparser in these two areas, reducing the collisional ionization rate, and mitigating the hot carrier injection effect in these areas.

The semiconductor device provided by the embodiments of the present specification has a first trench penetrating a body region and a drift region, the first trench is filled with an isolation layer covering the sidewall of the first trench and a gate structure filled in the remaining first trench; based on the above structure, the flow direction of electrons in the device can be changed from horizontal to vertical during the operation of the semiconductor device, and in the case that the depletion layer provided in the drift region remains unchanged, the space in the vertical direction of the device can be fully utilized, the wafer area required by the device in the horizontal direction is reduced, the size of the device is reduced, and thus the overall cost of the device is reduced. In addition, compared with the conventional lateral channel LDMOS device, the device has better low on-resistance characteristics and can maintain higher withstand voltage performance. Further, the preparation process of the device can be realized based on the DTI process, which is compatible with the BCD process, and compared with the existing LDMOS preparation process, the gate mask plate can be saved, which is conducive to reducing the preparation cost.

This invention relates to a laterally diffused metal-oxide-semiconductor device and its manufacturing method. The device includes: a bottom semiconductor layer; a buried dielectric layer located on the bottom semiconductor layer; a well region of a second conductivity type; a source region located in the well region of the second conductivity type; a drain region; a drift region; a gate; a first trench structure extending downward from the well region of the second conductivity type below the gate to the buried dielectric layer or the bottom semiconductor layer, including a first dielectric layer located on the inner surface of the first trench, and a first conductive material filling the first trench, the first conductive material being electrically connected to the gate; and a first doped region having a first conductivity type located below the first trench structure, the top of the first doped region being in direct contact with the bottom of the buried dielectric layer or the bottom of the first trench structure. This invention can reduce the on-resistance of the device.

The application discloses a high-mobility silicon carbide N-type LDMOS device with reduced on-resistance, which comprises an N-type substrate, a P-type epitaxial layer arranged on the N-type substrate, an N-type well region, a first P-type heavily doped region, a first N-type heavily doped region, a second P-type heavily doped region connected to a source, a second N-type heavily doped region connected to a drain arranged in the N-type well region, the first P-type heavily doped region, the first N-type heavily doped region and the second P-type heavily doped region being connected, an oxide layer arranged on the surface of the second N-type heavily doped region, the N-type well region, the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region and the P-type epitaxial layer, a polycrystalline silicon trench gate serving as a gate of the device and extending into the P-type epitaxial layer, and an N-type buried layer arranged in the P-type epitaxial layer, one end of the N-type buried layer being connected to a channel of the device and the other end being connected to the N-type well region.

This application relates to methods and systems for transistors having combined source and well contacts. A metal-oxide-semiconductor (MOS) transistor includes: a substrate including a well region; an insulating layer coupled to the substrate; and a source including a source region, a source contact passing through the insulating layer and the source region, and an ohmic contact disposed in the well region. The MOS transistor further includes: a gate region including a gate insulating layer and a gate contact; and a drain including a drain region and a drain contact passing through the insulating layer to the drain region. The MOS transistor may be an LDMOS transistor, such as an LNDMOS or LPDMOS transistor.

This invention relates to a laterally diffused metal-oxide-semiconductor (MOS) device and its manufacturing method. The MOS device includes: a substrate; a drift region disposed in the substrate; a drain region disposed in the substrate and in contact with the drift region; a body region disposed in the substrate; an insulating layer at least partially disposed in the body region; a source region located on the insulating layer; and a gate structure disposed on the substrate between the drain region and the source region. This invention, by forming isolation between the source region and the body region through the insulating layer, can mitigate the parasitic effects caused by the conduction of the PN junction formed between the source and body regions, reduce losses, and improve device performance.

This invention provides a power semiconductor device and its fabrication method, relating to the field of semiconductor technology. In this application, the power semiconductor device integrates a main power VDMOS cell array, sampling power VDMOS cells, and at least one discharge path control LDMOS cell on a SiC epitaxial layer. When the power semiconductor device is in operation, the sampling power VDMOS cell is used to acquire the real-time electrical signal of the JFET region; each discharge path control LDMOS cell is used to receive the real-time electrical signal, and when the real-time electrical signal exceeds a preset short-circuit threshold, it conducts a low-resistance discharge path to discharge the charge at the gate of the main power VDMOS cell array to the source of the main power VDMOS cell array. Based on this, this application improves its short-circuit withstand time by integrating a short-circuit protection structure, thereby enhancing the short-circuit reliability of the device.

The application provides an APC method, system, medium and product for threshold voltage of an LDMOS device, and belongs to the technical field of semiconductors. The APC method comprises the following steps: providing a substrate; etching a conductive layer and part of a first oxide layer to form a second opening, and obtaining the CD of the second opening and the thickness of the first oxide layer under the second opening; etching to form a third opening; obtaining the process conditions for performing first ion implantation on the current batch of substrates according to the CD of the second opening, the CD of the third opening and the thickness of the first oxide layer under the second opening of the current batch of substrates, combining a first APC model, and performing first ion implantation on the current batch of substrates based on the process conditions to adjust the threshold voltage of the LDMOS device. The application can be used to accurately and timely regulate the threshold voltage of the LDMOS device.

The application provides a multi-finger structure LDMOS model construction method, device and equipment, relates to the electronic circuit simulation technical field, and the method comprises the following steps: constructing a drift region resistance model reflecting the nonlinear influence of the number of finger-shaped units in the multi-finger structure on the drift region resistance; based on the drift region resistance model and the intrinsic metal oxide semiconductor, constructing an LDMOS electrical model reflecting the characteristics of the multi-finger structure; based on the thermal resistance, the heat capacity and the power consumption input source, constructing a non-distributed thermal network for simulating the self-heating effect, and nonlinearly correcting the thermal resistance of the multi-finger structure LDMOS; thermoelectrically coupling the LDMOS electrical model and the non-distributed thermal network to obtain a multi-finger structure LDMOS model including the self-heating effect. By adopting the multi-finger structure LDMOS model construction method, device and equipment, the construction accuracy of the multi-finger structure LDMOS model is improved.

This application belongs to the field of semiconductor technology and provides a high-voltage LDMOS device and its fabrication method. The high-voltage LDMOS device includes: a semiconductor substrate, a buried oxide region, a P-type well region, a source region, a P-type base region, a drain region, a drift region, a passivation layer, a dielectric layer, a source electrode, a drain electrode, a gate electrode, and a metal field plate. The dielectric layer is used to connect the drain electrode and the semiconductor substrate. By adding the dielectric layer, a MIS capacitor can be formed, making the electric field distribution near the drain region more uniform, thereby optimizing the electric field in the drain region, improving the breakdown voltage of the device, and solving the problem of low breakdown voltage in existing devices. By setting the metal field plate, the breakdown voltage space of the drain region can be fully utilized, and the electric field near the drain region can be introduced into the device, reducing the electric field pressure near the drain region, improving the breakdown voltage of the device, and thus improving the breakdown voltage capability of the device.

A semiconductor device comprises one or more LDMOS transistors and a semiconductor substrate with a top surface. Each of the one or more LDMOS transistors comprises: a plurality of impurity diffusion layers formed in the semiconductor substrate at the top surface; a plurality of drain layers formed in the semiconductor substrate at the top surface; and a plurality of insulating films formed on the top surface. Each plurality of impurity diffusion layers, each plurality of drain layers, and each plurality of insulating films extends along a first direction in the top view. The plurality of impurity diffusion layers are arranged along a second direction perpendicular to the first direction in the top view, with a gap inserted between two adjacent impurity diffusion layers beneath the plurality of impurity diffusion layers.

This invention discloses an LDMOS device and its manufacturing method. The manufacturing method includes: providing a substrate, forming a drift layer and a body region located in the drift layer on the substrate; depositing an HVOX layer on the substrate using thermal oxidation; fabricating a first field plate based on a defined first field plate region pattern; depositing a gate oxide layer on the substrate using thermal oxidation, and depositing a gate structure on the gate oxide layer; the first field plate is located on one side of the first gate structure and the second gate structure, respectively; depositing a sidewall material on the substrate; coating the deposited sidewall material with photoresist; providing a photomask for photolithography; and performing anisotropic etching after development to obtain the gate sidewall structure and the second field plate; and depositing an SAB layer on the second field plate structure to fabricate a third field plate, wherein the first field plate, the second field plate, and the third field plate constitute a stepped field plate structure.