297 results about "LDMOS" patented technology

An integrated circuit includes a nanosheet laterally-diffused metal oxide semiconductor (LDMOS) transistor. The transistor includes source and drain regions having a first conductivity type that extend into a semiconductor substrate. A nanosheet region including semiconducting nanosheets extends between the source region and the drain region. The nanosheets alternate with gate conductor layers that extend between the source region and the drain region. The nanosheets also alternate with field plate conductor layers that extend between the gate conductor layers and the drain region.

The invention relates to the technical field of semiconductors, and discloses an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a preparation method thereof, and the LDMOS device comprises a substrate layer comprising a drift region, a field oxide layer and a gate oxide layer which are located on the surface of the substrate layer, a gate structure, a polycrystalline silicon structure at the side part, a first dielectric layer and a first conductive column, the metal field plate, the second conductive through hole and the field plate connecting structure are arranged at the side part of the gate metal layer; wherein the field oxide layer is located on the surface of the drift region, and the gate structure, the drift region and the field oxide layer between the gate structure and the drift region form a first field plate structure; the metal field plate, the polycrystalline silicon structure and the first dielectric layer therebetween form a first capacitor, the polycrystalline silicon structure, the drift region and the field oxide layer therebetween form a second capacitor, and the first capacitor and the second capacitor are coupled in series to form a second field plate structure; the first field plate structure and the second field plate structure are connected through the field plate connecting structure and the second conductive through hole to form a double-field-plate structure. According to the invention, the breakdown voltage of the device can be improved under the condition of low on-resistance.

A LDMOS including a semiconductor substrate, a gate oxide, a gate, field plate oxide layers and field plate barrier layers is disclosed. A first field plate oxide layer and a second field plate oxide layer are positioned atop the gate oxide with a spacing between them. A first field plate barrier layer and a second field plate barrier layer are positioned atop the first and the second field plate oxide layers, respectively. A third field plate barrier layer is positioned atop the first and the second field plate barrier layers and the spacing. A third field plate oxide layer is positioned atop the third field plate barrier layer. The third field plate oxide layer includes a first portion positioned atop the first field plate oxide layer and a second portion positioned atop the spacing. A fourth field plate barrier layer is positioned atop the third field plate oxide layer.

The invention provides a low-delay level shift circuit, and belongs to the technical field of analog integrated circuit power management, the circuit comprises a level shift core circuit and an edge detection logic circuit, the level shift core circuit adopts a high-voltage-resistant LDMOS to complete conversion of different voltage domain signals on the basis of a traditional cross coupling structure, and the edge detection logic circuit is connected with the edge detection logic circuit. The edge detection logic circuit detects a fast falling edge of the level shift core circuit, and an output signal only related to the fast edge is obtained after logic operation. The low-delay level shift circuit provided by the invention has no static power consumption, the delay of the level shift circuit can be reduced to below 1ns, the delay time of the low-delay level shift circuit is obviously reduced compared with the delay time of a traditional two-stage cross coupling level shift circuit, and the low-delay level shift circuit is suitable for the field of SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) driving with higher requirements on propagation delay.

The invention discloses a preparation method of an LDMOS (Laterally Diffused Metal Oxide Semiconductor) and an LDMOS device, and the preparation method of the LDMOS comprises the steps: providing a semiconductor substrate, and forming an LDMOS device region on the semiconductor substrate; forming an oxide layer on the region where the LDMOS device is formed; forming a grid electrode on the oxidation layer corresponding to the area between the source electrode area and the drain electrode area, and forming a step-shaped field plate structure on the corresponding oxidation layer above the drift area; forming a first dielectric layer covering the grid electrode and the stepped field plate structure; forming a first through hole and a second through hole which are respectively communicated to the source region and the drain region in the first dielectric layer, and forming a plurality of third through holes which are respectively communicated to different steps of the stepped field plate structure; the at least one third through hole electrically connects a step of the stepped field plate structure with the drain region. By adopting the method, the drain-source breakdown voltage performance of the device in a conducting state is improved, and the high-voltage breakdown of the drain electrode is effectively prevented.

The invention provides an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a preparation method thereof. The LDMOS device comprises a substrate; the first conductive type drift region and the second conductive type body region adjacent to the first conductive type drift region are both located in the substrate; the grid electrode is located on the first conduction type drift region and extends to the second conduction type body region; the groove is positioned in the first conduction type drift region and is self-aligned with the edge of the grid electrode; the side walls are located on the side edges of the two sides of the grid electrode and extend to the side edges of the groove; and the barrier layer fills the groove and extends to a part of the upper surface of the grid electrode. According to the LDMOS device, breakdown voltage is maintained and even improved, on-resistance is reduced, the length of the drift region is reduced, and the size of the device is further reduced.

The invention discloses an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a preparation method thereof. The LDMOS device comprises a semiconductor layer of a first doping type; the body region and the drift region are located in the semiconductor layer, the body region is provided with a first doping type, the drift region is provided with a second doping type opposite to the first doping type, the drift region comprises a plurality of partitions arranged in the horizontal direction, and the partitions are separated from one another; the source region is positioned in the body region; the drain region is positioned in the drift region; the source region and the drain region have a second doping type; the gate conductor is positioned on the surface of the semiconductor layer between the source region and the drain region; the polycrystalline silicon field plates are positioned on the surface of the partition between the source region and the drain region; wherein the plurality of polycrystalline silicon field plates are electrically connected with one another and are externally connected with voltage.

The invention provides a thermal resistance model construction method of an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device, which is characterized in that a plurality of N-type doped isolation layers are formed on a substrate, an LDMOS structure is formed on each N-type doped isolation layer, all LDMOS structures are divided into different test groups according to different key sizes, and the key sizes at least comprise a total channel width and a cross index; measuring the thermal resistance of the LDMOS structure in each test group so as to respectively extract a thermal resistance value array of each group, and performing data fitting on the thermal resistance value array of each group so as to obtain a thermal resistance model of the relationship between the thermal resistance value of the LDMOS structure and the critical dimension; according to the method, the thermal resistance model of the full-size LDMOS device can be constructed by only utilizing a limited number of LDMOS structures in a primary tape, so that the thermal resistance of the LDMOS devices with different sizes can be predicted, the self-heating effect of the device can be accurately evaluated in the design stage, the device design is optimized, the development cost of the device is reduced, and the research and development period is shortened.

The invention provides an LDMOS device and a manufacturing method thereof, and relates to the technical field of semiconductors. The LDMOS device may include: a semiconductor substrate; the drift region is located on the semiconductor substrate and is provided with a first conduction type; the body region is located at one end of the drift region and has a second conductive type; the gate structure is positioned on the surface of the body region and partially extends to the drift region; the source region is located in the body region and is adjacent to one side of the gate structure, and the body contact region is adjacent to the source region and is of a second conduction type; the drain region is located at one end, away from the body region, of the drift region; and the plurality of strip-shaped current modulation units are arranged in the drift region in an interdigital alternate arrangement mode, and extend and are arranged in the direction from the body region to the drain region. The chip has the advantages of being low in cost, small in overall chip area and easier to manufacture.

A structure for a laterally diffused metal oxide semiconductor device and a method of forming a structure for a laterally diffused metal oxide semiconductor device. The structure includes a drain and a source in a semiconductor substrate. The source includes a source region having a first terminal, a second terminal, and a length between the first terminal and the second terminal. The structure also includes a shallow trench isolation region in the semiconductor substrate. The shallow trench isolation region surrounds the drain. The structure also includes a gate surrounding the shallow trench isolation region and the drain. The gate has a side portion between the drain and source regions, the side portion of the gate having a width, and the gate having a length in a direction transverse to the width. A length of the source region is substantially equal to a length of the gate.

The invention provides an LDMOS process TVS (Transient Voltage Suppressor) device and a manufacturing method thereof, and belongs to the technical field of TVS semiconductor preparation. Comprising a P-type silicon substrate, the surface of the P-type silicon substrate is provided with a deep N well, the deep N well is used for providing isolation for a source / drain high-voltage N + region and preventing punch-through or premature breakdown between the deep N well and the P-type substrate, the deep N well is used as a collector region of a parasitic NPN BJT, and a P-type body region is arranged in the deep N well. According to the invention, the inherent high-voltage capability of an LDMOS and a parasitic BJT structure are utilized to realize rapid triggering and low clamping, the manufacturing process is highly compatible with a standard CMOS / BCD process, key parameters such as breakdown voltage, clamping voltage, capacitance, surge capability and the like can be optimized by accurately designing a drift region, a P body region, a deep N well and layout, various harsh circuit protection requirements are met, and the reliability of the device is improved. The method is particularly applied to applications requiring low capacitance, high integration level and high reliability.

The invention relates to an LDMOS with a bias circuit for biasing a field plate. A semiconductor device (100) includes: a drain extension transistor (101) having: a semiconductor layer (104) including oppositely doped body and drain drift regions (104, 120); a gate dielectric layer (134) over the body region (104) and extending over a junction between the body region (104) and the drain drift region (120); a gate electrode (140) over the gate dielectric layer (134); a drain region (160) in the drain drift region (120) and having a dopant density greater than a dopant density of the drain drift region (120); and a field plate (142) between the gate electrode (140) and the drain region (160); and a bias circuit (190) including an output coupled to the field plate (142) and a bias input coupled to a gate drive circuit (192).

The embodiment of the invention provides a SiC LDMOS device, a manufacturing method and a chip. The SiC LDMOS device comprises a P-type substrate; the N-type buried layer is located in the P-type substrate; the N-type epitaxial layer is located on the surface of the P-type substrate and the surface of the N-type buried layer; the P-type injection layer is located in the N-type epitaxial layer, and the bottom of the P-type injection layer is connected with part of the surface of the N-type buried layer; the P-type body region is located in the N-type epitaxial layer and extends into the P-type substrate; and the N-type buffer layer is located in the P-type injection layer and extends into the N-type buried layer. When the device is in a reverse withstand voltage state, the drift region is depleted, ionization donors in the P-type injection layer and the P-type substrate emit power lines and point to ionization acceptors of the N-type buried layer and the N-type epitaxial layer, the N-type epitaxial layer and the N-type buried layer are mutually overlapped, electric field distribution in the drift region of the device can be effectively adjusted, an electric field peak is introduced to the surface of the drift region of the device, and the device is prevented from being damaged. And the overall electric field of the drift region is lifted, so that the voltage resistance of the device is improved.

A metal-oxide-semiconductor (MOS) transistor includes a substrate including a well region, an insulator layer coupled to the substrate, and a source including a source region, a source contact passing through the insulator layer and the source region, and an ohmic contact disposed in the well region. The MOS transistor also includes a gate region including a gate insulator layer and a gate contact and a drain including a drain region and a drain contact passing through the insulator layer to the drain region. The MOS transistor can be an LDMOS transistor, for example, an LNDMOS or LPDMOS transistor.

The invention provides a high-voltage Resurf LDMOS (Laterally Diffused Metal Oxide Semiconductor) device structure capable of resisting a single-particle burning effect. The device comprises a P-type substrate, an N-type epitaxy, a P-type buried layer, a P-type well region, a source region P + injection, an N-type well region, a source region N + injection, a drain region N + injection, a gate oxide layer, a field oxide layer, polycrystalline silicon and metal. According to the invention, the unequal-length P-type buried layer is introduced into the N-type drift region, and the P-type buried layer is directly connected with the P-type substrate, so that an extra leakage path is provided for hole current generated by single-particle radiation. A long P-type buried layer is introduced below an N-type drift region to improve the extraction capability of hole current, a short P-type buried layer is introduced above the N-type drift region to relieve the electric field concentration phenomenon of a drain side N + region, and the unequal-length P-type buried layers act together to inhibit the parasitic triode self-maintenance phenomenon caused by single-particle incidence and improve the single-particle burnout resistance of the device.

A structure for a FinFET, a FinFET and an LDMOS device are disclosed. The structures include a trench isolation adjacent a semiconductor fin and configured to increase a height of the semiconductor fin without increasing the footprint. The fin has junction and gate regions, and the trench isolation is adjacent a lower region the fin. The FinFET includes a first recess in the trench isolation adjacent the gate region of the fin, and a second recess in the trench isolation adjacent the junction region of the fin. The first recess is at least partially filled with a high dielectric constant (high-K) layer and a gate metal, and the second recess is at least partially filled with a low dielectric constant (low-K) layer. The trench isolation includes an upper portion and a lower portion that include materials of different compositions, e.g., a dopant in the upper portion.

Disclosed examples include microelectronic devices, e.g., integrated circuits and methods of making such devices. One example includes a microelectronic device including a nanosheet laterally-diffused metal oxide semiconductor (LDMOS) transistor. The LDMOS transistor may include a high-k gate dielectric and a metal gate. The (LDMOS) transistor includes source and drain regions having a first conductivity type that extend into a semiconductor substrate. A nanosheet region including semiconducting nanosheets extends between the source region and the drain region. The nanosheets alternate with gate conductor layers that extend between the source region towards the drain region and field plate conductor layers that extend from the drain region towards the source region with gate dielectric layers and field relief dielectric layers separating the gate conductor layers from the field plate conductor layers.

The invention discloses an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device in an FDSOI process, which is formed on a mixed region semiconductor substrate and comprises a channel region, a drift region and a gate structure, and the gate structure is formed on the top surface of the channel region and extends to the top surface of the adjacent drift region. The source region and the drain region are formed in the first lifting epitaxial layer and the second lifting epitaxial layer respectively, the second lifting epitaxial layer is formed on the top surface of the drift region, and a first spacer region is arranged between the second lifting epitaxial layer and the second side face of the gate structure. And a refractory silicide barrier layer is formed on the top surface of the drift region of the first spacer region. A high-resistance layer is further formed in the first spacer region, and the bottom surface of the high-resistance layer is in direct contact with the top surface of the refractory silicide barrier layer or an interlayer film is arranged between the bottom surface of the high-resistance layer and the top surface of the refractory silicide barrier layer in a spaced mode. The invention further discloses a manufacturing method of the LDMOS device in the FDSOI process. The on-state resistance of the device can be reduced, and meanwhile the breakdown voltage of the device is not reduced.

This invention provides a high-voltage LDMOS and its manufacturing method. The shallow region of the substrate has two mutually spaced-apart STI regions. The first STI region includes multiple mutually spaced-apart segmented structures. The deep region of the substrate has a drift region that encloses the first STI region. A shallow inversion region is located at the bottom of the multiple mutually spaced-apart segmented structures, formed by boron ion implantation. A first N+ region is located between the first and second STI regions. A second N+ region is located on the side of the second STI region away from the first STI region. A deep well is located on the side of the second STI region away from the first STI region, enclosing a portion of the second STI region. An N-well enclosing the second N+ region is located within the deep well. A P-well is located on the side of the first STI region away from the second STI region. A field plate is located on the upper surface of the substrate. A P+ region and a third N+ region are also located within the P-well. The LDMOS of this invention employs field plate STI segmentation and boron ion implantation after STI. The high-voltage NLDMOS structure can simultaneously improve low on-resistance and high breakdown voltage performance, thus improving device performance.

An LDMOS structure, its design layout, and manufacturing method are disclosed. The structure includes: a semiconductor substrate; a buried layer of a first doped type located within the semiconductor substrate; a well region of a second doped type located within the buried layer; and a drain region of a first doped type completely surrounding the well region located within the buried layer. In the channel direction parallel to the LDMOS structure, the buried layer within the drain region is divided into two parts by undoped buried regions. In the channel direction perpendicular to the LDMOS structure, the undoped buried regions are flush with the inner sides of the drain regions. This invention can effectively improve the bottom volume (BV) of the device and enhance the quality of the semiconductor device.

The application discloses a diode load type high-voltage level shift circuit with anti-negative voltage capability, and belongs to the technical field of power electronics and power integrated circuits. The application comprises a narrow pulse generation circuit, a level shift module, a cross-coupled current mirror module, a current-voltage conversion module and an RS latch. The narrow pulse generation circuit converts an input signal into two narrow pulse signals, controls the conduction and turn-off of an LDMOS tube in the level shift module, the cross-coupled current mirror module cross-mirrors the conduction current of the LDMOS tube, and outputs a clean and stable narrow pulse level signal through the current-voltage conversion module; and the RS latch restores the narrow pulse signal into a normal signal. The application adopts a diode load to replace a traditional resistor, reduces the sensitivity of an output voltage to resistance, avoids the breakdown of a gate in a later stage, and significantly improves the anti-negative voltage capability through optimization of a current path, and has the advantages of simple structure, high reliability, good temperature stability and the like.

The application discloses a super-junction LDMOS device with high-resistance substrate TSV grounding and a manufacturing method thereof. The super-junction LDMOS device comprises a high-resistance substrate, a body region and a drift region formed in the high-resistance substrate, a body region contact region and a source region formed in the body region, a polysilicon gate formed on a substrate surface above the body region, and a drain region formed in the drift region. The drift region comprises a super-junction structure formed by a first column region and a second column region arranged at intervals in a gate width direction. A first buffer layer is arranged between the first column region and the drain region, a second buffer layer is arranged between the second column region and the drain region, and the first buffer layer and the second buffer layer are arranged to surround the drain region. The super-junction LDMOS device can effectively suppress substrate auxiliary effect, can realize optimal design of device breakdown voltage and on-resistance, and can reduce output capacitance of the device.

A laterally-diffused metal-oxide semiconductor (LDMOS) device may include a semiconductor layer having a trench therein, and a superlattice liner in the trench. The superlattice liner may include stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer, and each at least one non-semiconductor monolayer of each group of layers being constrained within a crystal lattice of adjacent base semiconductor portions. The LDMOS may further include a shallow trench isolation (STI) region within the trench, spaced-apart source and drain regions in the semiconductor layer on opposite sides of the trench, a gate on the semiconductor layer between the source and drain regions, and a drift region in the semiconductor layer surrounding the trench and separated from the STI region by the superlattice liner.

A transistor is disclosed. The transistor includes a source region and a drain region, both exhibiting a first conductivity type. The transistor also includes a channel region adjacent to the source region, exhibiting a second conductivity type. The transistor further includes a drift region located between the drain region and the channel region, the drift region having a width smaller than the drain region. Additionally, the transistor includes a trench region located adjacent to the drift region on a first side and on a second side of the drift region.

The LDMOS device model comprises a BSIM4 model, a plurality of segmented resistor models which are sequentially connected in series and a plurality of drain substrate diode models, and the segmented resistor models which are sequentially connected in series are connected to a drain electrode of the BSIM4 model in series. A drift region of an LDMOS is simulated through a plurality of segmented resistor models which are sequentially connected in series, and the input end of each segmented resistor model is connected with a corresponding drain substrate diode model. Due to the fact that the segmented resistor models are connected in series, changes of electrical characteristics of drain substrate diodes at different positions of a drift region are simulated, and then the simulation precision of the LDMOS device model on drain substrate parasitic capacitance and gate channel intrinsic capacitance of an LDMOS is improved. And the simulation precision of the reverse leakage current of the drain substrate diode is improved.

The invention discloses a junction temperature online monitoring system and method of an LDMOS device, and relates to the technical field of power electronic junction temperature monitoring. Through mutual cooperation of a device port data acquisition and preprocessing module, an AI-based junction temperature analysis module and a junction temperature data display module, through the device port data acquisition and preprocessing module, a low-disturbance sampling circuit structure is adopted; the current, voltage, noise and port temperature data of the source electrode end, the grid electrode end and the drain electrode end of the LDMOS device are collected and preprocessed in real time; the AI-based junction temperature analysis module adopts a multi-feature fusion model based on a deep neural network, and combines the collected data to construct a target junction temperature analysis model for junction temperature prediction; and the junction temperature data display module visually displays the prediction result and automatically gives an alarm when the junction temperature is abnormal. According to the invention, real-time online junction temperature monitoring can be realized on the premise of not influencing the normal work of the device, and the operation state of the device can be accurately evaluated.

The application relates to a frequency doubling device and a multiple frequency doubling apparatus. The frequency doubling device comprises a substrate, a first high-voltage switch module, a second high-voltage switch module and a MOM capacitor. The application replaces the operational amplifier in the traditional frequency doubling circuit with the first high-voltage switch module, the second high-voltage switch module and the MOM capacitor, can generate a frequency doubling signal based on a reference pulse signal and an input voltage, and is suitable for a high-voltage environment. Meanwhile, due to the large chip area of the LDMOS tube, there is sufficient space above the first high-voltage switch module and the second high-voltage switch module to configure a suitable MOM capacitor.

The invention provides an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a manufacturing method thereof. The LDMOS device comprises an epitaxial layer; the drift region and the body region are located in the epitaxial layer; the gate structure is located on the epitaxial layer and stretches across the drift region and the body region; the drain injection region is positioned in the drift region; the source injection region and the plurality of body region injection regions are positioned in the body region; wherein the source injection region comprises a plurality of first source injection regions and a plurality of second source injection regions; the plurality of first source injection regions and the plurality of body region injection regions are alternately distributed in the channel width direction of the LDMOS device; and the plurality of second source injection regions are respectively positioned in the side edge regions, facing the gate structure, of the plurality of body region injection regions so as to form the source injection regions which are communicated along the width direction of the channel. According to the scheme, the N-type injection region is additionally arranged on the polycrystalline silicon channel side of the device to achieve channel compensation, and balance among the cellular pitch, the leakage current and the electric safety working region of the device is better achieved under the condition that the specific on-resistance of the device can be reduced.

The application relates to the technical field of LDMOS, and discloses an LDMOS transistor structure and a corresponding manufacturing method, which comprise a device body, the device body comprises a substrate layer and an N-type drift region located above the substrate layer, at least two second gates are arranged at a predetermined distance interval above the N-type drift region; when the device body is in an off state, a voltage is applied to the at least two second gates so as to increase the breakdown voltage at the corresponding positions; when the device body is in an on state, a voltage is applied to the at least two second gates so as to reduce the on-resistance; the application realizes a breakthrough in the contradiction between the breakdown voltage and the on-resistance through the above technical scheme, improves the reliability of a power semiconductor chip and an electric power intelligent device, and ensures the safe and stable operation of a power grid.

The invention discloses an ultrahigh-voltage isolating ring structure. The structure includes a laterally diffused metal oxide semiconductor structure and a floating metal field plate formed on a semiconductor substrate. The laterally diffused metal oxide semiconductor structure includes a drift region. The floating metal field plate is formed on the dielectric layer above the drift region and is electrically isolated from the drift region through the dielectric layer. By arranging the floating metal field plate, electric field distribution on the surface of the drift region can be homogenized by utilizing a capacitance coupling effect, and electric field concentration caused by charge accumulation under high-temperature reverse bias stress is inhibited, so that the long-term working reliability and the service life of the ultrahigh-voltage isolating ring structure are remarkably improved; and meanwhile, the original breakdown voltage performance is not influenced.