547 results about "LDMOS" patented technology

The invention relates to an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a manufacturing method thereof. The LDMOS device comprises a semiconductor substrate; the body region and the drift region are formed in the semiconductor substrate, the source region is located in the body region, and the drain region is located in the drift region; the at least two shallow trench isolation structures are formed in the drift region, the tops of the at least two shallow trench isolation structures are higher than the surface of the semiconductor substrate, and a dielectric layer is formed between the parts, higher than the surface of the semiconductor substrate, of the at least two shallow trench isolation structures; and the gate structure comprises a gate dielectric layer and a gate electrode layer located on the gate dielectric layer, and the gate structure transversely extends to the drift region from the body region and at least partially covers the shallow trench isolation structure. The LDMOS structure has a relatively high breakdown voltage.

There is provided a high withstand voltage LDMOS field-effect transistor that enables the compatibility of an increase of its withstand voltage and a decrease of its ON resistance. The high withstand voltage LDMOS is characterizing in including: a first electroconductive type body region formed on a main surface of a semiconductor substrate; a second electroconductive type source region formed on a surface of the body region; a second electroconductive type drift region formed so as to have contact with the body region; a second electroconductive type drain region formed on the drift region; a first electroconductive type buried region having contact with the body region and formed below the drift region; a gate electrode formed above the body region between the source region and the drift region and above the drift region nearer to the source region via a gate insulating film; a first field plate that extends from the gate electrode toward the drain region and that is formed above the drift region via a first insulating film; and a second field plate that has contact with the source region or the gate electrode and that is formed above the first field plate via a second insulating film, in which a distance between the buried region and the drain region is smaller than a distance between the first field plate and the drain region and larger than a distance between the second field plate and the drain region.

An integrated circuit includes a nanosheet laterally-diffused metal oxide semiconductor (LDMOS) transistor. The transistor includes source and drain regions having a first conductivity type that extend into a semiconductor substrate. A nanosheet region including semiconducting nanosheets extends between the source region and the drain region. The nanosheets alternate with gate conductor layers that extend between the source region and the drain region. The nanosheets also alternate with field plate conductor layers that extend between the gate conductor layers and the drain region.

The invention provides an LDMOS (Laterally Diffused Metal Oxide Semiconductor) drift region LOCOS growth method. The LDMOS drift region LOCOS growth method comprises the following steps: providing a silicon substrate; defining an LOCOS region on the surface of the silicon substrate, wherein the region except the LOCOS region in the silicon substrate is a non-LOCOS region; surface modification is carried out on the silicon substrate in the LOCOS area, a lattice damage area is formed in the LOCOS area, and the area outside the lattice damage area in the silicon substrate is a non-lattice damage area; the oxide growing on the surface of the silicon substrate is consumed through a furnace tube, and the growth rate of the oxide in the lattice damage area is larger than that of the oxide in the non-lattice damage area; the oxide is etched, the oxide in the non-LOCOS area is removed, and the remaining oxide in the LOCOS area serves as LOCOS. According to the technical scheme, the LOCOS is generated through the difference formed by the silicon substrate by utilizing the characteristics that crystal lattices are damaged after the ions are injected into the silicon substrate and the speed of generating oxides during high-temperature oxidation is higher than that of generating oxides during high-temperature oxidation of the silicon substrate, and compared with a traditional mode, the proportion of beaks is reduced, so that the size of the device is reduced.

The disclosure provides a LDMOS device and a fabrication method. By arranging a first field oxide, a second field oxide, a third field oxide, a gate polysilicon, and a gate oxide layer in the trench and making the surface of the gate polysilicon away from the trench flush with the trench opening, the lateral dimension of the LDMOS device is reduced. Meanwhile, by setting the thickness of the first field oxide and the third field oxide to be greater than that of the second field oxide, setting the height of the first field oxide to be less than or equal to the distance from the bottom of the trench to the channel region, and making the surface of the third field oxide away from the trench flush with the opening of the trench, three independent field plates are formed in the trench. This improves breakdown voltage resistance of the LDMOS device.

According to the semiconductor device and the manufacturing method thereof provided by the invention, the inversion lightly doped region different from the drift region is formed in the drift region close to the drain region below the field plate of the LDMOS device region, so that the electric field at the corner below the field plate is adjusted through the inversion lightly doped region, the breakdown voltage of the LDMOS device is improved, and the HCI effect can be improved. Besides, injection is carried out on the LDMOS device region when injection is carried out on the lightly doped drain region of the CMOS device region to form the inverted lightly doped region, so that a photomask does not need to be additionally arranged, and the cost is relatively low.

The utility model provides a double-channel planar gate silicon carbide LDMOS. The double-channel planar gate silicon carbide LDMOS is characterized in that a first N-type source region is connected with a silicon carbide substrate; the first channel region is connected with the silicon carbide substrate and the first N-type source region; the isolation region is respectively connected with the first channel region, the first N-type source region and the second N-type source region; the second channel region is connected to the isolation region and the first N-type source region; the P-type well region is connected with the isolation region and the second channel region, and the P-type well region is connected to the first N-type source region; the second N-type source region is arranged in the first through hole, the second N-type source region is connected to the isolation region, the body diode metal layer is arranged in the second through hole, and the body diode metal layer is connected to the isolation region; the gate dielectric layer is connected with the P-type well region, the source metal layer is arranged in the third through hole, and the source metal layer is connected to the second N-type source region and the body diode metal layer; the gate metal layer is connected to the gate dielectric layer; the drain metal layer is connected to the first N-type source region; double-channel structure design is carried out in the transverse power device, so that the on-resistance of the device is reduced.

The utility model provides a semiconductor device. The semiconductor device comprises a semiconductor substrate of a first conductive type; the deep well of the second conduction type is located in the semiconductor substrate; the shallow well of the first conductive type is located in the semiconductor substrate on the outer side of the deep well of the second conductive type; the JFET source electrode region, the drain electrode region and the LDMOS source electrode region are arranged at intervals; a field oxide layer, a JFET polysilicon gate and an LDMOS polysilicon gate, the field oxide layer is located in the deep trap of the second conduction type, and the JFET polysilicon gate and the LDMOS polysilicon gate are located on the field oxide layer; and the high-voltage well of the first conduction type comprises a first part and a second part, the first part is located in the deep well of the second conduction type between the JFET source region and the drain region, the second part is located in the deep well of the second conduction type between the drain region and the LDMOS polysilicon gate, and the second part is distributed in a polygonal matrix. The semiconductor device provided by the utility model can meet the performance requirements of the LDMOS and the JFET at the same time.

The invention discloses a semiconductor device critical breakdown characteristic simulation method based on a hybrid finite volume method. The method comprises the following steps: firstly, carrying out geometric modeling on a device, and carrying out mesh generation; then, the quality of the grids is judged, an FBM method is adopted for the grids with the good quality, and a CVFEM method is adopted for the grids with the poor quality to discretize a drift-diffusion equation set; and then, solving the discrete drift-diffusion equation set system by adopting a full-coupling Newton iteration method, and realizing the optimization of the boost numerical simulation process by adopting an automatic boost strategy and an initial value extrapolation method. And finally, obtaining physical field information of a power semiconductor device (LDMOS) under different external bias voltages, calculating terminal current through a post-processing method, and obtaining an I-V characteristic curve of the device after the avalanche breakdown effect is considered. The method has good numerical calculation precision, numerical stability and grid adaptability, and the complete benchmarking with the solution precision of an international advanced semiconductor simulation tool Sentaur TCAD is realized.

Novel NEDMOS and / or LDMOS FET integrated circuit structures that reduce or eliminate the floating body effect by reducing the built-in voltage Vbi of the device. Reduction of Vbi includes adding a source-side structure that includes a “Vbi Reduction Material” (VRM) layer. VRM has a bandgap less than the bandgap of Si and, for an N-type device, a valence band that is higher than the valence band of the body material. The low Vbi of the VRM layer on the source-side of a MOSFET device that would otherwise exhibit a floating body effect allows significantly freer movement of holes from the body of the device towards the source region, thus increasing body hole collection efficiency, and significantly reduces the floating body effect.

The present application relates to a laterally-diffused metal-oxide semiconductor device and a preparation method therefor. The laterally-diffused metal-oxide semiconductor device comprises: a substrate 10; a first doped region 111, which is arranged in the substrate 10; a second doped region 123, which is arranged in the substrate 10 and is located on the side of the first doped region 111 close to a surface of the substrate 10; a first trench 13, which is arranged in the substrate 10 and is open from the surface of the substrate 10 and extends to the first doped region 111 to expose part of the first doped region 111; a drain region 121, which is arranged in the exposed part of the first doped region 111; a source region 122, which is arranged in the substrate 10; a gate 20, which is arranged on the side of the source region 122 away from the drain region 121; and a well region 124, which is arranged in the substrate 10, wherein the well region 124 extends towards the first doped region 111 from the surface of the substrate 10 and is adjacent to the second doped region 123, and the well region 124 is located between the gate 20 and the drain region 121.

The invention relates to the technical field of semiconductors, and discloses an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a preparation method thereof, and the LDMOS device comprises a substrate layer comprising a drift region, a field oxide layer and a gate oxide layer which are located on the surface of the substrate layer, a gate structure, a polycrystalline silicon structure at the side part, a first dielectric layer and a first conductive column, the metal field plate, the second conductive through hole and the field plate connecting structure are arranged at the side part of the gate metal layer; wherein the field oxide layer is located on the surface of the drift region, and the gate structure, the drift region and the field oxide layer between the gate structure and the drift region form a first field plate structure; the metal field plate, the polycrystalline silicon structure and the first dielectric layer therebetween form a first capacitor, the polycrystalline silicon structure, the drift region and the field oxide layer therebetween form a second capacitor, and the first capacitor and the second capacitor are coupled in series to form a second field plate structure; the first field plate structure and the second field plate structure are connected through the field plate connecting structure and the second conductive through hole to form a double-field-plate structure. According to the invention, the breakdown voltage of the device can be improved under the condition of low on-resistance.

The present invention relates to an LDMOS device and a method of forming the device, in which a barrier layer includes n etch stop layers. Insulating layers are formed between adjacent etch stop layers. Since an interlayer dielectric layer and the insulating layers are both oxides that differ from the material of the etch stop layers, etching processes can be stopped at the n etch stop layers when they are proceeding in the oxides, thus forming n field plate holes terminating at the respective n etch stop layers. A lower end of the first field plate hole proximal to a gate structure is closest to a drift region, and a lower end of the n-th field plate hole proximal to a drain region is farthest from the drift region. With this arrangement, more uniform electric field strength can be obtained around front and rear ends of the drift region, resulting in an effectively improved electric field distribution throughout the drift region and thus in an increased breakdown voltage.

Structures for a laterally-diffused metal-oxide-semiconductor device and methods of forming same. The structure comprises a semiconductor substrate including a trench, a source and a drain in the semiconductor substrate, a dielectric layer inside the trench, and a gate in the dielectric layer. The trench has a first sidewall and a second sidewall, the source is adjacent to the first sidewall of the trench, the drain is adjacent to the second sidewall of the trench, and the gate is laterally between the first sidewall of the trench and the second sidewall of the trench. The structure further comprises an air gap in the dielectric layer. The air gap is below the gate, and the air gap is laterally between the first sidewall of the trench and the second sidewall of the trench.

A LDMOS including a semiconductor substrate, a gate oxide, a gate, field plate oxide layers and field plate barrier layers is disclosed. A first field plate oxide layer and a second field plate oxide layer are positioned atop the gate oxide with a spacing between them. A first field plate barrier layer and a second field plate barrier layer are positioned atop the first and the second field plate oxide layers, respectively. A third field plate barrier layer is positioned atop the first and the second field plate barrier layers and the spacing. A third field plate oxide layer is positioned atop the third field plate barrier layer. The third field plate oxide layer includes a first portion positioned atop the first field plate oxide layer and a second portion positioned atop the spacing. A fourth field plate barrier layer is positioned atop the third field plate oxide layer.

The invention provides an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a preparation method thereof, and the method comprises the steps: forming a first oxide layer on a substrate, the material of the first oxide layer being a silicon-rich oxide; performing nitrogen ion implantation and annealing process treatment on the first oxide layer to form a Si-N bond and an N-O bond in the first oxide layer, so that the relative dielectric constant of the first oxide layer is at least 4.2; a first nitride layer is formed on the first oxide layer, the first oxide layer and the first nitride layer form a silicide barrier layer, and the silicide barrier layer is located above a part of the gate structure of the substrate and on the substrate between the gate and the drain region; and forming a dielectric layer, which is higher than the first nitride layer, on the surface of the substrate, and forming a conductive structure at a preset position of the dielectric layer. According to the scheme of the invention, through a mode of improving the relative dielectric constant and the density of the first oxide layer, the damage of the first oxide layer is greatly reduced when the conductive structure is formed, and then the voltage endurance capability of the semiconductor device is improved.

The invention provides a manufacturing method of an SOI BCD process integrated SGT device, and the method comprises the steps: providing an SOI substrate of a first conduction type, the SOI substrate is composed of a substrate of the first conduction type, an oxide layer and a thin silicon layer which are sequentially stacked from bottom to top, and the substrate comprises a forming region of an MOS device of the first conduction type, a forming region of an LDMOS device and a forming region of an SGT device; removing the oxide layer and the thin silicon layer on the SGT device, and then forming an epitaxial layer of a first conductive type on the substrate; shallow trench isolation is formed on the epitaxial layer to define an active region, a first deep trench and a second deep trench are respectively formed on the epitaxial layer in the formation region of the MOS device of the first conductive type and the formation region of the LDMOS device, and the bottom ends of the first deep trench and the second deep trench extend to the substrate; and respectively forming a first deep trench isolation structure and a second deep trench isolation structure in the first deep trench and the second deep trench. According to the invention, the SGT device and the LDMOS device are integrated, a solution is provided for the manufacturing of the intelligent high-side switch chip, and the competitiveness is improved.

The invention relates to an LDMOS device and a preparation method thereof. The LDMOS device comprises a semiconductor substrate, a first drift region, a first well region, a first source-drain region, a second source-drain region and an embedded field plate unit. The first drift region and the first well region are formed in the semiconductor substrate and adjacent to each other. The first source-drain region is disposed in the first drift region. The second source-drain region is disposed in the first well region. The embedded field plate unit comprises a first shallow trench isolation structure and a conductive layer. The first shallow trench isolation structure is arranged in the first drift region and located between the first source-drain region and the second source-drain region. The conductive layer is embedded in the first shallow trench isolation structure.

A number of MOSFET architectures provide high-voltage capability (both drain-source breakdown voltage BVDSS and ON-state breakdown voltage BVON), low current leakage, and extended linearity. Embodiments of the invention overcome the limitations of conventional NEDMOS and LDMOS device designs by providing a low-resistance path for hole collection and by purposefully exhibiting multiple voltage thresholds VTH in different segments of the device. Embodiments includes NEDMOS and LDMOS device designs having multiple body contact regions for improved hole collection, sub-gate doped stripes or segments for even better hole collection and linearity, and sub-gate doped edge regions for increased local VTH and thus decreased current leakage. P– hole-collection stripes and P+ body contact regions may be formed of a semiconductor material that includes germanium. The inventive MOSFETs may be arranged as multi-MOSFET array elements, and multiple array elements may be arranged in a larger array.

The invention discloses an integrated high-performance LDMOS device and a preparation method thereof, and the method comprises the steps: forming a first polysilicon layer at one side of a second well region, a third well region and an oxide layer, forming a second polysilicon layer at the other side of the oxide layer, and forming resistive field plates which are located between the first polysilicon layer and the second polysilicon layer and are arranged on the oxide layer at intervals, resistive field plates are arranged in the LDMOS device, an equipotential ring is formed between the resistive field plates, the resistive field plates and the equipotential ring are arranged between a gate and a drain of the LDMOS device at intervals, only a thin silicon dioxide film layer is arranged between the surface of a drift region of the device and the resistive field plates at intervals, one side of each resistive field plate is connected with a drain electrode high potential, and a source electrode is connected with a lowest potential. A weak leakage current passing through the resistive field plate exists between the source electrode and the drain electrode, so that the surface electric field distribution between the grid electrode and the drain electrode of the device is more uniform, the peak electric fields near the grid electrode and the drain electrode are greatly weakened, the voltage resistance of the device is improved, and the HTRB reliability of the device is improved.

The invention provides an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a manufacturing method thereof. The method comprises the following steps: providing a semiconductor substrate; a photoresist layer with an opening is formed on the surface of the semiconductor substrate, the opening at least exposes the surface of a region, where a drain region is predetermined to be formed, of the semiconductor substrate, the photoresist layer covers part of the surface corresponding to the first region, and the body region is predetermined to be located on the side, away from the drain region, of the drift region; performing first-time first conduction type ion implantation on at least the first region exposed from the opening; performing a finishing process on the photoresist layer to enlarge the opening; taking the trimmed photoresist layer as a mask, and at least executing second-time first conductive type ion implantation on the first region exposed out of the opening; the trimming process and the first conduction type ion implantation step are repeatedly executed at least once, the drift region comprises a plurality of implantation regions with different doping concentrations, and the doping concentrations of the plurality of implantation regions are gradually reduced in the direction from the drain region to the body region, so that the breakdown voltage is improved, and the specific on-resistance is reduced.

The invention provides an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a preparation method thereof. The LDMOS device comprises a semiconductor substrate; the first well region and the second well region are arranged in the semiconductor substrate, and the first well region and the second well region are arranged adjacently; the body region is arranged in the second well region; the source region is arranged in the body region; the body extraction region and the Schottky region are arranged in the body region and are adjacent to the source region, a metal layer is formed on the Schottky region, and the Schottky region is in contact with the metal layer to form a Schottky diode; the drain region is arranged in the first well region; and the gate structure is formed on the surface of the semiconductor substrate. According to the invention, the device has a lower ESD trigger voltage in an ESD event, and the ESD protection capability of the device is greatly improved.

A new semiconductor structure is disclosed. The semiconductor structure includes patterned dielectric layers disposed between the field plates and the channel layer. These patterned dielectric layers serve to further shape the electric field in the channel layer. This structure is not only applicable to III-nitride semiconductor devices, such as transistors, diodes or any other devices, but also is applicable to other semiconductor devices, such as Si LDMOS, SiC transistors, GaAs transistors.

The invention discloses an H-bridge motor driving chip based on a segmented current driving technology, which belongs to the technical field of H-bridge motor driving chips, and comprises an H-bridge output stage circuit which consists of four LDMOS (laterally diffused metal oxide semiconductor) and is used for bearing high-voltage and large-current output of a power stage power supply, the high-side driving circuit is used for converting a high-side tube logic control signal from the logic control part into a switch tube driving signal with certain driving capability in a high-side tube power supply domain; the low-side driving circuit is used for converting a low-side tube logic control signal from the logic control part into a switch tube driving signal with a certain driving capability in a low-side tube power domain, and logic control is used for converting the switch tube driving signal into a switch tube driving signal with a certain driving capability according to input signals of PWM and DIR pins and detection signals of a state detection circuit and a protection circuit in an internal driving circuit. And a logic control signal for controlling four switching tubes of the H bridge is generated.

A number of MOSFET architectures provide high-voltage capability (both drain-source breakdown voltage BVDSS and ON-state breakdown voltage BVON), low current leakage, and extended linearity. Embodiments of the invention overcome the limitations of conventional NEDMOS and LDMOS device designs by providing a low-resistance path for hole collection and by purposefully exhibiting multiple voltage thresholds VTH in different segments of the device. Embodiments includes NEDMOS and LDMOS device designs having multiple body contact regions for improved hole collection, sub-gate doped stripes or segments for even better hole collection and linearity, and sub-gate doped edge regions for increased local VTH and thus decreased current leakage. P− hole-collection stripes and P+ body contact regions may be formed of a semiconductor material that includes germanium. The inventive MOSFETs may be arranged as multi-MOSFET array elements, and multiple array elements may be arranged in a larger array.

The invention relates to a preparation method of an LDMOS device and the LDMOS device, and relates to the technical field of semiconductors, in the preparation method, a first etching machine table is adopted for a self-aligned polycrystalline silicon material layer, a second etching machine table is adopted for a shielding material layer, and special etching machine tables are adopted for different materials, so that the etching precision can be improved, and the manufacturing cost is reduced. Therefore, the material loss caused by incomplete etching of the material needing to be etched or over-etching during etching is avoided, and the yield of the product is improved. In addition, according to the formed LDMOS device, the metal silicide covering the shielding layer serves as a supplementary grid electrode of the grid electrode of the LDMOS device, so that the length of a conducting channel is increased, and the LDMOS device has better high voltage resistance.

A microelectronic device including a substrate having a semiconductor material containing a laterally diffused metal oxide semiconductor (LDMOS) transistor, including a body region of a first conductivity type and a drift region of an opposite conductivity type. A gate dielectric layer over a channel region of the body, the gate dielectric extending over a junction between a body region and the drift region with a gate electrode on the gate dielectric and a drain contact in the drain drift region, having the second conductivity type. A field relief dielectric layer on the drain drift region extending from the drain region to the gate dielectric, having a thickness greater than the gate dielectric layer. A silicide-blocking layer extends from the drain region toward the gate, providing an unsilicided portion of the drift region at the substrate top surface between the drain region and the gate.

The invention relates to a laterally diffused metal oxide semiconductor device and a preparation method thereof. The laterally diffused metal oxide semiconductor device includes: a substrate; the first doped region is arranged in the substrate; the second doped region is arranged in the substrate and is positioned on one side, close to the surface of the substrate, of the first doped region; the first groove is formed in the substrate, is opened from the surface of the substrate and extends to the first doped region so as to expose part of the first doped region; the drain region is arranged in the exposed part of the first doped region; the source region is arranged in the substrate; the grid electrode is arranged on one side, away from the drain region, of the source region; the well region is arranged in the substrate; the well region extends from the surface of the substrate to the first doped region and is adjacent to the second doped region; the well region is located between the gate and the drain region. According to the embodiment of the invention, the Cgd capacitance can be reduced while the withstand voltage of the device is improved, so that the adverse effect on the FOM value is reduced.

The invention provides a low-delay level shift circuit, and belongs to the technical field of analog integrated circuit power management, the circuit comprises a level shift core circuit and an edge detection logic circuit, the level shift core circuit adopts a high-voltage-resistant LDMOS to complete conversion of different voltage domain signals on the basis of a traditional cross coupling structure, and the edge detection logic circuit is connected with the edge detection logic circuit. The edge detection logic circuit detects a fast falling edge of the level shift core circuit, and an output signal only related to the fast edge is obtained after logic operation. The low-delay level shift circuit provided by the invention has no static power consumption, the delay of the level shift circuit can be reduced to below 1ns, the delay time of the low-delay level shift circuit is obviously reduced compared with the delay time of a traditional two-stage cross coupling level shift circuit, and the low-delay level shift circuit is suitable for the field of SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) driving with higher requirements on propagation delay.

The invention belongs to the field of electrostatic discharge (ESD) and electrical overstress (EOS) pulse protection of an integrated circuit, and particularly provides an electrostatic surge integrated protection circuit of a high-reliability high-voltage driving chip, which is used for solving the problems of easy latching, high trigger voltage, poor robustness, low starting speed and the like in a traditional high-voltage ESD / EOS protection scheme. The SCR structure, the Zener structure and the LDMOS structure are technically embedded, the voltage clamping capacity of the Zener diode, the high voltage endurance capacity of the LDMOS, the quick response characteristic of the composite transistor and the strong discharge capacity of the SCR are integrated, the electrostatic and surge integrated protection efficiency is achieved, and under the ESD / EOS electric stress effect, the electrostatic and surge integrated protection effect is achieved. The composite structure promotes orderly opening of the Zener structure, the SCR structure and the LDMOS structure under the action of positive feedback, so that ESD and EOS protection requirements of different pulse frequencies are met, the hysteresis effect and the trigger voltage are remarkably reduced, and the latch-up phenomenon is effectively avoided.