798 results about "Breakdown voltage" patented technology

The invention relates to the technical field of semiconductors, in particular to a high-temperature reverse bias test method, an electrostatic discharge protection structure and electronic equipment, and the method comprises the steps: providing the electrostatic discharge protection structure; determining an initial leakage current at the initial voltage, and determining an initial breakdown voltage at the initial current; heating the electrostatic discharge protection structure for a preset time at a preset temperature and a preset voltage, and determining a target leakage current of the heated electrostatic discharge protection structure under the initial voltage and a target breakdown voltage of the heated electrostatic discharge protection structure under the initial current; performing current change analysis on the initial leakage current and the target leakage current to obtain a current change result, and performing voltage change analysis on the initial breakdown voltage and the target breakdown voltage to obtain a voltage change result; and according to the current change result and the voltage change result, generating a high-temperature reverse bias test result of the electrostatic discharge protection structure. According to the invention, the reliability of the electrostatic discharge protection structure can be accurately evaluated.

The invention relates to the technical field of gallium nitride transistors, and discloses a silicon carbide-gallium nitride heterogeneous integrated high-voltage power device structure, which comprises a silicon carbide device consisting of a plurality of parallel MOS (Metal Oxide Semiconductor) cells and a gallium nitride device consisting of two GaN structures, and is characterized in that the gallium nitride device is positioned on the back surface of the silicon carbide device; each MOS cell comprises a semiconductor epitaxial layer, an MOS source electrode, an MOS grid electrode and an MOS dielectric layer covering the surface of the MOS grid electrode; wherein the semiconductor epitaxial layer comprises an N substrate layer and an N diffusion layer from top to bottom. The transverse high electron mobility characteristic of the GaN HEMT and the longitudinal voltage withstanding advantage of the SiC MOSFET are combined, cooperative work of two wide bandgap semiconductors is achieved on a single substrate, the structure effectively utilizes the excellent heat conduction and voltage withstanding performance of the SiC substrate as a common carrier, meanwhile, through the series voltage withstanding design of the device level, the performance of the device level is improved, and the performance of the device level is improved. And the overall breakdown voltage is obviously improved.

A semiconductor device includes first and second N-type semiconductor regions provided selectively in an upper layer part of an N-type high-breakdown voltage isolation region, and a P-type semiconductor region provided selectively in the upper layer part of the N-type high-breakdown voltage isolation region and to be supplied with a first power supply voltage lower than a second power supply voltage. The second N-type semiconductor region is arranged closer to an N-type high-potential region than the first N-type semiconductor region and the P-type semiconductor region. The P-type semiconductor region is arranged between the first N-type semiconductor region and the second N-type high-potential region in a plan view. A diode has an anode to be supplied with the second power supply voltage, and a cathode electrically connected to the first N-type semiconductor region. The second N-type semiconductor region is electrically connected to the N-type high-potential region.

The present disclosure relates to a bulk acoustic wave (BAW) device with electrostatic discharge (ESD) protection. The disclosed BAW device includes a substrate (106), an ESD protection layer (106) over the substrate (106), a first bottom reflector (109-1) over the ESD protection layer (108), a first bottom electrode (112-1) over the first bottom reflector (109-1), a first top electrode (118-1) vertically aligned with the first bottom electrode (112-1), and a piezoelectric layer (116C) vertically between the first bottom electrode (112-1) and the first top electrode (118-1). Herein, the ESD protection layer (108) is electrically insulating and eligible to achieve at least a 400 V breakdown voltage with a 200 nm thickness. The first bottom reflector (109-1) includes a stack of alternating high acoustic impedance conductive layers (120A-E) and low acoustic impedance conductive layers (120A-E). The first bottom electrode (112-1) is electrically connected to the first bottom reflector (109-1). A breakdown voltage of the piezoelectric layer (116C) is no more than the breakdown voltage of the ESD protection layer (108).

The invention provides an anti-radiation high-performance enhanced gallium nitride-based power device and a manufacturing method thereof, and belongs to the technical field of semiconductors. On the basis of a traditional enhanced P-GaN HEMT device structure, a P-type InaGa1-aN back barrier layer, an InbGa1-bN / GaN superlattice layer, a composite gate structure composed of a dielectric layer and a gate Schottky metal layer and a gradient-changing island-shaped P-GaN layer are innovatively introduced, and a pair of composite problems of dynamic resistance instability and radiation sensitivity are cooperatively solved. The device not only maintains the normally-off characteristic and the high threshold voltage of an enhanced device, but also remarkably improves the anti-irradiation capability, the breakdown voltage and the dynamic resistance stability, and is particularly suitable for power electronics in strong irradiation environments such as aerospace and nuclear energy detection.

The invention discloses a ceramic substrate testing device capable of preventing broken contact, and relates to the technical field of insulation and voltage resistance detection of ceramic substrates, the ceramic substrate testing device capable of preventing broken contact comprises a rack, a master control system and PID thermal control equipment, the rack is provided with a detection table, the rack is provided with a push-pull positioning clamp, and the push-pull positioning clamp is connected with the master control system. A sealing cover is installed on the push-pull positioning clamp, an upper electrode assembly is arranged at the lower end of the push-pull positioning clamp, a lower electrode assembly and a heating module are arranged on the detection table, the ceramic substrate is placed on the detection table, the push-pull positioning clamp pushes the upper electrode assembly and the sealing cover to move downwards, and the heating module is started to heat the ceramic substrate. The upper electrode assembly and the lower electrode assembly are matched to apply high voltage to the substrate and monitor leakage current and breakdown voltage conditions in real time, so that the insulation and voltage resistance of the copper-clad ceramic substrate can be accurately evaluated under a high-temperature condition, and an insulation reliability test under an electric-thermal coupling condition can be realized; and the reliability and repeatability of the test are obviously improved.

The invention provides a high-voltage-resistant gallium oxide trench junction barrier Schottky diode. The high-voltage-resistant gallium oxide trench junction barrier Schottky diode comprises a cathode metal layer, a high-doping N-type gallium oxide substrate, a low-doping N-type gallium oxide epitaxial layer, an etching table top first dielectric layer, an etching table top second dielectric layer, a P-type nickel oxide layer, a dielectric layer and an anode metal layer which are sequentially stacked from bottom to top. According to the invention, P-type nickel oxide and gallium oxide are introduced to construct a heterostructure into a JBS structure, the JBS structure is combined with the etched trench to form a trench junction barrier Schottky diode, and the device has lower specific on-resistance, can bear higher reverse breakdown voltage, and is a gallium oxide JBS device with excellent performance.

An electrostatic discharge protection circuit includes an NMOS transistor connected to a supply voltage pin through a first node and connected to a ground pin through a second node, an RC circuit connected in parallel with the NMOS transistor and including a capacitor and a resistor, and a clamping circuit connected in parallel with the resistor of the RC circuit and including a plurality of diodes; and a switch connecting the clamping circuit to a gate node of the NMOS transistor, wherein a number of the plurality of diodes is set based on a breakdown voltage and an operating voltage of an internal circuit to be protected by the ESD protection circuit, and the switch includes a PMOS transistor connecting the gate node of the NMOS transistor to the clamping circuit and a sub-RC circuit connected in parallel with the PMOS transistor and including a sub-capacitor and a sub-resistor.

The invention provides a spark discharge device and a spark discharge accurate control method, and relates to the technical field of spark discharge. The device comprises a pair of spark electrodes, a rotary switch, a capacitor and a power supply, wherein a gap exists between working ends of the spark electrodes; the spark electrode, the rotary switch and the capacitor are connected in series to form a discharging loop, and the capacitor and the power supply are connected in series to form a charging loop; the rotary switch comprises a rotatable rotor and a toothed bar connected with the rotor; a contact is arranged in the discharge loop, and when the contact is in contact with the toothed bar, the discharge loop is conducted. According to the invention, the discharge loop is rapidly switched on and switched off through the rotary switch, various parameters of spark discharge can be accurately and stably controlled, so that the spark discharge is not influenced by the environment, such as spark breakdown voltage, discharge frequency and the like, and the spark discharge can be prevented from being converted into corona, glow or arc discharge, for example, the spark discharge can be normally generated under low air pressure.

The invention discloses an efficient electric flame furnace end and an electric flame stove. The efficient electric flame furnace end comprises a shell, a single anode needle, a single cathode tube, a ceramic tube, an air duct inner wall, an air duct outer wall, a heating coil and an airflow generation assembly. The single anode needle and the single cathode tube are arranged, the actual discharge gap between the single anode needle and the single cathode tube can be set to be 10-20 cm and is far larger than the preset discharge distance, air thermal breakdown can still be achieved by adopting stable breakdown voltage in the prior art, extra voltage increase is not needed, meanwhile, the long-distance arrangement of the single anode needle and the single cathode tube is achieved, and the service life of the anode needle and the cathode tube is prolonged. The collision probability of gas molecules and electric field electrons is increased through the long arc, and high-efficiency heating is achieved; in addition, due to the arrangement of the single anode needle and the single cathode tube, the structure of the furnace end is simplified, the number of electrodes and a complex arrangement structure are reduced, and the assembly difficulty and the production and manufacturing cost are reduced; and meanwhile, the simplified structure enables air flow in the furnace end to be smoother, electric field distribution to be more concentrated, and the problems of mutual interference among multiple electrodes, electric field disorder and unstable discharge are avoided.

The invention discloses an APD epitaxial wafer breakdown voltage testing method, which comprises the following steps of: (1) selectively corroding an APD epitaxial wafer, and ensuring that an uncorroded layer is a to-be-tested epitaxial layer (the upper surface is a P-type semiconductor region) and a corroded layer is a residual layer (the upper surface is an N-type semiconductor region); (2) dotting indium in the P-type semiconductor region to form an upper electrode, and dotting indium in the N-type semiconductor region to form a lower electrode; (3) connecting a positive electrode probe of a parameter analyzer with a lower electrode, connecting a negative electrode probe with an upper electrode, gradually applying reverse bias voltage from zero, and monitoring and recording a reverse bias voltage value, namely breakdown voltage Vbr, in real time when the current is subjected to avalanche increase; and (4) carrying out statistical analysis on all the breakdown voltage values on the same APD epitaxial wafer to obtain a final breakdown voltage value. The method effectively overcomes the problems of large test result deviation, low accuracy, long period and high cost in the traditional technology, can quickly evaluate the quality of the epitaxial wafer material, and is mainly used for process monitoring and material screening.

The invention discloses a preparation method of an LDMOS (Laterally Diffused Metal Oxide Semiconductor) and an LDMOS device, and the preparation method of the LDMOS comprises the steps: providing a semiconductor substrate, and forming an LDMOS device region on the semiconductor substrate; forming an oxide layer on the region where the LDMOS device is formed; forming a grid electrode on the oxidation layer corresponding to the area between the source electrode area and the drain electrode area, and forming a step-shaped field plate structure on the corresponding oxidation layer above the drift area; forming a first dielectric layer covering the grid electrode and the stepped field plate structure; forming a first through hole and a second through hole which are respectively communicated to the source region and the drain region in the first dielectric layer, and forming a plurality of third through holes which are respectively communicated to different steps of the stepped field plate structure; the at least one third through hole electrically connects a step of the stepped field plate structure with the drain region. By adopting the method, the drain-source breakdown voltage performance of the device in a conducting state is improved, and the high-voltage breakdown of the drain electrode is effectively prevented.

The application relates to a gallium nitride epitaxial structure forming method and a semiconductor device. The method comprises the following steps: sequentially forming a buffer layer, an intrinsic GaN layer and an AlGaN layer on a substrate; growing a P-type doped GaN epitaxial layer on the AlGaN layer, controlling the doping concentration and thickness of the P-type GaN layer, performing N-type ion implantation on the P-type GaN layer, controlling the implantation depth in the range of 20nm-30nm, and then performing annealing. In another mode, the AlGaN layer is subjected to P-type ion implantation before the P-type GaN layer is grown to form an asymmetric P-type doped area, and then annealing is performed, and the implantation area is still P-type after annealing by controlling the implantation dose. In the semiconductor device, the contact layer is obtained by patterning the P-type GaN layer, and the P-type doped area with the highest doping concentration or the largest doping area is arranged at the position of the contact layer. The gate breakdown voltage can be improved, the threshold voltage can be stabilized, the low on-resistance can be maintained, and the CMOS process compatibility can be realized.

The invention discloses a pressure stress passivation method, which is applied to a thin barrier gallium nitride millimeter wave device, and is characterized in that a laminated silicon nitride passivation layer with pressure stress is formed on the surface of the device through the synergistic effect of interface passivation and stress engineering, so that device passivation is realized; wherein the laminated silicon nitride passivation layer comprises an interface function layer positioned on the bottom layer and a stress modulation layer positioned on the interface function layer; the method comprises the following steps of: depositing a first layer of silicon nitride film on a barrier layer of the gallium nitride millimeter wave device under the conditions of a high-frequency source and rich silicon to form an interface function layer; and depositing a second layer of silicon nitride film on the interface function layer, and carrying out stress regulation and control in the deposition process to form a stress modulation layer with compression stress. According to the method, current collapse can be effectively suppressed, meanwhile, the breakdown voltage is remarkably improved, and finally the thin-barrier gallium nitride millimeter wave device is enabled, so that the thin-barrier gallium nitride millimeter wave device has excellent performance of high power output and high stability in a high-frequency working mode.

A power semiconductor device is provided. The power semiconductor device mainly comprises a first conductive-type highly-doped substrate and a second conductive-type contact region formed thereon. The contact region has a dual-layer doping structure comprising a highly-doped region and a lightly-doped region. Accordingly, the active area of the power device has a five-layer structure of a second conductive-type highly-doped region, a second conductive-type lightly-doped region, an intrinsic semiconductor epitaxial layer, a first conductive-type lightly-doped layer, and a first conductive-type highly-doped substrate, for improving the breakdown voltage of the power device. In addition, metal silicide layers are introduced on the front and back sides of the device and form ohmic contacts with the metal layers thereof to shorten the reverse recovery time (trr) of the device. The metal electrode on the front of the device has a plurality of ring-shaped designs, including at least one second conductive-type metal ring and one first conductive-type metal ring.

The present disclosure provides a trench gate semiconductor device and a manufacturing method therefor. Compared with the related art in which a gate oxide layer is formed by oxidizing a first epitaxial layer, in the embodiments of the present disclosure, the gate oxide layer is formed by oxidizing a prefabricated epitaxial layer, so as to address the problem of high roughness of trench sidewalls caused by the etching process during the forming the trench by means of etching on the first epitaxial layer, thereby reducing the influence of surface roughness scattering of the trench on channel mobility. Further, a shielding layer is arranged between the gate oxide layer on the outer bottom wall of the trench and the first epitaxial layer, so as to reduce the peak electric field at the bottom corners of the trench, thereby improving the breakdown voltage.

Disclosed are a one-time-programmable (OTP) memory device and an OTP memory cell having multiple program transistors. The OTP memory device may include a plurality of OTP memory cells, wherein each of the plurality of OTP memory cells may include a first program transistor having a first breakdown voltage, a second program transistor having a second breakdown voltage, and a read transistor connected to the first program transistor and the second program transistor. Each of the first program transistor, the second program transistor and the read transistor may include a fin-type active region extending in a first direction on a substrate. A first fin-type active region of the first program transistor, a second fin-type active region of the second program transistor, and a third fin-type active region of the read transistor may be separated from each other.

The invention relates to a semiconductor structure and a preparation method thereof, and relates to the technical field of semiconductors, the semiconductor structure is provided with a dielectric layer of a second doping type and a first columnar region, so that a super junction structure is realized, the specific on-resistance under a specific breakdown voltage is greatly reduced, and the reliability of the semiconductor structure is improved. And moreover, the dielectric layer of the second doping type is filled in the gate trench, and ion implantation is not needed during formation, so that the preparation cost is reduced, and the processing time is saved.

The application discloses an SGT device and a process method thereof, which comprises the following steps: first, forming a composite layer on the surface of a semiconductor substrate; etching the semiconductor substrate to form a groove; second, depositing a first oxide layer, then depositing a first polysilicon layer; filling the groove; third, performing back etching on the first polysilicon layer to form a source electrode of the SGT device; fourth, etching the first oxide layer in the groove; fifth, forming a pad oxide layer, then depositing a second polysilicon layer and performing back etching; sixth, depositing a dielectric layer; then removing the composite layer on the surface of the semiconductor substrate; performing etching to form an upper space in the groove; seventh, forming a gate dielectric layer and a gate electrode; eighth, respectively performing ion implantation to form a well region and a source region; forming a contact hole; and after the top metal layer is made, completing subsequent processes. The SGT device disclosed by the application comprises a floating electrode forming a lateral field plate, which optimizes the electric field of a drift region and improves the breakdown voltage.

This invention discloses a method, apparatus, electronic device, and storage medium for preparing cross-linked ethylene copolymer AC cables, belonging to the field of cable parameter design. The method includes: obtaining the electrical aging time and first breakdown field strength of a cable sample under different voltages, and calculating the electrical aging coefficient; obtaining the thermal aging time of the cable sample at different thermal aging temperatures, where the breakdown field strength drops to a preset proportion of the initial breakdown field strength, and calculating the thermal aging coefficient; obtaining the power frequency breakdown voltage of the cable sample under a power frequency breakdown test, and calculating the thickness coefficient; obtaining the second breakdown field strength of the cable sample under a power frequency breakdown test, and calculating the safety factor; and calculating the insulation thickness of the cable to be prepared based on the electrical aging coefficient, thermal aging coefficient, thickness coefficient, and safety factor, and preparing the corresponding cross-linked ethylene copolymer AC cable. Therefore, by implementing this invention, the problem that the insulation thickness design in the prior art cannot achieve the optimal performance of the cable can be solved.

This invention provides a semiconductor device, its fabrication method, and its application. By setting a multi-layered ring structure outside the X-ray sensitive region, including a P-type charge collection ring, multiple P-type guard rings, and multiple N-type guard rings, the influence of leakage current and external electric fields outside the X-ray sensitive region is effectively shielded, thereby significantly improving signal quality and the stability of the semiconductor device. Furthermore, this structural design effectively suppresses plasma effects, further enhancing the sensitivity and signal-to-noise ratio of the semiconductor device. These performance improvements are crucial for the stable operation of the semiconductor device under high operating voltage environments. The semiconductor device of this invention can achieve a breakdown voltage of at least 600V and an operating voltage of at least 300V under irradiation, fully meeting the requirements of specific applications such as XFELs.

The application discloses an insulating adhesive, an insulating adhesive tape and a preparation method of the insulating adhesive. The insulating adhesive comprises an insulating adhesive body and insulating particles doped in the insulating adhesive body. The breakdown field strength of the insulating particles is greater than that of the insulating adhesive body. Because the breakdown field strength of the insulating particles is greater than that of the insulating adhesive body, the insulating adhesive body is more likely to be broken down than the insulating particles. When an electrostatic discharge current acts on the insulating adhesive, the electrostatic discharge current will break down the insulating adhesive body with poor insulation performance and is more likely to be broken down, bypass the insulating particles with good insulation performance and are more difficult to be broken down, so that the breakdown path of the electrostatic discharge current is lengthened, the breakdown voltage required for breaking down the insulating adhesive is increased, and thus the insulation performance of the insulating adhesive is improved.

This invention relates to a GaN-based pn junction diode device with a polarized beveled termination structure and its fabrication method. The device includes a cathode, a GaN substrate, an epitaxial layer, and an anode. The epitaxial layer comprises a lightly doped n-type GaN layer, an intrinsic GaN layer, and a p-type doped GaN layer grown in a single epitaxial growth process. The anode ohmic contact metal is placed on the p-type doped GaN layer, and the cathode ohmic contact metal is placed on the back side of the GaN substrate. It also includes a polarized beveled termination structure formed at the interface containing the pn junction, using inductively coupled plasma reactive ion etching (ICP-R) and a photoresist mask. The photoresist mask is formed using thick photoresist, followed by high-temperature heating and annealing to form the reflow morphology of the photoresist. Finally, wet repair and a passivation layer are applied to suppress the beveled n-type donor surface states of the polarized beveled termination structure. This invention effectively alleviates the boundary electric field concentration problem of GaN-based pn junctions and improves the breakdown voltage of GaN-based pn junctions.

The application provides a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor structure comprises the following steps: providing a substrate, a surface of the substrate is formed with an epitaxial layer, and a groove is formed on a side of the epitaxial layer away from the substrate; a first gate oxide layer is formed through a thermal oxidation process, the first gate oxide layer covers at least a sidewall of the groove; a second gate oxide layer is formed through a chemical vapor deposition process, the second gate oxide layer fills a bottom of the groove and covers a surface of the first gate oxide layer away from the epitaxial layer, the first gate oxide layer and the second gate oxide layer jointly form a gate oxide structure, and a thickness of the gate oxide structure at the bottom of the groove is greater than or equal to a thickness of the gate oxide structure on the sidewall of the groove. The preparation method of the semiconductor structure is beneficial to improving the breakdown voltage and the gate oxide reliability of a semiconductor device.

A Schottky barrier diode, including a first n-type semiconductor layer including a β-Ga2O3-based single crystal epitaxial layer and having a first carrier concentration that determines reverse breakdown voltage and forward voltage, a second n-type semiconductor layer including a β-Ga2O3-based single crystal substrate and having a second carrier concentration that is higher than the first carrier concentration and determines forward voltage, a Schottky electrode provided on a surface of the first n-type semiconductor layer on the opposite side to the second n-type semiconductor layer, and an ohmic electrode provided on a surface of the second n-type semiconductor layer on the opposite side to the first n-type semiconductor layer. The β-Ga2O3-based single crystal substrate includes a surface that has a plane orientation rotated by an angle of not more than 37.5° from a (010) plane.

This application discloses a semiconductor device and its manufacturing method. The semiconductor device includes a first region and a second region. The second region contains a plurality of transistors. Each transistor includes: a semiconductor layer and a source region and a drain region, the source region and drain region being located in the semiconductor layer and close to its surface; a second gate dielectric layer located on the surface of the semiconductor layer; a gate conductor located on the second gate dielectric layer; a second sidewall located on the side surface of the gate conductor on the second gate dielectric layer; and a plurality of conductive channels respectively connected to the source region, drain region, gate conductor, and second sidewall as lead-out structures. The second sidewall includes a field plate, and the conductive channels of the field plate are connected to the conductive channels of the drain region. This application improves the breakdown voltage of the device without increasing the channel on-resistance.

The present invention provides a semiconductor device, a semiconductor memory device, and a method for manufacturing a semiconductor device that can suppress the decrease in the breakdown voltage of an insulating film. [Solution] The semiconductor device comprises an oxide semiconductor including an upper electrode, a lower electrode, a first part connected to the upper electrode, and a second part connected to the lower end of the first part and having a diameter larger than the diameter of the lower end of the first part, and connected to the lower electrode; a gate insulating film surrounding the side surface of the first part and having an outer diameter smaller than the diameter of the second part; a first insulating layer through which the first part passes; a gate electrode provided below the first insulating layer and through which the first part passes, the gate electrode facing the first part via the gate insulating film; and a second insulating layer provided below the gate electrode and having a connection portion between the first part and the second part.

The invention discloses a GaN HEMT epitaxial structure with a special high-resistance layer, the epitaxial structure is provided with the special high-resistance layer between a transition layer and a barrier layer, the special high-resistance layer comprises at least one high-resistance layer and at least one delta-doped layer which are sequentially and alternately stacked, the carbon doping concentration of the delta-doped layer is higher than that of the high-resistance layer, and the delta-doped layer is arranged between the transition layer and the barrier layer. The delta doping layer can optimize the electric field distribution so as to effectively improve the breakdown voltage of the HEMT epitaxial structure and further improve the voltage withstanding performance of the HEMT device.

The invention relates to a leakage current and breakdown voltage measuring device, which is applied to a semiconductor discrete device test and comprises a numerical control power supply, an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and a control circuit, the positive electrode of the numerical control power supply is connected with the D end of the MOSFET, the S end of the MOSFET is connected with the input end of the discrete semiconductor device, the output end of the discrete semiconductor device is connected with the negative electrode of the numerical control power supply and is grounded, the input end of the control circuit is connected with the output end of the discrete semiconductor device, and the output end of the control circuit is connected with the output end of the discrete semiconductor device. The output end of the control circuit is connected with the G end of the MOSFET tube. According to the leakage current and breakdown voltage measuring device provided by the invention, the MOSFET is arranged to replace a JEFT, and the control circuit is utilized to change the grid voltage of the MOSFET to realize accurate current limiting control, so that the test precision is ensured; meanwhile, the functions of leakage current testing and breakdown voltage testing are integrated, the testing cost is reduced, and the testing efficiency is improved.

The invention relates to a manufacturing method of a stepped field plate and a semiconductor device, and relates to the technical field of integrated circuits. According to the manufacturing method of the stepped field plate, at least two dielectric layers with different initial densities are formed on a substrate, the at least two dielectric layers are subjected to an etching process once to form a field plate pattern, then the at least two dielectric layers are subjected to heat treatment, and the dielectric layers with different initial densities are different in transverse shrinkage in heat treatment, so that the field plate pattern is formed. A step field plate can be formed on the substrate; on one hand, the step field plate can be formed only through single-time patterning etching, the number of photomasks is reduced, the process steps are reduced, the manufacturing cost is reduced, and the production period is shortened; and on the other hand, the appearance of the stepped contour of the stepped field plate can be flexibly adjusted by adjusting the initial density of the at least two dielectric layers, and the breakdown voltage of the device can be flexibly adjusted.