2114 results about "Breakdown voltage" patented technology

The invention relates to the technical field of MOS semiconductors, and discloses a variably doped planar gate silicon carbide VDMOS device and a preparation process thereof, the variably doped planar gate silicon carbide VDMOS device comprises a plurality of MOS cells which are parallel to each other, and each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of a single MOS cell; lateral symmetric P-layers are arranged in the single MOS cell and located on the left side and the right side of the N drift layer, and the section contours of the corresponding sides of the lateral symmetric P-layers on the two sides are in an arc shape. By arranging the lightly doped N layer in the middle of the N drift layer and introducing the arc-shaped laterally-symmetrical P-layers to the two sides, the electric field distribution of the device is optimized, the local electric field concentration is reduced, the breakdown voltage is remarkably improved, and the charge balance capability is enhanced and the leakage current is reduced through the contact between the laterally-symmetrical P-layers and the N substrate layer.

The invention relates to the technical field of MOS semiconductors, and discloses a silicon carbide thick-bottom oxide layer groove MOS structure and a preparation method thereof, the silicon carbide thick-bottom oxide layer groove MOS structure comprises a plurality of parallel MOS cells, and each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of each MOS cell; the lightly doped N layer is arranged in the middle of the N drift layer, the arc-shaped contour design with the inclined top is introduced to the two sides, the injection area is accurately controlled through the photoetching technology, the phenomenon that the edge electric field concentration of the N drift layer is effectively dispersed is effectively dispersed, in this way, electric field distribution is more uniform, breakdown voltage is improved, and local electric field concentration is reduced; moreover, the contact between the laterally symmetrical P-layer and the N substrate layer enhances the charge balance capability, and reduces the leakage current.

The present invention relates to a gallium oxide power diode with a high breakdown voltage and a preparation method thereof. The preparation method includes: selecting a substrate layer, preparing a drift layer on the upper surface of the substrate layer; preparing a cathode on the lower surface of the substrate layer; preparing an anode on the upper surface of the drift layer; performing a low-temperature annealing process on the device to obtain the gallium oxide power diode; wherein, both the substrate layer and the drift layer are Si- or Sn-doped β-Ga2O3 materials, and the doping concentration of the drift layer is lower than that of the substrate layer, the anode is a Ni / Au metal stack, and a NiO layer with P-type characteristics is formed at the interface between the metal Ni and the drift layer, and the NiO layer and the drift layer form a heterojunction PN junction structure. The preparation method of the present invention can form a heterojunction PN junction structure with a P-type characteristic thin layer NiO layer through low-temperature annealing, can modulate the electric field distribution, improve the interface characteristics between the anode metal and gallium oxide, reduce the reverse leakage current, and increase the breakdown voltage of the device.

The invention discloses a partial discharge and breakdown combined test system and test method under wide temperature range and variable air pressure, which are suitable for evaluating the insulating properties of insulating materials, cables and power equipment under high and low temperature and different air pressure conditions. The system comprises a vacuum oven, a partial discharge and withstand voltage breakdown joint test module, an explosion-proof cable joint, a control module and a detection module, the vacuum oven can realize temperature regulation and control from-70 DEG C to + 200 DEG C and an air pressure environment of 10 <-3 > Pa, and the test module integrates a high voltage generator, a coaxial electrode and a partial discharge sensor. Partial discharge detection and breakdown voltage measurement can be completed in the same test environment. According to the test method, the electrical response characteristics of the insulating material under different working conditions are obtained through regulation and control of environment temperature and pressure, execution of a test process and data acquisition and analysis. The device is compact in structure and high in safety, and has the capabilities of joint testing, high-precision regulation and control and adaptability to complex environments.

The invention relates to the technical field of MOS semiconductors, and discloses a heterojunction-based silicon carbide groove type MOSFET device structure and a preparation process thereof.The heterojunction-based silicon carbide groove type MOSFET device structure comprises a plurality of parallel MOS cells, each MOS cell comprises a drain electrode, a source electrode, a grid electrode and a semiconductor epitaxial layer, and each semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer; a groove is formed in the upper surface of the single MOS cell and located below the grid electrode, an N + layer is deposited in the groove, and the N + layer comprises a left N + layer and a right N + layer. Through the design of the split type left N + layer and the right N + layer in the groove and the combination of the middle N-layer or the middle P-layer filled in the middle, the electric field concentration phenomenon at the bottom of the groove is effectively dispersed, and the electric field peak value at the edge of the N drift layer is further inhibited in cooperation with the right triangle arrangement of the blocking ion bubbles, so that the breakdown voltage and the reliability of the device are remarkably improved, and the reliability of the device is improved. The method is suitable for high-voltage application scenes.

The invention relates to an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a manufacturing method thereof. The LDMOS device comprises a semiconductor substrate; the body region and the drift region are formed in the semiconductor substrate, the source region is located in the body region, and the drain region is located in the drift region; the at least two shallow trench isolation structures are formed in the drift region, the tops of the at least two shallow trench isolation structures are higher than the surface of the semiconductor substrate, and a dielectric layer is formed between the parts, higher than the surface of the semiconductor substrate, of the at least two shallow trench isolation structures; and the gate structure comprises a gate dielectric layer and a gate electrode layer located on the gate dielectric layer, and the gate structure transversely extends to the drift region from the body region and at least partially covers the shallow trench isolation structure. The LDMOS structure has a relatively high breakdown voltage.

The invention relates to an ultra-high voltage line lightning resistance level evaluation method and device based on a tower head gap structure. The method comprises the following steps: constructing a simulation model according to line structure information and electrical parameters of an extra-high voltage line and tower structure information of a power transmission tower; inputting lightning current waveform parameters and lightning channel wave impedance parameters of the extra-high voltage line into the simulation model to obtain voltage distribution information and current propagation characteristic information of the extra-high voltage line under a lightning stroke condition; flashover criterion information is determined according to the insulator string discharge voltage characteristic information and the tower head air gap breakdown voltage characteristic information of the extra-high voltage line; and according to the voltage distribution information, the current propagation characteristic information and the flashover criterion information, determining a lightning resistance level evaluation result. By adopting the method, the influence of the breakdown characteristic of the tower head air gap, the complexity of the tower structure and the dynamic characteristic of lightning current propagation on the lightning resistance level evaluation can be comprehensively considered, and the accuracy of the lightning resistance level evaluation result of the extra-high voltage line is improved.

The invention discloses a method and system for testing the electrical performance of a semiconductor chip, and the method comprises the steps: building a mapping relation between dielectric loss and loss frequency through obtaining the dielectric loss data, internal material characteristics and dynamic load power factors of the chip under each frequency band, recognizing a loss abnormal region, and analyzing the influence of the loss abnormal region on the performance of the chip; correcting test data by adopting a minimum mean square error algorithm, and optimizing the impedance of the power supply network and the dynamic switching characteristic of a functional module; calculating the breakdown voltage distribution of each layer in the chip, identifying a high-voltage risk region, optimizing the voltage distribution by using a gradient descent algorithm, and dynamically adjusting the working voltage and current; power factor fluctuation is analyzed through a sliding window algorithm, an abnormal area is identified, a power factor is optimized through a PID algorithm, and the working state and transient response of a chip in a dynamic load are improved. According to the method, the problems of nonlinearity of high-frequency dielectric loss, non-uniform breakdown voltage distribution and unstable power factor response under a dynamic load are solved, and comprehensive and accurate evaluation and optimization of chip performance are realized.

The utility model discloses a semiconductor device, which belongs to the field of semiconductors, and at least comprises a substrate; the well region is arranged in the substrate; the two drift regions are arranged in the well region at intervals, and shallow trench isolation structures are arranged in the drift regions; the body region is arranged in the well region between the two drift regions; the vertical grid electrode is located in the body region, and the vertical grid electrode extends into the well region from the surface of the substrate; the source doped regions are respectively arranged in the body regions on the two sides of the vertical grid electrode; the drain doping region is arranged in the drift region; and the planar grid electrode is arranged around the vertical grid electrode and the source doping region and covers part of the body region, part of the well region and part of the shallow trench isolation structure. According to the semiconductor device provided by the utility model, the characteristic on-resistance can be reduced and the performance of the semiconductor device can be improved under the condition that the breakdown voltage is not changed.

The invention relates to a SiC groove type JFET device structure and a preparation method thereof. The SiC groove type JFET device structure comprises a drain metallization layer, a SiC N + substrate layer, a first N type drift region, a source groove structure, a second N type drift region, a P-well region, an N + source region, a P + gate region, an isolation dielectric layer, a gate metallization layer and a source metallization layer. The source trench structure is arranged in the first N-type drift region, the upper surface of the source trench structure is in contact with the P-well region and the source metallization layer, and an oxide layer and a polycrystalline silicon layer are sequentially filled in a trench, so that the upper surface of the trench structure is flush with the upper surface of the first N-type drift region. By introducing the trench structure connected with the source electrode in the drift region, the transverse electric field distribution condition in the device can be optimized, the peak electric field is reduced, the conduction capability of the device is further improved under the condition of ensuring that the original breakdown voltage is not changed, the performance of the SiC JFET is greatly improved, and the conduction loss during working is reduced.

The invention discloses a preparation method of modified self-extinguishing insulating oil with flame-retardant and self-repairing functions. Wherein the insulating liquid is mixed oil of mineral oil and palm oil-based modified natural ester, and the inherent high flash point characteristic of the natural ester improves the fireproof safety of the insulating oil. The modified hexagonal boron nitride (h-BN), the magnesium hydroxide nano material and the microcapsule repairing agent are added into the insulating oil, and the h-BN can capture free electrons in the oil, so that the formation and expansion of electric arcs are inhibited, and the breakdown voltage is improved. Magnesium hydroxide is heated to decompose and absorb heat, the fault temperature is reduced, and therefore the arc self-extinguishing effect is achieved. Under the action of a high electric field and a high temperature, the capsule wall of the microcapsule repairing agent is broken, meanwhile, the repairing material is released, a chemical reaction is carried out, and the insulating property of the insulating oil is repaired. The modified insulating oil prepared by the invention has high insulating strength and high flame retardance, and also has a performance self-repairing function, so that the service life of the insulating oil is prolonged.

A current may be passed through a channel of an anti-fuse field-effect transistor (FET) to increase a temperature of a gate dielectric of the anti-fuse FET and change a rupture voltage of the gate dielectric of the anti-fuse FET from a first rupture voltage to a second rupture voltage. The gate dielectric may be ruptured by applying a first voltage between the gate dielectric and the channel of the anti-fuse FET, where the first voltage is between the first rupture voltage and the second rupture voltage.

The utility model relates to a power semiconductor device, in particular to a power semiconductor device, an upper P-type cover layer and a lower P-type cover layer are designed, the high doping concentration of the first P-type cover layer at the lower layer ensures that the threshold voltage of the device can reach a higher value, and the opportunity that an enhanced device is mistakenly opened is reduced; the doping concentration of the upper second P-type cover layer decreases progressively from bottom to top in the vertical direction and decreases progressively from the middle to the left edge and the right edge in the horizontal direction, the doping concentration of the surface corner position is low, when the grid electrode is pressed in the forward direction, the depletion region of the surface corner is deep, the formed peak electric field is low, the design reduces the leakage current of the grid electrode, and the reliability of the grid electrode is improved. And the breakdown voltage and the reliability of the gate are improved.

The invention relates to the technical field of electrical equipment insulation performance detection, in particular to an insulating oil dielectric loss test system based on temperature compensation, which comprises a temperature acquisition module for acquiring insulating oil temperature data and environment temperature data; the dielectric loss measurement module measures a dielectric loss value and a dielectric loss angle through a self-adaptive anti-interference algorithm, and synchronously records voltage and frequency; the intelligent compensation module matches temperature characteristic parameters for different temperature intervals, and compensates a dielectric loss detection value through a segmented temperature compensation model; the state analysis module judges the aging degree and state of the insulating oil according to the compensated dielectric loss value and acid value, generates a multi-stage early warning signal and a diagnosis report by combining the breakdown voltage and the moisture content, and dynamically adjusts the test frequency according to the oil sample type and the operating age limit; and the cloud management platform stores historical data and compensation parameters, establishes a performance degradation model, analyzes a dielectric loss trend and generates maintenance suggestions. Therefore, the problems of insufficient test precision, poor environmental adaptability and the like in the prior art are solved.

The disclosure provides a LDMOS device and a fabrication method. By arranging a first field oxide, a second field oxide, a third field oxide, a gate polysilicon, and a gate oxide layer in the trench and making the surface of the gate polysilicon away from the trench flush with the trench opening, the lateral dimension of the LDMOS device is reduced. Meanwhile, by setting the thickness of the first field oxide and the third field oxide to be greater than that of the second field oxide, setting the height of the first field oxide to be less than or equal to the distance from the bottom of the trench to the channel region, and making the surface of the third field oxide away from the trench flush with the opening of the trench, three independent field plates are formed in the trench. This improves breakdown voltage resistance of the LDMOS device.

The invention discloses a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit, and a vehicle. The semiconductor device includes: a semiconductor body; the semiconductor body comprises a well region and a first region; the first surface is provided with a gate trench; the gate trench comprises a first gate trench and a second gate trench which are communicated, and the second gate trench is located at one side, far away from the first surface, of the first gate trench; the first gate trench extends into the first region and the well region from the first surface, and the second gate trench is located at one side, far away from the first region, of the well region; the semiconductor body further comprises a first insulating layer and a second insulating layer, the first insulating layer is located on the side wall of the first gate trench, the second gate trench is filled with the second insulating layer, and the thickness of the second insulating layer is larger than or equal to that of the first insulating layer; and a trench gate located in the first gate trench. According to the technical scheme, the breakdown voltage of the semiconductor device is improved, and the device performance is improved.

The invention relates to the technical field of power semiconductor devices, in particular to a power semiconductor device with a shield gate trench structure and a manufacturing method thereof, and the power semiconductor device comprises a drain electrode located at the bottom, an N + substrate located on the upper end face of the drain electrode, an N-drift region located on the upper end face of the N + substrate, a P-type body region located on the upper end face of the N-drift region, and a source electrode located at the top. By introducing the nano-composite super-junction shielding structure, optimizing the shape and the size of the groove and integrating the micro-nano fin structure and the reconfigurable self-adaptive shielding grid structure, the electric field distribution in the device can be remarkably improved, and the nano-particles in the nano-composite super-junction shielding structure, the P columns and the N columns have a synergistic effect; the reconfigurable self-adaptive shield grid structure adjusts the electric field in real time according to the working state, and the measures effectively relieve the groove electric field aggregation effect, so that the electric field distribution is more uniform, and the breakdown voltage and reliability of the device are improved.

The invention discloses a method for preventing needle burning during testing of breakdown voltage of a discrete device. According to the method, in a test loop comprising a probe card and a test source, a voltage-withstanding module is connected in series between the probe card and a low-potential end of the test source. The voltage-withstanding module comprises a detection resistor Rx and a voltage-withstanding switching device connected with the detection resistor Rx in parallel. When the test current I is applied, if the current is increased abnormally due to poor contact and the like, and the voltage drop on the detection resistor Rx is greater than or equal to the starting voltage VT of the voltage-withstanding switching device, the voltage-withstanding switching device is switched on, the test current I is shunted, and the current flowing through the probe card is reduced, so that the probe is prevented from being burnt. The breakdown voltage of the tested device is calculated by measuring the total voltage V at the two ends of the test source and subtracting the voltage drop (I * Rx) on the detection resistor Rx, and the test accuracy is ensured. The method can effectively protect the probe card and improve the test reliability and efficiency.

The invention provides a process integration method of a high-voltage CMOS device and a semiconductor device.In the process integration method, before a floating gate material layer is formed, a high-voltage gate dielectric layer and a high-voltage well region of a high-voltage MOS device region are formed, and after the floating gate material layer is formed, the floating gate material layer and an ONO dielectric layer of the high-voltage MOS device region are reserved; the combination of the floating gate material layer, the ONO dielectric layer and the control gate material layer is used as a high-voltage gate structure of the high-voltage MOS device region, so that the thickness of the high-voltage gate structure is increased, and the thickness of the side wall structure of the high-voltage MOS device region is the same as that of the side wall structure of the flash memory device region, so that the thickness of the side wall structure of the high-voltage MOS device region is increased in a disguised manner; according to the invention, the ion implantation energy of the subsequent lightly-doped drain region can be correspondingly increased according to requirements, and a more slowly-changing LDD junction can be formed in a high-voltage MOS device region in a device integration process, so that the breakdown voltage of a high-voltage device is improved.

The invention relates to the technical field of semiconductor power devices, discloses a semiconductor power device and a preparation method thereof, and aims to improve the voltage resistance and reliability of the device. The terminal structure comprises a substrate; the epitaxial layer is positioned above the substrate; the heavily doped region is located in the epitaxial layer; the junction termination extension region is positioned in the epitaxial layer and is in contact with the heavily doped region; the oxide layer is positioned above the heavily doped region and the junction termination extension region and covers part of the heavily doped region and the junction termination extension region; and the field plate structure is positioned above the heavily doped region and the junction termination extension region, covers part of the heavily doped region and part of the junction termination extension region, and is positioned in the oxide layer. According to the technical scheme, electric field distribution can be effectively optimized, and breakdown voltage and terminal reliability are improved.

The invention discloses a power semiconductor device and a manufacturing method thereof. The device comprises a first base region, a second base region, a field stop region, a plasma storage region and a bottom doped region which are sequentially arranged from top to bottom, wherein a top P region and a terminal field limiting ring are arranged in the first base region. Wherein the first base region is used for optimizing the terminal structure; the second base region is used for improving a self-clamping function and adjusting power consumption and static breakdown voltage; the field termination region is used for terminating an electric field and suppressing current and voltage oscillation; the plasma storage area is used for expanding the safe working area and improving the self-clamping function. By optimizing and compromising the structural parameters of each area, the device can achieve the beneficial effects of self-clamping, low loss, wide safe working area and small terminal size.

The invention relates to the technical field of semiconductors, in particular to a heterogeneous power device and a preparation method thereof, and the heterogeneous power device comprises a base structure which comprises a substrate layer, a first epitaxial layer and a second epitaxial layer which are sequentially arranged from bottom to top; and the P-type semiconductor layer is grown on the surface of the second epitaxial layer in a sputtering manner. By selectively etching the P-type semiconductor layer for multiple times, forming the strip-shaped field limiting ring blocks and connecting the field limiting ring blocks, an electric field is more uniform and smoother, the phenomenon of local electric field concentration is avoided, and the electric field intensity peak of the P-type semiconductor layer close to the side edge of the drain electrode or the source electrode is remarkably weakened, so that the voltage endurance capability of the device in an off state is effectively improved; besides, due to the design of the strip-shaped field limiting ring blocks, the coverage area of the P-type semiconductor layer is greatly reduced, the parasitic plate capacitance at a channel is further remarkably reduced, the switching speed of the device is favorably improved, and the reliability of the dynamic characteristic is enhanced.

The invention relates to the technical field of liquid cooling, and discloses a cooling liquid composition, a preparation method and application thereof and an immersed cooling device. The cooling liquid composition is prepared from the following components in parts by mass: 30 to 50 parts of hydrogenated dipolydecene, 10 to 40 parts of II-type base oil and 10 to 40 parts of III-type base oil. Through mutual cooperation and optimization of the components, the low-cost and high-performance cooling liquid composition and the preparation method thereof are developed, and the provided cooling liquid composition has the characteristics of high flash point, large specific heat capacity, low kinematic viscosity, large breakdown voltage and good copper corrosion rating, can be applied to an immersed liquid cooling heat dissipation system and an immersed cooling device, and has good application prospects. The requirements for flowability, electrical insulation and metal compatibility are met, and excellent safety and heat exchange performance are shown.

The invention belongs to insulation of superconducting power equipment, and particularly relates to a breakdown voltage prediction method for a liquid nitrogen, insulation barrier and bubble composite system. Comprising the following steps: acquiring electric field distribution characteristic parameters of the resistance type superconducting current limiter through simulation, and designing an equivalent electrode structure capable of reproducing electric field characteristics in a liquid nitrogen environment; establishing a first breakdown voltage prediction model taking the insulation barrier position parameters and the electrode spacing as variables; calculating the surface heat flux of the superconducting strip in the quench fault state; and introducing a bubble influence factor for correction to obtain a second breakdown voltage prediction model. A complex actual insulation system prediction problem is converted into an equivalent model problem which can be verified in a laboratory. And an accurate basis is provided for the insulation design of the resistance-type superconducting current limiter.

An object is to provide a technique that eliminates the need for an external circuit for enhancing the breakdown voltage. A switching element drive circuit includes a primary circuit and a secondary circuit, and an insulating element isolating the primary circuit and the secondary circuit from each other in terms of a direct current. The secondary circuit includes a semiconductor substrate, a detector provided on a portion of the semiconductor substrate, including a pn junction isolation portion, and configured to detect a voltage of a high voltage terminal, and a controller provided on a remaining portion of the semiconductor substrate and configured to control a control voltage of a semiconductor switching element based on a second signal and a detection result of the detector.

The invention relates to the technical field of semiconductors, and discloses an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a preparation method thereof, and the LDMOS device comprises a substrate layer comprising a drift region, a field oxide layer and a gate oxide layer which are located on the surface of the substrate layer, a gate structure, a polycrystalline silicon structure at the side part, a first dielectric layer and a first conductive column, the metal field plate, the second conductive through hole and the field plate connecting structure are arranged at the side part of the gate metal layer; wherein the field oxide layer is located on the surface of the drift region, and the gate structure, the drift region and the field oxide layer between the gate structure and the drift region form a first field plate structure; the metal field plate, the polycrystalline silicon structure and the first dielectric layer therebetween form a first capacitor, the polycrystalline silicon structure, the drift region and the field oxide layer therebetween form a second capacitor, and the first capacitor and the second capacitor are coupled in series to form a second field plate structure; the first field plate structure and the second field plate structure are connected through the field plate connecting structure and the second conductive through hole to form a double-field-plate structure. According to the invention, the breakdown voltage of the device can be improved under the condition of low on-resistance.

The invention provides a high-reliability super-junction trench gate silicon carbide VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) with voltage higher than 3kV and a preparation method thereof. The method comprises the following steps: depositing metal on the lower side surface of a silicon carbide substrate to form a drain metal layer, and epitaxially growing on the upper side surface of the silicon carbide substrate to form a buffer region; performing epitaxial growth on the buffer region to obtain a first drift region; performing ion implantation to form a P-type region; removing the barrier layer, and performing epitaxial growth on the first drift region to obtain a second drift region; forming a barrier layer, and performing etching and ion implantation to form a P-type well region, a P + region and an N-type source region; etching the P-type well region and the N-type source region to form a first groove; etching the N-type source region, and then depositing metal to form a source metal layer; oxidizing to form an insulating dielectric layer, wherein a groove is formed in the insulating dielectric layer; and depositing metal, forming a gate metal layer, removing the barrier layer, and completing preparation. The voltage endurance capability and reliability of the device are improved by constructing a device gate and a source which are comprehensively wrapped by a P-type well region and a P-type region.

The invention relates to the technical field of semiconductors, in particular to a high-temperature reverse bias test method, an electrostatic discharge protection structure and electronic equipment, and the method comprises the steps: providing the electrostatic discharge protection structure; determining an initial leakage current at the initial voltage, and determining an initial breakdown voltage at the initial current; heating the electrostatic discharge protection structure for a preset time at a preset temperature and a preset voltage, and determining a target leakage current of the heated electrostatic discharge protection structure under the initial voltage and a target breakdown voltage of the heated electrostatic discharge protection structure under the initial current; performing current change analysis on the initial leakage current and the target leakage current to obtain a current change result, and performing voltage change analysis on the initial breakdown voltage and the target breakdown voltage to obtain a voltage change result; and according to the current change result and the voltage change result, generating a high-temperature reverse bias test result of the electrostatic discharge protection structure. According to the invention, the reliability of the electrostatic discharge protection structure can be accurately evaluated.

According to the junction field effect transistor device, the preparation method thereof and the electronic equipment provided by the invention, the threshold voltage of the device can be controlled through the low-voltage JFET channel region (namely the first horizontal part) formed by the first P-type ion implantation. Meanwhile, the size of the vertical channel (namely the first vertical part) is determined through first P-type ion implantation, groove etching is carried out in an implantation region, the size of the etched vertical channel and the size of the P-type gate (namely the second P-type region) are decoupled, and the influence of vertical channel etching on threshold voltage and drain breakdown voltage is avoided. Moreover, the gate ohmic contact layer is formed in the trench region (namely above the second horizontal part) to be connected to the gate of the device, so that the gate-drain capacitance CGD of the device can be reduced, the input capacitance and gate charge of the device are reduced, the switching speed of the device can be improved, the switching loss of the device is reduced, and the switching performance of the device is improved. The method is very suitable for the common direct drive type application of the high-voltage normally-open JFET.

The invention discloses a cable accessory interface breakdown voltage testing device and method. The cable accessory interface breakdown voltage testing device comprises a conductor, a first shrinkage pipe, a second shrinkage pipe, a first electrode, a second electrode and voltage detection equipment. And the first shrinkage pipe wraps the outer wall of the conductor after being shrunk. And the second shrinkage pipe covers the outer wall of the first shrinkage pipe after being shrunk. The first electrode and the second electrode are arranged between the first shrinkage pipe and the second shrinkage pipe, and the first electrode and the second electrode are arranged at intervals in the axial direction. The voltage detection device is connected with the first electrode and the second electrode. According to the invention, the interface breakdown voltage of the cable accessory can be detected quickly, economically, effectively and accurately.