2545 results about "Breakdown voltage" patented technology

The invention relates to the technical field of MOS semiconductors, and discloses a variably doped planar gate silicon carbide VDMOS device and a preparation process thereof, the variably doped planar gate silicon carbide VDMOS device comprises a plurality of MOS cells which are parallel to each other, and each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of a single MOS cell; lateral symmetric P-layers are arranged in the single MOS cell and located on the left side and the right side of the N drift layer, and the section contours of the corresponding sides of the lateral symmetric P-layers on the two sides are in an arc shape. By arranging the lightly doped N layer in the middle of the N drift layer and introducing the arc-shaped laterally-symmetrical P-layers to the two sides, the electric field distribution of the device is optimized, the local electric field concentration is reduced, the breakdown voltage is remarkably improved, and the charge balance capability is enhanced and the leakage current is reduced through the contact between the laterally-symmetrical P-layers and the N substrate layer.

The invention relates to the technical field of MOS semiconductors, and discloses a silicon carbide thick-bottom oxide layer groove MOS structure and a preparation method thereof, the silicon carbide thick-bottom oxide layer groove MOS structure comprises a plurality of parallel MOS cells, and each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of each MOS cell; the lightly doped N layer is arranged in the middle of the N drift layer, the arc-shaped contour design with the inclined top is introduced to the two sides, the injection area is accurately controlled through the photoetching technology, the phenomenon that the edge electric field concentration of the N drift layer is effectively dispersed is effectively dispersed, in this way, electric field distribution is more uniform, breakdown voltage is improved, and local electric field concentration is reduced; moreover, the contact between the laterally symmetrical P-layer and the N substrate layer enhances the charge balance capability, and reduces the leakage current.

The present disclosure provides an interdigitated back contact cell and a manufacturing method thereof. The interdigitated back contact cell includes: a substrate including a front side and a back side, the front side being arranged opposite to the back side; where, along a first direction, first functional regions and second functional regions are alternately arranged on the back side of the substrate; an isolation region is arranged between every adjacent first functional region and second functional region; and the first emitter is spatially isolated from one adjacent second emitter by a corresponding isolation region; and the first diffusion layer is in contact with at least one adjacent second diffusion layer in a corresponding region of a corresponding isolation region. The interdigitated back contact cell provided by the present disclosure has a lower reverse breakdown voltage, a high component reliability, and a high cell efficiency.

The present invention relates to a gallium oxide power diode with a high breakdown voltage and a preparation method thereof. The preparation method includes: selecting a substrate layer, preparing a drift layer on the upper surface of the substrate layer; preparing a cathode on the lower surface of the substrate layer; preparing an anode on the upper surface of the drift layer; performing a low-temperature annealing process on the device to obtain the gallium oxide power diode; wherein, both the substrate layer and the drift layer are Si- or Sn-doped β-Ga2O3 materials, and the doping concentration of the drift layer is lower than that of the substrate layer, the anode is a Ni / Au metal stack, and a NiO layer with P-type characteristics is formed at the interface between the metal Ni and the drift layer, and the NiO layer and the drift layer form a heterojunction PN junction structure. The preparation method of the present invention can form a heterojunction PN junction structure with a P-type characteristic thin layer NiO layer through low-temperature annealing, can modulate the electric field distribution, improve the interface characteristics between the anode metal and gallium oxide, reduce the reverse leakage current, and increase the breakdown voltage of the device.

The invention discloses a partial discharge and breakdown combined test system and test method under wide temperature range and variable air pressure, which are suitable for evaluating the insulating properties of insulating materials, cables and power equipment under high and low temperature and different air pressure conditions. The system comprises a vacuum oven, a partial discharge and withstand voltage breakdown joint test module, an explosion-proof cable joint, a control module and a detection module, the vacuum oven can realize temperature regulation and control from-70 DEG C to + 200 DEG C and an air pressure environment of 10 <-3 > Pa, and the test module integrates a high voltage generator, a coaxial electrode and a partial discharge sensor. Partial discharge detection and breakdown voltage measurement can be completed in the same test environment. According to the test method, the electrical response characteristics of the insulating material under different working conditions are obtained through regulation and control of environment temperature and pressure, execution of a test process and data acquisition and analysis. The device is compact in structure and high in safety, and has the capabilities of joint testing, high-precision regulation and control and adaptability to complex environments.

The invention discloses a motor insulation breakdown voltage prediction method based on a continuous hidden Markov model, and the method comprises the steps: taking a plurality of groups of obtained experimental data of an insulating material of a motor in different motor operation time periods as a training set, and enabling the experimental data to comprise capacitance, insulation resistance, dielectric loss, maximum discharge capacity and breakdown voltage; constructing a continuous hidden Markov model by taking the test parameters as an observation sequence and taking the discretized breakdown voltage as a hidden state; performing iterative calculation on parameters of the continuous hidden Markov model through a Baum-Welch algorithm based on the training set, and determining optimal parameters of the continuous hidden Markov model; and based on the continuous hidden Markov model of the optimal parameters, determining a hidden state sequence with the maximum probability under the observation sequence at the current moment through a Viterbi algorithm, and determining the breakdown voltage at the current moment based on the hidden state sequence with the maximum probability. According to the invention, the breakdown voltage of the motor insulating material in the motor operation process can be effectively predicted.

The invention relates to the technical field of MOS semiconductors, and discloses a heterojunction-based silicon carbide groove type MOSFET device structure and a preparation process thereof.The heterojunction-based silicon carbide groove type MOSFET device structure comprises a plurality of parallel MOS cells, each MOS cell comprises a drain electrode, a source electrode, a grid electrode and a semiconductor epitaxial layer, and each semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer; a groove is formed in the upper surface of the single MOS cell and located below the grid electrode, an N + layer is deposited in the groove, and the N + layer comprises a left N + layer and a right N + layer. Through the design of the split type left N + layer and the right N + layer in the groove and the combination of the middle N-layer or the middle P-layer filled in the middle, the electric field concentration phenomenon at the bottom of the groove is effectively dispersed, and the electric field peak value at the edge of the N drift layer is further inhibited in cooperation with the right triangle arrangement of the blocking ion bubbles, so that the breakdown voltage and the reliability of the device are remarkably improved, and the reliability of the device is improved. The method is suitable for high-voltage application scenes.

The invention discloses a high-voltage SiC MOSFET cellular structure. The high-voltage SiC MOSFET cellular structure comprises an N + type silicon carbide power substrate, an N type drift region and a current expansion layer which are stacked in sequence, the electric field modulation regions are arranged on the left side and the right side of the current expansion layer, the P-body region is arranged above the current expansion layer, and the N + type source region and the P + type source region are arranged above the P-body region; the gate trench is arranged in the middle of the current expansion layer, a P + type shielding region is arranged at the bottom of the gate trench, a gate is arranged in the gate trench, and the gate is located above the P + type shielding region; and the gate oxide layer covers the upper surfaces of the gate, the N + type source region and the P + type source region. According to the structure, the electric field modulation areas are arranged on the two sides of the current expansion layer, the peak electric field intensity of the bottom of the groove of the UMOSFET device is reduced, the reverse breakdown voltage of the device is greatly improved, and meanwhile, the N-type areas in the electric field modulation areas also effectively reduce the characteristic on-resistance when the power device is conducted.

According to the SGT MOSFET of the Low-k material and the preparation method of the SGT MOSFET, a gate insulating layer of the SGT MOSFET is deposited by adopting the Low-k material based on carbon-doped silicon oxide, and an oxide layer on the side wall of a shielding gate adopts an ONO structure, so that on one hand, the capacitance effect of a device can be reduced through the Low-k material under the condition that the physical thickness of the insulating layer is kept unchanged and electric leakage is not influenced, and the performance of the device is improved; the performance of the device is improved; and on the other hand, the compactness of the silicon nitride layer is high, and the side wall and the bottom of the shield gate polycrystalline silicon are protected by the silicon nitride layer, so that the on resistance of the device is further reduced and the conduction loss of the device is reduced by improving the doping concentration of the epitaxial layer on the basis of not reducing the breakdown voltage. Meanwhile, by controlling the depth of the oxide layer and the silicon nitride layer which are etched on the side wall of the groove, the silicon nitride layer is far away from the grid polycrystalline silicon, and the reliability of the device is improved.

The invention relates to an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a manufacturing method thereof. The LDMOS device comprises a semiconductor substrate; the body region and the drift region are formed in the semiconductor substrate, the source region is located in the body region, and the drain region is located in the drift region; the at least two shallow trench isolation structures are formed in the drift region, the tops of the at least two shallow trench isolation structures are higher than the surface of the semiconductor substrate, and a dielectric layer is formed between the parts, higher than the surface of the semiconductor substrate, of the at least two shallow trench isolation structures; and the gate structure comprises a gate dielectric layer and a gate electrode layer located on the gate dielectric layer, and the gate structure transversely extends to the drift region from the body region and at least partially covers the shallow trench isolation structure. The LDMOS structure has a relatively high breakdown voltage.

The invention relates to an ultra-high voltage line lightning resistance level evaluation method and device based on a tower head gap structure. The method comprises the following steps: constructing a simulation model according to line structure information and electrical parameters of an extra-high voltage line and tower structure information of a power transmission tower; inputting lightning current waveform parameters and lightning channel wave impedance parameters of the extra-high voltage line into the simulation model to obtain voltage distribution information and current propagation characteristic information of the extra-high voltage line under a lightning stroke condition; flashover criterion information is determined according to the insulator string discharge voltage characteristic information and the tower head air gap breakdown voltage characteristic information of the extra-high voltage line; and according to the voltage distribution information, the current propagation characteristic information and the flashover criterion information, determining a lightning resistance level evaluation result. By adopting the method, the influence of the breakdown characteristic of the tower head air gap, the complexity of the tower structure and the dynamic characteristic of lightning current propagation on the lightning resistance level evaluation can be comprehensively considered, and the accuracy of the lightning resistance level evaluation result of the extra-high voltage line is improved.

The invention provides a semiconductor device and a preparation method thereof, and the method comprises the following steps: providing a substrate which comprises a base layer and a spacer layer located on the base layer, and is divided into a first region for forming a BCD device and a second region for forming an SGT device, a BCD structure is arranged in the substrate layer of the first area, and a first SGT structure and a second SGT structure which are spaced from each other are arranged in the substrate layer of the second area; forming a patterned photoresist layer on the first SGT structure in the second region and the spacer layer above the BCD structure in the first region, and etching the spacer layer to expose a part of the substrate layer and the second SGT structure; and forming a control gate on the spacer layer above a part of the BCD structure and extending to a part of the exposed substrate layer, wherein the control gate is also formed on the exposed second SGT structure. On the basis of not increasing a photomask and a process, the breakdown voltage can be increased, and the electrical performance of the device is improved.

The invention discloses a composite terminal structure of a silicon carbide PIN diode and a design method of the composite terminal structure. The composite terminal structure comprises a device cell and a device terminal. The device cell comprises an N + type heavily doped substrate, an N-type lightly doped drift layer and a P + type heavily doped layer which are arranged in sequence; the device terminal is located in the N-type lightly doped drift layer, the device terminal comprises two parts of P + type junction terminal expansion regions and three groups of P + type field limiting ring structures, P + injection rings formed by P + type ion injection are arranged in the P + type junction terminal expansion regions, a plurality of P + injection rings form the P + type field limiting ring structures, the adjacent P + injection rings are separated by the P + type junction terminal expansion regions, and the P + type field limiting ring structures are arranged in the N-type lightly doped drift layer. And the upper surfaces of the P + type junction terminal expansion region and the P + injection ring are covered with oxide layers. The high-voltage power device has the advantages of being compact in structure, small in device area, low in production cost and the like, higher breakdown voltage, better process robustness and long-term reliability are achieved within the limited chip area, and the requirements of the next-generation high-voltage power device are met.

The invention discloses a method and system for testing the electrical performance of a semiconductor chip, and the method comprises the steps: building a mapping relation between dielectric loss and loss frequency through obtaining the dielectric loss data, internal material characteristics and dynamic load power factors of the chip under each frequency band, recognizing a loss abnormal region, and analyzing the influence of the loss abnormal region on the performance of the chip; correcting test data by adopting a minimum mean square error algorithm, and optimizing the impedance of the power supply network and the dynamic switching characteristic of a functional module; calculating the breakdown voltage distribution of each layer in the chip, identifying a high-voltage risk region, optimizing the voltage distribution by using a gradient descent algorithm, and dynamically adjusting the working voltage and current; power factor fluctuation is analyzed through a sliding window algorithm, an abnormal area is identified, a power factor is optimized through a PID algorithm, and the working state and transient response of a chip in a dynamic load are improved. According to the method, the problems of nonlinearity of high-frequency dielectric loss, non-uniform breakdown voltage distribution and unstable power factor response under a dynamic load are solved, and comprehensive and accurate evaluation and optimization of chip performance are realized.

The invention provides an electric field enhancement type shield gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), which comprises a substrate, an epitaxial layer formed on the substrate, a gate trench formed on a cellular region on the epitaxial layer, and a first gate dielectric layer formed at the bottom of the gate trench and a first polycrystalline silicon layer located in the first gate dielectric layer, a P-type epitaxial layer is formed on the first gate dielectric layer and the first polycrystalline silicon layer, and an isolation dielectric layer is formed on the P-type epitaxial layer; a second gate dielectric layer is formed on the side wall of the residual gate trench, and a second polycrystalline silicon layer is formed in the residual gate trench; a well region and a source region of a cellular region are formed on the epitaxial layer, and a contact hole dielectric layer is formed on the epitaxial layer; and contact holes communicated with the well region are formed on the contact hole dielectric layer and the epitaxial layer below the contact hole dielectric layer. By adding the shield grid P-type epitaxial layer, the electric field intensity in the middle of the drift region is effectively improved, the breakdown voltage is improved, and meanwhile, the conduction loss can be further reduced by adjusting epitaxy.

The utility model discloses a semiconductor device, which belongs to the field of semiconductors, and at least comprises a substrate; the well region is arranged in the substrate; the two drift regions are arranged in the well region at intervals, and shallow trench isolation structures are arranged in the drift regions; the body region is arranged in the well region between the two drift regions; the vertical grid electrode is located in the body region, and the vertical grid electrode extends into the well region from the surface of the substrate; the source doped regions are respectively arranged in the body regions on the two sides of the vertical grid electrode; the drain doping region is arranged in the drift region; and the planar grid electrode is arranged around the vertical grid electrode and the source doping region and covers part of the body region, part of the well region and part of the shallow trench isolation structure. According to the semiconductor device provided by the utility model, the characteristic on-resistance can be reduced and the performance of the semiconductor device can be improved under the condition that the breakdown voltage is not changed.

The invention discloses a back contact battery and a photovoltaic module, and relates to the technical field of photovoltaics. The back contact cell comprises a silicon substrate which comprises a first surface and a second surface which are oppositely arranged, and a side surface which connects the first surface and the second surface; the first interface passivation layer, the first doped silicon layer, the intrinsic silicon layer, the second doped silicon layer and the transparent conducting layer are sequentially arranged on the side face in the direction away from the side face. On the side surface of the silicon substrate, the first doped silicon layer is in direct contact with the intrinsic silicon layer; wherein the conduction types of the first doped silicon layer and the second doped silicon layer are opposite. On the side face of the silicon substrate, the first doped silicon layer can be electrically connected with the second doped silicon layer with the conduction type opposite to that of the first doped silicon layer through the intrinsic silicon layer, so that a diode structure with low reverse breakdown voltage is formed on the side face of the silicon substrate, and the hot spot risk of the back contact battery is reduced.

The invention relates to the technical field of battery structures, and provides a single battery, a battery and electric equipment.The single battery comprises a shell, an electrode assembly, a first insulation protection layer and a second insulation protection layer, a containing cavity is formed in the shell, the electrode assembly is arranged in the containing cavity, the first insulation protection layer is arranged on the inner wall of the shell, and the second insulation protection layer is arranged on the inner wall of the shell. The second insulating protection layer is configured to cover at least part of the electrode assembly; according to the battery monomer provided by the embodiment of the invention, the first insulation protection layer is arranged on the inner wall of the shell, the second insulation protection layer is coated on at least part of the electrode assembly, and the shell and the electrode assembly are separated by utilizing the first insulation protection layer and the second insulation protection layer, so that the creepage distance between the shell and the electrode assembly is increased; the purpose of improving the breakdown voltage resistance between the shell and the electrode assembly can be achieved, so that the high-voltage breakdown resistance of the shell can be effectively improved, and the probability of combustion or explosion of the single battery is further reduced.

The invention relates to a SiC groove type JFET device structure and a preparation method thereof. The SiC groove type JFET device structure comprises a drain metallization layer, a SiC N + substrate layer, a first N type drift region, a source groove structure, a second N type drift region, a P-well region, an N + source region, a P + gate region, an isolation dielectric layer, a gate metallization layer and a source metallization layer. The source trench structure is arranged in the first N-type drift region, the upper surface of the source trench structure is in contact with the P-well region and the source metallization layer, and an oxide layer and a polycrystalline silicon layer are sequentially filled in a trench, so that the upper surface of the trench structure is flush with the upper surface of the first N-type drift region. By introducing the trench structure connected with the source electrode in the drift region, the transverse electric field distribution condition in the device can be optimized, the peak electric field is reduced, the conduction capability of the device is further improved under the condition of ensuring that the original breakdown voltage is not changed, the performance of the SiC JFET is greatly improved, and the conduction loss during working is reduced.

The invention discloses a preparation method of modified self-extinguishing insulating oil with flame-retardant and self-repairing functions. Wherein the insulating liquid is mixed oil of mineral oil and palm oil-based modified natural ester, and the inherent high flash point characteristic of the natural ester improves the fireproof safety of the insulating oil. The modified hexagonal boron nitride (h-BN), the magnesium hydroxide nano material and the microcapsule repairing agent are added into the insulating oil, and the h-BN can capture free electrons in the oil, so that the formation and expansion of electric arcs are inhibited, and the breakdown voltage is improved. Magnesium hydroxide is heated to decompose and absorb heat, the fault temperature is reduced, and therefore the arc self-extinguishing effect is achieved. Under the action of a high electric field and a high temperature, the capsule wall of the microcapsule repairing agent is broken, meanwhile, the repairing material is released, a chemical reaction is carried out, and the insulating property of the insulating oil is repaired. The modified insulating oil prepared by the invention has high insulating strength and high flame retardance, and also has a performance self-repairing function, so that the service life of the insulating oil is prolonged.

A current may be passed through a channel of an anti-fuse field-effect transistor (FET) to increase a temperature of a gate dielectric of the anti-fuse FET and change a rupture voltage of the gate dielectric of the anti-fuse FET from a first rupture voltage to a second rupture voltage. The gate dielectric may be ruptured by applying a first voltage between the gate dielectric and the channel of the anti-fuse FET, where the first voltage is between the first rupture voltage and the second rupture voltage.

The utility model relates to a power semiconductor device, in particular to a power semiconductor device, an upper P-type cover layer and a lower P-type cover layer are designed, the high doping concentration of the first P-type cover layer at the lower layer ensures that the threshold voltage of the device can reach a higher value, and the opportunity that an enhanced device is mistakenly opened is reduced; the doping concentration of the upper second P-type cover layer decreases progressively from bottom to top in the vertical direction and decreases progressively from the middle to the left edge and the right edge in the horizontal direction, the doping concentration of the surface corner position is low, when the grid electrode is pressed in the forward direction, the depletion region of the surface corner is deep, the formed peak electric field is low, the design reduces the leakage current of the grid electrode, and the reliability of the grid electrode is improved. And the breakdown voltage and the reliability of the gate are improved.

The invention relates to the technical field of electrical equipment insulation performance detection, in particular to an insulating oil dielectric loss test system based on temperature compensation, which comprises a temperature acquisition module for acquiring insulating oil temperature data and environment temperature data; the dielectric loss measurement module measures a dielectric loss value and a dielectric loss angle through a self-adaptive anti-interference algorithm, and synchronously records voltage and frequency; the intelligent compensation module matches temperature characteristic parameters for different temperature intervals, and compensates a dielectric loss detection value through a segmented temperature compensation model; the state analysis module judges the aging degree and state of the insulating oil according to the compensated dielectric loss value and acid value, generates a multi-stage early warning signal and a diagnosis report by combining the breakdown voltage and the moisture content, and dynamically adjusts the test frequency according to the oil sample type and the operating age limit; and the cloud management platform stores historical data and compensation parameters, establishes a performance degradation model, analyzes a dielectric loss trend and generates maintenance suggestions. Therefore, the problems of insufficient test precision, poor environmental adaptability and the like in the prior art are solved.

The disclosure provides a LDMOS device and a fabrication method. By arranging a first field oxide, a second field oxide, a third field oxide, a gate polysilicon, and a gate oxide layer in the trench and making the surface of the gate polysilicon away from the trench flush with the trench opening, the lateral dimension of the LDMOS device is reduced. Meanwhile, by setting the thickness of the first field oxide and the third field oxide to be greater than that of the second field oxide, setting the height of the first field oxide to be less than or equal to the distance from the bottom of the trench to the channel region, and making the surface of the third field oxide away from the trench flush with the opening of the trench, three independent field plates are formed in the trench. This improves breakdown voltage resistance of the LDMOS device.

The invention discloses a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit, and a vehicle. The semiconductor device includes: a semiconductor body; the semiconductor body comprises a well region and a first region; the first surface is provided with a gate trench; the gate trench comprises a first gate trench and a second gate trench which are communicated, and the second gate trench is located at one side, far away from the first surface, of the first gate trench; the first gate trench extends into the first region and the well region from the first surface, and the second gate trench is located at one side, far away from the first region, of the well region; the semiconductor body further comprises a first insulating layer and a second insulating layer, the first insulating layer is located on the side wall of the first gate trench, the second gate trench is filled with the second insulating layer, and the thickness of the second insulating layer is larger than or equal to that of the first insulating layer; and a trench gate located in the first gate trench. According to the technical scheme, the breakdown voltage of the semiconductor device is improved, and the device performance is improved.

The invention relates to an enameled flat wire. The surface of a conductor is sequentially coated with first polyimide paint, second polyamide-imide paint, third polyimide paint and fourth polyimide paint, wherein the second polyamide-imide paint and the third polyimide paint are alternately arranged; wherein the peel strength of the first polyimide paint is not lower than 1.5 N / mm; the relative dielectric constant of the third polyimide paint is not greater than 2.1; nanoscale zirconium dioxide and nanoscale aluminum oxide are added into the fourth polyimide paint. The tensile strength of the enameled flat wire is not lower than 230 MPa; in a measurement standard within 100PC, a partial discharge initial voltage value of 50Hz-20kHz is not less than 2000V; under the condition that the leakage current does not exceed 5mA, the breakdown voltage value is not lower than 11kV; in a corona environment with the temperature being 155 DEG C, the voltage of Vp-p being 4000 V, the rising edge being 100 ns and the frequency being 20 kHz, the corona-resistant service life is 100-400 hours; in an ATF oil resistance test of T / CEEIA415-2019 standard, a partial discharge initial voltage value and a breakdown voltage value are both not lower than 90% of an initial value.

The invention relates to the technical field of power semiconductor devices, in particular to a power semiconductor device with a shield gate trench structure and a manufacturing method thereof, and the power semiconductor device comprises a drain electrode located at the bottom, an N + substrate located on the upper end face of the drain electrode, an N-drift region located on the upper end face of the N + substrate, a P-type body region located on the upper end face of the N-drift region, and a source electrode located at the top. By introducing the nano-composite super-junction shielding structure, optimizing the shape and the size of the groove and integrating the micro-nano fin structure and the reconfigurable self-adaptive shielding grid structure, the electric field distribution in the device can be remarkably improved, and the nano-particles in the nano-composite super-junction shielding structure, the P columns and the N columns have a synergistic effect; the reconfigurable self-adaptive shield grid structure adjusts the electric field in real time according to the working state, and the measures effectively relieve the groove electric field aggregation effect, so that the electric field distribution is more uniform, and the breakdown voltage and reliability of the device are improved.

The invention discloses a method for preventing needle burning during testing of breakdown voltage of a discrete device. According to the method, in a test loop comprising a probe card and a test source, a voltage-withstanding module is connected in series between the probe card and a low-potential end of the test source. The voltage-withstanding module comprises a detection resistor Rx and a voltage-withstanding switching device connected with the detection resistor Rx in parallel. When the test current I is applied, if the current is increased abnormally due to poor contact and the like, and the voltage drop on the detection resistor Rx is greater than or equal to the starting voltage VT of the voltage-withstanding switching device, the voltage-withstanding switching device is switched on, the test current I is shunted, and the current flowing through the probe card is reduced, so that the probe is prevented from being burnt. The breakdown voltage of the tested device is calculated by measuring the total voltage V at the two ends of the test source and subtracting the voltage drop (I * Rx) on the detection resistor Rx, and the test accuracy is ensured. The method can effectively protect the probe card and improve the test reliability and efficiency.

The invention discloses a semiconductor device and a manufacturing method of the semiconductor device. The semiconductor device includes a substrate having opposing front and back surfaces. A main junction region, a terminal region and a field cut-off region are sequentially arranged in the position, close to the front surface, of the substrate in the first direction parallel to the front surface. At least one groove is formed in the position, close to the field stop region, in the terminal region, a field limiting ring is formed in the terminal region, at least one part of the field limiting ring surrounds the groove, and the junction depth of the field limiting ring with the groove surrounded therein is larger than that of the field limiting ring with no groove surrounded therein. According to the semiconductor device, the groove structure is arranged in the terminal region, so that the ion implantation depth can be increased, and a deeper junction depth can be formed subsequently. The deeper junction depth can reduce the surface peak electric field intensity, the peak electric field intensity is transferred from the surface to a silicon body, and the curvature radius of the terminal P-type injection region is increased, so that the effect of increasing the breakdown voltage of the terminal structure is achieved.

The invention provides a process integration method of a high-voltage CMOS device and a semiconductor device.In the process integration method, before a floating gate material layer is formed, a high-voltage gate dielectric layer and a high-voltage well region of a high-voltage MOS device region are formed, and after the floating gate material layer is formed, the floating gate material layer and an ONO dielectric layer of the high-voltage MOS device region are reserved; the combination of the floating gate material layer, the ONO dielectric layer and the control gate material layer is used as a high-voltage gate structure of the high-voltage MOS device region, so that the thickness of the high-voltage gate structure is increased, and the thickness of the side wall structure of the high-voltage MOS device region is the same as that of the side wall structure of the flash memory device region, so that the thickness of the side wall structure of the high-voltage MOS device region is increased in a disguised manner; according to the invention, the ion implantation energy of the subsequent lightly-doped drain region can be correspondingly increased according to requirements, and a more slowly-changing LDD junction can be formed in a high-voltage MOS device region in a device integration process, so that the breakdown voltage of a high-voltage device is improved.