1438 results about "Breakdown voltage" patented technology

The utility model discloses a semiconductor device, which belongs to the field of semiconductors, and at least comprises a substrate; the well region is arranged in the substrate; the two drift regions are arranged in the well region at intervals, and shallow trench isolation structures are arranged in the drift regions; the body region is arranged in the well region between the two drift regions; the vertical grid electrode is located in the body region, and the vertical grid electrode extends into the well region from the surface of the substrate; the source doped regions are respectively arranged in the body regions on the two sides of the vertical grid electrode; the drain doping region is arranged in the drift region; and the planar grid electrode is arranged around the vertical grid electrode and the source doping region and covers part of the body region, part of the well region and part of the shallow trench isolation structure. According to the semiconductor device provided by the utility model, the characteristic on-resistance can be reduced and the performance of the semiconductor device can be improved under the condition that the breakdown voltage is not changed.

The invention relates to the technical field of electrical equipment insulation performance detection, in particular to an insulating oil dielectric loss test system based on temperature compensation, which comprises a temperature acquisition module for acquiring insulating oil temperature data and environment temperature data; the dielectric loss measurement module measures a dielectric loss value and a dielectric loss angle through a self-adaptive anti-interference algorithm, and synchronously records voltage and frequency; the intelligent compensation module matches temperature characteristic parameters for different temperature intervals, and compensates a dielectric loss detection value through a segmented temperature compensation model; the state analysis module judges the aging degree and state of the insulating oil according to the compensated dielectric loss value and acid value, generates a multi-stage early warning signal and a diagnosis report by combining the breakdown voltage and the moisture content, and dynamically adjusts the test frequency according to the oil sample type and the operating age limit; and the cloud management platform stores historical data and compensation parameters, establishes a performance degradation model, analyzes a dielectric loss trend and generates maintenance suggestions. Therefore, the problems of insufficient test precision, poor environmental adaptability and the like in the prior art are solved.

The invention provides a process integration method of a high-voltage CMOS device and a semiconductor device.In the process integration method, before a floating gate material layer is formed, a high-voltage gate dielectric layer and a high-voltage well region of a high-voltage MOS device region are formed, and after the floating gate material layer is formed, the floating gate material layer and an ONO dielectric layer of the high-voltage MOS device region are reserved; the combination of the floating gate material layer, the ONO dielectric layer and the control gate material layer is used as a high-voltage gate structure of the high-voltage MOS device region, so that the thickness of the high-voltage gate structure is increased, and the thickness of the side wall structure of the high-voltage MOS device region is the same as that of the side wall structure of the flash memory device region, so that the thickness of the side wall structure of the high-voltage MOS device region is increased in a disguised manner; according to the invention, the ion implantation energy of the subsequent lightly-doped drain region can be correspondingly increased according to requirements, and a more slowly-changing LDD junction can be formed in a high-voltage MOS device region in a device integration process, so that the breakdown voltage of a high-voltage device is improved.

The invention relates to the technical field of semiconductor power devices, discloses a semiconductor power device and a preparation method thereof, and aims to improve the voltage resistance and reliability of the device. The terminal structure comprises a substrate; the epitaxial layer is positioned above the substrate; the heavily doped region is located in the epitaxial layer; the junction termination extension region is positioned in the epitaxial layer and is in contact with the heavily doped region; the oxide layer is positioned above the heavily doped region and the junction termination extension region and covers part of the heavily doped region and the junction termination extension region; and the field plate structure is positioned above the heavily doped region and the junction termination extension region, covers part of the heavily doped region and part of the junction termination extension region, and is positioned in the oxide layer. According to the technical scheme, electric field distribution can be effectively optimized, and breakdown voltage and terminal reliability are improved.

The invention discloses a power semiconductor device and a manufacturing method thereof. The device comprises a first base region, a second base region, a field stop region, a plasma storage region and a bottom doped region which are sequentially arranged from top to bottom, wherein a top P region and a terminal field limiting ring are arranged in the first base region. Wherein the first base region is used for optimizing the terminal structure; the second base region is used for improving a self-clamping function and adjusting power consumption and static breakdown voltage; the field termination region is used for terminating an electric field and suppressing current and voltage oscillation; the plasma storage area is used for expanding the safe working area and improving the self-clamping function. By optimizing and compromising the structural parameters of each area, the device can achieve the beneficial effects of self-clamping, low loss, wide safe working area and small terminal size.

The invention relates to the technical field of liquid cooling, and discloses a cooling liquid composition, a preparation method and application thereof and an immersed cooling device. The cooling liquid composition is prepared from the following components in parts by mass: 30 to 50 parts of hydrogenated dipolydecene, 10 to 40 parts of II-type base oil and 10 to 40 parts of III-type base oil. Through mutual cooperation and optimization of the components, the low-cost and high-performance cooling liquid composition and the preparation method thereof are developed, and the provided cooling liquid composition has the characteristics of high flash point, large specific heat capacity, low kinematic viscosity, large breakdown voltage and good copper corrosion rating, can be applied to an immersed liquid cooling heat dissipation system and an immersed cooling device, and has good application prospects. The requirements for flowability, electrical insulation and metal compatibility are met, and excellent safety and heat exchange performance are shown.

The invention belongs to insulation of superconducting power equipment, and particularly relates to a breakdown voltage prediction method for a liquid nitrogen, insulation barrier and bubble composite system. Comprising the following steps: acquiring electric field distribution characteristic parameters of the resistance type superconducting current limiter through simulation, and designing an equivalent electrode structure capable of reproducing electric field characteristics in a liquid nitrogen environment; establishing a first breakdown voltage prediction model taking the insulation barrier position parameters and the electrode spacing as variables; calculating the surface heat flux of the superconducting strip in the quench fault state; and introducing a bubble influence factor for correction to obtain a second breakdown voltage prediction model. A complex actual insulation system prediction problem is converted into an equivalent model problem which can be verified in a laboratory. And an accurate basis is provided for the insulation design of the resistance-type superconducting current limiter.

An object is to provide a technique that eliminates the need for an external circuit for enhancing the breakdown voltage. A switching element drive circuit includes a primary circuit and a secondary circuit, and an insulating element isolating the primary circuit and the secondary circuit from each other in terms of a direct current. The secondary circuit includes a semiconductor substrate, a detector provided on a portion of the semiconductor substrate, including a pn junction isolation portion, and configured to detect a voltage of a high voltage terminal, and a controller provided on a remaining portion of the semiconductor substrate and configured to control a control voltage of a semiconductor switching element based on a second signal and a detection result of the detector.

The invention relates to the technical field of semiconductors, and discloses an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a preparation method thereof, and the LDMOS device comprises a substrate layer comprising a drift region, a field oxide layer and a gate oxide layer which are located on the surface of the substrate layer, a gate structure, a polycrystalline silicon structure at the side part, a first dielectric layer and a first conductive column, the metal field plate, the second conductive through hole and the field plate connecting structure are arranged at the side part of the gate metal layer; wherein the field oxide layer is located on the surface of the drift region, and the gate structure, the drift region and the field oxide layer between the gate structure and the drift region form a first field plate structure; the metal field plate, the polycrystalline silicon structure and the first dielectric layer therebetween form a first capacitor, the polycrystalline silicon structure, the drift region and the field oxide layer therebetween form a second capacitor, and the first capacitor and the second capacitor are coupled in series to form a second field plate structure; the first field plate structure and the second field plate structure are connected through the field plate connecting structure and the second conductive through hole to form a double-field-plate structure. According to the invention, the breakdown voltage of the device can be improved under the condition of low on-resistance.

The invention provides a high-reliability super-junction trench gate silicon carbide VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) with voltage higher than 3kV and a preparation method thereof. The method comprises the following steps: depositing metal on the lower side surface of a silicon carbide substrate to form a drain metal layer, and epitaxially growing on the upper side surface of the silicon carbide substrate to form a buffer region; performing epitaxial growth on the buffer region to obtain a first drift region; performing ion implantation to form a P-type region; removing the barrier layer, and performing epitaxial growth on the first drift region to obtain a second drift region; forming a barrier layer, and performing etching and ion implantation to form a P-type well region, a P + region and an N-type source region; etching the P-type well region and the N-type source region to form a first groove; etching the N-type source region, and then depositing metal to form a source metal layer; oxidizing to form an insulating dielectric layer, wherein a groove is formed in the insulating dielectric layer; and depositing metal, forming a gate metal layer, removing the barrier layer, and completing preparation. The voltage endurance capability and reliability of the device are improved by constructing a device gate and a source which are comprehensively wrapped by a P-type well region and a P-type region.

The invention relates to the technical field of semiconductors, in particular to a high-temperature reverse bias test method, an electrostatic discharge protection structure and electronic equipment, and the method comprises the steps: providing the electrostatic discharge protection structure; determining an initial leakage current at the initial voltage, and determining an initial breakdown voltage at the initial current; heating the electrostatic discharge protection structure for a preset time at a preset temperature and a preset voltage, and determining a target leakage current of the heated electrostatic discharge protection structure under the initial voltage and a target breakdown voltage of the heated electrostatic discharge protection structure under the initial current; performing current change analysis on the initial leakage current and the target leakage current to obtain a current change result, and performing voltage change analysis on the initial breakdown voltage and the target breakdown voltage to obtain a voltage change result; and according to the current change result and the voltage change result, generating a high-temperature reverse bias test result of the electrostatic discharge protection structure. According to the invention, the reliability of the electrostatic discharge protection structure can be accurately evaluated.

According to the junction field effect transistor device, the preparation method thereof and the electronic equipment provided by the invention, the threshold voltage of the device can be controlled through the low-voltage JFET channel region (namely the first horizontal part) formed by the first P-type ion implantation. Meanwhile, the size of the vertical channel (namely the first vertical part) is determined through first P-type ion implantation, groove etching is carried out in an implantation region, the size of the etched vertical channel and the size of the P-type gate (namely the second P-type region) are decoupled, and the influence of vertical channel etching on threshold voltage and drain breakdown voltage is avoided. Moreover, the gate ohmic contact layer is formed in the trench region (namely above the second horizontal part) to be connected to the gate of the device, so that the gate-drain capacitance CGD of the device can be reduced, the input capacitance and gate charge of the device are reduced, the switching speed of the device can be improved, the switching loss of the device is reduced, and the switching performance of the device is improved. The method is very suitable for the common direct drive type application of the high-voltage normally-open JFET.

The invention relates to the technical field of gallium nitride transistors, and discloses a silicon carbide-gallium nitride heterogeneous integrated high-voltage power device structure, which comprises a silicon carbide device consisting of a plurality of parallel MOS (Metal Oxide Semiconductor) cells and a gallium nitride device consisting of two GaN structures, and is characterized in that the gallium nitride device is positioned on the back surface of the silicon carbide device; each MOS cell comprises a semiconductor epitaxial layer, an MOS source electrode, an MOS grid electrode and an MOS dielectric layer covering the surface of the MOS grid electrode; wherein the semiconductor epitaxial layer comprises an N substrate layer and an N diffusion layer from top to bottom. The transverse high electron mobility characteristic of the GaN HEMT and the longitudinal voltage withstanding advantage of the SiC MOSFET are combined, cooperative work of two wide bandgap semiconductors is achieved on a single substrate, the structure effectively utilizes the excellent heat conduction and voltage withstanding performance of the SiC substrate as a common carrier, meanwhile, through the series voltage withstanding design of the device level, the performance of the device level is improved, and the performance of the device level is improved. And the overall breakdown voltage is obviously improved.

An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a body region and a plurality of gates formed in the epitaxial layer, an interlayer dielectric layer over the epitaxial layer, a gate-source electrostatic discharge (ESD) diode in the interlayer dielectric layer, a source contact connected to the source and a first terminal of the gate-source ESD diode structure, a gate contact connected to the plurality of gates and a second terminal of the gate-source ESD diode structure, a drain contact on opposing sides of the epitaxial layer of the source contact, a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure, wherein the breakdown voltage enhancement and leakage prevention structure comprises a body ring structure.

The invention discloses a gallium nitride power device and a preparation method thereof, and relates to a power semiconductor device, in order to simplify a forming process of a multilayer field plate, the invention provides the gallium nitride power device which is provided with a plurality of dielectric layers rising in a step shape, and a step-shaped side edge is formed on the side surface of each dielectric layer; according to the method provided by the invention, no matter how many layers of the field plates are, field plate deposition only needs to be carried out once, etching can be carried out twice and two layers of field plates can be formed during photoetching each time, the number of layers of the field plates can be increased without increasing the complexity and cost of the process, and the manufacturing cost of the field plates can be reduced. The electric field distribution between the gate metal and the drain metal of the device is more uniform, and the breakdown voltage and the reliability of the device are improved.

A gate structure is formed on a substrate at the junction of a well region and a drift region, the gate structure on the drift region is doped to form a first doped region and a second doped region which are adjacent to each other, the first doped region is doped with first type ions, and the second doped region is doped with second type ions; the conduction types of the second type ions and the first type ions are different, so that the first doped region and the second doped region form a reverse biased PN junction, an electric field caused by the interconnection structure can be balanced and dispersed in the direction from the drain electrode to the source electrode, and the high voltage of the interconnection structure can be effectively isolated; besides, the first doped region and the second doped region form a reverse-biased PN junction to disperse the high potential difference between the first doped region and the second doped region, so that the electric field intensity and the potential peak value on the surface of the device are effectively reduced, the segmented voltage division effect is beneficial to optimization of electric field distribution on the surface of the device, electric field concentration is reduced, and the performance of the device is improved. Therefore, the breakdown voltage of the semiconductor structure is improved.

A semiconductor device includes first and second N-type semiconductor regions provided selectively in an upper layer part of an N-type high-breakdown voltage isolation region, and a P-type semiconductor region provided selectively in the upper layer part of the N-type high-breakdown voltage isolation region and to be supplied with a first power supply voltage lower than a second power supply voltage. The second N-type semiconductor region is arranged closer to an N-type high-potential region than the first N-type semiconductor region and the P-type semiconductor region. The P-type semiconductor region is arranged between the first N-type semiconductor region and the second N-type high-potential region in a plan view. A diode has an anode to be supplied with the second power supply voltage, and a cathode electrically connected to the first N-type semiconductor region. The second N-type semiconductor region is electrically connected to the N-type high-potential region.

The invention relates to insulation performance testing of superconducting equipment of an electric power system, in particular to a superconducting quench bubble, insulation barrier and liquid nitrogen composite insulation breakdown voltage testing method considering the influence of a bubble heat effect. Comprising the following steps: S1, acquiring the relation between the resistance and the surface temperature of the superconducting conductor in a quenching interval; s2, arranging a dielectric barrier member between the superconducting current limiting unit and the electrode; and S3, driving the superconducting current limiting unit to quench, and measuring the breakdown voltage between the superconducting current limiting unit and the first electrode. And S4, determining the representative value of the surface temperature of the superconducting conductor in the quenching process. And S5, performing heat and force coupling numerical simulation. And S6, measuring the change relation of the parameters of the insulation barrier along with the temperature. And S7, obtaining a key electrical parameter corresponding to the temperature parameter T in the step S5. According to the invention, accurate quantification of the influence of the quench bubble heat effect on the composite insulation breakdown characteristic is realized.

The embodiment of the invention provides a method for determining a breakdown voltage prediction model of a capacitor device, and the method comprises the steps: carrying out the modeling of the capacitor device according to the size information and technological process of the capacitor device, and determining a simulation model of the capacitor device; performing test design on the simulation model according to influence factors in the manufacturing process of the capacitor, acquiring field intensity distribution of the simulation model by applying a voltage signal to the simulation model in each test design scene, comparing the field intensity distribution with breakdown field intensity, and determining a predicted breakdown voltage value; and applying a voltage signal to the capacitor device to determine an actual breakdown voltage value, and adjusting the influence factors according to a comparison result of the predicted breakdown voltage value and the actual breakdown voltage value to obtain a breakdown voltage prediction model of the capacitor device. According to the embodiment of the invention, the problem that the breakdown voltage of the capacitor cannot be effectively predicted in the prior art is solved.

The invention relates to the technical field of MOS semiconductors, and discloses a SiC MOSFET structure with a second-order oxide layer and a preparation technology thereof.The SiC MOSFET structure comprises a plurality of MOS cells arranged in parallel, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a grid electrode, a source electrode and a grid oxide layer, each semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, a P well layer and an N well layer, an N-doped layer is formed in the N drift layer of the single MOS cell through ion implantation, and the N-doped layer is located under the grid electrode; and a plurality of N + doped isolation layers which are not in contact with each other are formed in the N-doped layer through ion implantation. By introducing the N-doped layer right below the grid electrode and the doped N + isolation layers arranged and distributed in the N-doped layer, the distribution of an electric field below the gate oxide is effectively modulated, and the peak of the electric field is inhibited, so that the breakdown voltage of the device is remarkably improved, the reliability of the gate oxide layer is enhanced, and meanwhile, relatively low specific on-resistance is kept.

The present disclosure relates to a bulk acoustic wave (BAW) device with electrostatic discharge (ESD) protection. The disclosed BAW device includes a substrate (106), an ESD protection layer (106) over the substrate (106), a first bottom reflector (109-1) over the ESD protection layer (108), a first bottom electrode (112-1) over the first bottom reflector (109-1), a first top electrode (118-1) vertically aligned with the first bottom electrode (112-1), and a piezoelectric layer (116C) vertically between the first bottom electrode (112-1) and the first top electrode (118-1). Herein, the ESD protection layer (108) is electrically insulating and eligible to achieve at least a 400 V breakdown voltage with a 200 nm thickness. The first bottom reflector (109-1) includes a stack of alternating high acoustic impedance conductive layers (120A-E) and low acoustic impedance conductive layers (120A-E). The first bottom electrode (112-1) is electrically connected to the first bottom reflector (109-1). A breakdown voltage of the piezoelectric layer (116C) is no more than the breakdown voltage of the ESD protection layer (108).

The invention provides an anti-radiation high-performance enhanced gallium nitride-based power device and a manufacturing method thereof, and belongs to the technical field of semiconductors. On the basis of a traditional enhanced P-GaN HEMT device structure, a P-type InaGa1-aN back barrier layer, an InbGa1-bN / GaN superlattice layer, a composite gate structure composed of a dielectric layer and a gate Schottky metal layer and a gradient-changing island-shaped P-GaN layer are innovatively introduced, and a pair of composite problems of dynamic resistance instability and radiation sensitivity are cooperatively solved. The device not only maintains the normally-off characteristic and the high threshold voltage of an enhanced device, but also remarkably improves the anti-irradiation capability, the breakdown voltage and the dynamic resistance stability, and is particularly suitable for power electronics in strong irradiation environments such as aerospace and nuclear energy detection.

The present disclosure relates to Gallium Nitride (GaN) High Electron Mobility Transistor (HEMT) (100) i.e. a semiconductor device (100) which includes a buffer layer (104) formed on the substrate (120). An unintentionally doped (UID) Gallium Nitride (GaN) channel layer (102) is positioned on the buffer layer (104). A barrier layer (106) is formed on the UID channel layer (102) to enable formation of two-dimensional electron gas (2DEG) at interface between UID GaN channel layer (102) and barrier layer (106). A stress transfer layer (116) having tunable intrinsic compressive mechanical stress is deposited on barrier layer (106) to enhance device performance and reliability. Further, the intrinsic stress in the stress transfer layer (116) is tailored to enhance performance in terms of higher threshold voltage and breakdown voltage, and reliability in terms of reduced dynamic RON under DC and switching stress and stable threshold voltage under ON and OFF state gate stress.

The utility model discloses a power supply input surge protection and isolation device, which comprises a piezoresistor, a surge decoupling power resistor and a TVS (Transient Voltage Suppressor) tube which are sequentially connected in series, and a self-adaptive surge control circuit which is connected with the surge decoupling power resistor in parallel, when surge overvoltage occurs, the TVS tube is firstly broken down, and transient large current flows through the adaptive surge control circuit; the surge decoupling power resistor is used for enabling the passing surge current to generate relatively large voltage drop after the TVS tube is broken down; the self-adaptive surge control circuit comprises a first MOS tube which is used for conducting transient large current passing through a TVS (Transient Voltage Suppressor) tube; when the voltage drop on the MOS tube is greater than the breakdown voltage of the voltage-regulator tube, the voltage-regulator tube is broken down to trigger the conduction of the triode; when the voltage-regulator tube is broken down, the triode is conducted, so that the GS voltage drop of the first MOS tube is reduced, and the first MOS tube is turned off; when the sum of the clamping voltage of the TVS tube end and the voltage drop of the surge decoupling power resistor exceeds the minimum action voltage of the piezoresistor, the piezoresistor acts, so that high-energy transient interference flows through the piezoresistor, and surge protection is realized. According to the utility model, the surge protection and isolation protection functions of the input end of the power supply can be effectively realized, and the safety and stability of the use of the power supply are ensured.

The invention discloses a ceramic substrate testing device capable of preventing broken contact, and relates to the technical field of insulation and voltage resistance detection of ceramic substrates, the ceramic substrate testing device capable of preventing broken contact comprises a rack, a master control system and PID thermal control equipment, the rack is provided with a detection table, the rack is provided with a push-pull positioning clamp, and the push-pull positioning clamp is connected with the master control system. A sealing cover is installed on the push-pull positioning clamp, an upper electrode assembly is arranged at the lower end of the push-pull positioning clamp, a lower electrode assembly and a heating module are arranged on the detection table, the ceramic substrate is placed on the detection table, the push-pull positioning clamp pushes the upper electrode assembly and the sealing cover to move downwards, and the heating module is started to heat the ceramic substrate. The upper electrode assembly and the lower electrode assembly are matched to apply high voltage to the substrate and monitor leakage current and breakdown voltage conditions in real time, so that the insulation and voltage resistance of the copper-clad ceramic substrate can be accurately evaluated under a high-temperature condition, and an insulation reliability test under an electric-thermal coupling condition can be realized; and the reliability and repeatability of the test are obviously improved.

The invention relates to an endoscope, a pressure resistance testing method of the endoscope and an endoscopic system. The endoscope comprises an endoscope shell, a signal interface module, a camera module, a traction steel wire and a lightning protection tube, wherein the camera module is connected with the signal interface module through a transmission signal line; one end of the traction steel wire is connected with a metal structure on the camera module, and the other end is connected with the lightning protection tube; the lightning protection tube and the camera module are arranged in the accommodating space; and the lightning protection tube and the signal interface module are common-grounded. According to the endoscope with the structure, static electricity can be released through the transmission signal line and the traction steel wire under the condition that the static electricity is accumulated to the breakdown voltage of the lightning protection tube, so that the static electricity protection capability of the endoscope is improved by utilizing a limited accommodating space, and meanwhile, the voltage resistance of an insulating material of the endoscope cannot be reduced.

The invention provides a high-voltage-resistant gallium oxide trench junction barrier Schottky diode. The high-voltage-resistant gallium oxide trench junction barrier Schottky diode comprises a cathode metal layer, a high-doping N-type gallium oxide substrate, a low-doping N-type gallium oxide epitaxial layer, an etching table top first dielectric layer, an etching table top second dielectric layer, a P-type nickel oxide layer, a dielectric layer and an anode metal layer which are sequentially stacked from bottom to top. According to the invention, P-type nickel oxide and gallium oxide are introduced to construct a heterostructure into a JBS structure, the JBS structure is combined with the etched trench to form a trench junction barrier Schottky diode, and the device has lower specific on-resistance, can bear higher reverse breakdown voltage, and is a gallium oxide JBS device with excellent performance.

The invention discloses a pit filling type current collector transfer welding structure and a conductive insulating coating process thereof, and relates to the technical field of lithium battery manufacturing. The current collector transfer welding structure comprises a polymer film base material, metal layers on the two sides of the polymer film base material, periodic pits formed in the surfaces of the metal layers through ultrasonic roll welding, conductive adhesive filled in the periodic pits and insulating adhesive covering the surfaces of the conductive adhesive and the metal layers from inside to outside. A functional coating containing fluorinated polyurethane-epoxy hybrid resin, an intelligent anti-corrosion microcapsule and a flame-retardant component can be selectively introduced between the conductive adhesive and the insulating adhesive; and a roll welding-micro spraying-UV-thermal gradient curing process is adopted for preparation. After the structure is applied, the volume resistivity of the pit area is low, the resistance of a welding loop is reduced, the breakdown voltage of the insulation paste is greater than or equal to 5kV, and the safety and the reliability of the power battery are remarkably improved.

The invention provides a silicon substrate gallium nitride power semiconductor device and a preparation method thereof, and relates to the technical field of semiconductors. The device comprises a first silicon substrate layer, a second substrate layer, a substrate electrode and a gallium nitride device layer, the second substrate layer comprises a laminated structure which is periodically arranged; the laminated structure sequentially comprises a substrate functional layer and a second silicon substrate layer from bottom to top; wherein the first silicon substrate layer and the second silicon substrate layer adopt a first type of doping, and the substrate functional layer adopts a second type of doping, so that a bipolar doped substrate structure is formed. Based on this, when the silicon substrate gallium nitride power semiconductor device is in a high-voltage reverse bias state, at least one PN junction in the bipolar doped substrate structure can be in a reverse bias state due to the potential difference between the lower substrate electrode and the drain electrode of the silicon substrate gallium nitride power semiconductor device; and the breakdown voltage of the silicon substrate gallium nitride power semiconductor device in the vertical direction is further improved.

An electrostatic discharge protection circuit includes an NMOS transistor connected to a supply voltage pin through a first node and connected to a ground pin through a second node, an RC circuit connected in parallel with the NMOS transistor and including a capacitor and a resistor, and a clamping circuit connected in parallel with the resistor of the RC circuit and including a plurality of diodes; and a switch connecting the clamping circuit to a gate node of the NMOS transistor, wherein a number of the plurality of diodes is set based on a breakdown voltage and an operating voltage of an internal circuit to be protected by the ESD protection circuit, and the switch includes a PMOS transistor connecting the gate node of the NMOS transistor to the clamping circuit and a sub-RC circuit connected in parallel with the PMOS transistor and including a sub-capacitor and a sub-resistor.