10330 results about "Semiconductor technology" patented technology

The invention provides a wafer factory-level real-time scheduling method in semiconductor manufacturing based on deep reinforcement learning, which relates to the technical field of semiconductors, and comprises the following steps: constructing a state space vector by collecting equipment state, batch information and process flow information based on deep reinforcement learning, inputting a pre-trained deep reinforcement learning network model, and constructing a state space vector; the model includes a value assessment network and a policy network. The model generates matching probability distribution of batches and devices, a hierarchical reinforcement learning method is adopted to decompose the distribution into two sub-tasks of batch selection and device allocation, and a plurality of candidate matching schemes are generated. And then evaluating the candidate schemes by applying a multi-target reward and punishment function, selecting an optimal scheduling scheme in combination with a Monte Carlo tree search algorithm, and issuing a processing instruction. And real-time processing data is collected in the working procedure processing process to update the state space vector, so that real-time scheduling is realized.

The invention relates to the technical field of MOS semiconductors, and discloses a variably doped planar gate silicon carbide VDMOS device and a preparation process thereof, the variably doped planar gate silicon carbide VDMOS device comprises a plurality of MOS cells which are parallel to each other, and each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of a single MOS cell; lateral symmetric P-layers are arranged in the single MOS cell and located on the left side and the right side of the N drift layer, and the section contours of the corresponding sides of the lateral symmetric P-layers on the two sides are in an arc shape. By arranging the lightly doped N layer in the middle of the N drift layer and introducing the arc-shaped laterally-symmetrical P-layers to the two sides, the electric field distribution of the device is optimized, the local electric field concentration is reduced, the breakdown voltage is remarkably improved, and the charge balance capability is enhanced and the leakage current is reduced through the contact between the laterally-symmetrical P-layers and the N substrate layer.

The invention relates to the technical field of semiconductors, and discloses a full-temperature-zone polynomial digital temperature compensation method and system based on an SOI chip, and the method comprises the steps: obtaining the temperature frequency data of a preset temperature zone of a target SOI chip, fitting a full-temperature-zone curve, extracting a critical point of the temperature zone, dividing a segmented compensation interval according to the critical point, and obtaining the temperature frequency data of the preset temperature zone of the target SOI chip; the method comprises the following steps: calculating frequency drift amounts under different voltages to construct a full-automatic test framework, acquiring an environment temperature parameter and an instantaneous temperature value by using the framework, analyzing a temperature compensation vector of a segmented compensation interval, further monitoring a signal frequency interval output by a chip, extracting a phase noise parameter, calculating a frequency offset error amount with a preset value, and calculating the frequency offset error amount. And analyzing an error source, optimizing a polynomial compensation order, and collecting temperature drift suppression data to generate a full temperature region compensation report. According to the invention, the performance stability of the chip in a complex environment can be improved.

The invention relates to the technical field of semiconductors, and particularly discloses a multiband LED chip and a preparation method thereof, and a white light LED light source, the LED chip comprises a light-emitting layer, and the light-emitting layer comprises a first cyan light multi-quantum well layer, a second long-wave blue light multi-quantum well layer, a third short-wave blue light multi-quantum well layer and a fourth purple light multi-quantum well layer which are sequentially stacked in the epitaxial direction; the first cyan light multi-quantum well layer, the second long-wave blue light multi-quantum well layer, the third short-wave blue light multi-quantum well layer and the fourth purple light multi-quantum well layer are each of a periodic structure formed by alternately stacking well layers and barrier layers, and the light-emitting wavelengths of the first cyan light multi-quantum well layer, the second long-wave blue light multi-quantum well layer, the third short-wave blue light multi-quantum well layer and the fourth purple light multi-quantum well layer are sequentially decreased. And the forbidden band widths of the barrier layers are sequentially decreased. According to the LED chip, the overall excitation efficiency can be effectively improved, and the output full-spectrum white light LED light source is higher in color rendering index, better in stability, less in damage to human eyes and high in light emitting efficiency.

The invention relates to the technical field of sensors, and provides a six-dimensional force sensor based on a planar semiconductor process and a preparation method thereof, and the six-dimensional force sensor comprises a central bearing platform, a housing, an elastic beam and a buffer beam. One end of the elastic beam is connected to the center bearing table, the other end of the elastic beam is connected to the buffer beam, the buffer beam and the elastic beam are orthogonally arranged, and the end, away from the elastic beam, of the buffer beam is connected to the shell. Wherein the surfaces of the elastic beam and the buffer beam are provided with six groups of strain gauges, and the six groups of strain gauges are respectively used for measuring forces in three directions and moments in three directions. According to the method, the multi-load-step-based least square method linear matrix decoupling is adopted, so that the inter-dimensional coupling error of the six-dimensional force sensor is reduced to below 2%. According to the invention, the six-dimensional force sensor is prepared by adopting a planar semiconductor process, the difficulties of side surface attachment and side wall lead binding of the strain gauges are avoided, and the six-dimensional force sensor has the advantages of simple process, low manufacturing cost and small crosstalk error.

The invention provides a third-generation semiconductor device multi-physical field coupling effect dynamic monitoring method and system, and relates to the technical field of semiconductors, and the method comprises the steps: collecting the data of a temperature field, an electric field, a magnetic field and a stress field through a complementary sensor array, constructing a feature tensor, inputting the feature tensor into a pre-trained graph neural network, and extracting a coupling effect dynamic evolution rule; on-line analysis and prediction are carried out by using an adaptive time window and a recurrent neural network, a multi-field coupling correlation degree evaluation model is established, an early warning level is determined according to the deviation between the coupling correlation degree and an early warning threshold value, and device risk evaluation and maintenance suggestions are generated, so that early warning of the failure risk of the semiconductor device is realized.

The embodiment of the invention provides a differential Hall current sensor and a manufacturing method thereof, and belongs to the technical field of semiconductors. The differential Hall current sensor comprises a current bar; the insulating layer is bonded on the upper surface of the current bar; the at least two Hall elements are symmetrically arranged on the two sides of the upper surface of the insulating layer in the current direction; and the at least one deflection magnetism gathering block is attached to the magnetic induction surfaces of the at least two Hall elements and is used for deflecting a magnetic field component of the current magnetic field in the direction parallel to the magnetic induction surfaces of the Hall elements into a magnetic field component in the direction perpendicular to the magnetic induction surfaces of the Hall elements. According to the differential Hall current sensor, the current magnetic field is gathered through the deflection magnetism gathering block to form a conduction magnetic circuit, the directions of the magnetic field components are changed, the Hall element obtains the magnetic field intensity formed by superposing the magnetic field components in the two directions, and the measurement sensitivity is improved.

The invention relates to the technical field of MOS semiconductors, and discloses a silicon carbide thick-bottom oxide layer groove MOS structure and a preparation method thereof, the silicon carbide thick-bottom oxide layer groove MOS structure comprises a plurality of parallel MOS cells, and each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of each MOS cell; the lightly doped N layer is arranged in the middle of the N drift layer, the arc-shaped contour design with the inclined top is introduced to the two sides, the injection area is accurately controlled through the photoetching technology, the phenomenon that the edge electric field concentration of the N drift layer is effectively dispersed is effectively dispersed, in this way, electric field distribution is more uniform, breakdown voltage is improved, and local electric field concentration is reduced; moreover, the contact between the laterally symmetrical P-layer and the N substrate layer enhances the charge balance capability, and reduces the leakage current.

The invention provides a semiconductor manufacturing machine control method and system, and relates to the technical field of semiconductors, and the method comprises the steps: obtaining the operation parameters of an equipment cavity, and building a multi-objective optimization model containing the manufacturing cost, the manufacturing quality and the manufacturing efficiency. And training the model by adopting a deep reinforcement learning algorithm to generate an optimized prediction result. And performing deviation analysis on the prediction result and the target parameter, and inputting a deviation feature vector into a compensation amount calculation model constructed based on a long short-term memory network to generate a compensation control instruction. And inputting the compensation instruction into the multi-objective optimization model, calculating an optimal parameter combination by adopting a multi-objective optimization algorithm of dynamic weight distribution, and generating a parameter adjustment instruction. And finally, the adjustment instruction is sent to the execution unit, and self-adaptive feedback regulation and control in the semiconductor manufacturing process are realized, so that the manufacturing cost is reduced, and the manufacturing quality and the manufacturing efficiency are improved.

The invention discloses a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with a high-mobility gate oxide layer and a preparation process of the SiC MOSFET device, and belongs to the technical field of semiconductors. Comprising a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of each MOS cell; by optimizing the gate oxide layer preparation process and combining the design of the T-shaped P-layer, the semi-elliptical lightly doped N-type half layer and the like in the device, the interface quality of the gate oxide layer and a semiconductor material is effectively improved, the scattering of a carrier by an interface state is reduced, and meanwhile, due to the synergistic effect of the structures such as the quarter-circle-shaped side symmetric P-layer and the square heavily doped N layer, the performance of the device is improved. The internal electric field distribution and the carrier transmission path of the device are optimized, and the channel carrier mobility is remarkably improved.

The invention relates to the technical field of MOS semiconductors, and discloses a silicon carbide plane MOS device polysilicon gate self-alignment process and a low resistance structure, the silicon carbide plane MOS device polysilicon gate self-alignment process comprises a plurality of parallel MOS cells, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, an N well layer, a P + layer and a P well layer, and the N drift layer comprises a drain electrode, a source electrode and a grid electrode. The height of the P well layer in the single MOS cell is aligned with that of the grid electrode, and the P well layer is located on the left side and the right side of the grid electrode; the N well layer and the P + layer are both located above the grid electrode and the P well layer, and the P + layer is located on the outer side of the N well layer. According to the invention, the height of the P well layer is accurately aligned with the grid electrode, the P well layer is arranged at the two sides of the grid electrode, the design of the T-shaped source electrode is combined, the conduction path is optimized, and when the voltage is applied to the grid electrode, vertical channels are formed at the two sides of the P well layer, so that the path of current flowing from the drain electrode to the source electrode through the N drift layer is shorter and the distribution is uniform.

The invention discloses an irradiation-reinforced SiC super-junction MOS (Metal Oxide Semiconductor) structure and a preparation process thereof, and belongs to the technical field of MOS semiconductors. Comprising a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer; by arranging the lightly doped N layer in the middle of the N drift layer and arranging the laterally symmetrical trapezoidal P-layers on the two sides of the N drift layer, the device can interact with electrons in the N drift layer, accelerate carrier recombination, reduce the influence of redundant carriers on the performance of the device, effectively reduce the performance degradation caused by irradiation, and improve the performance of the device. According to the invention, the concave heavily-doped N layer is formed at the bottom end of the lightly-doped N layer, so that the carrier concentration of the region can be greatly improved, and the conductivity is remarkably enhanced.

The invention discloses a light-emitting diode epitaxial wafer, a preparation method thereof and a light-emitting diode, and relates to the technical field of semiconductors. The light-emitting diode epitaxial wafer comprises a substrate, a buffer layer, an N-type semiconductor layer, a low-temperature stress release layer, a multi-quantum well light-emitting layer, an electron blocking layer and a P-type semiconductor layer. The multi-quantum well light-emitting layer comprises a first sub-layer, a second sub-layer, a third sub-layer and a fourth sub-layer which are stacked in sequence, and each of the first sub-layer, the second sub-layer, the third sub-layer and the fourth sub-layer comprises an InGaN quantum well layer and a GaN quantum barrier layer which are periodically and alternately stacked; an electron injection layer is inserted into at least one of the GaN quantum barrier layer of the first sub-layer, the GaN quantum barrier layer of the second sub-layer and the GaN quantum barrier layer of the third sub-layer; and a hole injection layer is inserted into the GaN quantum barrier layer of the fourth sub-layer. By implementing the invention, the electron hole matching degree of the multi-quantum well light-emitting layer can be improved, so that the luminous efficiency of the light-emitting diode is improved.

The invention belongs to the technical field of semiconductors, and discloses a SiC power semiconductor module with low parasitic parameters and a preparation method. Comprising a SiC power semiconductor chip, a SiC power semiconductor chip substrate cushion block, a positive electrode power terminal, a negative electrode power terminal, an output power terminal, a positive electrode side middle layer cushion block, a positive electrode side ceramic decoupling capacitor, a positive electrode side substrate middle layer cushion block, a negative electrode side middle layer cushion block, a negative electrode side ceramic decoupling capacitor and a negative electrode side substrate middle layer cushion block. A first copper-clad ceramic substrate, a third copper-clad ceramic substrate, a fourth copper-clad ceramic substrate, a second copper-clad ceramic substrate, a first commutation loop middle copper layer and a second commutation loop middle copper layer; according to the invention, a commutation path is provided for the SiC power semiconductor device by using the middle layer copper of the laminated copper-clad ceramic substrate, the concept of mutual inductance offset of double commutation loops is innovatively introduced, and the parasitic inductance of the module is further reduced.

The invention discloses a manufacturing method of a groove, a semiconductor device and a manufacturing method of the semiconductor device, and relates to the technical field of semiconductors, and the manufacturing method comprises the steps: providing a substrate, forming a first mask layer on the substrate, and etching the first mask layer by taking a photomask as a mask, so that the first mask layer covers the substrate of a first groove region, forming a second mask layer on the substrate, etching the second mask layer to enable the second mask layer to expose the first mask layer and the substrate in the second groove region, etching the substrate in the second groove region by taking the first mask layer and the second mask layer as masks to form a relatively shallow second groove, and etching the first mask layer to form a relatively shallow second groove; according to the method, the substrate of the first trench region and the substrate of the second trench region are exposed by the second mask layer, and the substrate of the first trench region and the substrate of the second trench region are etched by taking the second mask layer as a mask to form a deeper second trench and a shallower first trench, so that a shallow trench and a deep trench can be manufactured by adopting one photomask, and the manufacturing cost can be further reduced.

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a double-gate structure for a high-performance MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and an optimization method, the double-gate structure comprises a plurality of MOS cells, and each MOS cell comprises a drain electrode, a source electrode, a gate electrode, a gate oxide layer and a semiconductor epitaxial layer; the semiconductor epitaxial layer comprises an N substrate layer, an N diffusion layer, a P-layer, a P well layer and an N well layer, two grid electrodes are arranged in a single MOS cell and are respectively positioned on the left side and the right side in a grid oxide layer, and the section outline of the grid oxide layer is semicircular; polycrystalline silicon is arranged in the gate oxide layer and located between the two grid electrodes, and the polycrystalline silicon is in ohmic contact with the source electrode. Through the double-gate structure, geometric shape optimization, doping layer design and process innovation, the switching speed, the voltage endurance capability, the thermal stability and the integration degree of the MOSFET are remarkably improved, meanwhile, the leakage current and the on-resistance are reduced, and the MOSFET is suitable for high-performance power devices and high-frequency application scenes.

The embodiment of the invention provides a differential Hall current sensor and a manufacturing method thereof, and belongs to the technical field of semiconductors. The differential Hall current sensor includes: a substrate; the magnet yoke is provided with a semi-enclosed structure formed by a bottom surface and two side surfaces positioned on the same side of the bottom surface, and the bottom surface is bonded on the substrate; the current bar is placed in the cavity of the semi-surrounding structure and allows two end parts of the current bar to extend out of the semi-surrounding structure; the insulating layer is arranged on the upper surface of the current bar and located in the cavity; the at least two Hall elements are symmetrically arranged on the two sides of the upper surface of the insulating layer in the current direction; the at least two groups of magnetism gathering blocks are attached to the magnetic induction surfaces of the at least two Hall elements; at least two groups of magnetism gathering blocks and the magnet yoke form a conducting magnetic circuit, and the magnetic field component of the current magnetic field in the parallel direction of the magnetic induction surface is deflected into the magnetic field component in the vertical direction. According to the differential Hall current sensor, the Hall perceptible magnetic field intensity is enhanced through the conduction magnetic circuit of the gathered current magnetic field, and the measurement sensitivity is improved.

The invention relates to the technical field of semiconductors, in particular to a preparation method of a graphite piece containing a tantalum carbide coating, which at least comprises the following steps: preparing a slurry suspension containing a tantalum source, a carbon source, a sintering agent, a dispersing agent and an adhesive; coating the surface of a graphite piece with the slurry suspension, and drying to form a pre-coating layer; the pre-coating layer is subjected to high-temperature sintering, the tantalum carbide coating layer is formed after natural cooling, the grain size of the tantalum carbide coating layer is 30-90 microns, the tantalum carbide coating layer graphite piece which is high in bonding strength, large in grain size and of a porous structure is obtained through slurry suspension preparation, graphite coating and high-temperature sintering, operation is easy, the production cost is low, and the actual application requirement is better met.

The invention belongs to the technical field of semiconductors, and particularly relates to a gradient transition composite tantalum carbide coating and a preparation method thereof.The gradient transition composite tantalum carbide coating is located on the surface of a graphite substrate material and sequentially comprises a pyrolytic carbon coating, a tantalum carbide-pyrolytic carbon composite coating and a tantalum carbide coating from inside to outside; wherein the thermal expansion coefficient of the pyrolytic carbon coating is 2.5-4.5 * 10 <-6 > / K, the thermal expansion coefficient of the composite coating is 4.5-6.0 * 10 <-6 > / K, and the thermal expansion coefficient of the tantalum carbide coating is 6.1-8.0 * 10 <-6 > / K. According to the gradient transition structure of the coating, the problem that thermal expansion coefficients between the coating and a base body are not matched is solved, the thermal shock resistance of the coating is effectively improved, meanwhile, the pinning effect can be achieved, the adhesive force between the coatings is enhanced, and the service life of a product is prolonged; compared with a single tantalum carbide coating, crack accumulation and through holes cannot be generated.

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a semiconductor device with an integrated heat dissipation function for a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The single MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, the profile of the cross section of the grid electrode is in an H shape, and the grid electrode comprises two longitudinal parts and a transverse part used for bridging the two longitudinal parts. According to the invention, the H-shaped gate structure is in bridge connection with the double longitudinal grooves through the transverse part, so that the channel width is increased, and the on-resistance is reduced; a current path is further optimized by combining a metal deposition layer and a heavily doped N + layer in the bottom doping layer; and the metal layer is connected in parallel to conduct electricity, so that the resistance is reduced, and the heavily doped N + layer inhibits the JFET effect, so that the resistance is reduced by more than 10%.

The embodiment of the invention relates to the technical field of semiconductors, and discloses a data management method, system and device for semiconductor process formula parameters and a medium, and the method comprises the steps: carrying out the data analysis of a collected process formula of one or more data formats, converting the data into a target data format, and storing the data in a database; and in response to a data request transmitted through the data interface, returning the corresponding process formula data in the database through the data interface in a data request format based on the configured mapping relationship. Through the scheme of the invention, standardized semiconductor process formula parameter related data can be provided and output to other systems in a standard data structure, and at least the technical problems of low efficiency of checking different equipment parameters, low production management efficiency, frequent errors, high management cost and the like in the prior art are solved.

The invention belongs to the technical field of semiconductors, and particularly discloses a photoetching hot spot detection method and system based on a graph neural network. The method comprises the following steps: decomposing each polygonal metal in a layout into rectangles by scanning in the horizontal direction, and taking the rectangles as nodes of the layout; adding an internal edge and an external edge between the rectangles according to a specific rule; the diagonal vertex coordinates of the rectangles are used as node features, the minimum distance between the rectangles represents edge features, and graph representation of the layout is completed; inputting the graph representation of the layout into a message passing layer of a GNN model to perform graph feature extraction, and performing global maximum pooling and global average pooling on each dimension of all node features to obtain global graph representation; and classifying the global graph representation into hotspots and non-hotspots. According to the invention, the accuracy and calculation efficiency of layout hot spot detection can be improved.

The invention relates to the technical field of MOS semiconductors, and discloses a low-groove high-power MOS device which comprises a plurality of MOS cells which are arranged in parallel, and each MOS cell comprises a metal source electrode, a grid electrode, a semiconductor epitaxial layer and a drain electrode; wherein the semiconductor epitaxial layer comprises a substrate layer, a diffusion layer, a P well layer and an N well layer; the N-well layer comprises a heavily doped N-well layer I and a lightly doped N-well layer II; the P well layer comprises a heavily doped P well layer I, a heavily doped P well layer II, a heavily doped P well layer III, a lightly doped P well layer I and a lightly doped P well layer II. According to the invention, the lightly-doped P-well layers are arranged at the left and right lower corners of the gate, so that the phenomenon that the lightly-doped P-well layers and the gate oxide layer are punctured together in the background is avoided, and the stable use of the MOS device in high-power equipment is realized.

The invention relates to the technical field of semiconductors, particularly provides an IGBT and silicon carbide MOSFET hybrid parallel power module, a motor controller and a vehicle, and aims to solve the problems of high cost and low yield of a power module manufactured by a full silicon carbide MOSFET chip. In order to achieve the purpose, the IGBT and silicon carbide MOSFET hybrid parallel power module comprises a mounting base, semiconductor modules distributed in an array mode are arranged on the mounting base, each semiconductor module comprises an upper bridge arm mechanism, a lower bridge arm mechanism and a substrate, and the upper bridge arm mechanisms and the lower bridge arm mechanisms are connected in series to form a half-bridge structure; the upper bridge arm mechanism comprises an IGBT chipset, a silicon carbide MOSFET chipset and an upper bridge gate signal terminal; a gate of the silicon carbide MOSFET chip of the upper bridge arm mechanism and a gate of the IGBT chip are connected with the upper bridge gate signal terminal; the lower bridge arm mechanism comprises an IGBT chip set, a silicon carbide MOSFET chip set and a lower bridge grid signal terminal. A grid of the silicon carbide MOSFET chip of the lower bridge arm mechanism and a grid of the IGBT chip are connected with the lower bridge grid signal terminal.

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses a VDMOSFET (vertical double-diffused metal oxide semiconductor field effect transistor) device with low threshold voltage, which comprises a drain electrode, a semiconductor epitaxial layer, a source electrode, a grid electrode and a grid oxide layer covering the surface of the grid electrode, and is characterized in that an N substrate layer, an N drift layer, an N well layer, a P well layer and a heavily doped P layer are formed in the semiconductor epitaxial layer through ion implantation, the grid electrode comprises a triangular grid electrode and a rectangular grid electrode, the grid oxide layer covering the surface of the triangular grid electrode is in contact with the N substrate layer, and the N drift layer is divided into a left part and a right part by the grid oxide layer. According to the invention, the grid electrode is designed to further comprise the triangular grid electrode, the electric field effect of the grid electrode between the tip part of the triangular grid electrode and the drain electrode is better, but the grid oxide layer wrapped by the triangular grid electrode at the tip part is thicker, so that charges flowing out of the drain electrode gather towards the inside of the heavily doped N layer more quickly along the grid oxide layer; at the moment, more charge flow can be provided in a smaller grid voltage environment.

A method for incorporating tempering hollow structures (22) into a substrate (12) of a mirror (10) for an EUV projection exposure system is described, comprising the following steps: (A) providing a substrate (12) consisting of a substrate material 12a; (B) successively focusing a processing light beam (46) onto processing sites (54) where tempering hollow structures (22) are to be formed, such that the substrate material 12a is removed at the processing sites (54), leaving adjacent modified substrate material (58) that has an increased susceptibility to etching relative to the substrate material 12a; (C) applying a rinsing fluid (82; 82.1) to the processing sites (54) while step (B) is carried out, thereby rinsing away the removed substrate material.In step (D), the processing locations (54) are treated with an etching medium (80) while step (B) is carried out, whereby the etching medium (80) exerts an etching effect at the processing locations (54) and any modified substrate material (58) present there is removed by an etching process. A processing system (40) for carrying out the process, as well as a method and a substrate (12) for producing an optical element (8) and an optical element (8) are also specified. Furthermore, a semiconductor technology system (6) and a structured electronic component (224) are specified.

The invention relates to the technical field of semiconductors, and discloses a glass-based three-dimensional interconnection structure and a packaging framework based on the glass-based three-dimensional interconnection structure, the glass-based three-dimensional interconnection structure comprises a glass plate core, two opposite sides of the glass plate core are respectively a first surface and a second surface; the front rewiring layer is arranged on the first surface; the back rewiring layer is arranged on the second surface; the glass through hole penetrates through the glass plate core, and a base metal interconnection layer is filled in the glass through hole; the base metal interconnection layer extends to the first surface and is electrically connected with the front rewiring layer; and the base metal interconnection layer extends to the second surface and is electrically connected with the back rewiring layer. According to the technical scheme provided by the invention, the technical effects of vertical integration capability, thermal management efficiency, electromagnetic performance and the like can be remarkably improved in a high-frequency and high-integration scene.

The invention provides a wafer testing device capable of being rapidly maintained, and relates to the technical field of semiconductors, the wafer testing device comprises a fixed plate, the fixed plate is provided with a control module, and a power supply module, a probe card, a heating lifting module and at least one testing module which are connected with the control module, and a wafer to be tested is integrally arranged in the probe card. The power supply module is connected with the probe card to supply power to the to-be-tested wafer, a heater and a probe are arranged in the heating lifting module, and the heating lifting module is used for driving the to-be-tested wafer in the probe card to be in contact with the probe and heating the to-be-tested wafer. The test module comprises a bottom plate which is in push-pull connection with the fixed plate along the first direction and a switch array measurement assembly which is arranged on the bottom plate and is in plug-in connection with the bottom plate along the second direction, and the switch array measurement assembly is used for testing different parameters of the to-be-tested wafer when the to-be-tested wafer is in contact with the probe. The switch array measurement assembly is in plug-in connection with the bottom plate, and the bottom plate is in push-pull connection with the fixed plate, thereby facilitating the replacement of the test module, and achieving the quick disassembly and assembly.

The invention relates to the technical field of semiconductors, in particular to a shield gate groove type power device and a preparation method thereof. The method comprises the following steps: preparing a semiconductor wafer to be processed; performing grid polycrystalline silicon deposition on the upper surface of the epitaxial layer of the semiconductor wafer and the groove structure, so that a groove is formed above the groove structure; etching the grid polycrystalline silicon in the groove until the grid polycrystalline silicon reaches the oxide layer above the source polycrystalline silicon to form two sub-grids, and forming an inter-grid groove between the two sub-grids; performing planarization processing on the grid polycrystalline silicon until the oxide layer on the surface of the epitaxial layer is exposed; forming an oxide film dielectric layer which covers the oxide layer covering the upper surface of the epitaxial layer and the grid polycrystalline silicon; and performing planarization processing on the oxide film dielectric layer to obtain a flat surface of the oxide film dielectric layer. According to the shield gate trench type power device and the preparation method thereof provided by the invention, the gate-source overlapping area can be adjusted, the gate-source capacitance is reduced, and the freedom degree of device preparation is increased.

The invention relates to the technical field of MOS semiconductors, and discloses a heterojunction-based silicon carbide groove type MOSFET device structure and a preparation process thereof.The heterojunction-based silicon carbide groove type MOSFET device structure comprises a plurality of parallel MOS cells, each MOS cell comprises a drain electrode, a source electrode, a grid electrode and a semiconductor epitaxial layer, and each semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer; a groove is formed in the upper surface of the single MOS cell and located below the grid electrode, an N + layer is deposited in the groove, and the N + layer comprises a left N + layer and a right N + layer. Through the design of the split type left N + layer and the right N + layer in the groove and the combination of the middle N-layer or the middle P-layer filled in the middle, the electric field concentration phenomenon at the bottom of the groove is effectively dispersed, and the electric field peak value at the edge of the N drift layer is further inhibited in cooperation with the right triangle arrangement of the blocking ion bubbles, so that the breakdown voltage and the reliability of the device are remarkably improved, and the reliability of the device is improved. The method is suitable for high-voltage application scenes.