4067 results about "Semiconductor technology" patented technology

The embodiment of the invention relates to the technical field of semiconductor manufacturing, in particular to a volume calibration method, a controller and a gas mass flow verification system. Obtaining an accurate second volume verification parameter of the calibration tank when the second pipeline space is in a gas stable state, and calculating an accurate and high-precision second volume of the second pipeline space by combining a first volume verification parameter and a first volume of the calibration tank when the fourth valve is in a closed state; a target mole of gas in the calibration tank is diffused to a target pipeline space, an accurate third volume verification parameter of the calibration tank is obtained when the target pipeline space is in a gas stable state, and a third volume verification parameter of the calibration tank is obtained by combining a first volume verification parameter and a first volume of the calibration tank when a fourth valve is in a closed state; the third volume of the third pipeline space is accurate and high in precision, and the requirement of the semiconductor technology for volume precision is met.

The invention belongs to the technical field of semiconductors, and discloses a method for manufacturing a sigma trench in a semiconductor device, which comprises the following steps of: providing a substrate which comprises a first device region and a second device region; a PMOS (P-channel Metal Oxide Semiconductor) region gate and a PMOS gate mask layer are formed on the first active region of the first device region; exposing the top of the PMOS gate mask layer outside the first device region photoresist layer; depositing a deposition silicon oxide layer on the top of the second device region and the top of the PMOS gate mask layer; removing the photoresist layer in the first device region; etching to remove the natural silicon oxide layer on the surface of the first active region, further etching silicon in the first active region, and forming a U-shaped groove in the semiconductor substrate in the first device region; and carrying out TMAH etching on the U-shaped groove to form a sigma groove. According to the invention, in the process of embedding germanium-silicon into the source and the drain, the height difference between the PMOS and the NMOS is avoided, and the subsequent process is not influenced.

The invention relates to the technical field of semiconductors, in particular to an ultrasonic transmitting circuit, a chip and an ultrasonic module. The ultrasonic transmitting circuit comprises a first control circuit and a signal generating circuit. The first control circuit is used for outputting a first control signal; the signal generation circuit is used for outputting a driving signal according to the first control signal; the driving signal is used for driving a first booster circuit to output an excitation signal, and the voltage of the excitation signal is higher than that of the driving signal; the excitation signal is used for exciting the ultrasonic transducer to emit ultrasonic waves. According to the embodiment of the invention, the energy of ultrasonic waves emitted by the ultrasonic transducer can be improved, so that the ultrasonic receiving circuit can receive echoes with higher energy, and the sensitivity and the signal-to-noise ratio of ultrasonic detection are improved.

The invention discloses a rapid thermal simulation method and system for a semiconductor power assembly, and relates to the technical field of semiconductors, and the method comprises the steps: collecting a voltage V (t) signal and a current I (t) signal of the semiconductor power assembly in real time through a voltage and current sampling circuit, constructing a power pulse input sequence A, and carrying out the hot carrier accumulation analysis according to the power fluctuation change amplitude; introducing a transient thermal resistance function Zth (t), fitting the transient thermal resistance function Zth (t) with a hot carrier pulse response index Mcx after numerical integration to analyze junction temperature change caused by power pulse, and evaluating an equivalent junction temperature dynamic change rate; when the analysis result is that the thermal drift out-of-control trend exists, thermal risk analysis is carried out, and thermal risk state assessment is generated; the simulation model optimizes thermal model parameters and outputs thermal control suggestions through a rollback correction path, and the working state of the semiconductor power assembly is automatically adjusted. According to the method, real-time monitoring and effective prevention and control of thermal runaway can be realized, and the reliability and safety of the semiconductor power assembly are improved.

The utility model discloses a wafer processing device, and belongs to the technical field of semiconductors. The wafer processing device comprises a carrying table, a shock insulation pad and an ultrasonic device, wherein the carrying table is used for carrying a crystal ingot with a modified layer; the ultrasonic device is arranged above the carrying table, the ultrasonic device can generate transverse vibration waves, and the transverse vibration waves are used for vibrating along the crystal ingot and enabling cracks of the modified layer to extend in the transverse direction; and the bottom of the carrying table is fixedly arranged on the shock insulation pad. According to the utility model, the cracks of the modified layer formed on the crystal ingot by the laser pulse grow and are connected along the transverse direction, the longitudinal growth of the cracks is avoided, the production efficiency of the modified layer is improved, the laser pulse does not need to be intensively emitted, and the wafer processing period is shortened.

The invention belongs to the pulse power semiconductor technology, and provides a drift step recovery diode with an anode short circuit structure, a cell of the drift step recovery diode comprises an anode structure, a voltage-withstanding layer structure and a cathode structure from top to bottom, and the anode structure is a mixed anode structure comprising a diode anode part, an NPN transistor part and an isolation and insulation part; the diode anode part, the NPN transistor part and the isolation and insulation part are jointly positioned on the voltage-withstanding layer structure; the anode part of the diode comprises a P-type low-doped layer, a P-type anode region and anode metal from bottom to top; the NPN transistor part comprises a P-type base region and an N-type anode region from bottom to top, and then the P-type base region and the N-type anode region form an NPN transistor together with an N-type drift region; the anode metal is located on the upper surfaces of the P-type anode region of the anode part of the diode, the NPN transistor part and the isolation and insulation part and makes contact with the P-type anode region and the N-type anode region at the same time to form a short circuit point, namely, anode short circuit, and better pulse output characteristics and lower process difficulty are achieved.

The invention relates to the technical field of semiconductors, in particular to a source heterojunction contact semiconductor structure and device and a manufacturing method, the semiconductor structure comprises a gate structure, a body region structure, a source structure and a drain structure, and the source structure comprises a polycrystalline silicon source contact layer; the semiconductor structure comprises a body region structure and a polycrystalline silicon source contact layer, the body region structure is surrounded by the gate structure, a source contact region is arranged in the body region structure, the polycrystalline silicon source contact layer is in contact with the source structure through the source contact region so as to form a heterojunction diode with the source structure, and the heterojunction diode is a freewheeling diode of the semiconductor structure. The drain electrode structure is located on one side, back to the gate electrode structure, of the body region structure; the semiconductor structure can be a SiC MOSFET structure, reverse conduction voltage drop during follow current of the SiC MOSFET can be greatly reduced, and conduction loss and loss caused during switching are reduced.

The invention discloses a semiconductor device and a manufacturing method thereof, and electronic equipment, and belongs to the technical field of semiconductors, and the semiconductor device comprises a plurality of layers of storage units which are stacked in the direction perpendicular to a substrate; the memory cell includes: a transistor; the transistor comprises a grid electrode extending in the direction perpendicular to a substrate, a semiconductor layer surrounding the side wall of the grid electrode, and a transition layer surrounding the side wall of the semiconductor layer and making contact with the semiconductor layer. Wherein the transition layer comprises two conductive contact areas which are isolated from each other, and two insulating areas which are positioned between the two conductive contact areas.

Embodiments of the present application provide an electronic device, a manufacturing method thereof and an electronic device, and relate to the technical field of semiconductors. The electronic device can be used for growing nanowires in a plane. The electronic device can include a substrate and at least one nanowire. The substrate has at least one groove. The nanowire is embedded in the groove. The groove has at least one groove wall. The nanowire extends along one groove wall of the groove and is in contact with the groove bottom. The groove wall has a guiding effect, so that the nanowire can grow in the plane of the groove bottom along the extension direction of the groove wall, which is conducive to large-scale manufacturing of the electronic device. The plane of the groove bottom can be parallel to the surface of the circuit board for carrying the electronic device. Therefore, when the nanowire grows in the plane of the groove bottom, it is conducive to large-scale integration of the electronic device on the circuit board.

The invention relates to the technical field of semiconductors, and discloses a wafer defect visual AI detection method, device and equipment and a storage medium, and the method comprises the steps: extracting a single target die image from a complete wafer image, forming a data set original image, carrying out the automatic marking of the data set original image, and generating a wafer defect instance segmentation marking data set. Calling a PyTorch framework to construct an initial deep learning wafer detection model, wherein the initial deep learning wafer detection model uses a Vue framework to realize front-end logic; training the initial deep learning wafer detection model pair according to the wafer defect instance segmentation labeling data set to obtain a trained deep learning wafer detection model, obtaining a to-be-detected wafer, detecting the to-be-detected wafer according to the trained deep learning wafer detection model to obtain wafer defect data corresponding to the to-be-detected wafer, and obtaining the wafer defect data corresponding to the to-be-detected wafer. The detection process is high in automation degree, high in accuracy, good in expansibility and wide in application range.

The invention discloses a method for forming a shallow trench isolation structure, and belongs to the technical field of semiconductors, the method for forming the shallow trench isolation structure comprises the steps of forming a first stop layer on a substrate, etching the first stop layer and a part of the substrate, and forming a trench; an insulating material is deposited in the groove and on the first stop layer, a second stop layer and a sacrificial layer are sequentially deposited on the insulating material, and the insulating material, the second stop layer and the sacrificial layer are provided with recesses in the groove; the sacrificial layer is ground and thinned until the second stop layer is exposed, and part of the sacrificial layer is reserved at the concave position of the second stop layer; and synchronously etching the second stop layer and the sacrificial layer until the second stop layer is completely removed. A stop layer and a sacrificial layer are deposited on an unground insulating material, the height difference of a wafer surface film layer is preliminarily compensated by using a grinding process, and then the residual film layer is synchronously consumed by using an etching process, so that the height difference of the insulating material is reduced, and the difficulty of a CMP (Chemical Mechanical Polishing) process is reduced.

The invention relates to a method. The invention discloses an ATE-based method for batch detection of pseudo soldering and sealing-off of chip packaging bonding, and belongs to the technical field of semiconductors. The method comprises the following steps: aiming at packaged and bonded chips, providing excitation current for each chip to be tested through an ATE test machine, and conducting an ESD (Electro-Static Discharge) diode connected with each pin of the chip; detecting the voltage drop between each pin and the pin GND; and calculating the equivalent resistance to determine whether pseudo soldering or unsoldering exists. The detection method has high practicability, is simple to operate, is very suitable for large-scale application and popularization, and has a certain promotion effect on improvement of a chip packaging test technology, improvement of chip performance reliability and chip packaging inspection.

The invention relates to the technical field of semiconductors, and discloses a preparation method of a heat-conducting polyurethane polishing pad, which comprises the following steps: coupling a silane coupling agent with a hydroxylated inorganic heat-conducting material, and carrying out condensation reaction on silanol groups in the silane coupling agent and hydroxyl groups in the hydroxylated inorganic heat-conducting material to form Si-O-Si covalent bonds; bridging a hydroxylated inorganic heat-conducting material at one end of a silane coupling agent to obtain an intermediate; the intermediate is an inorganic heat-conducting material modified by a silane coupling agent; mixing the polyurethane prepolymer with the intermediate to form a mixed prepolymer, and curing the mixed prepolymer at a first temperature to obtain heat-conducting polyurethane; or curing the polyurethane prepolymer to obtain polyurethane, carrying out melt blending on the polyurethane and the intermediate at a second temperature, and curing at a first temperature to obtain heat-conducting polyurethane, in the heat-conducting polyurethane, polyurethane is bridged at the other end of the silane coupling agent. Compared with the prior art, the heat transfer and heat conduction performance of the polishing pad is effectively improved.

The invention relates to the technical field of semiconductors, in particular to a semiconductor laser and a processing method thereof.The semiconductor laser comprises a mounting frame, a bottom plate, a top plate, an electrode plate and a plurality of laser stacking assemblies, and each laser stacking assembly comprises a first laser unit and a second laser unit; the first laser unit comprises a first laser body, a first supporting plate and a first bottom plate; the second laser unit comprises a second laser body, a second supporting plate and a second top plate, the second supporting plate is provided with a second liquid inlet and a second flow passing channel, the second liquid inlet is communicated with the first liquid outlet, the second top plate is fixed to the top of the second supporting plate, a second liquid outlet is formed, and the second liquid outlet and the first liquid inlet are located on the same axis. A plurality of laser stacking assemblies can be connected in sequence, heat dissipation is carried out in a series connection mode, and therefore the heat dissipation capacity of the laser stacking assemblies is greatly improved.

The invention relates to the technical field of semiconductors, and discloses an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a preparation method thereof, and the LDMOS device comprises a substrate layer comprising a drift region, a field oxide layer and a gate oxide layer which are located on the surface of the substrate layer, a gate structure, a polycrystalline silicon structure at the side part, a first dielectric layer and a first conductive column, the metal field plate, the second conductive through hole and the field plate connecting structure are arranged at the side part of the gate metal layer; wherein the field oxide layer is located on the surface of the drift region, and the gate structure, the drift region and the field oxide layer between the gate structure and the drift region form a first field plate structure; the metal field plate, the polycrystalline silicon structure and the first dielectric layer therebetween form a first capacitor, the polycrystalline silicon structure, the drift region and the field oxide layer therebetween form a second capacitor, and the first capacitor and the second capacitor are coupled in series to form a second field plate structure; the first field plate structure and the second field plate structure are connected through the field plate connecting structure and the second conductive through hole to form a double-field-plate structure. According to the invention, the breakdown voltage of the device can be improved under the condition of low on-resistance.

The invention relates to the technical field of semiconductors, in particular to a high-temperature reverse bias test method, an electrostatic discharge protection structure and electronic equipment, and the method comprises the steps: providing the electrostatic discharge protection structure; determining an initial leakage current at the initial voltage, and determining an initial breakdown voltage at the initial current; heating the electrostatic discharge protection structure for a preset time at a preset temperature and a preset voltage, and determining a target leakage current of the heated electrostatic discharge protection structure under the initial voltage and a target breakdown voltage of the heated electrostatic discharge protection structure under the initial current; performing current change analysis on the initial leakage current and the target leakage current to obtain a current change result, and performing voltage change analysis on the initial breakdown voltage and the target breakdown voltage to obtain a voltage change result; and according to the current change result and the voltage change result, generating a high-temperature reverse bias test result of the electrostatic discharge protection structure. According to the invention, the reliability of the electrostatic discharge protection structure can be accurately evaluated.

The utility model relates to the technical field of semiconductors, in particular to a backlight source chip and an LCD display screen, the backlight source chip comprises a substrate, interdigital electrodes and LED chips distributed on the substrate, and a light color conversion layer covering the surfaces of the LED chips, and the LED chips comprise a blue light LED chip and a green light LED chip; the blue-light LED chip and the green-light LED chip are electrically connected with an external driver through the interdigital electrodes and leads; the light color conversion layer is used for converting the color of light emitted by the blue light LED chip and the green light LED chip into white, compared with a backlight source chip only comprising the blue light LED chip, the backlight source chip has the advantage that a green light component is added, and the color gamut of an LCD display screen can be improved.

The embodiment of the application provides an optical amplifier, an optical assembly, an optical module, an optical communication network system and a detection device, relates to the technical field of semiconductors, and is used for solving the problem of one-way light emission of the optical amplifier. The optical amplifier comprises a waveguide and a photonic crystal. The waveguide comprises a core region and a cladding region arranged at the periphery of the core region. The waveguide further comprises an incident light side, a first light emission side and a second light emission side. The photonic crystal is arranged in the cladding region of the waveguide. The core region is located between the incident light side and the first light emission side, and the photonic crystal is located between the second light emission side and the core region. The photonic crystal is used for receiving incident light from the incident light side and emitting first emitted light and second emitted light. The first emitted light is emitted from the first light emission side, and the second emitted light is emitted from the second light emission side.

The invention belongs to the technical field of semiconductors, and particularly relates to a preparation method of a single-crystal-on-silicon thin film product and the thin film product. The method comprises the following steps: high-temperature oxidation: feeding a support wafer into a high-temperature vertical furnace for high-temperature oxidation; fusing and bonding: fusing and bonding the device wafer and the support wafer to form a first bonded wafer; the first bonding wafer is preprocessed to obtain a second bonding wafer, the first bonding wafer is placed on a multi-point support, a force F perpendicular to the surface of the first bonding wafer is applied to the upper portion of the corresponding fulcrum, and F ranges from 0.5 N to 3 N; low-temperature annealing: carrying out low-temperature annealing on the second bonding wafer at 100-300 DEG C to obtain a third bonding wafer; and thinning treatment: carrying out thinning treatment on the third bonding wafer to obtain a single crystal film product on silicon. According to the method, the stress damage problem of the single crystal film product on the semiconductor silicon is solved, the generation probability of wafer surface defects is reduced, and the yield of the single crystal film product on the silicon is improved.

The embodiment of the invention relates to the technical field of semiconductors, and discloses a radio frequency module, radar and electronic equipment, the radio frequency module comprises a chip packaging body, the chip packaging body is provided with at least one radiation part, and a plurality of salient points are arranged around the radiation part and form a first waveguide channel; a second waveguide channel is arranged at the position, corresponding to each first waveguide channel, of the PCB carrier plate; the waveguide antenna is provided with at least one antenna unit and a third waveguide channel; wherein the first waveguide channel, the second waveguide channel and the third waveguide channel are communicated to form a radio frequency signal transmission channel. According to the scheme, the loss of the module on the feeder line can be effectively reduced, and the waveguide antenna is externally connected to the PCB, so that replacement is convenient to realize.

The embodiments of the present application relate to the technical field of semiconductors. Disclosed are a chip packaging structure and a preparation method therefor, and an electronic device. The chip packaging structure comprises a first substrate, a first chip, a second substrate, a first heat dissipation component, a first connecting portion and a second chip, wherein the first chip is electrically connected to one side of the first substrate; the second substrate is located on the side of the first chip away from the first substrate and is electrically connected to the first substrate; the second substrate is internally provided with an opening extending therethrough, and the orthographic projection of the opening on the first substrate at least partially overlaps the orthographic projection of the first chip on the first substrate; the first heat dissipation component is located in the opening; the first connecting portion is connected between the first chip and the first heat dissipation component; and the second chip is electrically connected to the side of the second substrate away from the first substrate. By means of the provision of the opening in the second substrate and the arrangement of the first heat dissipation component in the opening, an upward heat dissipation path can be provided for the first chip, and the overall heat capacity of the chip packaging structure can also be improved, thereby effectively improving the heat dissipation effect of POP packaging.

The invention relates to the technical field of semiconductors, and provides a memory and an operation method thereof, which are used for relieving harm caused by line hammering. The memory comprises a memory array and a control circuit. The control circuit is configured to enter a first mode in response to a command address signal and a mode control signal when a preset condition is met, execute an updating operation on a counting storage unit corresponding to an activated word line at a first moment, execute a pre-charging operation on the activated word line at a second moment, and take counting data as a counting value of row hammer refreshing; or, responding to the command address signal and the mode control signal when the preset condition is not met, entering a second mode, not executing the updating operation on the counting storage unit corresponding to the activated word line, and starting to execute the pre-charging operation on the activated word line at a second moment, and taking an activation count value of an activation word line in the dynamic lookup table as a count value of row hammer refreshing. In this way, balance is achieved between flexible configuration and reliability guarantee, and harm caused by hammering is relieved.

The invention relates to a conduit assembly (70, 90) for a fluid line (39, 42, 43) for a system (1, 101) for semiconductor technology, comprising at least one damping element (72.1, 72.2, 92) for damping acoustic vibrations in the fluid (79), wherein the conduit assembly (70, 90) has a compressible primary volume (77.1, 77.2, 97) into which the damping element (72.1, 72.2, 92) moves at least partially upon deformation. The conduit assembly (70, 90) is characterized in that it has a compressible secondary volume (78.1, 78.2, 98) which is formed as a part of the primary volume (77.1, 77.2, 97). The invention further relates to a system (1,101) for semiconductor technology with a conductor assembly (70,90) according to one of the embodiments described.

The invention relates to a thermalization plate (30) for a system (1,101) of semiconductor technology with at least two thermalization plate elements (40,41,50,51,52), wherein the thermalization plate (30) is characterized in that at least one thermalization plate element (40,41) is manufactured using an additive manufacturing process. Furthermore, the invention relates to a system (1,101) for semiconductor technology, in particular a projection exposure system (1,101). Furthermore, the invention relates to a method for manufacturing a thermalization plate (30) for a semiconductor technology system (1,101), with at least two interconnected thermalization plate elements (40,41,50,51,52), wherein at least one thermalization plate element (40,41) is manufactured using an additive manufacturing process and comprises the following process steps: - Production of at least one thermalization sheet element (40,41) using an additive manufacturing process. - Joining of the thermalization sheet elements (40,41,50,51,52) by laser welding.

The invention provides a method for correcting the layout of a photomask, and is applied to the technical field of semiconductors. According to the method and the device, a plurality of pixel graphs of which the interval lengths do not meet a preset range are screened out based on the interval lengths between adjacent pixel graphs, and then the key sizes of the screened pixel graphs are multiplied by N times according to different proportions, so that a plurality of first test photomasks are constructed; and then determining the optimal magnification ratio of the initial photomask based on the combination of the wafer data, the incremental limit suboptimal solution and the two-side clamping theorem, namely obtaining the target photomask, so that the unexpected effects are that the optimal magnification ratio of each pixel graph in the initial photomask can be rapidly determined only by using a small part of pixel graphs in the initial photomask, and the target photomask is obtained. The manufacturing efficiency and quality of the photomask and the space utilization rate of the photomask and the wafer are improved, and the manufacturing cost of the photomask is reduced.

The invention provides a light emitting diode chip and a preparation method thereof, and belongs to the technical field of semiconductors. The light emitting diode chip comprises an epitaxial layer, a distributed Bragg reflection layer, a first primary electrode and a second primary electrode; the epitaxial layer comprises a first semiconductor layer, an active layer and a second semiconductor layer which are stacked in sequence; the distributed Bragg reflection layer is stacked on one side of the epitaxial layer, and the distributed Bragg reflection layer is provided with a first electrode hole and a second electrode hole; the first primary electrode penetrates through the first electrode hole and is electrically connected with the first semiconductor layer, and the second primary electrode penetrates through the second electrode hole and is electrically connected with the second semiconductor layer. The preparation cost can be effectively reduced.

The invention provides a method for measuring a sample hole, and relates to the technical field of semiconductors, and the method comprises the steps: marking a first target surface of a to-be-measured sample, and determining the region range of a target hole of the to-be-measured sample located in the to-be-measured sample through the first target surface; coating the first target surface of the to-be-detected sample to form a glue protective layer; depositing metal on the glue protection layer to form a metal protection layer; the material of the glue protection layer comprises M-Bond 610, and the material of the metal protection layer comprises metal platinum; the thickness of the glue protection layer is 500 nm to 1 [mu] m, and the thickness of the metal protection layer is 300 nm to 600 nm; etching along the second target surface of the to-be-tested sample until the target hole is exposed; sampling the to-be-tested sample with the exposed target hole to obtain a sample piece with the target hole; detecting a target hole; after the first target surface of the to-be-detected sample is coated to form the glue protection layer, the method further comprises the following steps: performing vacuum pumping to remove gas in the target hole.

The invention discloses a shallow trench isolation structure and a preparation method thereof, and belongs to the technical field of semiconductors, and the preparation method comprises the steps: providing a semiconductor substrate, and sequentially forming a liner oxide layer and a nitride layer on the semiconductor substrate; forming grooves in the liner oxide layer, the nitride layer and the semiconductor substrate; the grooves extend into the semiconductor substrate from the nitride layer and divide the semiconductor substrate into a plurality of active regions; performing back etching on the pad oxide layer and the nitride layer on the two sides of the groove so as to expose the top surface of the active region of the semiconductor substrate close to the top of the side wall of the groove; forming an epitaxial layer on the inner wall of the groove and the exposed top surface of the active region of the semiconductor substrate; smoothing the top corner of the exposed active region of the semiconductor substrate to form a line oxide layer; and forming an isolation region in the groove, performing planarization processing on the isolation region to expose the nitride layer, and removing the nitride layer.

The invention relates to the technical field of semiconductors, in particular to an ultrasonic chip and an ultrasonic module. The ultrasonic chip comprises a circuit layer, a piezoelectric layer and an electrode layer; the circuit layer comprises a substrate, an on-chip circuit of an ultrasonic transmitting circuit is arranged in the substrate, a first bonding pad, a second bonding pad and a first electrode are arranged on the substrate, and the electrode layer comprises a second electrode; the first electrode, the second electrode and the piezoelectric layer are used for forming an ultrasonic transducer; the on-chip circuit is used for generating an electric signal and transmitting the electric signal to the first bonding pad, the first bonding pad is used for transmitting the electric signal to an off-chip circuit of the ultrasonic transmitting circuit, and the off-chip circuit is used for generating an excitation signal according to the electric signal and transmitting the excitation signal to the second bonding pad; the second bonding pad is used for transmitting an excitation signal to the second electrode so as to drive the ultrasonic transducer to emit ultrasonic waves, and the on-chip circuit is located in an area outside an ultrasonic area. According to the embodiment of the invention, the integration level of the ultrasonic chip can be improved.

The invention relates to a conduit assembly (70) for a system (1, 101) for semiconductor technology, comprising at least one elastic fluid conduit section (76) for conveying a fluid (40, 79) at a nominal operating line pressure and a casing (75, 78) surrounding the elastic fluid conduit section (76), wherein the casing (75, 78) and the elastic fluid conduit section (76) are connected to each other via at least one connecting adapter (74.1, 74.2) and / or at least one conduit connection (73.1, 73.2) of the conduit assembly (70). The casing (75, 78), the elastic fluid conduit section (76), and the at least one connecting adapter (74.1, 74.2) and / or the at least one conduit connection (73.1, 73.2) enclose a pressurized gas space (77).The invention is characterized in that the pressure in the gas space (77) is configured such that the elastic fluid line section (76) exhibits a maximum permissible expansion or contraction of less than 60%, preferably less than 30%, and particularly preferably less than 15%, during operation. Furthermore, the invention relates to a system for semiconductor technology (1, 101) with a line assembly (70) according to one of the described embodiments. The invention further relates to a method for adjusting the pressure in a line assembly (70) according to one of the described embodiments. The method comprises the following steps: - Determination of the nominal operating line pressure, - Determination of the corresponding pressure in the gas space (77) based on the maximum permissible expansion or contraction of the fluid line section (76), - Adjusting the determined pressure in the gas space (77).