714 results about "Semiconductor technology" patented technology

The invention relates to a MEMS mirror array module (100) for use in semiconductor technology equipment. The MEMS mirror array module (100) comprises at least one MEMS micromirror unit (200) with a MEMS mirror array structure (210) and an elongated interface element (250) over which the MEMS mirror array structure (210) projects laterally, and a higher-level assembly (300) with at least one receptacle (350) for the interface element (250) of the MEMS micromirror unit (200), wherein the MEMS micromirror unit (200) is mounted in a receptacle (350) of the higher-level assembly (300) such that the MEMS mirror array structure (210) of the MEMS micromirror unit (200) abuts the higher-level assembly (300). A gas atmosphere with a thermal conductivity of more than 0.05 W / (m·K) is introduced into a gap (400) between the interface element (250) and the receptacle (350).

The invention relates to a system for semiconductor technology comprising at least one fluid channel (105) for a temperature control medium for temperature control of at least one component, e.g. a mirror (25, M4) of a projection exposure system (1) for photolithography. The system comprises at least two pressure fluctuation measuring devices (210) and a pressure surge sensor (220), arranged in series along the fluid channel (105) and connected to a control unit (230). The control unit (230) is configured to detect pressure fluctuations in the temperature control medium propagating from the pressure fluctuation measuring devices (210) towards the pressure surge sensor (220) from the signals of the pressure fluctuation measuring devices (210) and to control the pressure surge sensor (220) appropriately to generate destructive interference and reduce pressure fluctuations in the temperature control medium.

The invention relates to a MEMS mirror array module (100) for use in semiconductor technology equipment. The MEMS mirror array module (100) comprises at least one MEMS micromirror unit (200) with a MEMS mirror array structure (210) and a higher-level assembly (300), wherein the MEMS micromirror unit (200) is attached to the higher-level assembly (230) such that the MEMS mirror array structure (210) of the MEMS micromirror unit (200) is in contact with the higher-level assembly (300). The MEMS mirror array module (100) is configured such that sufficient heat conduction from the MEMS mirror array structure (210) to the higher-level assembly (300) is achieved to prevent an undesirably high temperature rise in or on the MEMS mirror array structure (210).

This disclosure relates to the field of semiconductor technology, providing a semiconductor structure and its manufacturing method. The semiconductor structure includes: a transistor structure and a capacitor structure arranged along a first direction, the capacitor structure extending along the first direction; and a word line staircase structure arranged at intervals from the transistor structure along a second direction, the word line staircase structure extending along the first direction, the first direction intersecting the second direction, and the word line staircase structure and the transistor structure being electrically connected. Using a plane perpendicular to the second direction as a reference plane, the orthographic projection of the transistor structure onto the reference plane is a first projection, the orthographic projection of the capacitor structure onto the reference plane is a second projection, and the orthographic projection of the word line staircase structure onto the reference plane is a third projection. The third projection covers the first projection, and the third projection partially overlaps with the second projection. This disclosure at least helps to improve the integration density of the transistor structure and capacitor structure in the semiconductor structure.

This invention relates to the field of semiconductor technology, and more particularly to a method, apparatus, and device for controlling the intrinsic temperature of a wafer. The method involves extracting features from amplitude ratio and phase difference spectra based on a preset time sequence to obtain a corrected growth rate; calculating the process formulation change sequence according to a preset thermal inertia equation and a preset growth kinetic relationship to obtain feedforward compensation power; calculating the corrected growth rate according to a preset multivariable PID control algorithm to obtain feedback regulation power; and solving the feedforward compensation power and feedback regulation power according to a preset decoupling formula to obtain the intrinsic temperature power control command for the wafer. By generating feedback regulation power through the multivariable PID control algorithm, and reducing temperature zone interference through decoupling, the method achieves zoned temperature control, improves the system's anti-interference capability, ensures the stability of epitaxial layer quality, enhances the consistency and reliability of MOCVD processes, and provides support for the large-scale production of semiconductor devices.

The application provides a glue-dipping needle, and relates to the technical field of semiconductors. A cavity is formed in a shell. The cavity has an opening. A valve core and a driving assembly connected with the valve core are arranged in the cavity. The driving assembly is used to drive the valve core to move in a first direction, so that an end of the valve core penetrates through the opening. Glue liquid enters the cavity through the opening. When the end of the valve core penetrates through the opening, the end of the valve core has a clamping state with the opening, so that the cavity is sealed to contain the glue liquid. The valve core can block the opening when the valve core penetrates through the opening. The cavity becomes a sealed cavity. The glue-dipping needle can be integrally transferred with the glue liquid sealed in the cavity. The valve core is reversely reset. The opening of the sealed cavity is opened. The glue liquid in the cavity can be dropped on a target position. The valve core switches the cavity between the opened state and the sealed state. When the sealed cavity is transferred with the glue liquid, defects such as glue liquid overflow and glue throwing can be avoided. The functionality and reliability of a product are improved.

This invention relates to the field of semiconductor technology, providing a Si VDMOS device and electronic device. The Si VDMOS device includes a Si VDMOS chip, which comprises a drain electrode, a substrate, and an epitaxial layer connected sequentially from bottom to top. The epitaxial layer contains P-type and N-type doped regions. An insulating dielectric layer and several source electrodes are disposed on the side of the epitaxial layer facing away from the substrate. Several gate electrodes are disposed on the side of the insulating dielectric layer facing away from the epitaxial layer. The source electrodes and gate electrodes form an active region. A metal ring is connected to the insulating dielectric layer, surrounding the active region. The distance between the metal ring and the active region is greater than or equal to 150 μm. The metal ring is connected to a potential structure, the potential of which is equal to the potential of the drain electrode. By employing this structure, silver ion migration can be suppressed at its source.

The present invention relates to the technical field of semiconductors, and provides a CS-JL device and a manufacturing method therefor, and an electronic device. In the manufacturing method for the CS-JL device, a Core layer is prepared first; then a dummy gate structure, a sidewall structure, a source, and a drain are prepared; then a Shell layer is prepared by removing the dummy gate structure; and finally a gate structure is formed. This method effectively avoids the impact of high temperatures required during the preparation of the sidewall structure, the source, the drain, etc. on impurity diffusion in a channel region, facilitates accurate control of the doping concentrations and thicknesses of the Core layer and the Shell layer, reduces an off-state leakage current of the CS-JL device, and improves the device performance thereof.

The utility model discloses a gallium nitride output essential safety type power supply, including power supply body and bottom mounting plate, the casing bottom of power supply body is fixed with bottom mounting plate, still include guide and scatter mechanism, the guide and scatter mechanism includes top and exposes the groove, heat conduction silicon pad, double -faced wrong groove board, edge and exposes the groove, gantry clamping plate, lead touch piece, edge fin, bottom link and horn, through setting up guide and scatter mechanism and carry out heat dissipation improvement to the essential safety type power supply of gallium nitride semiconductor technology's application, and the top and exposes the groove of guide and scatter mechanism cooperation deep groove reduces the casing thickness of power supply body, and then combines heat conduction silicon pad and double -faced wrong groove board, forms the efficient heat conduction path and conducts heat dissipation outward, and simultaneously, the gantry clamping plate collocates lead touch piece and edge fin, constructs the multi -point three -dimensional heat dissipation surface of top surface and side surface formula, solves the casing heat dissipation blind area problem of power supply body, realizes the heat of power supply body and multi -point dispersion export.

The disclosure provides a semiconductor structure defect monitoring method and device, and relates to the technical field of semiconductors. The semiconductor structure defect monitoring method comprises the following steps: acquiring a overlay accuracy offset of a capacitor column and a support structure; acquiring an etching opening size of an etching film layer; determining a corresponding relationship between the overlay accuracy offset and the etching opening size; and monitoring a structure defect in a semiconductor production process based on the corresponding relationship. The technical problem of poor defect monitoring effect of the capacitor is solved, and the technical effect of improving the defect monitoring effect of the capacitor is achieved.

This invention discloses an MSM interdigitated wideband ultraviolet photodetector and its fabrication method, belonging to the field of semiconductor technology. The detector includes: a substrate; an AlN nucleation layer on the substrate surface; a heterostructure on the surface of the AlN nucleation layer away from the substrate, wherein the heterostructure includes GaN, GaON, and Ga2O3 layers stacked sequentially from bottom to top; and interdigitated electrodes on the surface of the Ga2O3 layer away from the substrate. This invention introduces a GaON layer between the Ga2O3 and GaN heterojunctions. This GaON layer acts as a lattice buffer layer, effectively releasing the lattice mismatch stress between Ga2O3 and GaN, significantly improving the interface quality of the heterojunction, and enhancing the separation and collection efficiency of charge carriers, thus significantly improving the overall performance of the MSM interdigitated ultraviolet photodetector.

The application provides a deep silicon etching method and a semiconductor process equipment, and relates to the technical field of semiconductors. The deep silicon etching method comprises a first cycle step and a second cycle step. The first cycle step and the second cycle step both comprise an etching step for etching a silicon substrate to form a groove, a removal step for removing by-products, and a deposition step for forming a protective layer on the sidewall of the groove. The protective gas used in the deposition step of the second cycle step comprises an oxygen-containing gas, and the lower electrode power of the deposition step of the second cycle step is greater than that of the deposition step of the first cycle step. The deep silicon etching method can balance the etching rate of different regions of the isolation groove, optimize the depth micro-loading effect, and improve the depth consistency of the isolation groove. Meanwhile, the deposition step does not consume the mask layer, thereby reducing the consumption of the mask layer, ensuring the effective height of the mask layer, improving the morphology precision of the formed isolation groove and AA, and improving the electrical properties and yield of the product.

The application belongs to the technical field of semiconductor, and provides a MOSFET power device with low on-resistance and a preparation method thereof. The MOSFET power device with low on-resistance comprises a semiconductor substrate, an N-type drift region, a P-type well region, a P-type doped region, a source doped region, a source, a gate, a gate dielectric layer and a drain. When the voltage of the gate of the MOSFET power device exceeds the threshold voltage, the channels formed by the positions of the P-type doped region and the P-type well region in contact with the gate dielectric layer are all turned on, and then the MOSFET power device starts to work. Since the on-resistance of the P-type doped region is small, the MOSFET power device can have a small on-resistance when working, so that the MOSFET power device can have a large threshold voltage while reducing the on-resistance of the MOSFET power device.

This invention relates to the field of semiconductor technology, disclosing a semiconductor structure and its fabrication method, and a heterojunction bipolar transistor, comprising: forming a germanium-silicon layer on one side of a substrate layer, and forming a polysilicon layer on the side of the germanium-silicon layer facing away from the substrate layer; patterning the substrate layer and the germanium-silicon layer to obtain a predetermined collector region based on the substrate layer and a base region based on the germanium-silicon layer; performing ion implantation on the side of the predetermined collector region facing away from the base region to form a collector region; exposing a portion of the surface of the base region on the side of the collector region; patterning the polysilicon layer to form an emitter structure; and the width of the collector region being less than or equal to the width of the emitter structure. This invention can reduce the lateral dimensions of the device, increase integration density, reduce parasitic capacitance and resistance, and also improve the reliability of the collector region, ensuring that the doping concentration distribution of the collector region is within the target range.

This invention relates to the field of semiconductor technology, specifically to a molecular junction of a metal oxide semiconductor and its applications, wherein the molecular junction is composed of oxygen vacancies and hydroxyl groups, which are bonded to the same metal atom to form an oxygen vacancy-hydroxyl metal oxide molecular junction (Oxygen vacancy-hydroxyl metal oxide, V). O (-M-OH). The molecular junction of this invention can achieve efficient hole injection / transmission, optimize interface band arrangement, and effectively suppress dark current.

This application provides a chip and its fabrication method, chip packaging structure, and electronic device, relating to the field of semiconductor technology. In this semiconductor structure, a ferroelectric capacitor is placed within the second dielectric layer of a first back-end trace layer. If the capacitance value of the ferroelectric capacitor meets the requirements, there is no need to add an additional sub-transfer layer. This eliminates the impact of the additional sub-transfer layer on the semiconductor structure performance (e.g., it can eliminate the impact of the additional sub-transfer layer on the signal transmission speed of logic circuits in the semiconductor structure). Even if the thickness of the first back-end trace layer cannot meet the capacitance requirement of the ferroelectric capacitor, and an additional sub-transfer layer is needed to increase the space for the ferroelectric capacitor, the additional sub-transfer layer only serves to supplement space, and its thickness is relatively thin, resulting in a relatively small impact on the semiconductor structure performance.

This invention belongs to the field of semiconductor technology, specifically disclosing a depletion-mode GaN chip with an internally integrated diode and a cascaded device. The GaN chip includes a GaN body structure and a diode structure. The GaN body structure has a source electrode, a drain electrode, and a gate electrode. The gate electrode of the GaN body structure is connected to the positive or negative electrode of the diode structure. The diode structure includes a cathode ohmic metal and an anode metal. The anode metal includes an anode Schottky metal, or the anode metal includes multiple anode Schottky metals and anode ohmic metals arranged alternately and at intervals along the same horizontal direction. The forward conduction resistance of the diode structure is less than the reverse conduction resistance of the diode structure. The turn-on speed and turn-off speed of the cascaded device obtained by cascading the depletion-mode GaN chip of this invention with an enhancement-mode MOS chip can be adjusted separately.

This invention discloses a sheet resistance testing unit and structure, belonging to the field of semiconductor technology. The sheet resistance testing unit includes a first resistor, formed by the length and width of a layout design; and a second resistor with the same layout design dimensions as the first resistor, and an angle between the first and second resistors to achieve mutual resistance compensation. The second resistor is also connected to the first resistor via a connector to ensure that the current flow directions in the first resistor, the second resistor, and the connector are the same. By providing a first resistor and a second resistor with correspondingly equal layout dimensions and the same current direction, under the same process fluctuation conditions, the differential polarities of the first and second resistors are opposite, and the resulting resistance value deviations can be mutually compensated, effectively reducing the impact of active region process fluctuations on sheet resistance testing in small-size applications.

The application relates to the technical field of semiconductors, and provides a micro health detection device. The device comprises a chip-level light source for emitting detection light; a photodiode module stacked above the chip-level light source and facing the light-emitting front surface of the chip-level light source, for receiving light signals transmitted or reflected by the detection light and converting the light signals into electric signals; and an analog front end module stacked above the photodiode module, for receiving the electric signals sent by the photodiode module and processing the electric signals. The device solves the problem of large size of the health detection device in the prior art, reduces the size of the health detection device, and makes the health detection device more suitable for wearable or portable health monitoring applications.

The invention relates to a system for semiconductor technology, comprising at least one fluid channel (105) for a temperature control medium for controlling the temperature of at least one component, for example a mirror (25, M4) of a projection exposure system (1) for photolithography. The system comprises, along the fluid channel (105), at least two pressure fluctuation measuring devices (210) and a pressure surge generator (220), which are spaced apart from one another in series and are connected to a control apparatus (230), the fluid channel (105), between two adjacent pressure fluctuation measuring devices (210), at least partially comprising a wall made of elastic material (215). The control device (230) is designed to ascertain pressure fluctuations in the temperature control medium that move from the pressure fluctuation measuring devices (210) toward the pressure surge generator (220) from the signals from the pressure fluctuation measuring devices (210) and to control the pressure surge generator (220) appropriately in order to generate destructive interference for the purpose of reducing pressure fluctuations in the temperature control medium. (Figure 2)

The application discloses a ring gate transistor and a manufacturing method thereof, and relates to the technical field of semiconductors, which is used for effectively inhibiting the parasitic channel leakage of the ring gate transistor, preventing the band tunneling problem, improving the working performance of the ring gate transistor, and reducing the manufacturing difficulty of the ring gate transistor. The ring gate transistor comprises a semiconductor substrate, an active structure, a heavily doped epitaxial structure, and a gate stack structure. The active structure is formed on the semiconductor substrate. The active structure comprises a source region, a drain region, and a channel region between the source region and the drain region. A first recess is formed in the part of the semiconductor substrate below the channel region and is inwardly recessed. The heavily doped epitaxial structure fills the first recess. The conductive type of the heavily doped epitaxial structure is opposite to the conductive type of the source region and the drain region. The gate stack structure surrounds the outer periphery of the channel region. The part of the gate stack structure below the channel region is formed between the heavily doped epitaxial structure and the channel region.

The present application belongs to the technical field of semiconductor, and particularly relates to a gate structure containing an effective work function adjustable work function metal layer and a preparation method thereof. The gate structure comprises a semiconductor substrate, a gate dielectric layer, a work function metal layer, and the material of the work function metal layer is TiAlC. The work function metal layer is changed in density so that the effective work function of the metal is regulated to the effective work function required by the target threshold voltage, and other gate layers. In the process of forming the work function metal layer on the gate dielectric layer, the work function metal layer with different densities is obtained through different process conditions, so that the effective work function of the metal is regulated to the effective work function required by the target threshold voltage. The different process conditions include the pretreatment process of the gate dielectric layer and / or the deposition process of the work function metal layer. The present application only needs one layer of work function metal layer to realize the regulation of the threshold voltage, meets the multi-threshold voltage device, avoids the complex process of other work function regulation methods, and reduces the manufacturing cost.

This invention discloses a semiconductor device and its manufacturing method, relating to the field of semiconductor technology, to improve the yield and performance of P-type gate-around transistors (GOTMTs). The semiconductor device includes a semiconductor substrate and a P-type GOTMT formed on the semiconductor substrate. The P-type GOTMT includes a channel region having at least one nanostructure layer. Each nanostructure layer includes a first material portion, a second material portion, and a third material portion, all made of germanium-silicon. The germanium content in the second material portion is greater than the germanium content in the first and third material portions, respectively, and the germanium content in the third material portion is greater than the germanium content in the first material portion. The second material portions are located on both sides of the first material portion along its thickness direction, and the third material portions are located on both sides of the first material portion along its width direction. The manufacturing method of the semiconductor device is used to manufacture the above-described semiconductor device.

A method for manufacturing an optical element (1) of an optical system, which optical element has a target surface shape (1a) and / or a target optical effect during operation of the optical system, wherein the optical element (1) has an average operating temperature (F), which is controlled by at least one thermal manipulator (2) during operation of the optical system. The invention also relates to an optical element for an optical system and to an optical system for a semiconductor technology device.

The application relates to the technical field of semiconductors, and provides a logic operation method and device based on a ferroelectric transistor and electronic equipment, the logic operation method based on the ferroelectric transistor comprises the following steps: obtaining an operation instruction to be executed, the operation instruction comprising input variables and the type of the logic operation to be executed; determining an assignment relationship between the input variables and logic variables of a target logic gate according to the working principle of the target logic gate and the type of the logic operation to be executed, wherein the target logic gate comprises at least one ferroelectric transistor; assigning the values of the input variables to the logic variables according to the assignment relationship; controlling the ferroelectric transistor to execute the logic operation according to the logic variables, and storing the result of the logic operation in situ by using the polarization state of the ferroelectric transistor. The method realizes the integration of storage and calculation based on the Boolean logic gate of the ferroelectric transistor, breaks through the limitations of the storage wall and the power consumption wall, and improves the flexibility of the Boolean logic gate of the ferroelectric transistor when performing the logic operation.

Examples of the present disclosure provides a memory system, a memory controller, an operating method, a computing readable storage medium and a computer program product, and the present disclosure relates to the technical field of semiconductors. The method includes: determining that a first die of a plurality of dies fails; obtaining valid data of the first die based on stored redundant data; and send a first program command sequence to second dies, wherein the first program command sequence includes a first program command and the valid data of the first die, and the second dies comprise other dies different from the first die among the plurality of dies, and reliability of the memory system can be improved.

The present application relates to the technical field of semiconductor, in particular to a hole and groove isolation structure and a semiconductor preparation method. The hole and groove preparation method comprises the following steps: providing a layer structure, the layer structure comprising a target layer and a hard mask layer formed on the target layer; introducing a photoetching technology to form a window on the hard mask layer, a top edge of the window being provided with an edge defect; selectively forming a filling structure in the window, the material of the filling structure being different from that of the hard mask layer, and a top surface height of the filling structure being adapted to a height of the edge defect; filling a repairing material at the edge defect to repair the edge defect, the repairing material being different from the material of the filling structure; removing the filling structure and etching the target layer in a direction of the target layer along the window to form a hole and groove. Based on the above method, the present application can solve the problem of critical dimension deviation.

This application discloses a surface acoustic wave (SAW) resonator, filter, and electronic device, belonging to the field of semiconductor technology. The SAW resonator includes: a substrate; a piezoelectric layer located on one side of the substrate along its thickness direction; an interdigital transducer located on the side of the piezoelectric layer opposite to the substrate, the interdigital transducer including a plurality of electrode fingers extending along a first direction and spaced apart along a second direction; the overlapping region of the plurality of electrode fingers along the second direction constitutes an active region; the thickness direction, the first direction, and the second direction are mutually perpendicular; a functional layer located in the active region and between the plurality of electrode fingers, the SAW velocity of the functional layer being greater than the SAW velocity of the piezoelectric layer. This application can suppress stray modes and improve the performance of the resonator.

The present invention relates to the technical field of semiconductors, and provides a MOSFET device and a manufacturing method therefor, and a layout arrangement structure. A P-type buried layer is disposed within an N-type voltage-withstanding layer between the bottom of a trench and a substrate, and the P-type buried layer is electrically connected to a source, thereby solving the problem of insufficient electric field protection at the bottom of a trench gate and achieving effective protection of a gate dielectric layer under a high drain voltage. In addition, because a gap exists between the P-type buried layer and the bottom of a channel, current can still flow between the bottom of the trench and the P-type buried layer, and the design of the P-type buried layer does not hinder current flow, thereby comprehensively improving the operational performance of the MOSFET device.