7510 results about "Semiconductor technology" patented technology

The invention relates to the technical field of MOS semiconductors, and discloses a variably doped planar gate silicon carbide VDMOS device and a preparation process thereof, the variably doped planar gate silicon carbide VDMOS device comprises a plurality of MOS cells which are parallel to each other, and each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of a single MOS cell; lateral symmetric P-layers are arranged in the single MOS cell and located on the left side and the right side of the N drift layer, and the section contours of the corresponding sides of the lateral symmetric P-layers on the two sides are in an arc shape. By arranging the lightly doped N layer in the middle of the N drift layer and introducing the arc-shaped laterally-symmetrical P-layers to the two sides, the electric field distribution of the device is optimized, the local electric field concentration is reduced, the breakdown voltage is remarkably improved, and the charge balance capability is enhanced and the leakage current is reduced through the contact between the laterally-symmetrical P-layers and the N substrate layer.

The invention relates to the technical field of semiconductors, and discloses a full-temperature-zone polynomial digital temperature compensation method and system based on an SOI chip, and the method comprises the steps: obtaining the temperature frequency data of a preset temperature zone of a target SOI chip, fitting a full-temperature-zone curve, extracting a critical point of the temperature zone, dividing a segmented compensation interval according to the critical point, and obtaining the temperature frequency data of the preset temperature zone of the target SOI chip; the method comprises the following steps: calculating frequency drift amounts under different voltages to construct a full-automatic test framework, acquiring an environment temperature parameter and an instantaneous temperature value by using the framework, analyzing a temperature compensation vector of a segmented compensation interval, further monitoring a signal frequency interval output by a chip, extracting a phase noise parameter, calculating a frequency offset error amount with a preset value, and calculating the frequency offset error amount. And analyzing an error source, optimizing a polynomial compensation order, and collecting temperature drift suppression data to generate a full temperature region compensation report. According to the invention, the performance stability of the chip in a complex environment can be improved.

The invention relates to the technical field of semiconductors, and particularly discloses a multiband LED chip and a preparation method thereof, and a white light LED light source, the LED chip comprises a light-emitting layer, and the light-emitting layer comprises a first cyan light multi-quantum well layer, a second long-wave blue light multi-quantum well layer, a third short-wave blue light multi-quantum well layer and a fourth purple light multi-quantum well layer which are sequentially stacked in the epitaxial direction; the first cyan light multi-quantum well layer, the second long-wave blue light multi-quantum well layer, the third short-wave blue light multi-quantum well layer and the fourth purple light multi-quantum well layer are each of a periodic structure formed by alternately stacking well layers and barrier layers, and the light-emitting wavelengths of the first cyan light multi-quantum well layer, the second long-wave blue light multi-quantum well layer, the third short-wave blue light multi-quantum well layer and the fourth purple light multi-quantum well layer are sequentially decreased. And the forbidden band widths of the barrier layers are sequentially decreased. According to the LED chip, the overall excitation efficiency can be effectively improved, and the output full-spectrum white light LED light source is higher in color rendering index, better in stability, less in damage to human eyes and high in light emitting efficiency.

The invention provides a third-generation semiconductor device multi-physical field coupling effect dynamic monitoring method and system, and relates to the technical field of semiconductors, and the method comprises the steps: collecting the data of a temperature field, an electric field, a magnetic field and a stress field through a complementary sensor array, constructing a feature tensor, inputting the feature tensor into a pre-trained graph neural network, and extracting a coupling effect dynamic evolution rule; on-line analysis and prediction are carried out by using an adaptive time window and a recurrent neural network, a multi-field coupling correlation degree evaluation model is established, an early warning level is determined according to the deviation between the coupling correlation degree and an early warning threshold value, and device risk evaluation and maintenance suggestions are generated, so that early warning of the failure risk of the semiconductor device is realized.

The invention relates to the technical field of MOS semiconductors, and discloses a silicon carbide thick-bottom oxide layer groove MOS structure and a preparation method thereof, the silicon carbide thick-bottom oxide layer groove MOS structure comprises a plurality of parallel MOS cells, and each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of each MOS cell; the lightly doped N layer is arranged in the middle of the N drift layer, the arc-shaped contour design with the inclined top is introduced to the two sides, the injection area is accurately controlled through the photoetching technology, the phenomenon that the edge electric field concentration of the N drift layer is effectively dispersed is effectively dispersed, in this way, electric field distribution is more uniform, breakdown voltage is improved, and local electric field concentration is reduced; moreover, the contact between the laterally symmetrical P-layer and the N substrate layer enhances the charge balance capability, and reduces the leakage current.

The invention discloses a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with a high-mobility gate oxide layer and a preparation process of the SiC MOSFET device, and belongs to the technical field of semiconductors. Comprising a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of each MOS cell; by optimizing the gate oxide layer preparation process and combining the design of the T-shaped P-layer, the semi-elliptical lightly doped N-type half layer and the like in the device, the interface quality of the gate oxide layer and a semiconductor material is effectively improved, the scattering of a carrier by an interface state is reduced, and meanwhile, due to the synergistic effect of the structures such as the quarter-circle-shaped side symmetric P-layer and the square heavily doped N layer, the performance of the device is improved. The internal electric field distribution and the carrier transmission path of the device are optimized, and the channel carrier mobility is remarkably improved.

The invention relates to the technical field of MOS semiconductors, and discloses a silicon carbide plane MOS device polysilicon gate self-alignment process and a low resistance structure, the silicon carbide plane MOS device polysilicon gate self-alignment process comprises a plurality of parallel MOS cells, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, an N well layer, a P + layer and a P well layer, and the N drift layer comprises a drain electrode, a source electrode and a grid electrode. The height of the P well layer in the single MOS cell is aligned with that of the grid electrode, and the P well layer is located on the left side and the right side of the grid electrode; the N well layer and the P + layer are both located above the grid electrode and the P well layer, and the P + layer is located on the outer side of the N well layer. According to the invention, the height of the P well layer is accurately aligned with the grid electrode, the P well layer is arranged at the two sides of the grid electrode, the design of the T-shaped source electrode is combined, the conduction path is optimized, and when the voltage is applied to the grid electrode, vertical channels are formed at the two sides of the P well layer, so that the path of current flowing from the drain electrode to the source electrode through the N drift layer is shorter and the distribution is uniform.

The invention discloses an irradiation-reinforced SiC super-junction MOS (Metal Oxide Semiconductor) structure and a preparation process thereof, and belongs to the technical field of MOS semiconductors. Comprising a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer; by arranging the lightly doped N layer in the middle of the N drift layer and arranging the laterally symmetrical trapezoidal P-layers on the two sides of the N drift layer, the device can interact with electrons in the N drift layer, accelerate carrier recombination, reduce the influence of redundant carriers on the performance of the device, effectively reduce the performance degradation caused by irradiation, and improve the performance of the device. According to the invention, the concave heavily-doped N layer is formed at the bottom end of the lightly-doped N layer, so that the carrier concentration of the region can be greatly improved, and the conductivity is remarkably enhanced.

The invention discloses a light-emitting diode epitaxial wafer, a preparation method thereof and a light-emitting diode, and relates to the technical field of semiconductors. The light-emitting diode epitaxial wafer comprises a substrate, a buffer layer, an N-type semiconductor layer, a low-temperature stress release layer, a multi-quantum well light-emitting layer, an electron blocking layer and a P-type semiconductor layer. The multi-quantum well light-emitting layer comprises a first sub-layer, a second sub-layer, a third sub-layer and a fourth sub-layer which are stacked in sequence, and each of the first sub-layer, the second sub-layer, the third sub-layer and the fourth sub-layer comprises an InGaN quantum well layer and a GaN quantum barrier layer which are periodically and alternately stacked; an electron injection layer is inserted into at least one of the GaN quantum barrier layer of the first sub-layer, the GaN quantum barrier layer of the second sub-layer and the GaN quantum barrier layer of the third sub-layer; and a hole injection layer is inserted into the GaN quantum barrier layer of the fourth sub-layer. By implementing the invention, the electron hole matching degree of the multi-quantum well light-emitting layer can be improved, so that the luminous efficiency of the light-emitting diode is improved.

The invention belongs to the technical field of semiconductors, and discloses a SiC power semiconductor module with low parasitic parameters and a preparation method. Comprising a SiC power semiconductor chip, a SiC power semiconductor chip substrate cushion block, a positive electrode power terminal, a negative electrode power terminal, an output power terminal, a positive electrode side middle layer cushion block, a positive electrode side ceramic decoupling capacitor, a positive electrode side substrate middle layer cushion block, a negative electrode side middle layer cushion block, a negative electrode side ceramic decoupling capacitor and a negative electrode side substrate middle layer cushion block. A first copper-clad ceramic substrate, a third copper-clad ceramic substrate, a fourth copper-clad ceramic substrate, a second copper-clad ceramic substrate, a first commutation loop middle copper layer and a second commutation loop middle copper layer; according to the invention, a commutation path is provided for the SiC power semiconductor device by using the middle layer copper of the laminated copper-clad ceramic substrate, the concept of mutual inductance offset of double commutation loops is innovatively introduced, and the parasitic inductance of the module is further reduced.

The invention discloses a manufacturing method of a groove, a semiconductor device and a manufacturing method of the semiconductor device, and relates to the technical field of semiconductors, and the manufacturing method comprises the steps: providing a substrate, forming a first mask layer on the substrate, and etching the first mask layer by taking a photomask as a mask, so that the first mask layer covers the substrate of a first groove region, forming a second mask layer on the substrate, etching the second mask layer to enable the second mask layer to expose the first mask layer and the substrate in the second groove region, etching the substrate in the second groove region by taking the first mask layer and the second mask layer as masks to form a relatively shallow second groove, and etching the first mask layer to form a relatively shallow second groove; according to the method, the substrate of the first trench region and the substrate of the second trench region are exposed by the second mask layer, and the substrate of the first trench region and the substrate of the second trench region are etched by taking the second mask layer as a mask to form a deeper second trench and a shallower first trench, so that a shallow trench and a deep trench can be manufactured by adopting one photomask, and the manufacturing cost can be further reduced.

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a double-gate structure for a high-performance MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and an optimization method, the double-gate structure comprises a plurality of MOS cells, and each MOS cell comprises a drain electrode, a source electrode, a gate electrode, a gate oxide layer and a semiconductor epitaxial layer; the semiconductor epitaxial layer comprises an N substrate layer, an N diffusion layer, a P-layer, a P well layer and an N well layer, two grid electrodes are arranged in a single MOS cell and are respectively positioned on the left side and the right side in a grid oxide layer, and the section outline of the grid oxide layer is semicircular; polycrystalline silicon is arranged in the gate oxide layer and located between the two grid electrodes, and the polycrystalline silicon is in ohmic contact with the source electrode. Through the double-gate structure, geometric shape optimization, doping layer design and process innovation, the switching speed, the voltage endurance capability, the thermal stability and the integration degree of the MOSFET are remarkably improved, meanwhile, the leakage current and the on-resistance are reduced, and the MOSFET is suitable for high-performance power devices and high-frequency application scenes.

The invention belongs to the technical field of semiconductors, and particularly relates to a gradient transition composite tantalum carbide coating and a preparation method thereof.The gradient transition composite tantalum carbide coating is located on the surface of a graphite substrate material and sequentially comprises a pyrolytic carbon coating, a tantalum carbide-pyrolytic carbon composite coating and a tantalum carbide coating from inside to outside; wherein the thermal expansion coefficient of the pyrolytic carbon coating is 2.5-4.5 * 10 <-6 > / K, the thermal expansion coefficient of the composite coating is 4.5-6.0 * 10 <-6 > / K, and the thermal expansion coefficient of the tantalum carbide coating is 6.1-8.0 * 10 <-6 > / K. According to the gradient transition structure of the coating, the problem that thermal expansion coefficients between the coating and a base body are not matched is solved, the thermal shock resistance of the coating is effectively improved, meanwhile, the pinning effect can be achieved, the adhesive force between the coatings is enhanced, and the service life of a product is prolonged; compared with a single tantalum carbide coating, crack accumulation and through holes cannot be generated.

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a semiconductor device with an integrated heat dissipation function for a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The single MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, the profile of the cross section of the grid electrode is in an H shape, and the grid electrode comprises two longitudinal parts and a transverse part used for bridging the two longitudinal parts. According to the invention, the H-shaped gate structure is in bridge connection with the double longitudinal grooves through the transverse part, so that the channel width is increased, and the on-resistance is reduced; a current path is further optimized by combining a metal deposition layer and a heavily doped N + layer in the bottom doping layer; and the metal layer is connected in parallel to conduct electricity, so that the resistance is reduced, and the heavily doped N + layer inhibits the JFET effect, so that the resistance is reduced by more than 10%.

The invention belongs to the technical field of semiconductors, and particularly discloses a photoetching hot spot detection method and system based on a graph neural network. The method comprises the following steps: decomposing each polygonal metal in a layout into rectangles by scanning in the horizontal direction, and taking the rectangles as nodes of the layout; adding an internal edge and an external edge between the rectangles according to a specific rule; the diagonal vertex coordinates of the rectangles are used as node features, the minimum distance between the rectangles represents edge features, and graph representation of the layout is completed; inputting the graph representation of the layout into a message passing layer of a GNN model to perform graph feature extraction, and performing global maximum pooling and global average pooling on each dimension of all node features to obtain global graph representation; and classifying the global graph representation into hotspots and non-hotspots. According to the invention, the accuracy and calculation efficiency of layout hot spot detection can be improved.

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses a VDMOSFET (vertical double-diffused metal oxide semiconductor field effect transistor) device with low threshold voltage, which comprises a drain electrode, a semiconductor epitaxial layer, a source electrode, a grid electrode and a grid oxide layer covering the surface of the grid electrode, and is characterized in that an N substrate layer, an N drift layer, an N well layer, a P well layer and a heavily doped P layer are formed in the semiconductor epitaxial layer through ion implantation, the grid electrode comprises a triangular grid electrode and a rectangular grid electrode, the grid oxide layer covering the surface of the triangular grid electrode is in contact with the N substrate layer, and the N drift layer is divided into a left part and a right part by the grid oxide layer. According to the invention, the grid electrode is designed to further comprise the triangular grid electrode, the electric field effect of the grid electrode between the tip part of the triangular grid electrode and the drain electrode is better, but the grid oxide layer wrapped by the triangular grid electrode at the tip part is thicker, so that charges flowing out of the drain electrode gather towards the inside of the heavily doped N layer more quickly along the grid oxide layer; at the moment, more charge flow can be provided in a smaller grid voltage environment.

The invention relates to the technical field of semiconductors, and discloses a glass-based three-dimensional interconnection structure and a packaging framework based on the glass-based three-dimensional interconnection structure, the glass-based three-dimensional interconnection structure comprises a glass plate core, two opposite sides of the glass plate core are respectively a first surface and a second surface; the front rewiring layer is arranged on the first surface; the back rewiring layer is arranged on the second surface; the glass through hole penetrates through the glass plate core, and a base metal interconnection layer is filled in the glass through hole; the base metal interconnection layer extends to the first surface and is electrically connected with the front rewiring layer; and the base metal interconnection layer extends to the second surface and is electrically connected with the back rewiring layer. According to the technical scheme provided by the invention, the technical effects of vertical integration capability, thermal management efficiency, electromagnetic performance and the like can be remarkably improved in a high-frequency and high-integration scene.

The invention provides a wafer testing device capable of being rapidly maintained, and relates to the technical field of semiconductors, the wafer testing device comprises a fixed plate, the fixed plate is provided with a control module, and a power supply module, a probe card, a heating lifting module and at least one testing module which are connected with the control module, and a wafer to be tested is integrally arranged in the probe card. The power supply module is connected with the probe card to supply power to the to-be-tested wafer, a heater and a probe are arranged in the heating lifting module, and the heating lifting module is used for driving the to-be-tested wafer in the probe card to be in contact with the probe and heating the to-be-tested wafer. The test module comprises a bottom plate which is in push-pull connection with the fixed plate along the first direction and a switch array measurement assembly which is arranged on the bottom plate and is in plug-in connection with the bottom plate along the second direction, and the switch array measurement assembly is used for testing different parameters of the to-be-tested wafer when the to-be-tested wafer is in contact with the probe. The switch array measurement assembly is in plug-in connection with the bottom plate, and the bottom plate is in push-pull connection with the fixed plate, thereby facilitating the replacement of the test module, and achieving the quick disassembly and assembly.

The invention relates to the technical field of MOS semiconductors, and discloses a heterojunction-based silicon carbide groove type MOSFET device structure and a preparation process thereof.The heterojunction-based silicon carbide groove type MOSFET device structure comprises a plurality of parallel MOS cells, each MOS cell comprises a drain electrode, a source electrode, a grid electrode and a semiconductor epitaxial layer, and each semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer; a groove is formed in the upper surface of the single MOS cell and located below the grid electrode, an N + layer is deposited in the groove, and the N + layer comprises a left N + layer and a right N + layer. Through the design of the split type left N + layer and the right N + layer in the groove and the combination of the middle N-layer or the middle P-layer filled in the middle, the electric field concentration phenomenon at the bottom of the groove is effectively dispersed, and the electric field peak value at the edge of the N drift layer is further inhibited in cooperation with the right triangle arrangement of the blocking ion bubbles, so that the breakdown voltage and the reliability of the device are remarkably improved, and the reliability of the device is improved. The method is suitable for high-voltage application scenes.

The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof. The preparation method comprises the steps that a substrate is provided, the substrate comprises an SGT device region and a BCD device region which are transversely arranged, and the conduction types of the SGT device region and the BCD device region are different; forming a plurality of deep grooves in the SGT device region and the BCD device region; gate material filling is carried out on the multiple deep grooves, a first voltage-withstanding gate structure and at least one gate filling structure of the SGT device area and a second voltage-withstanding gate structure of the BCD device area are formed, and the first voltage-withstanding gate structure is close to the BCD device area; forming a shield gate structure based on the at least one gate filling structure; and forming a plurality of shallow trench isolation structures arranged at intervals in the BCD device region, wherein the shallow trench isolation structures are located between the first voltage-withstanding gate structure and the second voltage-withstanding gate structure. According to the invention, the process cost of SGT and BCD device integration can be reduced, and the device connection is simplified.

The invention belongs to the technical field of semiconductors, and discloses an image sensor and a manufacturing method thereof. The photoelectric sensing areas are arranged on the substrate, the isolation structures are arranged between the adjacent photoelectric sensing areas on the substrate, and each isolation structure is a grating structure which is formed by stacking a plurality of material layers and has a light blocking effect; the light filtering element is arranged on the photoelectric sensing area; and the grating is arranged on the isolation structure. The imaging performance of the image sensor can be effectively improved.

The invention relates to the technical field of diodes, and particularly discloses a high-temperature superconducting diode structure model which is used for solving the problems that an integrated circuit is high in power consumption and low in speed, and a traditional semiconductor technology is difficult to meet requirements. The semiconductor diode has the problems of power consumption and time delay, the research of the existing superconducting diode mostly focuses on low-temperature superconducting, low working temperature hinders the application and contradicts with the original intention of low power consumption, and the high-temperature superconducting diode which can work in a liquid nitrogen environment is urgently needed, including geometric, material and physical models. The geometric model is provided with a substrate with a superconductive microbridge strip with an asymmetric structure and metal films at two ends, the physical model contains an external magnetic field and current, and electromagnetic transport characteristics are analyzed through simulation modeling; through geometric structure and material selection and physical model setting, electromagnetic transport characteristics are analyzed by using the corrected RCSJ model, the geometric structure of the superconducting micro-bridge strip is optimized, and the problems of power consumption and speed of an integrated circuit are solved.

The invention provides an optical proximity correction method which is applied to the technical field of semiconductors. In the invention, aiming at some special areas in the target layout, such as the condition that only one auxiliary graph can be added between adjacent main graphs, a new auxiliary graph adding mode and the auxiliary graph after shape adjustment are provided; specifically, an initial auxiliary graph with the width equal to that of a main graph is added between adjacent main graphs of a target main graph group, the graph density of the main graphs in a target layout is changed, sparse graphs also have the characteristics of dense graphs, then the added initial auxiliary graph is adjusted, and the graph density of the main graphs in the target layout is changed. And changing the initial auxiliary pattern into a target auxiliary pattern with a plurality of spacing gaps inside, so as to reduce the actual width of the target auxiliary pattern by using the spacing gaps, reduce the light intensity value of diffracted light at the target auxiliary pattern during exposure and development, improve the normalized logarithmic slope of the main pattern, reduce the edge placement error (EPE) and enlarge the process window.

The invention provides a preparation method of a semiconductor structure and the semiconductor structure, and particularly relates to the technical field of semiconductors. The preparation method of the semiconductor structure comprises the following steps: providing an initial semiconductor structure, wherein a metal layer is deposited on the initial semiconductor structure; performing first annealing treatment on the metal layer to generate a metal silicon compound; processing the initial semiconductor structure by using a first cleaning solution, wherein the first cleaning solution is a mixed solution of sulfuric acid, hydrogen peroxide and ferrous ions; processing the initial semiconductor structure by using a second cleaning solution, wherein the second cleaning solution is a mixed solution of hydrochloric acid, hydrogen peroxide and water; and performing second annealing treatment on the metal silicon compound to generate a self-aligned silicide layer. By adopting the preparation method of the semiconductor structure, the removal temperature of the unreacted metal layer can be reduced, the influence and damage of high temperature on the thermal stability of the metal silicon compound are avoided, and the product yield is improved.

The invention belongs to the technical field of semiconductors, and particularly discloses a depletion type GaN device and a preparation method thereof.The depletion type GaN device comprises a source electrode, a drain electrode, a gate electrode, a plurality of gate structures, a field plate unit, a gate connecting assembly, a field plate connecting assembly, a gate driving resistor, a field plate driving resistor, a first dielectric layer and a second dielectric layer; the field plate unit comprises a plurality of field plates; one end of each of the plurality of gate structures is electrically connected with one end of the gate connecting assembly, and the other end of the gate connecting assembly is electrically connected with one end of the gate driving resistor; one end of each of a plurality of field plates of the field plate unit is connected with one end of the field plate connecting assembly, and the other end of the field plate connecting assembly is electrically connected with one end of the field plate driving resistor; the gate driving resistor and the field plate driving resistor are both connected in parallel with the gate electrode. According to the depletion type GaN device, the gate structure and the field plate unit are respectively provided with respective driving loops, so that voltage division adjustment is facilitated.

The invention relates to the technical field of semiconductors, in particular to die bonding equipment and a die bonding method, and the die bonding equipment comprises a bearing table, and a feeding device, a discharging device, a mounting device, a glue dipping device, a transfer table device and a die supply device which are mounted in the bearing table; the feeding device and the discharging device are arranged at the two opposite ends of the bearing table in parallel, the surface mounting device is arranged between the discharging end of the feeding device and the feeding end of the discharging device, the glue dipping device is located on one side of the feeding device, and the glue dipping device and the transfer table device are arranged on the two sides of the surface mounting device respectively. The crystal supply device is located on the side, away from the mounting device, of the transfer table device. A movable main binding head assembly, a first binding head assembly and a second binding head assembly are arranged in the bearing table, the main binding head assembly is arranged on one side of the discharging device, the first binding head assembly is arranged on one side of the feeding device, and the second binding head assembly is arranged on one side of the crystal supplying device.

The embodiment of the invention relates to the technical field of semiconductor manufacturing, in particular to a volume calibration method, a controller and a gas mass flow verification system. Obtaining an accurate second volume verification parameter of the calibration tank when the second pipeline space is in a gas stable state, and calculating an accurate and high-precision second volume of the second pipeline space by combining a first volume verification parameter and a first volume of the calibration tank when the fourth valve is in a closed state; a target mole of gas in the calibration tank is diffused to a target pipeline space, an accurate third volume verification parameter of the calibration tank is obtained when the target pipeline space is in a gas stable state, and a third volume verification parameter of the calibration tank is obtained by combining a first volume verification parameter and a first volume of the calibration tank when a fourth valve is in a closed state; the third volume of the third pipeline space is accurate and high in precision, and the requirement of the semiconductor technology for volume precision is met.

The invention relates to the technical field of semiconductors, in particular to a device integrated with a deep trench isolation structure and a preparation method of the device. The preparation method comprises the steps that a semiconductor structure is provided, the semiconductor structure comprises a substrate, a gate material layer stacked on the surface of the substrate and a mask layer stacked on the gate material layer, and a functional element of the semiconductor device is formed in the substrate; forming a deep trench in the semiconductor structure, wherein the deep trench penetrates through the mask layer and the gate material layer and goes deep into the substrate; the deep trench is filled to form a deep trench isolation structure, the deep trench isolation structure comprises a filling structure, the filling structure is not higher than the surface of the substrate, and the material of the filling structure is a conductive non-metal material; patterning and etching the gate material layer to form a gate structure; and removing the mask layer. According to the invention, the preparation process of the deep trench isolation structure can be integrated into the standard process for preparing the gate structure of devices such as a BCD, the integration process of deep trench isolation is simplified, and the preparation cost is reduced.

The present invention relates to the field of semiconductor technology, and particularly relates to an optoelectronic chip packaging structure, comprising: a substrate, on the upper surface of which a signal transmission layer is provided, and on the signal transmission layer a signal processing layer is provided; the signal transmission layer includes: a first electrical chip, which has a first surface and a second surface, and the first surface faces the substrate, and the second surface faces the signal processing layer; the signal processing layer includes: a signal conversion area and a data storage area; a photonic chip is correspondingly arranged in the signal conversion area, and the photonic chip includes: N*M photon computing units, and each photon computing unit includes: an optical waveguide layer, and a modulation layer located on the optical waveguide layer, and the modulation layer is a phase change material layer or the modulation layer includes a phase change material layer; a second electrical chip is correspondingly arranged in the data storage area, which is used for receiving and storing calculation data. The present invention solves the problems of high preparation difficulty and poor heat dissipation performance of the existing packaging structure.

The invention discloses a simulation test method and device, computer equipment and a storage medium, and relates to the technical field of semiconductors, and the method comprises the steps: carrying out the simulation test of a to-be-tested design, and carrying out the decrement counting of a work clock of the to-be-tested design based on a preset timer; detecting an output result of the to-be-tested design; and if the output result is not detected when the counting is finished, stopping the simulation test of the to-be-tested design. According to the method, whether the to-be-tested design has the abnormal state or not is judged by detecting the output condition of the to-be-tested design in real time, and simulation is automatically stopped if the abnormal condition exists. The overtime detection time does not need to be set, and the management of the test case is simplified, so that the simulation test efficiency is improved, the promotion of the verification task is accelerated, and the problem of easy suspension in the simulation test process is solved.