6055 results about "Semiconductor technology" patented technology

The invention relates to the technical field of semiconductors, and discloses a full-temperature-zone polynomial digital temperature compensation method and system based on an SOI chip, and the method comprises the steps: obtaining the temperature frequency data of a preset temperature zone of a target SOI chip, fitting a full-temperature-zone curve, extracting a critical point of the temperature zone, dividing a segmented compensation interval according to the critical point, and obtaining the temperature frequency data of the preset temperature zone of the target SOI chip; the method comprises the following steps: calculating frequency drift amounts under different voltages to construct a full-automatic test framework, acquiring an environment temperature parameter and an instantaneous temperature value by using the framework, analyzing a temperature compensation vector of a segmented compensation interval, further monitoring a signal frequency interval output by a chip, extracting a phase noise parameter, calculating a frequency offset error amount with a preset value, and calculating the frequency offset error amount. And analyzing an error source, optimizing a polynomial compensation order, and collecting temperature drift suppression data to generate a full temperature region compensation report. According to the invention, the performance stability of the chip in a complex environment can be improved.

The invention provides a third-generation semiconductor device multi-physical field coupling effect dynamic monitoring method and system, and relates to the technical field of semiconductors, and the method comprises the steps: collecting the data of a temperature field, an electric field, a magnetic field and a stress field through a complementary sensor array, constructing a feature tensor, inputting the feature tensor into a pre-trained graph neural network, and extracting a coupling effect dynamic evolution rule; on-line analysis and prediction are carried out by using an adaptive time window and a recurrent neural network, a multi-field coupling correlation degree evaluation model is established, an early warning level is determined according to the deviation between the coupling correlation degree and an early warning threshold value, and device risk evaluation and maintenance suggestions are generated, so that early warning of the failure risk of the semiconductor device is realized.

The invention relates to the technical field of MOS semiconductors, and discloses a silicon carbide thick-bottom oxide layer groove MOS structure and a preparation method thereof, the silicon carbide thick-bottom oxide layer groove MOS structure comprises a plurality of parallel MOS cells, and each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of each MOS cell; the lightly doped N layer is arranged in the middle of the N drift layer, the arc-shaped contour design with the inclined top is introduced to the two sides, the injection area is accurately controlled through the photoetching technology, the phenomenon that the edge electric field concentration of the N drift layer is effectively dispersed is effectively dispersed, in this way, electric field distribution is more uniform, breakdown voltage is improved, and local electric field concentration is reduced; moreover, the contact between the laterally symmetrical P-layer and the N substrate layer enhances the charge balance capability, and reduces the leakage current.

The invention discloses a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with a high-mobility gate oxide layer and a preparation process of the SiC MOSFET device, and belongs to the technical field of semiconductors. Comprising a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of each MOS cell; by optimizing the gate oxide layer preparation process and combining the design of the T-shaped P-layer, the semi-elliptical lightly doped N-type half layer and the like in the device, the interface quality of the gate oxide layer and a semiconductor material is effectively improved, the scattering of a carrier by an interface state is reduced, and meanwhile, due to the synergistic effect of the structures such as the quarter-circle-shaped side symmetric P-layer and the square heavily doped N layer, the performance of the device is improved. The internal electric field distribution and the carrier transmission path of the device are optimized, and the channel carrier mobility is remarkably improved.

The invention relates to the technical field of MOS semiconductors, and discloses a silicon carbide plane MOS device polysilicon gate self-alignment process and a low resistance structure, the silicon carbide plane MOS device polysilicon gate self-alignment process comprises a plurality of parallel MOS cells, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, an N well layer, a P + layer and a P well layer, and the N drift layer comprises a drain electrode, a source electrode and a grid electrode. The height of the P well layer in the single MOS cell is aligned with that of the grid electrode, and the P well layer is located on the left side and the right side of the grid electrode; the N well layer and the P + layer are both located above the grid electrode and the P well layer, and the P + layer is located on the outer side of the N well layer. According to the invention, the height of the P well layer is accurately aligned with the grid electrode, the P well layer is arranged at the two sides of the grid electrode, the design of the T-shaped source electrode is combined, the conduction path is optimized, and when the voltage is applied to the grid electrode, vertical channels are formed at the two sides of the P well layer, so that the path of current flowing from the drain electrode to the source electrode through the N drift layer is shorter and the distribution is uniform.

The invention discloses an irradiation-reinforced SiC super-junction MOS (Metal Oxide Semiconductor) structure and a preparation process thereof, and belongs to the technical field of MOS semiconductors. Comprising a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer; by arranging the lightly doped N layer in the middle of the N drift layer and arranging the laterally symmetrical trapezoidal P-layers on the two sides of the N drift layer, the device can interact with electrons in the N drift layer, accelerate carrier recombination, reduce the influence of redundant carriers on the performance of the device, effectively reduce the performance degradation caused by irradiation, and improve the performance of the device. According to the invention, the concave heavily-doped N layer is formed at the bottom end of the lightly-doped N layer, so that the carrier concentration of the region can be greatly improved, and the conductivity is remarkably enhanced.

The invention belongs to the technical field of semiconductors, and discloses a SiC power semiconductor module with low parasitic parameters and a preparation method. Comprising a SiC power semiconductor chip, a SiC power semiconductor chip substrate cushion block, a positive electrode power terminal, a negative electrode power terminal, an output power terminal, a positive electrode side middle layer cushion block, a positive electrode side ceramic decoupling capacitor, a positive electrode side substrate middle layer cushion block, a negative electrode side middle layer cushion block, a negative electrode side ceramic decoupling capacitor and a negative electrode side substrate middle layer cushion block. A first copper-clad ceramic substrate, a third copper-clad ceramic substrate, a fourth copper-clad ceramic substrate, a second copper-clad ceramic substrate, a first commutation loop middle copper layer and a second commutation loop middle copper layer; according to the invention, a commutation path is provided for the SiC power semiconductor device by using the middle layer copper of the laminated copper-clad ceramic substrate, the concept of mutual inductance offset of double commutation loops is innovatively introduced, and the parasitic inductance of the module is further reduced.

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a semiconductor device with an integrated heat dissipation function for a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The single MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, the profile of the cross section of the grid electrode is in an H shape, and the grid electrode comprises two longitudinal parts and a transverse part used for bridging the two longitudinal parts. According to the invention, the H-shaped gate structure is in bridge connection with the double longitudinal grooves through the transverse part, so that the channel width is increased, and the on-resistance is reduced; a current path is further optimized by combining a metal deposition layer and a heavily doped N + layer in the bottom doping layer; and the metal layer is connected in parallel to conduct electricity, so that the resistance is reduced, and the heavily doped N + layer inhibits the JFET effect, so that the resistance is reduced by more than 10%.

The invention relates to the technical field of MOS semiconductors, and discloses a heterojunction-based silicon carbide groove type MOSFET device structure and a preparation process thereof.The heterojunction-based silicon carbide groove type MOSFET device structure comprises a plurality of parallel MOS cells, each MOS cell comprises a drain electrode, a source electrode, a grid electrode and a semiconductor epitaxial layer, and each semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer; a groove is formed in the upper surface of the single MOS cell and located below the grid electrode, an N + layer is deposited in the groove, and the N + layer comprises a left N + layer and a right N + layer. Through the design of the split type left N + layer and the right N + layer in the groove and the combination of the middle N-layer or the middle P-layer filled in the middle, the electric field concentration phenomenon at the bottom of the groove is effectively dispersed, and the electric field peak value at the edge of the N drift layer is further inhibited in cooperation with the right triangle arrangement of the blocking ion bubbles, so that the breakdown voltage and the reliability of the device are remarkably improved, and the reliability of the device is improved. The method is suitable for high-voltage application scenes.

The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof. The preparation method comprises the steps that a substrate is provided, the substrate comprises an SGT device region and a BCD device region which are transversely arranged, and the conduction types of the SGT device region and the BCD device region are different; forming a plurality of deep grooves in the SGT device region and the BCD device region; gate material filling is carried out on the multiple deep grooves, a first voltage-withstanding gate structure and at least one gate filling structure of the SGT device area and a second voltage-withstanding gate structure of the BCD device area are formed, and the first voltage-withstanding gate structure is close to the BCD device area; forming a shield gate structure based on the at least one gate filling structure; and forming a plurality of shallow trench isolation structures arranged at intervals in the BCD device region, wherein the shallow trench isolation structures are located between the first voltage-withstanding gate structure and the second voltage-withstanding gate structure. According to the invention, the process cost of SGT and BCD device integration can be reduced, and the device connection is simplified.

The embodiment of the invention relates to the technical field of semiconductor manufacturing, in particular to a volume calibration method, a controller and a gas mass flow verification system. Obtaining an accurate second volume verification parameter of the calibration tank when the second pipeline space is in a gas stable state, and calculating an accurate and high-precision second volume of the second pipeline space by combining a first volume verification parameter and a first volume of the calibration tank when the fourth valve is in a closed state; a target mole of gas in the calibration tank is diffused to a target pipeline space, an accurate third volume verification parameter of the calibration tank is obtained when the target pipeline space is in a gas stable state, and a third volume verification parameter of the calibration tank is obtained by combining a first volume verification parameter and a first volume of the calibration tank when a fourth valve is in a closed state; the third volume of the third pipeline space is accurate and high in precision, and the requirement of the semiconductor technology for volume precision is met.

The invention relates to the technical field of semiconductors, in particular to a device integrated with a deep trench isolation structure and a preparation method of the device. The preparation method comprises the steps that a semiconductor structure is provided, the semiconductor structure comprises a substrate, a gate material layer stacked on the surface of the substrate and a mask layer stacked on the gate material layer, and a functional element of the semiconductor device is formed in the substrate; forming a deep trench in the semiconductor structure, wherein the deep trench penetrates through the mask layer and the gate material layer and goes deep into the substrate; the deep trench is filled to form a deep trench isolation structure, the deep trench isolation structure comprises a filling structure, the filling structure is not higher than the surface of the substrate, and the material of the filling structure is a conductive non-metal material; patterning and etching the gate material layer to form a gate structure; and removing the mask layer. According to the invention, the preparation process of the deep trench isolation structure can be integrated into the standard process for preparing the gate structure of devices such as a BCD, the integration process of deep trench isolation is simplified, and the preparation cost is reduced.

The present invention relates to the field of semiconductor technology, and particularly relates to an optoelectronic chip packaging structure, comprising: a substrate, on the upper surface of which a signal transmission layer is provided, and on the signal transmission layer a signal processing layer is provided; the signal transmission layer includes: a first electrical chip, which has a first surface and a second surface, and the first surface faces the substrate, and the second surface faces the signal processing layer; the signal processing layer includes: a signal conversion area and a data storage area; a photonic chip is correspondingly arranged in the signal conversion area, and the photonic chip includes: N*M photon computing units, and each photon computing unit includes: an optical waveguide layer, and a modulation layer located on the optical waveguide layer, and the modulation layer is a phase change material layer or the modulation layer includes a phase change material layer; a second electrical chip is correspondingly arranged in the data storage area, which is used for receiving and storing calculation data. The present invention solves the problems of high preparation difficulty and poor heat dissipation performance of the existing packaging structure.

The invention discloses a simulation test method and device, computer equipment and a storage medium, and relates to the technical field of semiconductors, and the method comprises the steps: carrying out the simulation test of a to-be-tested design, and carrying out the decrement counting of a work clock of the to-be-tested design based on a preset timer; detecting an output result of the to-be-tested design; and if the output result is not detected when the counting is finished, stopping the simulation test of the to-be-tested design. According to the method, whether the to-be-tested design has the abnormal state or not is judged by detecting the output condition of the to-be-tested design in real time, and simulation is automatically stopped if the abnormal condition exists. The overtime detection time does not need to be set, and the management of the test case is simplified, so that the simulation test efficiency is improved, the promotion of the verification task is accelerated, and the problem of easy suspension in the simulation test process is solved.

The invention provides a multifunctional floating gate transistor based on a two-dimensional material heterojunction and a preparation method thereof, and relates to the technical field of semiconductors, and the multifunctional floating gate transistor comprises a substrate which comprises a back gate and a gate dielectric layer which are stacked from bottom to top; the floating gate layer is located on the surface, away from the back gate, of the gate dielectric layer; the tunneling dielectric layers are located on the surfaces, away from the back gate, of the floating gate layer and the gate dielectric layer respectively, and the floating gate layer is covered with the tunneling dielectric layers; the channel layer is located on the surface, away from the substrate, of the tunneling dielectric layer, and the first orthographic projection of the channel layer on the substrate and the second orthographic projection of the floating gate layer on the substrate are at least partially overlapped; the channel layer is also provided with a source electrode and a drain electrode, and a channel region is formed between the source electrode and the drain electrode. The multifunctional floating gate transistor based on the two-dimensional material heterojunction can be used as a nonvolatile memory and has excellent storage capability.

The invention provides a TF-SAW resonator, a preparation method thereof and a filter, and relates to the technical field of semiconductors. The interdigital electrode comprises piston structures, sub-bus bars and metal bumps, the piston structures are positioned at two ends of the acoustic part, it can be understood that the piston structures are arranged at the tail end areas of the acoustic part on the electrode finger strips, and larger sound velocity difference is realized by changing the sound velocity of the tail end areas; therefore, the transverse mode is reflected in different directions to avoid energy dissipation caused by resonance; on a propagation path of a transverse mode, the sub bus bars and the metal bumps are sequentially arranged, clutter interference is eliminated by causing sound velocity difference, so that clutter mode interference is inhibited to the greatest extent, the Q value is improved, the insertion loss flatness in a passband is improved, and the performance of the TF-SAW resonator is further improved.

The invention provides an etching parameter adjusting method and device in MOSFET chip production, and relates to the technical field of semiconductors, and the method comprises the steps: obtaining plasma density distribution data and an etching rate monitoring value of a wafer surface, and dynamically dividing the wafer surface into a plurality of segment independent control units; adjusting a radio frequency power distribution weight, and synchronously adjusting a reaction gas injection parameter; carrying out coupling analysis on the concentration gradient of the etching by-product and the matching degree of the surface morphology of the wafer; and when the deviation of the target value threshold is detected, temperature compensation and air pressure compensation are carried out. According to the method and the device, the technical problem of poor etching precision of the MOSFET chip caused by non-uniform etching rates of different regions in the etching process is solved, and the uniformity of the etching rates is improved through real-time monitoring and dynamic compensation, so that the etching precision of the MOSFET chip is improved.

The invention relates to the technical field of MOS semiconductors, and discloses a vertical D-MOSFET with trench isolation and an improved channel structure and a preparation method, the vertical D-MOSFET comprises a plurality of MOS cells which are parallel to one another, each MOS cell comprises a drain electrode, a source electrode, a grid electrode, a grid oxide layer and a semiconductor epitaxial layer, the semiconductor epitaxial layer comprises an N substrate layer, an N diffusion layer, a P + layer, a P well layer and an N well layer, the profile of the cross section of the grid electrode is triangular, and a polycrystalline silicon covering layer is deposited at the junction of the grid electrode and the gate oxide layer; the profile of the cross section of the gate oxide layer is in a semi-elliptical shape, and the profile of the cross section of the polycrystalline silicon covering layer is in a triangular shape. The section profile of the grid electrode is designed to be triangular, the grid oxide layer is controlled to be in a semi-oval shape, electric field distribution and a carrier migration path are optimized, the triangular grid electrode can reduce electric field concentration at the edge of the grid electrode, and the breakdown risk is reduced.

The invention belongs to the technical field of semiconductors, and discloses a multi-core GPU interconnection architecture and a self-adaptive cache allocation method thereof.The multi-core GPU interconnection architecture comprises a plurality of GPU clusters and a global cluster, the global cluster comprises a global router, a global scheduler, a directory, a memory and a plurality of GPU clusters, each GPU cluster is composed of a plurality of GPU cores, and the GPU cores are arranged in the global router. Each GPU core grain comprises a plurality of independent primary data caches, secondary data caches, a local router and a network interface, and the network interface judges whether a current request is processed by the GPU core grains in a GPU cluster or not according to whether a target address in a target node belongs to the GPU cluster or not, so that a high-level multi-core grain interconnection architecture supporting cross-cluster communication is formed. According to the method, performance is optimized by adapting to different access modes, private and shared cache modes are switched in real time, single data access delay is reduced, the overall system efficiency is improved, and the method is used for a multi-core-particle heterogeneous system with a plurality of GPUs.

The invention relates to the technical field of semiconductors, and provides a method for determining a working curve of a chip, a program product, a storage medium and electronic equipment. The method for determining the working curve of the chip comprises the steps that by running a test case for a target chip, the corresponding minimum working voltage of the target chip at a plurality of target frequency points is obtained, and the minimum working voltage is the minimum working voltage enabling the target chip to correctly execute the test case; and fitting a working curve of the target chip by using the plurality of target frequency points and the corresponding minimum working voltage, wherein the working curve is a curve representing the relationship between the frequency and the minimum working voltage. According to the method, the working curve of the target chip can be simply and efficiently determined, and the minimum working voltage of the target chip under the frequency can be obtained by randomly assigning one working frequency based on the working curve, so that great convenience is provided for obtaining the minimum working voltage of the target chip under different frequencies, and the working efficiency of the target chip is improved. And the method has good universality.

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses a low-on-resistance SiC MOSFET (metal oxide semiconductor field effect transistor) terminal structure, which consists of a plurality of parallel MOS cells, and is characterized in that each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode, a grid electrode and a grid oxide layer, the semiconductor epitaxial layer sequentially comprises an N substrate layer, an N drift layer, a P well layer and an N well layer from bottom to top, P + layers are arranged on the two sides of the P well layer and the N well layer in a single MOS cell, a heavily doped N-layer is formed in the semiconductor epitaxial layer of the single MOS cell through ion implantation, and the heavily doped N-layer is located below the P well layer and is in contact with the P well layer. The heavily doped N-layer is additionally arranged below the P well layer to form a vertical low-resistance path, the uniformity of a grid electric field is destroyed in combination with the conduction P region, suppression of the grid on charge diffusion of a drain is weakened, the conduction resistance is greatly reduced compared with a traditional structure, and then the conduction current is greatly improved.

The invention relates to the technical field of semiconductors, and discloses an edge-emitting semiconductor laser and a preparation method thereof, and the preparation method comprises the steps: forming a current injection region and a passivation layer at the side part of the current injection region on the surface of one side, opposite to an upper limiting layer, of a P-surface contact layer of a laser wafer; the laser wafer is divided into a plurality of laser chips in the vertical direction through a plurality of first cleavage channels and a plurality of second cleavage channels; forming a first P-type metal layer on the surface of the laser chip, the surface of the first cleavage channel and the surface of the first region of the second cleavage channel; forming a second P-type metal layer on the surface of one side of the first P-type metal layer of the laser chip through an electroplating process; the first P-type metal layer in the first region is used for communicating the surfaces of the plurality of laser chips; the laser wafer is cleaved into a plurality of edge-emitting semiconductor lasers. Compared with the prior art, the reliability and the yield of the edge-emitting high-power laser can be improved, and the cost of a preparation process is reduced.

The invention provides a wide bandgap semiconductor heteroepitaxial layer growth process parameter adjustment method and system, and relates to the technical field of semiconductors, and the method comprises the steps: obtaining substrate parameters, constructing a digital twin model, predicting an initial strain evolution trend, and determining an optimal initial process parameter; acquiring multi-source data through an in-situ ellipsometer, a reflective high-energy electron diffraction sensor and an acoustic emission sensor in the growth process, and calculating a strain tensor field and defect density distribution by adopting a deep neural network; layered progressive process parameter optimization is executed; and adjusting the growth process according to an optimization result. According to the method, accurate regulation and control of process parameters can be realized, the defect density is reduced, and the quality of the wide bandgap semiconductor heteroepitaxial layer is improved.

The invention belongs to the technical field of semiconductors, and discloses a method for manufacturing a sigma trench in a semiconductor device, which comprises the following steps of: providing a substrate which comprises a first device region and a second device region; a PMOS (P-channel Metal Oxide Semiconductor) region gate and a PMOS gate mask layer are formed on the first active region of the first device region; exposing the top of the PMOS gate mask layer outside the first device region photoresist layer; depositing a deposition silicon oxide layer on the top of the second device region and the top of the PMOS gate mask layer; removing the photoresist layer in the first device region; etching to remove the natural silicon oxide layer on the surface of the first active region, further etching silicon in the first active region, and forming a U-shaped groove in the semiconductor substrate in the first device region; and carrying out TMAH etching on the U-shaped groove to form a sigma groove. According to the invention, in the process of embedding germanium-silicon into the source and the drain, the height difference between the PMOS and the NMOS is avoided, and the subsequent process is not influenced.

The invention relates to the technical field of MOS semiconductors, and discloses a high-temperature-resistant VDMOS power transistor used in an extreme environment and a preparation method, the high-temperature-resistant VDMOS power transistor used in the extreme environment comprises a plurality of parallel MOS cells, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a grid electrode and a source electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a lower P + layer, a P well layer and an N well layer, side P + layers are formed on the two sides of the single MOS cell and located between the source electrode and the lower P + layer through ion implantation. The side P + layer and the N well layer are distributed in an axial symmetry mode, and the profile of the section formed after the side P + layer and the N well layer are combined is in a shape like a Chinese character'ao '. According to the invention, through the axisymmetric concave deep junction structure formed by the side P + layer and the N well layer, the lateral expansion capability of a depletion region is obviously enhanced, the parasitic resistance of the P well layer is reduced, the conduction path of a parasitic bipolar transistor is blocked by the structure, and the latch-up effect at high temperature is avoided.

The invention discloses a manufacturing method of a semiconductor device, and belongs to the technical field of semiconductors. The manufacturing method comprises the following steps: providing a substrate, forming a dummy gate on the substrate, and forming a hard mask layer on the dummy gate; forming side wall structures on two sides of the dummy gate; forming a contact hole etching stop layer on the substrate, the side wall structure and the pseudo gate, wherein the material of the contact hole etching stop layer is the same as that of the hard mask layer; forming an interlayer dielectric layer on the contact hole etching stop layer, and planarizing the interlayer dielectric layer to the residual preset thickness of the hard mask layer; oxidizing the hard mask layer, a part of the contact hole etching stop layer and a part of the side wall structure to form a surface oxide layer; synchronously removing the surface oxide layer and a part of the interlayer dielectric layer, wherein the surface of the dummy gate is flush with the surfaces of the interlayer dielectric layers on the two sides; and removing the dummy gate to form a metal gate. According to the manufacturing method of the semiconductor device provided by the invention, the height of the formed metal gate can be ensured, the manufacturing process is simple, and the controllability is high.

The present application belongs to the field of semiconductor technology and provides a load port for a wafer pod. To address the problem of lower wafer transfer efficiency caused by limited operational efficiency of load ports, the present application provides said load port for a wafer pod, comprising: a support plate; a first loading module and a second loading module are vertically arranged on the support plate; a control module is simultaneously connected to the first loading module and the second loading module and alternately controls the first loading module and the second loading module to convey wafer pods; the control module is arranged on a first side face of the support plate; and an accommodating space is formed between a second side face of the support plate and the first and second loading modules. The present application improves operational efficiency of the load port by means of the first loading module and the second loading module working in alternation, uninterrupted wafer conveyance by a wafer conveyance mechanical arm among process equipment is implemented, and thereby wafer transfer efficiency is improved.

The invention relates to the technical field of semiconductors, in particular to an ultrasonic transmitting circuit, a chip and an ultrasonic module. The ultrasonic transmitting circuit comprises a first control circuit and a signal generating circuit. The first control circuit is used for outputting a first control signal; the signal generation circuit is used for outputting a driving signal according to the first control signal; the driving signal is used for driving a first booster circuit to output an excitation signal, and the voltage of the excitation signal is higher than that of the driving signal; the excitation signal is used for exciting the ultrasonic transducer to emit ultrasonic waves. According to the embodiment of the invention, the energy of ultrasonic waves emitted by the ultrasonic transducer can be improved, so that the ultrasonic receiving circuit can receive echoes with higher energy, and the sensitivity and the signal-to-noise ratio of ultrasonic detection are improved.

The invention discloses a manufacturing method of a semiconductor structure, which belongs to the technical field of semiconductors, and comprises the following steps: providing a substrate, and sequentially forming a pad oxide layer and a pad nitride layer on the substrate; etching a part of the pad oxide layer, the pad nitride layer and the substrate to form a shallow trench; an insulating medium is deposited in the shallow trench, the insulating medium is planarized for the first time, and the insulating medium is flush with the pad nitride layers on the two sides; performing micro-etching treatment on the pad nitriding layer to form a micro-structure layer, and performing micro-etching by adopting a weak physical sputtering mode; oxidizing the pad nitride layer to form an intermediate oxide layer; equivalently removing the intermediate oxide layer and part of the insulating medium; repeating the micro-etching treatment, the oxidation treatment and the equivalent removal step until the pad nitride layer is removed; and removing the pad oxide layer and a part of the insulating medium. According to the manufacturing method of the semiconductor structure provided by the invention, the phenomenon that the corner edge of the shallow trench isolation structure is sunken can be avoided, and the performance of the semiconductor structure is improved.

The utility model relates to the technical field of semiconductors, in particular to a chip mounter binding head device and a correction mounting system, and the chip mounter binding head device comprises a driving assembly and a suction nozzle assembly. The driving assembly comprises a driving part and a connecting assembly connected with the driving part, the suction nozzle assembly comprises an adsorption assembly and a suction nozzle detachably connected with one end of the adsorption assembly, and the other end of the adsorption assembly is connected with the driving part through the connecting assembly; a hollow cavity with two through ends is formed in the driving part, the suction nozzle is at least partially transparent, an adsorption hole with two through ends is formed in the suction nozzle, the driving part is communicated with the adsorption hole in the suction nozzle through the hollow cavity, and the adsorption assembly and the suction nozzle are located at an opening in one end of the hollow cavity; a first air path is arranged in the connecting assembly, a ventilation module is externally connected to the first air path, a second air path is arranged in the adsorption assembly, and when the suction nozzle is connected with the adsorption assembly, the ventilation module is in air path conduction with the suction nozzle through the first air path and the second air path in sequence.