75 results about "Physical design" patented technology

The invention discloses a distributed parallel computing method and system for physical implementation of a large scale integrated circuit. According to the method, physical design problems of different stages are divided into sub-problems on a host, different division methods are applied to the different stages, then the sub-problems are sent to distributed servers by the host in a network communication mode to be computed, and computing results are sent back to the host. The host and a computing cluster are respectively provided with a servo management program, the program is an impotent component of a distributed computing frame and is in charge of management of distributed computing resources, and management of the distributed computing resources comprises resource allocation, resource recovery and the like. According to the distributed parallel computing method and system for physical implementation of the large scale integrated circuit, the physical design problems of a super-large scale integrated circuit can be solved rapidly and effectively, physical design efficiency of the integrated circuit can be improved greatly, and rapider and more-effective physical design of the large scale integrated circuit can be achieved compared with multithreading computing on a single computer.

Disclosed are methods, systems, and articles of manufactures for implementing physical design decomposition with custom conductivity by identifying custom, incomplete conductivity for an electronic design, partitioning a physical design space multiple non-overlapping cells, and iteratively moving at least some of the nodes of these multiple cells to generate a floorplan or a placement layout until one or more convergence criteria are satisfied while maintaining the custom, incomplete conductivity. The floorplan or a placement layout generated resembles the final floorplan obtained through a floorplanner or the final placement layout through a placement tool without requiring that complete conductivity information be provided to the floorplanner or placement tool.

The invention discloses a method and system for accelerating storage component netlist simulation and a medium, and the method comprises the steps of enabling an original RTL design of a storage subsystem to be integrally replaced with a storage subsystem netlist in a verification environment of the subsystem; register configuration irrelevant to operation of the simulation test program in the memory controller and the memory physical interface is reduced; the clock frequency configured by registers in a memory controller and a memory physical interface is increased to the highest clock frequency tolerable by physical design, and the registers in the memory controller and the memory physical interface are independently configured in a forced assignment mode. The RTL verification environment of the original storage subsystem can be used, the original test case can be inherited, the original correctness checking mechanism is continuously used, and the development cost of the post-simulation verification environment is reduced. According to the method, the register configuration time can be shortened, a large amount of manpower and time cost is saved, the netlist simulation efficiencyis greatly improved, and the project period is shortened.

Methods and systems for fabricating an integrated circuit include training a machine learning model using a training set that includes known physical design layout patterns that are classified according to whether the patterns include a hotspot. It is determined whether an input physical design layout pattern includes a hotspot using the machine learning model. A hotspot localization is generated for the input physical design layout patterns. The input physical design pattern is adjusted to cure the hotspot. A circuit is fabricated in accordance with the adjusted input physical design layout pattern.

The invention discloses a method and a system for judging relevance between integrated circuit performance and complex network characteristics thereof. The method comprises the following steps: carrying out multi-tool physical design on a super-large-scale integrated circuit in a layout and wiring stage in the physical design, i.e., carrying out layout and wiring on an initial circuit by using different tools to obtain completely different layout diagrams and layouts so as to obtain different circuit performances; afterwards, complex network conversion is conducted on the layout diagram and the layout of the circuit, feature parameters of a complex network diagram of the circuit are calculated through a complex network analysis tool, network feature parameter-circuit performance correlation coefficients are calculated according to circuit performance changes and feature parameter changes, and the correlation between the performance of the integrated circuit and the feature parameters of the complex network is judged. According to the invention, the circuit performance and characteristics are not changed in the process of carrying out complex network conversion on the layout diagramand the layout, and the method has transparency.

The invention discloses an integrated circuit floorplanning method based on a best fit heuristic sequence and multi-objective organizational evolution, and belongs to the technical field of physical design floorplanning. The method uses the best fit heuristic sequence for encoding and decoding, is combined with a multi-objective organizational evolutionary algorithm, and is used for solving the very large scale integration floorplanning problem. The method is characterized in that firstly each individual is initialized, then each individual is coded and decoded through the best fit heuristic sequence, and finally, a designed split operator, a designed annexation operator and a designed training operator are used for optimizing the multi-objective organization. Verification results show that the integrated circuit floorplanning method has advantages on two important aspects of methods and effectiveness for evaluating and solving the very large scale integration floorplanning problem, namely, the area utilization ratio and optimal line length of an optimal chip, and the method effectively solves the very large scale integration floorplanning problem and can be expanded to solve other multi-objective organizational optimization problems.

The invention discloses an automatic physical unit insertion method based on original layout planning. The method comprises the steps: S1, expanding the top layer of a chip, and recording the name ofa macro module in a document 1; s2, reading the document 1, and obtaining information of a hard macro unit Box; s3, reporting chip congestion information, and establishing a blocking rectangle Box ata hot spot; s4, recording all Box names and parameters into a document 2; s5, establishing a Box0 array with the distance range from the physical unit to the boundary of the chip; s6, Box1 of the unitspacing range is established at the same position of each Box0; s7, selecting Box4 capable of laying units from each Box1, and finding Box5 with the maximum area from the Box4; s8, calculating a central coordinate of each unit in each Box 5; s9, determining a central coordinate of the blank Box 9 calculation unit in the blank Box 9 calculation unit; s10, deleting the Block and inserting the Blockinto the physical unit; s11, ending is carried out. The method has the advantages of being simple in principle, easy to operate, capable of improving overall physical design efficiency and the like.

The invention discloses an asynchronous circuit physical implementation method and system, and the method comprises the steps: performing a data preparation stage: importing comprehensive data, physical data and a file for interrupting a combinational logic ring; in the design planning stage, inputting an IO pin constraint file; in the layout stage, carrying out false path constraint on IO; in the wiring stage, carrying out global wiring, wiring channel distribution, detailed wiring and wiring repair on the signal lines; in the manufacturability design stage, the antenna effect problem, the chip density non-uniformity problem and the metal density problem are solved; exporting design data, performing post-simulation, and returning to the manufacturability design stage for processing if errors occur in simulation; and performing physical verification on the exported gate-level netlist and the physical layout. The invention provides a novel asynchronous circuit physical implementation scheme, which can realize the physical design of a large-scale asynchronous integrated circuit based on a synchronous design tool, is compatible with the current synchronous circuit design process, and can be widely applied to the technical field of integrated circuits.

Test coverage for a circuit design may be determined by obtaining node testability data and physical location data for each node of a plurality of nodes in the circuit design. A determination is made that one or more low test coverage areas within the circuit design include untested nodes based on the node testability data and the physical location data of each node of the plurality of nodes. Test coverage data is generated for the circuit design including at least an identification of the one or more low test coverage areas.

The invention relates to a low-pass band elimination filter and a low-pass band elimination filter circuit, a low-pass band elimination filter module and a tuning method thereof, which not only can theoretically realize near-pass band suppression requirements, but also can realize physical design in actual processing, and is simple and convenient to process. And meanwhile, the characteristics of ultra wide band and near-passband strong suppression can be considered. Moreover, under the condition that the same difficulty index is achieved, the size is reduced, and the cost is lower. Moreover, each capacitor element is realized by utilizing the conduction band piece, the structural form is simple and reliable, the stability is high, and the consistency is good.

The invention provides a redundant metal filling method, device and equipment, and a computer readable storage medium. The method comprises the steps of obtaining a to-be-filled integrated circuit layout; wherein the time sequence of the integrated circuit layout is converged; screening out a signal path sensitive to the filling metal from a design circuit of the integrated circuit layout; acquiring physical information of the signal path; according to physical design requirements and the physical information, obtaining a customized layer area forbidden to be filled with redundant metal in theintegrated circuit layout; and performing redundant metal filling on areas, except the customized layer area, in the integrated circuit layout. According to the invention, coupling noise between a signal path sensitive to redundant metal filling and the redundant metal filling can be weakened.

The invention belongs to the technical field of integrated circuits, and particularly relates to an instruction transmitting and processing circuit of an RISC processor, wherein the interior of the circuit mainly comprises an instruction fetching module, a pre-decoding module, a decoding module and a scoreboard module, and the external interface comprises an Icache, a register file (RF) and an execution unit; wherein the instruction fetching module is connected with the pre-decoding module, the decoding module and the Icache; the pre-decoding module is connected with the instruction fetching module, the decoding module and the scoreboard module; the decoding module is connected with the pre-decoding module, the instruction fetching module and the execution unit; and the scoreboard module is connected with the pre-decoding module and the execution unit. By adopting the instruction transmitting and processing circuit of the RISC processor, the time sequence performance requirement of instruction transmitting of the RISC processor is effectively met and improved, and the implementation of physical design of the instruction transmitting and processing circuit is facilitated.

The invention provides a chip design method, device and equipment, a readable storage medium and a program product. The method comprises the following steps: determining a second device in a to-be-designed second module having data connection interaction with a first device in a first module; in the first module, arranging the second device in the first module so that an interface of the first device in the first module and an interface of the second device in the first module are located on the same side; and based on data connection interaction between the first device in the first module and the second device in the second module to be designed, connecting an interface of the first device in the first module and an interface of the second device in the first module. The method further comprises the steps of: in the second module, copying a second device in the first module after physical design to serve as a second device in the second module after design, so that the first device in the first module and the second device in the second module after design are in axial symmetry; and disconnecting the interface of the first device in the first module from the interface of the second device in the first module, and connecting the interface of the first device in the first module from the interface of the second device in the designed second module.