17 results about "Physical design" patented technology

This application relates to a clock tree synthesis method and system for reducing the vertical coupling capacitance of the clock tree, belonging to the field of clock tree synthesis technology. The core of the method lies in the fact that, during the clock tree synthesis process in the physical design phase, by using a preset vertical design of the clock tree and a coupling-aware clock tree synthesis optimization cost function, the parasitic coupling capacitance between clock lines and adjacent signal lines in the vertical metal layer is systematically reduced, thereby improving the noise immunity of the clock network and reducing delay uncertainty and dynamic power consumption.

The application discloses a method and device for efficient automatic power consumption optimization of chip physical design, solves the problem that the prior art cannot balance the time cost and optimization effect in design space exploration, realizes efficient exploration of high-dimensional continuous physical design parameters, and thus optimizes design parameters and reduces chip power consumption under the premise of guaranteeing design constraints; the method comprises the following steps: determining physical design parameters and boundaries based on a chip process node, sampling and constructing an initial data set; using a pre-trained large model to establish a small sample power consumption evaluation proxy model through context learning; parameter generation model iterative optimization: generating a candidate parameter combination, inputting the proxy model to obtain predicted power consumption, and updating model parameters until convergence according to the predicted power consumption; after training, the model generates a parameter combination to call an EDA tool to obtain real power consumption, so as to feed back the optimization model, and finally output a chip design with optimized power consumption.

Method and system are provided for performing physical-aware logic synthesis. A synthesis environment receives an RTL design, associated design constraints, and one or more design flow and physical design parameter settings. The RTL design is synthesized into a gate-level netlist while incorporating physical design considerations. A scoring result is computed from a logic synthesis result including the synthesized gate-level netlist to provide a quantitative measure of design quality. In certain aspects, the scoring result includes a scattering metric that evaluates placement density of standard cell instances, rankings across multiple modules, PPA results, and runtime prediction estimates. In further aspects, the design parameters are iteratively adjusted using artificial intelligence, reinforcement learning, or machine learning agents to optimize design quality. The invention enables improved integration of logical and physical design stages at advanced semiconductor process nodes.

The application discloses a chip smoking test method, device, equipment, medium and program product. The method comprises the following steps: obtaining module to be tested requirement information; constructing a module to be tested model according to the module to be tested requirement information; the module to be tested model is a behavior level function model; driving the module to be tested model to a chip to be tested design, and performing a smoking test on the chip to be tested design. On the basis of meeting the quality of integration verification of different IPs on an SoC, the standard of IP area evaluation is met. The smoking test for the chip to be tested design can be performed earlier, the intervention time node of a physical design team is advanced, the research and development cycle can be significantly compressed, and the project research and development progress of the whole chip is accelerated.

This application discloses a computational system for implementing yield improvement tools. It extracts cell characteristics from a physical layout design for integrated circuits, determines the location of empty regions in the physical layout design, and applies electrical design rules for manufacturing integrated circuits to the extracted characteristics to identify cells in the physical layout design that will violate the electrical design rules. The computational system can select fill cells for empty regions based at least in part on the extracted characteristics of cells adjacent to empty regions and the electrical design rules, and insert the selected fill cells into the empty regions of the physical design layout. The computational system can perform a design rule checking operation that applies the electrical design rules to the physical design layout where the selected fill cells have been inserted.

The present application belongs to the technical field of structure optimization design, and discloses a structure topology optimization design method and device, steps are as follows: (1) dividing a physical design domain into a background grid, based on coordinate information of background nodes of the background grid, a sparse filtering matrix is constructed by using a Gaussian kernel function with row normalization; (2) using the sparse filtering matrix to perform front filtering on design variables on the background nodes to obtain a smooth density field, and then obtaining a level set function field; (3) using an adaptive grid subdivision algorithm to cut and locally adaptively reconstruct the level set function field to obtain an analysis grid; (4) interpolating the level set function field to the analysis grid through a sparse global interpolation matrix from the background grid to the analysis grid to obtain a level set function field; (5) projecting the level set function field to obtain a pseudo-density field on the analysis grid nodes, and then obtaining an optimal topology configuration. The present application realizes good boundary smoothness while improving optimization efficiency.

This invention discloses a method, apparatus, device, medium, and program product for chip smoke testing. It includes: acquiring the requirements information of the module under test (DUT); constructing a DUT model based on the DUT requirements information; the DUT model being a behavioral-level functional model; driving the DUT model into the DUT chip design; and performing smoke testing on the DUT chip design. This method meets the standards for IP area evaluation while satisfying the quality requirements for integrating and verifying different IPs on a SoC. It allows for earlier smoke testing of the DUT chip design, advancing the involvement time of the physical design team, significantly compressing the development cycle, and accelerating the overall chip project development progress.

The present technology is related to transistor synthesis optimization during the physical design stage of EDA. Aspects of the present technology introduces new ways to restructure transistor-level netlists, such as by reducing transistor count, for digital circuit designs based on the enumeration of “don't cares” of internal nets. One aspect of the present technology includes connecting internal nets with the same truth table up to don't cares without changing the functionality of the entire circuit. With an additional connection in the netlist, optimization opportunities can be identified that may remove transistors and / or improve placement, routing, and / or timing metrics. Furthermore, optimization opportunities may be further increased by (pre)computing satisfiability don't cares at the inputs of the netlist and observability don't cares at the outputs of the netlist from the environment.

A system and method for determining the criticality of basic sub-components in circuit design are proposed. The determination of criticality values ​​(220) for basic sub-components (e.g., registers) in a logic-level circuit design (210) can be based on input flip-flop factors, input combinational logic factors, and output flip-flop factors. The input flip-flop factors can be based on the number of other registers in the logic-level circuit design (210) that affect the input signals of a given register; the input combinational logic factors can be based on the number of logic gates affecting the input signals; and the output flip-flop factors can be based on the number of other registers in the logic-level circuit design (210) whose input signals are affected by the output signals of a given register. The determined criticality values ​​(220) can be used to set the physical design of the corresponding basic sub-component.

The application discloses an AI-assisted chip layout planning method and system, and belongs to the technical field of integrated circuit physical design. The method comprises the following steps: analyzing RTL code to construct a directed weighted graph; adopting a graph neural network to learn a module importance evaluation rule from the graph, and combining an area constraint to generate a recommended area proportion; analyzing a memory structure to generate a memory placement suggestion matched with a data flow direction; and comprehensively generating a module-level layout placement suggestion based on the above information. The application automatically analyzes a data flow interaction relationship through an AI algorithm, reduces manual intervention, optimizes area allocation and memory layout, speeds up physical design iteration, and improves timing convergence efficiency.

Embodiments of the application disclose a physical layout method, system, device and storage medium of a turn-off power module, and relate to the technical field of chip low-power consumption design, which facilitates to improve layout efficiency and flexibility. The method comprises the following steps: based on a chip physical design file and a power design intention description file, performing a global layout operation on the turn-off power module in the case that a physical voltage domain is not defined in advance, to obtain an initial layout result, the initial layout result comprising coordinates of logic units; dividing a layout area of the turn-off power module into a plurality of power pixel blocks; determining the power pixel blocks in which the logic units are located according to the coordinates, and counting the number proportion of always-on logic units and turn-off logic units in each power pixel block; according to the number proportion, assigning an initial power type to each power pixel block, and generating distributed physical voltage domains corresponding to the always-on logic units and the turn-off logic units, respectively. The application is applicable to the scenario of power-gated physical layout.

This invention relates to a method, system, and storage medium for processor clock tree deskewing and timing optimization. The method for processor clock tree deskewing and timing optimization, through joint timing and topology analysis, automatic candidate copy object identification, and topology-aware logical copying and connection reconstruction, can effectively reduce the fan-out delay of critical signals and achieve clock tree load balancing and deskewing without modifying the RTL code during the back-end design process. At the same time, iterative optimization ensures timing convergence and logical equivalence, thereby improving the efficiency of processor physical design.

The technology involves exploration of design space for photomask patterns that is unconstrained by manufacturability constraints while still yielding photomask patterns that satisfy those manufacturability constraints. A method includes determining a first photomask pattern corresponding to a target physical design of a semiconductor device. Detennining the first photomask pattern is unconstrained by a minimum feature size. Features of the first photomask pattern that are smaller than the minimum feature size are removed to generate a second photomask pattern. A gradient mask is determined based on the second photomask pattern, by setting values of a first set of pixels of a gradient pattern corresponding to boundary pixels of the second photomask pattern to one, and setting values of a second set of pixels of tire gradient pattern to zero. A third photomask pattern is determined based on the gradient mask pattern and the second photomask pattern.

The present application belongs to the technical field of electronic design automation physical design in integrated circuits, and relates to a chip-oriented global routing method based on directed acyclic graph and congestion awareness, which can be used for global routing in chip physical design. The present application innovatively introduces a wire mesh routing sequence strategy based on internal pin density and average congestion density, dynamically gives the most difficult-to-route wire mesh the highest routing priority by scientifically quantifying the internal topology of the wire mesh and the congestion degree of the external environment; a dynamic via punishment mechanism with congestion awareness is proposed, which can obtain the congestion gradient of the underlying grid in real time, and intelligently apply nonlinear vertical layer transition resistance in the congestion hotspot area; an enhanced directed acyclic graph mode routing space is constructed in the underlying engine, and combined with a node cost fast updating algorithm based on dynamic programming, the iteration number of wire breaking and rerouting is reduced, and the time overhead of the super large scale integrated circuit routing link is saved.

The application provides a method for reducing static power consumption in a verification stage of a digital chip physical design. In the verification stage of the digital chip physical design, in addition to optimizing power consumption on a data path, threshold voltage of a standard cell on a clock tree is lowered and a channel length is increased to further reduce static power consumption. The method saves a large amount of time cost without increasing additional chip area, and realizes 5%-10% reduction of static power consumption.

This invention relates to the field of circuit performance testing technology, specifically a method for predicting integrated circuit aging effects and assessing circuit lifetime reliability. The specific implementation process includes: acquiring the physical design netlist and basic process library; parsing the test load into transient flip-flop density and generating a time-varying excitation flow based on layout geometry information; dividing the aging-sensitive region using a dual-track aging differential mechanism; quantifying circuit aging parameters by integrating the time-varying excitation flow; performing full-chip timing simulation on the circuit aging parameters to predict the performance erosion index; calculating the dynamic redundancy shrinkage vector and adjusting the guard band reduction magnitude to converge the evaluation to the target design range. This invention utilizes time-varying excitation flow and sensitivity partitioning topology to effectively capture the multi-physics coupling effect under dynamic loads, improving the prediction distortion problem caused by static assumptions. By optimizing the guard band design through dynamic redundancy shrinkage vector, a balance between chip area, power consumption, and reliability lifetime is achieved.

This invention relates to the field of integrated circuit design and manufacturing, and particularly to a method and apparatus for improving yield in integrated circuit manufacturing. The method involves collecting full-process manufacturing data at the integrated circuit manufacturing end and generating a wafer defect map based on this data. The manufacturing end then extracts graphic features of manufacturing weaknesses from the wafer defect map, constructing a weakness graphic database. This database is then transmitted to the integrated circuit design end, enabling the design end to adjust routing strategies and graphics during the chip physical design routing stage. This avoids weak point graphics in the layout that match the graphic features in the database, resulting in an adjusted routing layout. This invention avoids layout structures prone to manufacturing defects from the design stage, thereby expanding the process window and significantly improving finished product yield.