121 results about "Physical design" patented technology

The invention relates to the technical field of circuit performance testing, in particular to an integrated circuit aging effect prediction and circuit life reliability evaluation method. The specific implementation process comprises the following steps: acquiring a physical design netlist and a basic process library, analyzing a test load into transient upset density, and generating a time-varying excitation flow in combination with layout geometric information; dividing an aging sensitive domain by using a double-track aging difference mechanism, and performing integration processing on the time-varying excitation flow to quantify a circuit aging parameter; performing full-chip time sequence simulation on the circuit aging parameter, and predicting a performance erosion index; and calculating a dynamic redundancy retraction vector, adjusting the reduction amplitude of the guard band, and converging the evaluation in a target design interval. According to the method, the time-varying excitation flow and the sensitivity partition topology are utilized, the multi-physical field coupling effect under the dynamic load is effectively captured, the problem of prediction distortion caused by static hypothesis is solved, and the balance of the chip area, the power consumption and the reliability service life is achieved through the dynamic redundancy retraction vector optimization design protection band.

The invention provides a DFT resource configuration prediction method and device, electronic equipment and a storage medium, and belongs to the technical field of electronic design automation, and the method comprises the steps: determining a reference device density based on a process node of a target chip; determining an effective digital logic layout area based on the chip planning area of the target chip and the estimated non-digital logic function region; according to a utilization rate factor corresponding to the physical design constraint of the target chip, correcting the effective digital logic layout area to obtain an available standard cell layout capacity; according to the standard unit layout capacity and the reference device density, generating a time sequence element number prediction interval of the target chip through a logic depth mapping model; and according to the time sequence element number prediction interval, generating testability design DFT architecture configuration parameters of the target chip. The number of chip registers can be quickly and accurately predicted and the DFT architecture configuration parameters can be generated in the early stage of chip design.

The invention relates to the field of integrated circuit physical design, in particular to an automatic layout wiring method, system and device, a medium and a product. The layout automatic wiring method comprises the following steps that an initial layout file, a corresponding physical design rule file and a function dictionary are input, a physical design rule is converted into a Boolean operation code, and the Boolean operation code comprises an intermediate variable and a Boolean operator; reading a Boolean operation code, finding a corresponding function in the dictionary according to a Boolean operator, substituting the intermediate variable as a parameter, and generating internal design rule data; wiring the initial layout according to the internal design rule data to obtain an initial wiring layout; performing rule violation check on the initial wiring layout, and if violation exists, repairing; and if the violation does not exist, outputting a final wiring layout. The system, the computer equipment, the computer readable storage medium and the computer program product have the same beneficial effects as the layout automatic wiring method.

An interconnect fabric in an integrated circuit (IC) device can be hierarchically partitioned into a set of peripheral sub-fabrics and a glue sub-fabric coupled to each of the peripheral sub-fabrics based on the physical design information associated with the IC device. Each of the peripheral sub-fabrics and the glue sub-fabric can be implemented using 2:1 hierarchical multiplexers based on an agglomerative clustering scheme. Physically aware design of the hierarchical multiplexer tree along with the optimal placement of the 2:1 multiplexers can provide smaller overall wire length and reduced routing congestion in the interconnect.

The invention provides a design rule detection and model training method and device and electronic equipment. The design rule detection and model training method comprises the steps that an initial design rule detection model is constructed; the design rule detection model comprises a multi-scale feature extraction module and an attention mechanism module; acquiring a data set of a design rule detection task; the data set comprises feature mapping and real violation labels corresponding to each feature region in the layout; after a rule detection model is designed to obtain each feature map, a multi-scale feature extraction module and an attention mechanism module are combined to obtain optimized multi-scale features, and the multi-scale features are used to predict prediction violation labels of each feature region; and optimizing parameters of the detection model according to the error between the real violation label and the predicted violation label until the loss function value of the design rule detection model is minimum. According to the method, the violation detection accuracy of a design rule detection model in a complex physical design layout can be improved, and the method has higher robustness and generalization ability in small-scale violation and boundary detail recognition.

Embodiments of the present disclosure provide enhanced systems and methods for predicting optimal design flow parameters for optimized output targets for physical design synthesis of a given IC design. A Variational Autoencoder (VAE) along with a regression network are trained using a dataset comprising synthesis design construction flows from historical IC designs to provide a training data representation of the dataset constrained to a latent space of the VAE. The system generates feature vectors based on the training data representation of the dataset and updates the feature vectors with initial design characteristics of the given IC design. The system iteratively performs an input gradient search of the updated feature vectors to optimize an objective function of the design targets to identify locally optimal design parameters. The system identifies globally optimal design flow parameters for optimized design targets based on locally optimal design parameters.

The invention relates to the field of integrated circuit design and photoetching manufacturing simulation, in particular to a layout violation repair guidance method, layout violation repair guidance equipment, a medium and a product. The layout violation repair guidance method comprises the following steps: inputting an initial layout and a physical design rule to be checked, dividing the initial layout into a plurality of layout blocks, and carrying out physical design rule checking on each layout block; if the design rule violation exists, analyzing graphic attributes around the violation to obtain the cause of the violation; and outputting violation repair guidance information according to the violation cause. And outputting violation repair guidance information of each layout block until all the layout blocks complete rule check. Wherein the graph attributes comprise fixed graphs, access paths of pins and ports, and a wiring network. The electronic equipment, the computer storage medium and the computer program product have the same beneficial effects as the layout violation repair guidance method.

A computing power chip and a physical design method thereof, and a three-dimensional integrated circuit chip, the method comprising: determining a structure and a design level of the computing power chip, the computing power chip comprising a plurality of computing groups arranged along a first direction, each computing group comprising a plurality of computing units arranged along a second direction, the design level comprises a calculation unit layer, a calculation group layer and a top layer from bottom to top, and the first direction and the second direction intersect; in the calculation unit layer, first layout wiring design is carried out on the calculation units, and the calculation units with time sequence convergence are obtained; in the calculation group layer, calling a plurality of calculation units, flattening the calculation units, deleting wires in the calculation units, and carrying out second layout wiring design on the calculation groups to obtain the calculation groups with time sequence convergence; and at the top layer, calling the calculation group, and carrying out third layout wiring design on the top layer to obtain a designed computing power chip.

The application provides a design rule detection and model training method and device and electronic equipment, comprising: constructing an initial design rule detection model; the design rule detection model comprises a multi-scale feature extraction module and an attention mechanism module; obtaining a data set of a design rule detection task; the data set contains feature maps corresponding to each feature area in the layout and real violation labels; after the design rule detection model obtains each feature map, the multi-scale feature extraction module and the attention mechanism module are combined to obtain optimized multi-scale features, and the multi-scale features are used to predict the predicted violation labels of each feature area; the parameters of the detection model are optimized according to the error of the real violation labels and the predicted violation labels until the loss function value of the design rule detection model is minimum. The application can improve the violation detection accuracy of the design rule detection model in a complex physical design layout, and has stronger robustness and generalization ability in the identification of small-scale violations and boundary details.

The present application belongs to the technical field of distributed cooperative control system, and discloses a multi-point high-precision cooperative ignition system for firework display, comprising: a central controller which non-timely distributes delay time stamps to a plurality of distributed ignition modules and broadcasts a content-neutral synchronization event at a starting moment; the distributed ignition module starts a local timer upon detecting the synchronization event and autonomously counts down according to the pre-stored delay time stamp to execute ignition, the present application decentralizes intelligent time decision to the terminal, avoids the interference of signal physical transmission delay on the overall ignition precision of the system, and replaces the complex real-time clock synchronization and delay compensation mechanism in the traditional control system, so that the architecture simplifies the physical design and deployment complexity of the system, and improves the synchronization robustness and scalability when a large number of nodes work cooperatively.

Embodiments of the present disclosure provide enhanced systems and methods for optimal design process parameters for predicting optimal output objectives for physical design synthesis of a given IC design. A variational automatic encoder (VAE) is trained along with a regression network using a dataset that includes an integrated design build stream from a historical IC design to provide a training data representation of the dataset constrained to a potential space of the VAE. The system generates a feature vector based on the training data representation of the dataset and updates the feature vector with initial design characteristics of the given IC design. The system iteratively performs an input gradient search of the updated feature vectors to optimize an objective function of the design objective to identify locally optimized design parameters. The system identifies global optimization design process parameters for optimization design objectives based on the local optimization design parameters.

The invention relates to a computer-implemented design synchronization system for designing a layout of an electronic system. At least two design editors of the system comprise a physical design editor and a logical design editor. The design editors are connected to a design database associated with the unified design model, and the synchronization manager manages design synchronization between the design editors by receiving operations from one of the design editors, updating the operations in the unified design model, and broadcasting the operations to the other design editors. Each of the design editors includes a revocation stack. The revocation stack is to receive operations from users or broadcasts and maintain a sequence of operations tracking respective design editors whereby the design editors perform operations for design synchronization in accordance with operations received from users or broadcasts corresponding to the unified design model. The invention further discloses a computer implementation method for electronic system design synchronization.

This application relates to a clock tree synthesis method and system for reducing the vertical coupling capacitance of the clock tree, belonging to the field of clock tree synthesis technology. The core of the method lies in the fact that, during the clock tree synthesis process in the physical design phase, by using a preset vertical design of the clock tree and a coupling-aware clock tree synthesis optimization cost function, the parasitic coupling capacitance between clock lines and adjacent signal lines in the vertical metal layer is systematically reduced, thereby improving the noise immunity of the clock network and reducing delay uncertainty and dynamic power consumption.

The present application provides a physical design method, device, server and storage medium, which are applied to the field of computer technology. After merging the netlists of the first module and the second module to generate the netlist of the general module, the method performs physical design based on the netlist of the general module, and splits the physical design of the general module into a first module database and a second module database. Finally, physical verification and timing verification are performed on the first module database and the second module database respectively. Compared with the physical design method in the prior art that requires physical design and verification of the first module and the second module respectively, the method reduces one physical design process by merging the first module and the second module into a general module and performing physical design on the general module, and can also simplify the subsequent physical verification and timing verification processes, which helps to improve the design efficiency of integrated circuits.

Integrated circuit (IC) design based on timing slack according to an example includes accessing physical design data for an IC layout, wherein the physical design data comprises a netlist including active metal shapes of a metal shapes infrastructure forming signal path nets connecting different parts of the IC layout. Timing-based design rule checking of the physical design data is performed to identify slack stealing information for the signal path nets. Shape-based density design rule checking of the metal shapes infrastructure is performed, based on the slack stealing information, to perform fill insertion of metal fill shapes to satisfy density requirements in the IC layout.

The invention discloses a time sequence driven macro module layout method, which comprises the following steps of: clustering standard units and macro modules in a circuit netlist to generate a clustering hierarchical tree; abstracting a leaf node cluster of the clustering hierarchical tree into a pseudo macro with a specific area and shape, and generating a global initial layout position of the pseudo macro; aiming at the interior of each cluster, constructing a virtual connection weight model, and solving a relative position relationship of macro modules in the cluster; the intra-cluster macro modules with the relative positions determined are regarded as macro groups, macro group position optimization is carried out, global macro layout is completed, key macro modules are screened out according to a time sequence analysis report, the key macro modules are classified and recognized as array macro or free macro, and position updating is carried out respectively; and then direction optimization is carried out, and a final macro-module layout result is output. According to the method, the layout problem of a large-scale mixed-size circuit can be effectively solved, the layout regularity is kept, meanwhile, the worst negative relaxation and the total negative relaxation are remarkably improved, and the timing convergence of physical design is improved.

The application provides a continuous microfluidic biochip underflow layer physical collaborative design method, which realizes the underflow layer physical design work in three stages.(1) Logic design stage: through the first proposed logic layout and component direction layout adjustment method, the excellent logic position and logic direction of the component are obtained, which greatly improves the efficiency while ensuring the high-quality layout solution.(2) Component mapping and bounding box gap layout adjustment stage: based on the bounding box strategy, the component logic design result of the previous stage is mapped to the actual physical design space, and the best bounding box gap is obtained through the bounding box gap layout adjustment.(3) Shrink layout adjustment stage: based on the connection graph relationship between components, two new layout adjustment methods, namely along-flow channel shrinkage and multi-graph shrinkage, are proposed, which further efficiently improves the quality of the underflow layer physical design. The application not only effectively improves the quality of the underflow layer physical design, but also greatly improves the efficiency.

This invention relates to a method for autonomously controlling a device. The device typically moves in the real world and is not subject to physical design constraints. The advantage of this method is that the device can perform an autonomous learning process and continuously improve the learned knowledge or behavior. It overcomes the disadvantage of prior art methods that require the generation of training data first, which is often the case with traditional artificial intelligence methods. In general, this method is widely applicable, and the device can automatically learn and continuously revise its own knowledge base in the process. Furthermore, the invention also relates to an apparatus designed to implement the method, a system component comprising a plurality of the proposed apparatus, a computer program product, and a computer-readable storage medium that executes the method or causes a computer to execute the method.

The application discloses a method and device for efficient automatic power consumption optimization of chip physical design, solves the problem that the prior art cannot balance the time cost and optimization effect in design space exploration, realizes efficient exploration of high-dimensional continuous physical design parameters, and thus optimizes design parameters and reduces chip power consumption under the premise of guaranteeing design constraints; the method comprises the following steps: determining physical design parameters and boundaries based on a chip process node, sampling and constructing an initial data set; using a pre-trained large model to establish a small sample power consumption evaluation proxy model through context learning; parameter generation model iterative optimization: generating a candidate parameter combination, inputting the proxy model to obtain predicted power consumption, and updating model parameters until convergence according to the predicted power consumption; after training, the model generates a parameter combination to call an EDA tool to obtain real power consumption, so as to feed back the optimization model, and finally output a chip design with optimized power consumption.

Method and system are provided for performing physical-aware logic synthesis. A synthesis environment receives an RTL design, associated design constraints, and one or more design flow and physical design parameter settings. The RTL design is synthesized into a gate-level netlist while incorporating physical design considerations. A scoring result is computed from a logic synthesis result including the synthesized gate-level netlist to provide a quantitative measure of design quality. In certain aspects, the scoring result includes a scattering metric that evaluates placement density of standard cell instances, rankings across multiple modules, PPA results, and runtime prediction estimates. In further aspects, the design parameters are iteratively adjusted using artificial intelligence, reinforcement learning, or machine learning agents to optimize design quality. The invention enables improved integration of logical and physical design stages at advanced semiconductor process nodes.

The present disclosure provides a DFT resource configuration prediction method and device, electronic equipment and storage medium, belonging to the technical field of electronic design automation. The method comprises the following steps: determining a reference device density based on a process node of a target chip; determining an effective digital logic layout area based on a chip planning area of the target chip and a predicted non-digital logic function area; correcting the effective digital logic layout area according to a utilization factor corresponding to a physical design constraint of the target chip to obtain an available standard cell layout capacity; generating a timing element quantity prediction interval of the target chip through a logic depth mapping model according to the standard cell layout capacity and the reference device density; and generating a design for test (DFT) architecture configuration parameter of the target chip according to the timing element quantity prediction interval. The chip register quantity can be quickly and accurately predicted and the DFT architecture configuration parameter can be generated at an early stage of chip design.

Disclosed herein is a method for performing top-down design for optimizing synthesizable FPGA fabrics which eliminates the need for floorplanning and manual buffering by providing a global timing view of the FPGA fabric to the electronic design automation (EDA) tools. This is accomplished by providing the EDA tools with a global timing view spanning multiple tiles. The method restructures the switch-box muliplexers in a unique way to enable the use of powerful static timing analysis (STA) exceptions supported by modern EDA tools to work around the problem of combinational loops and long false paths created by the interconnect mesh in the FPGA fabric.

This application discloses a computational system for implementing yield improvement tools. It extracts cell characteristics from a physical layout design for integrated circuits, determines the location of empty regions in the physical layout design, and applies electrical design rules for manufacturing integrated circuits to the extracted characteristics to identify cells in the physical layout design that will violate the electrical design rules. The computational system can select fill cells for empty regions based at least in part on the extracted characteristics of cells adjacent to empty regions and the electrical design rules, and insert the selected fill cells into the empty regions of the physical design layout. The computational system can perform a design rule checking operation that applies the electrical design rules to the physical design layout where the selected fill cells have been inserted.

The invention relates to an odd number ring violation check optimization method and system based on standard unit adjacent combination, and belongs to the field of integrated circuit physical design verification (DRC) and electronic design automation (EDA). According to the method, all adjacent combinations possibly forming odd rings among standard units are identified in advance before layout, a violation database is established, and a layout tool is guided to avoid using corresponding combinations in the violation database. According to the method, the layout efficiency can be remarkably improved, and later DRC violations are reduced; and through equivalence class merging and symmetric combination merging, a comprehensive violation combination database is provided, a layout tool is guided to make a better decision, and the calculation complexity is greatly reduced.

The application discloses a machine room deployment method, device, equipment, storage medium and computer program product. The method comprises the following steps: acquiring machine room data center basic physical design unit (POD) networking information and machine room parameters; calculating the number of network devices, the number of servers and the target cabinet number of racks according to the POD networking information and the machine room parameters, and constructing a base minimum construction unit; calculating the number of servers that can be carried by the base and the number of racks that are preoccupied by the base according to the port proportion of the network device and the base minimum construction unit, and constructing a standardized base model; and deploying the machine room according to the computing power resource construction demand and the standardized base model. The application can effectively improve the delivery efficiency of the liquid cooling data center computing power resource project construction engineering by the proactive response of the pre-designed standardized base model to the resource demand, and realizes the rapid response and agile delivery of the computing power resource demand under the intelligent computing scene.

The present application belongs to the technical field of structure optimization design, and discloses a structure topology optimization design method and device, steps are as follows: (1) dividing a physical design domain into a background grid, based on coordinate information of background nodes of the background grid, a sparse filtering matrix is constructed by using a Gaussian kernel function with row normalization; (2) using the sparse filtering matrix to perform front filtering on design variables on the background nodes to obtain a smooth density field, and then obtaining a level set function field; (3) using an adaptive grid subdivision algorithm to cut and locally adaptively reconstruct the level set function field to obtain an analysis grid; (4) interpolating the level set function field to the analysis grid through a sparse global interpolation matrix from the background grid to the analysis grid to obtain a level set function field; (5) projecting the level set function field to obtain a pseudo-density field on the analysis grid nodes, and then obtaining an optimal topology configuration. The present application realizes good boundary smoothness while improving optimization efficiency.

This application discloses a computing system implementing a yield enhancer tool to extract characteristics of cells from a physical layout design for an integrated circuit, determine locations of vacant regions in the physical layout design, apply electrical design rules for manufacture of the integrated circuit to the extracted characteristics in order to identify cells in the physical layout design that would violate the electrical design rules. The computing system can select filler cells for the vacant regions based, at least in part, on extracted characteristics of the cells abutting the vacant regions and the electrical design rules, and insert the selected filler cells in the vacant regions of the physical design layout. The computing system can perform a design rule check operation, which applies the electrical design rules to the physical design layout having been inserted with the selected filler cells.

The invention provides a curve-based wiring layer GDSII optimization method and system, a medium, a program and an electronic terminal.The method comprises the steps that initial wiring is generated through a Manhattan type global wiring algorithm to serve as a base line, then the initial wiring is compared with a preset wekpoins graphic library to mark a wekpoins area in the initial wiring, only the wekpoins area is traversed, and the initial wiring is subjected to GDSII optimization; and the right-angle configuration blocks are screened out for curve replacement. Therefore, a wekpoins area is reduced under the condition that global curve wiring is not carried out, and a physical design drawing is consistent with a circuit wiring form of actual wafer photoetching; in addition, compromise among sharp corner electric stress weakening, data increment compression, calculation acceleration or template rapid replacement can be achieved by selecting different curve replacement strategies.

The present disclosure provides a system chip pin assignment method and device, electronic equipment and storage medium, which can perform directional decomposition on a module sequence based on a physical path topology, and obtain a common boundary by intersecting assignable areas of related module boundaries, thereby improving the success rate and automation degree of pin assignment. Meanwhile, by performing logical AND operation on the common boundaries of each instance of a multiplexing module, a general common boundary is obtained, which can realize consistent pin mapping between multiplexing instances under the premise of meeting physical constraints, thereby reducing subsequent maintenance and ECO costs. When the common boundary resource is insufficient, by re-determining the physical path topology and iteratively assigning, a rollback and convergent assignment process is realized, manual intervention is reduced, and the overall efficiency and realizability of SoC physical design are improved.