56 results about "Floorplan" patented technology

Methods for generating a floor plan from a building scan of a building using an electronic computing device are presented, the method including: causing the electronic computing device to receive the building scan; converting the building scan to a floor plan; and refining the floor plan to approximate the building. In some embodiments, the causing the electronic computing device to receive the building scan further includes: extracting information from an input file to obtain a representation of a number of rooms and walls corresponding with the building scan, where the information is selected from the group consisting of: a set of vertices, a set of triangles, and a set of rooms.

Systems and methods for generating wiring diagrams for equipment are disclosed. The system may include at least one processor configured to perform operations that may include accessing a floor plan defining a plurality of rooms, receiving input associating at least one of a plurality of functional requirements with at least one room of the plurality of rooms, and accessing, in a data structure, technical specifications associated with electrical equipment. Operations may include selecting, from the data structure, a plurality of the technical specifications, generatively analyzing the at least one room in conjunction with the functional requirement and the selected technical specifications in order to select a piece of equipment for the at least one room and select an equipment placement location, accessing structural data associated with the at least one room, and generating a wiring diagram for the at least one room using the selected technical specifications and the structural data.

System and methods are disclosed for synthesis of network, such as a network-on-chip (NoC), to generate a network description. The system generates a NoC from a set of physical constraints and performance constraints as well as a set of inputs to a sequencer. The system produces the NoC with all its elements. The resulting output includes placement of the elements on a floorplan of a chip that represents the network, such as the NoC.

There is provided a floorplan visualisation system comprising a visualisation studio; a matrix of ceiling mounted edge-blended overlapping projectors projecting onto a floor surface of the visualisation studio; a controller computer comprising: a user interface; and a video output operably coupled to the matrix of projectors for controlling the video projected from such. In use the controller computer is configured for: receiving floor plan representative data; segmenting the floor plan representation data into a plurality of display segments; and outputting the plurality of display segments to respective projectors, and wherein the controller computer is configured to receiving scale adjustment commands via a scale adjustment control of the user interface and adjusting the scale of the segments to display a floor plan representation on the floor surface to a real world scale.

In one embodiment, a cleaning robot stores multiple floorplans. The robot automatically determines which floorplan it is in by localizing and trying to match its detected environment to the stored map. The best fit is the map for the current floor. If there is no match above a confidence threshold, the robot assumes it is a new floor or the floorplan has changed (e.g., furniture has moved), and the robot initiates a discovery mode to map the floorplan and add it to the robot's memory.

Methods for generating a floor plan from a building scan of a building using an electronic computing device are presented, the method including: causing the electronic computing device to receive the building scan; converting the building scan to a floor plan; and refining the floor plan to approximate the building. In some embodiments, the causing the electronic computing device to receive the building scan further includes: extracting information from an input file to obtain a representation of a number of rooms and walls corresponding with the building scan, where the information is selected from the group consisting of: a set of vertices, a set of triangles, and a set of rooms.

In accordance with a method for generating a trial placement plan for an IC having two or more identical modules, a floor plan reserves a separate area of identical size and shape for each of the identical modules, one of which is designated a “master module” and the others designated “clone modules”. A placement and routing (P&R) tool initially places all of the cell instances of the clone modules at the center of their reserved areas. The P&R tool then employs a conventional placement algorithm to iteratively adjust positions of cell instances of all other modules, including the master module within their reserved areas in a manner that tries to minimize net lengths. The P&R tool copies the placement within the master module area into the clone module areas either after every N>0 iterations of the placement algorithm and / or after the placement algorithm has completed placement for the master module area.

In one embodiment, a cleaning robot stores multiple floorplans. The robot automatically determines which floorplan it is in by localizing and trying to match its detected environment to the stored map. The best fit is the map for the current floor. If there is no match above a confidence threshold, the robot assumes it is a new floor or the floorplan has changed (e.g., furniture has moved), and the robot initiates a discovery mode to map the floorplan and add it to the robot's memory.

A method of generating a floorplan layout of an integrated circuit (IC) that is amenable to implementation in a computer-aided design tool. The method is capable of performing placement and routing processing for the IC while requiring very little information about the specific circuitry used in various functional blocks of the IC. For example, at the time of the placement and routing processing, one or more functional blocks of the IC can be specified as empty functional blocks and / or functional blocks that are only partially rendered in gates.

The invention discloses a temperature-sensitive mixed storage framework and a data distribution strategy of the temperature-sensitive mixed storage framework. The method comprises the following steps: (1) according to a storage component cache and an area model of a (scratch pad memory) SPM, designing floorplans with different cache / SPM capacity ratios; (2) according to a temperature model of an embedded processor, working out cache / SPM usage time t1 / t2 ratios in storage system temperature changing periods aiming at different cache / SPM capacity ratios, choosing a floorplan with the maximal t1 / t2 ratio as a designing scheme; (3) according to the designing scheme obtained from the step (2), designing the data distribution strategy; and under the condition of limiting peak temperature, using a greedy algorithm to achieve the data distributed to the cache or the SPM to obtain shortest data access time.

A method of registering distributed devices includes discovering a plurality of devices at a central panel or server, localizing the devices, and authorizing the devices with a mobile device communicating with the central panel or server. The method also includes registering the devices with the central panel. The model can include verifying link quality with each of the devices before registering the devices with the central panel by comparing signal quality between each device and a central panel with a pre-defined threshold level.

A device comprises at least one pair of excitation electrodes forming a capacitor; a floorplan (e.g., a ground plane); and an electronic circuit. The device comprises at least one control electrode arranged at a distance from the capacitor. A switching circuit, of the device, comprises a switch having an open state and a closed state. The switching circuit is designed to apply, to the control electrode, an electric potential common to the floorplan when the switch is in the closed state. The switching circuit is also designed to leave a floating electrical potential for the control electrode when the switch is in the open state. The electronic circuit is designed to measure the mutual capacitance between the pair of excitation electrodes when the switch is in the open state and when it is in the closed state.

A system and method for estimating a floorplan designs based on feedback to machine learning algorithms to accumulate data for improving future floorplan design estimates and reducing design time.

A SoC interconnect network topology is represented. The corresponding SoC floorplan is divided into windows, which are contiguous and non-overlapping. Within each window a subnetwork of the SoC interconnect network topology is defined that includes links or communication paths between IP blocks in the window as well as links or communication paths that traverse the window. At the shared boundaries of the windows, ports are added and defined as virtual ports. The overall SoC topology can be optimized and synthesized by optimizing each window independently and then incrementally optimizing all links, from end-to-end, that traverse two or more windows. The SoC topology is edited, such as by adding switches, removing switches, and adding and removing switches on routes. An initial location of elements within the floorplan is automatically computed and recommended. Locations can also be edited. Statistical metrics are calculated, including wire length, switch area, SoC area, and maximum signal propagation rate. The SoC overall interconnect network topology is represented by the plurality of windows and the respective subnetworks of each widow. The windows are analyzed and combined and optimized to obtain an overall near-optimal SoC interconnect network topology.

A system, method and program product that utilizes flat pattern based L3GO elaboration in a hierarchical environment to create a nested conventional layout. A system is provide for processing a glyph layout to generate shapes for use in a VLSI (very large scale integrated circuit) design process, including: a hierarchical pattern search system that matches patterns from a pattern library to a set of glyph data, wherein the patterns have dependencies that cross hierarchical design boundaries; and a target shape generation system that selects patterns from a set of matching patterns and generates associated shapes.