44 results about "Floorplan" patented technology

The invention discloses a preparation method of an environment-friendly 3D printing three-dimensional surface floor, which comprises the following steps: S1, drawing a plane drawing of the floor, generating a 3D model of the floor by using a computer, and obtaining all layered structures and arrangement modes for forming the floor; and S2, raw materials for preparing the floor are prepared according to the 3D model of the floor in the S1, the raw materials are conveyed into a 3D printer for 3D printing, and all layered structures for the floor are printed. Through a sustainable raw material system, a formaldehyde-free laminating process, high-precision 3D printing texture forming, a three-layer environment-friendly protection layer, a bio-based edge sealing technology and an internet-of-things intelligent production system, production energy consumption is reduced by 40%, waste is reduced by 50%, closed-loop recovery is achieved, meanwhile, the international environment protection certification is met, the production efficiency is improved by 30%, and the production cost is reduced. And a full-chain green manufacturing scheme for synergistically improving the environmental protection performance, the production efficiency and the product quality is formed, and the double-carbon target requirement is met.

The application provides a multiple layout splitting method, system, medium and program product. First, an initial splitting coloring operation is performed based on a saturation priority strategy to generate an initial layout splitting scheme. Then, the global exploration ability of a tabu search algorithm is utilized, and a preset target function is combined to perform multiple rounds of iteration update operations on an initial conflict node set to generate a multiple layout splitting optimization scheme. For ultimate conflict nodes that cannot be completely eliminated by the tabu search algorithm, a backtracking pruning algorithm is started to maximize the attempt to eliminate all ultimate conflicts to generate a final multiple layout splitting target scheme. The application combines the initial optimization ability of the saturation priority strategy, the global exploration ability of the tabu search algorithm, and the quality guarantee of the backtracking pruning algorithm to realize accurate splitting of multiple layouts, guarantee splitting quality and lithography yield, improve splitting efficiency, reduce computational complexity, and adapt to the needs of multiple layout splitting.

An exemplary method to design an integrated circuit includes generating a first floorplan for an integrated circuit, the first floorplan including a plurality of first rows having a first cell height and a plurality of second rows having a second cell height. Generating the first floorplan includes organizing the first rows and the second rows in a first row pattern. The method also includes modifying the first floorplan based on a predetermined cell density of a plurality of first cells and a plurality of second cells to generate a second floorplan, the first cells having the first cell height and the second cells having the second cell height. Modifying the first floorplan includes organizing a set of first rows and a set of second rows in a second row pattern. The second row pattern has X' first rows and Y' second rows, where X' and Y' are positive integers.

A tool makes modifications to the chip floorplan and the network-on-chip (NoC) elements' position on the floorplan and updates the number and position of the pipeline elements in a pipeline stage automatically, resulting in fewer errors and higher productivity.

A method, performed by a computing system, of designing an integrated circuit includes extracting first process information, first floorplan information, and first power plan information from a power plan of a first process, extracting second process information and second floorplan information from a floorplan of a second process, recognizing a regular wiring pattern of a power line from the power plan of the first process based on the first power plan information, forming a new wiring pattern of the power line according to the second process information and the second floorplan information, and generating second power plan information including the new wiring pattern.

A computer-implemented method of generating a network-on-chip (NoC) topology for an electronic system includes creating a logical description of a plurality of empty sub-networks that connect initiators to targets of an electronic system. The method further includes placing the sub-networks within free space of a floorplan of the electronic system in a desired topology shape; and performing automated topology synthesis to add switches to each of the sub-networks such that the initiators are connected to the targets in accordance with a communication policy.

The memory device includes a die with a first set of planes and a second set of planes. The planes are rectangular in shape with a major dimension and a minor dimension. The die includes a CMOS layer with at least one common peripheral circuitry area, and each of the planes includes a non-common peripheral circuitry area in the CMOS layer. Each plane of the first set of planes is oriented such that its major dimension extends in a first direction, and each plane of the second set of planes is oriented such that its major dimension extends in a second direction that is different than the first direction such that the non-common peripheral circuitry area of each plane is immediately adjacent the at least one common peripheral circuitry area in the CMOS layer.

The invention belongs to the technical field of semiconductors, and discloses a large-piece laminating structure and a laminating method applying the same, the large-piece laminating structure comprises a substrate, cofferdam glue, filling glue and cover plate glass, the cofferdam glue forms a cofferdam structure, the filling glue is coated on the substrate and is located in the cofferdam structure, and the cover plate glass is coated on the cofferdam structure. A plane pattern is formed after coating of the filling glue is completed, the plane pattern comprises a main pattern and corner patterns, the main pattern is located in the center of the cofferdam structure, the shape of the main pattern is consistent with the shape formed by surrounding of the cofferdam structure, the corner patterns are located at all corners of the main pattern, and the corner patterns are smaller than the main pattern. According to the invention, the problem of corner bubbles in a large-piece laminating process is eliminated. Meanwhile, coating can be conducted with the accurate filling glue using amount on the basis of the plane pattern, and the puncture problem caused by too much glue using amount is not prone to occurring.

Devices, systems, methods, and processes for managing network devices through generated predictions and associated confidence levels are described herein. Networks within a floorplan can be operated at full capacity all day in an inefficient way when not adjusted due to traffic patterns and seasonality changes. Data related to the topology of the network, along with historical data can be utilized to generate predictions of various network needs. For example, the overall network throughput capacity needs may be predicted for a series of points in the future. An associated confidence level can be generated as well including one or more confidence intervals. These can be utilized to select a future need for the network and generate a corresponding sustainable network configuration for the network devices and / or their transceivers that can provide sufficient network needs while minimizing the overall power used. This can be automated over time once trust has been established.

Embodiments herein describe a method including receiving an initial chiplet layout, determining chiplet size for improving mask field utilization (MFU) using a plurality of first parameters, determining chiplet placement for improving gross modules per wafer (GMPW) using a plurality of second parameters, and generating an updated chiplet floorplan based on the determined chiplet size and the determined chiplet placement. Machine learning (ML) models are used to generate the optimized updated chiplet floorplan.

The application provides a multiple layout splitting method, system, medium and program product. First, an initial splitting coloring operation is performed based on a saturation priority strategy to generate an initial layout splitting scheme. Then, the global exploration ability of a tabu search algorithm is utilized, and a preset target function is combined to perform multiple rounds of iteration update operations on an initial conflict node set to generate a multiple layout splitting optimization scheme. For ultimate conflict nodes that cannot be completely eliminated by the tabu search algorithm, a backtracking pruning algorithm is started to maximize the attempt to eliminate all ultimate conflicts to generate a final multiple layout splitting target scheme. The application combines the initial optimization ability of the saturation priority strategy, the global exploration ability of the tabu search algorithm, and the quality guarantee of the backtracking pruning algorithm to accurately split the multiple layout, guarantee the splitting quality and the lithography yield, improve the splitting efficiency, reduce the calculation complexity, and adapt to the demand for multiple layout splitting.

A device according to one aspect is provided with an acquisition unit for acquiring an input data set including an outer shape diagram indicating the outer shape of a floor plan and information indicating an installation position of a wireless communication device within the outer shape diagram, and a generation unit for outputting a floor plan diagram having the same outer shape as the outer shape of the floor plan and having an excellent radio wave propagation characteristic, by inputting the input data set to an AI model trained through machine learning using a training data set including a training floor plan diagram having an excellent radio wave propagation characteristic and information indicating an installation position of the wireless communication device within the training floor plan diagram.

Managing a gaming venue floor layout can comprise maintaining a biometric information model and a floor layout model. Biometric information can be received from sensors associated with players in a gaming venue, each player using a gaming system of the gaming venue. The plurality of gaming systems can be physically located in the gaming venue according to a predefined floorplan for the gaming venue. An excitement level for each player of the plurality of players can be rated based on the received biometric information and the biometric information model. A heatmap representing the gaming venue can be created based on the rated excitement level for and a location of each player of the plurality of players in the gaming venue. The predefined floorplan for the gaming venue can be updated based on the created heatmap and the floor layout model.

Systems, methods, apparatuses, and computer program products of a user interface configured for automated generation and optimization of floorplan designs. One method may include automatically generating a plurality of floorplans. At least one of the room's corner offsets is determined after at least one other room's position has been determined. The method further includes scoring a plurality of generated floorplans according to a scoring function; calculating, for at least one generated floorplan, whether it has a path with width at least as large as a number from a door of the respective generated floorplan to an exit; displaying, in an interactive computerized user interface, a subset of the generated plurality of floorplans that has been selected based on the scores of the floorplans; and based upon input from the interactive computerized user interface, transmitting at least one of the generated plurality of floorplans.

A system and method for mapping indoor spaces including a mobile mapping device having a camera; a plan database configured to store 2-D floorplans; and a processor configured to integrate a selected floorplan from the plan database with object data received from the mobile mapping device to create a mountable evacuation sign of a venue. The processor is configured to recognise objects from an image from the camera and anchor the recognised object within a 2-D floorplan.

A package structure can be formed by providing a composite package including at least one semiconductor die and a die frame; attaching the composite package to a package substrate to form a bonded assembly; providing a lid structure including a floor portion, a ceiling portion, a sidewall frame portion laterally surrounding a cavity between the floor portion and the ceiling portion, and a solid block portion extending vertically between the floor portion and the ceiling portion; and attaching the lid structure to the bonded assembly such that a thermal interface material (TIM) layer is interposed between the at least one semiconductor die and the floor portion. The solid block portion does not overlap any area of the at least one semiconductor die in a plan view along a vertical direction.

The invention discloses a method and device for generating an indoor distribution system scheme and electronic equipment, the method is applied to the field of indoor distribution, and the method comprises the steps: obtaining an architectural plane graph, segmenting the architectural plane graph into a plurality of regions, and calculating the region area of each region; determining an initial scheme based on a center-of-gravity method according to the signal coverage requirement, the three-dimensional model constructed by the plurality of regions and the region area of each region; verifying the antenna coordinate information of each area based on multiple dimensions to obtain a first verification result; and verifying the initial scheme based on a plurality of constraint conditions to obtain a second verification result, and generating an indoor distribution system scheme corresponding to the architectural plane graph according to the first verification result, the second verification result and the initial scheme. Through the method and the device, the problem of low generation efficiency of the indoor distribution system scheme caused by high dependence on manual operation and low automation and intelligence degree in the design and auditing process of the indoor distribution system scheme in related technologies is solved.

Various embodiments can include integrated circuits (ICs) and methods for designing integrated circuits (200), such as system on a chip (SOC). Embodiments include methods for planning and producing ICs without communication channels (also referred to as channel-less ICs). Embodiments can include overlay hard macros (210) that support routing and communication designs without requiring dedicated communication channels between functional hard macros, such as cores of a SOC. Various embodiments can include an IC in which one or more interconnect hard macros and wires connecting a first functional hard macro, a second functional hard macro, and the one or more interconnect hard macros are located within a third functional hard macro. In some embodiments, there can be no communication channels between the first functional hard macro, the second functional hard macro, and the third functional hard macro.

A front-end-of-line (FEOL) floorplan of an integrated circuit includes a plurality of FEOL components, a non-rectangle-shaped empty region, a first FEOL dummy, and a second FEOL dummy. The non-rectangle-shaped empty region is located between the FEOL components, and includes a first empty region in a first direction and a second empty region in a second direction perpendicular to the first direction, where the first empty region has a first end connected to the second empty region. The first FEOL dummy is inserted in the first empty region. The second FEOL dummy is inserted in the second empty region. The first FEOL dummy is separated from the second FEOL dummy at the first end of the first empty region.

1. The name of the design product: the graphic user interface of two-dimensional and three-dimensional one-key switching comprehensive display diagram for electronic equipment six-chain flow management platform. 2. The use of the design product: electronic equipment. 3. The design points of the design product: the graphic user interface. 4. The picture or photo that best indicates the design points: design 1 front view. 5. Design 1 is specified as the basic design. 6. The use of the graphic user interface: the graphic user interface of the design is the comprehensive display page of the six-chain flow management platform, and in the management mode and the scheduling mode, the interface can one-key switch the two-dimensional and three-dimensional interface effects. The design 1 front view is the comprehensive display page of the six-chain flow management platform in the management mode, the function switching label is set at the top of the interface, the related information modules are displayed on both sides of the interface, when the user selects the “two-dimensional” label, the mine two-dimensional plan and the detail information are displayed in the middle of the interface, when the user selects the “three-dimensional” label, the mine three-dimensional space graph and the detail information are displayed in the middle of the interface, and the design 1 interface change state diagram is displayed. The design 2 front view is the comprehensive display page of the six-chain flow management platform in the scheduling mode, the function switching label is set at the top of the interface, the related information modules are displayed on both sides of the interface, when the user selects the “two-dimensional” label, the mine two-dimensional plan and the detail information are displayed in the middle of the interface, when the user selects the “three-dimensional” label, the mine three-dimensional space graph and the detail information are displayed in the middle of the interface, and the design 2 interface change state diagram is displayed. In the design 1 front view, the user can also click the “management” label to switch to the design 2 front view. In each view, the character represented by the letter ‘X’ can be replaced, and the number of the letter ‘X’ does not constitute a limitation on the number of replaced characters.

A system and method for mapping indoor spaces including a mobile mapping device having a camera; a plan database configured to store 2-D floorplans; and a processor configured to integrate a selected floorplan from the plan database with object data received from the mobile mapping device to create a mountable evacuation sign of a venue. The processor is configured to recognise objects from an image from the camera and anchor the recognised object within a 2-D floorplan.

Techniques are provided for congestion aware placement of the fabric components of an interconnect in an integrated circuit device. A floorplan of the interconnect is projected on a virtual grid that includes placement locations for the fabric components. Locations of the fabric components can be initialized with the placement locations of the virtual grid. Updated locations for the placement of each of the fabric components on the virtual grid can be determined based on minimization of a total wirelength (TWL) cost function of all the nets in the interconnect. Timing slices are inserted in the interconnect after the placement of the fabric components at the updated locations. The floorplan information with the placement information of the fabric components and the timing slices can be used for the physical design of the interconnect to provide a timing clean result.

The application discloses a four-core CPU chip layout optimization method and system, which comprises the following steps: configuring a command to close a useful skew environment in an IC design system, controlling chip size, placing memory and pin position through overall layout of a floorplan, setting parameters including cell spacing, timing, area and power consumption through a place mode, and placing standard cells; adjusting memory in the overall layout stage of the floorplan through a debug net method according to a place result; repeating the place method and the debug net method, and judging an optimal chip layout strategy according to timing slack, a drv violation and a 'congestion' condition in a timing report, and re-executing the optimal chip layout strategy in a useful skew opening environment.

Systems and methods for floorplan generation using models are disclosed. A system receives a request to generate a floorplan from a user device. The request includes a category placement parameter. The system also obtains a floorplan parameter from a database. The system determines, based on the category placement parameter and the floorplan parameter, the floorplan. The floorplan assigns categories to respective portions of a location represented by the floorplan. The system, in accordance with a determination that the floorplan satisfies an infeasibility criteria threshold, causes the user device to present an error notification that identifies an infeasibility error in at least one of the category placement parameter or the floorplan parameter, and requests, from the user device, at least one of an updated category placement parameter or an updated floorplan parameter.

The invention provides means for generating at least one digital twin of at least one building for its supervision, which comprise a plurality of devices including a first device and a second device, a data storage unit for storing floor plan data content, and a processing unit that is part of the first device. The processing unit is configured to operate modules and / or their related data content, which are being provided, and / or previously provided, by the second device to the first device. The processing unit generates digital twin data content that forms the digital twin of the building from the floor plan data files, for the digital twin to be further included with information collected from the building, for supervision of the building through its digital twin via the first device.

The invention relates to the field of integrated circuit chip rear-end design, in particular to an advanced process standard unit row lattice point layout planning method, which comprises the following steps: S1, module initialization and layout planning; s2, adjusting a macro cell; s3, checking and verifying; and S4, finally adjusting and optimizing. According to the design layout requirement rule of the standard unit, the script provided by the embodiment of the invention is used for quickly and accurately carrying out standard unit row lattice point layout planning on the module; a back-end design implementation engineer only needs to operate the script according to the embodiment of the invention in a module initialization stage and a floorplan design stage to quickly and accurately complete the layout planning of the row lattice points of the standard cell, so that the layout design of the chip standard cell can meet the requirement rule of a FinFET process on the row lattice points of the standard cell; and the back-end layout and wiring design of the chip is ensured to be smoothly advanced, so that the chip can be smoothly tapped out.

Various embodiments relate to a method, apparatus, and machine-readable storage medium including one or more of the following: associating a first floorplan image with a first surface in a three-dimensional scene; associating a second floorplan image with a second surface in the three-dimensional scene, wherein the first surface and second surface are vertically-aligned; rendering a stacked floorplan image of the three-dimensional scene, whereby the stacked floorplan image includes image data read from both the first floorplan image and the second floorplan image; and displaying the stacked floorplan image on the user interface.

Various methods, systems, and / or processes are described herein that can operate on a minimally energized power level to detect motion and paths of motion within an environment. A device suitable for carrying out these operations may include an energization optimization logic which can be responsible for selecting a floorplan, identifying access points associated with the floorplan, determining identities, such as persons, located within the floorplan, and tracking their motion. Once this information is gathered, the logic determines a reduced power configuration and passes it to various access points in the floorplan area to reduce the energy consumption based on the configuration. This allows for energy optimization while still maintaining the tracked motion of the identities within the floorplan. The logic allows for efficient power usage in areas with high traffic flow, while still maintaining the quality of service for the identities within the space, which can change dynamically over time.

An optimal layout of a network-on-chip (NoC) is generated. A plurality of candidate layouts of a NoC are generated from a system on chip (SoC) floorplan, socket locations, address maps, and key performance indicators (KPIs). The candidate layouts have different KPIs. A supervised machine learning (ML) model trained on optimized layouts for different KPIs is used to select one of the candidate layouts as an optimal layout for a given set of KPIs. Channels of the optimal layout are globally optimized to meet NoC requirements.