98 results about "Floorplan" patented technology

Various embodiments relate to a method, apparatus, and machine-readable storage medium including one or more of the following: associating a first floorplan image with a first surface in a three-dimensional scene; associating a second floorplan image with a second surface in the three-dimensional scene, wherein the first surface and second surface are vertically-aligned; rendering a stacked floorplan image of the three-dimensional scene, whereby the stacked floorplan image includes image data read from both the first floorplan image and the second floorplan image; and displaying the stacked floorplan image on the user interface.

Methods, systems, and devices for determination and notification of a location of a building safety system event are described herein. One embodiment includes a method for notifying a user of a fire system event, comprising detecting an event in a building through an event detection device and transmitting information about at least one of the event or the event detection device to a remote server and to a first computing device. The first computing device may include a memory wherein floorplans of each floor of the building are stored. The method may further comprise determining, based on the information and through the first computing device, a floor of the building on which the first event was detected; transmitting a particular floorplan of that floor to the remote server; determining a specific location within the floor at which the first event was detected; generating a visual floor representation, including an indication of the specific location, based on the particular floorplan and the specific location; and transmitting the visual floor representation to a software application comprised of executable instructions stored in the memory of a second computing device to present the visual floor representation to a user.

Various embodiments relate to a method, apparatus, and machine-readable storage medium including one or more of the following: associating a first floorplan image with a first surface in a three-dimensional scene; associating a second floorplan image with a second surface in the three-dimensional scene, wherein the first surface and second surface are vertically-aligned; rendering a stacked floorplan image of the three-dimensional scene, whereby the stacked floorplan image includes image data read from both the first floorplan image and the second floorplan image; and displaying the stacked floorplan image on the user interface.

The invention provides an internal dimension marking method and device for an architectural plane graph, electronic equipment and a storage medium. The method comprises the following steps: acquiring a to-be-labeled architectural plane graph, and identifying a to-be-labeled object in an internal space of the to-be-labeled architectural plane graph; generating a size mark of the to-be-marked object based on a preset mark generation condition, and obtaining a first architectural plane graph; the first architectural plane graph comprises at least one size mark, and each size mark in the first architectural plane graph is located at an initial position; according to the initial position of each size mark, determining the movable range of each size mark; based on the movable range of each size mark, position adaptability scoring is conducted on each size mark, the position with the highest score is determined as the target position of the corresponding size mark, and a target building plane graph is obtained. According to the invention, the readability and aesthetic property of the size marking of the internal space in the building plan can be improved.

Examples describe using a two dimensional floor plan, rather than a three dimensional (3D) reconstruction of a scene, to localize a camera. A floorplan of an environment is accessed and an image of the environment captured by a camera in the environment is received. The image is input to a trained neural network to predict an array of rays from the camera to surfaces in the environment indicated in the floorplan. Using the array of rays it is then possible to compute 3D position and orientation of the camera with respect to the floorplan.

The disclosed computer-implemented method can include defining, by at least one processor, one or more boundary conditions. The method can additionally include importing, by the at least one processor, one or more tiles outlines that at least define importing, by the at least one processor, one or more tiles outlines that at least define a cell hierarchy for one or more chiplets. The method can also include defining, by the at least one processor and based at least in part on the one or more tiles outlines, one or more cells of the one or more chiplets at least in part by automatically filling one or more slave cells of the one or more chiplet with a same bump pattern as a master cell of the one or more chiplets. The method can further include generating, by the at least one processor and based at least in part on the defined boundary conditions and the defined one or more cells, a floorplan and bump placement for a package design. Various other methods, systems, and computer-readable media are also disclosed.

Image data and depth information of at least a portion of a building are received. An edge existence probability mask is generated based on the image data. The edge existence probability mask represents confidence levels associated with identifying each of the one or more edges of a surface in the at least the portion of the building. The edge existence probability mask is optimized using the depth information to obtain an optimized edge existence probability mask. The one or more edges of the surface are then identified based on the optimized edge existence probability mask.

One or more embodiments disclose techniques for generating a layout for a physical space or a building. The techniques include generating a layout based on a floorplan of a physical space, generating a plurality of spatial unit grids corresponding to a plurality of spatial units to be placed in the physical space, identifying a placement for a first spatial unit grid in the plurality of spatial unit grids within the layout by matching a corner cell in the first spatial unit grid with a given available cell in the layout, generating a score associated with the placement for the first spatial unit grid based on one or more placement parameters that define placement constraints for a first spatial unit included in the plurality of spatial units and corresponding to the first spatial unit grid, and placing the first spatial unit grid in the layout based on the score.

The purpose of the present invention is to provide a device and a method with which it is possible to generate a floor plan according to a user's desire.　A reception unit 101 of a prompt generation server 100 according to the present disclosure receives, from a user terminal 500, input information for requesting generation of a floorplan image of a house. Then, a concept information acquisition unit 102 determines concept information of the house on the basis of the input information. Meanwhile, a reference floorplan image acquisition unit 103 acquires a reference floorplan image from a reference floorplan database 400 by using the concept information. A prompt generation unit 104 generates a prompt for indicating generation of a recommended floorplan image by using the concept information and the reference floorplan image.　Thus, a prompt can be generated from inputted images, and a recommended floorplan image can be generated by an image generation model such as DCGAN.

The invention discloses a preparation method of an environment-friendly 3D printing three-dimensional surface floor, which comprises the following steps: S1, drawing a plane drawing of the floor, generating a 3D model of the floor by using a computer, and obtaining all layered structures and arrangement modes for forming the floor; and S2, raw materials for preparing the floor are prepared according to the 3D model of the floor in the S1, the raw materials are conveyed into a 3D printer for 3D printing, and all layered structures for the floor are printed. Through a sustainable raw material system, a formaldehyde-free laminating process, high-precision 3D printing texture forming, a three-layer environment-friendly protection layer, a bio-based edge sealing technology and an internet-of-things intelligent production system, production energy consumption is reduced by 40%, waste is reduced by 50%, closed-loop recovery is achieved, meanwhile, the international environment protection certification is met, the production efficiency is improved by 30%, and the production cost is reduced. And a full-chain green manufacturing scheme for synergistically improving the environmental protection performance, the production efficiency and the product quality is formed, and the double-carbon target requirement is met.

The application provides a multiple layout splitting method, system, medium and program product. First, an initial splitting coloring operation is performed based on a saturation priority strategy to generate an initial layout splitting scheme. Then, the global exploration ability of a tabu search algorithm is utilized, and a preset target function is combined to perform multiple rounds of iteration update operations on an initial conflict node set to generate a multiple layout splitting optimization scheme. For ultimate conflict nodes that cannot be completely eliminated by the tabu search algorithm, a backtracking pruning algorithm is started to maximize the attempt to eliminate all ultimate conflicts to generate a final multiple layout splitting target scheme. The application combines the initial optimization ability of the saturation priority strategy, the global exploration ability of the tabu search algorithm, and the quality guarantee of the backtracking pruning algorithm to realize accurate splitting of multiple layouts, guarantee splitting quality and lithography yield, improve splitting efficiency, reduce computational complexity, and adapt to the needs of multiple layout splitting.

An exemplary method to design an integrated circuit includes generating a first floorplan for an integrated circuit, the first floorplan including a plurality of first rows having a first cell height and a plurality of second rows having a second cell height. Generating the first floorplan includes organizing the first rows and the second rows in a first row pattern. The method also includes modifying the first floorplan based on a predetermined cell density of a plurality of first cells and a plurality of second cells to generate a second floorplan, the first cells having the first cell height and the second cells having the second cell height. Modifying the first floorplan includes organizing a set of first rows and a set of second rows in a second row pattern. The second row pattern has X' first rows and Y' second rows, where X' and Y' are positive integers.

Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.

1. The name of the design product: graphical user interface for automatic design and drawing of building structure (pile cap). 2. The use of the design product: for displaying the graphical user interface of building structure design and drawing system. 3. The design points of the design product: the content of the graphical user interface in the display screen. 4. The picture or photo that best shows the design points: design 1 variation state diagram 2. 5. Design 1 is designated as the basic design. 6. The use of the graphical user interface: for building structure design and drawing system. 7. The human-computer interaction mode of the graphical user interface: mouse or keyboard input, display screen panel output. 8. The variation state description of the graphical user interface: in design 1, the main view of design 1 displays the starting page, clicking the "foundation" button in the main view of design 1 displays design 1 variation state diagram 1, clicking the "pile cap" button in design 1 variation state diagram 1 displays design 1 variation state diagram 2-automatic specification, automatic addition and automatic modification of layout; in design 2, the main view of design 2 displays the starting page, clicking the "foundation" button in the main view of design 2 displays design 2 variation state diagram 1, clicking the "foundation sample" button in design 2 variation state diagram 1 displays design 2 variation state diagram 2-automatic drawing and automatic modification of layout of pile cap plan and section view.

Generating local- and global-walkable paths for route guidance. At least one example is a computer-implemented method of generating comprehensive maps for route guidance, the method comprising: determining, by the computing device, a trigger event occurred; determining, by an application executed on the computing device, an initial location of the computing device; sending, by the application executed on the computing device, to a server an indication of the initial location of the computing device; receiving, by the computing device from the server, a map comprising a floorplan including at least the initial location and a plurality of locations; and presenting, by the application executed on the computing device, the map on a display.

A tool makes modifications to the chip floorplan and the network-on-chip (NoC) elements' position on the floorplan and updates the number and position of the pipeline elements in a pipeline stage automatically, resulting in fewer errors and higher productivity.

A method, performed by a computing system, of designing an integrated circuit includes extracting first process information, first floorplan information, and first power plan information from a power plan of a first process, extracting second process information and second floorplan information from a floorplan of a second process, recognizing a regular wiring pattern of a power line from the power plan of the first process based on the first power plan information, forming a new wiring pattern of the power line according to the second process information and the second floorplan information, and generating second power plan information including the new wiring pattern.

The present application provides a method, device, electronic device and storage medium for determining a 5G indoor distribution solution, and relates to the field of communication technology. The method includes: obtaining the building information of the target building, the building information includes: the floor plan of each floor, the number of floors, the floor height and the number of elevators; determining the material list corresponding to all floors according to the floor plan of each floor and the pre-established antenna coverage standard block and the number of standard antennas required for 5G indoor distribution antenna coverage; determining the material list corresponding to all elevators according to the number of floors, floor heights and the number of elevators; determining the material list corresponding to the signal source trunk line according to the number of floors and floor heights; accumulating the material lists corresponding to all floors, all elevators and signal source trunk lines to obtain the 5G indoor distribution solution of the target building. The present application can quickly calculate the equipment and materials required for the 5G indoor distribution solution based on the building information of the target building, thereby improving the construction efficiency of the 5G indoor distribution system.

Cells in a superconducting electronics (SCE) netlist may be levelized. The SCE may use multiple clock phases, and each level in the levelized SCE netlist may be associated with a clock phase. Buffers may be inserted in the SCE netlist so that output ports of the SCE netlist are associated with the same clock phase. A floorplan may be created for the SCE netlist. A placed SCE netlist may be generated based on the floorplan, where cells in each row of the placed SCE netlist may be clocked using the same clock phase.

Systems, devices, and methods may provide technology that determines multiple transient thermal responses for corresponding multiple energy source positions on a semiconductor die, obtains Corner Block List (CBL) representations associated with multiple candidate floorplans, and performs an artificial intelligence (AI)-based search of the CBL representations, wherein an output of the AI-based search is one or more proposed floorplans having a transient thermal response that is below a thermal threshold.

A computer-implemented method of generating a network-on-chip (NoC) topology for an electronic system includes creating a logical description of a plurality of empty sub-networks that connect initiators to targets of an electronic system. The method further includes placing the sub-networks within free space of a floorplan of the electronic system in a desired topology shape; and performing automated topology synthesis to add switches to each of the sub-networks such that the initiators are connected to the targets in accordance with a communication policy.

A three-dimensional (3D) memory includes a first semiconductor structure having a 3D memory array, wherein the 3D memory array includes a plurality of memory planes, and a second semiconductor structure having a plurality of page buffer circuits, wherein each memory plane has a plurality of bit lines oriented in a bit line direction, a memory-plane-boundary, and a fixed location on the first semiconductor structure, each page buffer circuit has a page-buffer-circuit-boundary, the first semiconductor structure and the second semiconductor structure are bonded to each other in a face-to-face orientation, and a first memory-plane-boundary of a first memory plane, and a first page-buffer-circuit-boundary of a first page buffer circuit, are vertically aligned with each other such that a first portion of the first page-buffer-circuit-boundary is offset from the first memory-plane-boundary in the bit line direction so as to be non-overlapping with an area defined by the first memory-plane-boundary.

The memory device includes a die with a first set of planes and a second set of planes. The planes are rectangular in shape with a major dimension and a minor dimension. The die includes a CMOS layer with at least one common peripheral circuitry area, and each of the planes includes a non-common peripheral circuitry area in the CMOS layer. Each plane of the first set of planes is oriented such that its major dimension extends in a first direction, and each plane of the second set of planes is oriented such that its major dimension extends in a second direction that is different than the first direction such that the non-common peripheral circuitry area of each plane is immediately adjacent the at least one common peripheral circuitry area in the CMOS layer.

The present invention relates to a computer-implemented design synchronizing system (1) for designing floorplan of electronic systems. The system (1) characterized by at least two design editors comprise of a physical design editor (11) and a logical design editor (12), the design editors (11, 12) are connected to a design database associated with a unified design model (14), and a synchronization manager (13) manages design synchronization among the design editors (11, 12) by receiving an action from one of the design editors (11, 12), updating the action in the unified design model (14), and broadcasting the action to other design editor, wherein each of the design editors (11, 12) comprises an undo stack (15, 16) to receive an action from a user or broadcast, and to keep track a sequence of actions of the respective design editor, whereby the design editors (11, 12) perform an action according to the action received from the user or broadcast corresponding to the unified design model (14) for design synchronization. A computer-implemented method for design synchronization of electronic systems is also disclosed herein.

The invention belongs to the technical field of semiconductors, and discloses a large-piece laminating structure and a laminating method applying the same, the large-piece laminating structure comprises a substrate, cofferdam glue, filling glue and cover plate glass, the cofferdam glue forms a cofferdam structure, the filling glue is coated on the substrate and is located in the cofferdam structure, and the cover plate glass is coated on the cofferdam structure. A plane pattern is formed after coating of the filling glue is completed, the plane pattern comprises a main pattern and corner patterns, the main pattern is located in the center of the cofferdam structure, the shape of the main pattern is consistent with the shape formed by surrounding of the cofferdam structure, the corner patterns are located at all corners of the main pattern, and the corner patterns are smaller than the main pattern. According to the invention, the problem of corner bubbles in a large-piece laminating process is eliminated. Meanwhile, coating can be conducted with the accurate filling glue using amount on the basis of the plane pattern, and the puncture problem caused by too much glue using amount is not prone to occurring.

1. Name of the Design Product: Graphical User Interface for Editing and Generating Floor Plan of Electronic Device 2. Use of the Design Product: For an electronic device 3. Design Key Points of the Design Product: Lies in the graphical user interface 4. Picture or Photograph Most Indicating the Design Key Points: Front View of Design 1 5. The electronic device has a conventional design, and other views of the electronic device are omitted 6. Design 1 is designated as the basic design 7. Use of the Graphical User Interface: For editing and generating floor plan in room measurement scenario and viewing legend 8. Human - computer Interaction Method of the Graphical User Interface: In the front view of Design 1, click on the lines representing doors and windows in the floor plan in the middle of the interface, and the interface jumps to the first interface change state diagram of Design 1; in the first interface change state diagram of Design 1, click on the "Edit Elevation" button on the pop - up window corresponding to any door or window, and the interface jumps to the second interface change state diagram of Design 1; in the front view of Design 2, click on the "Legend" button at the bottom of the interface, and the interface jumps to the interface change state diagram of Design 2; "XXX" in the above interfaces represents replaceable text and / or numbers, and the gray color blocks represent replaceable content images

Devices, systems, methods, and processes for managing network devices through generated predictions and associated confidence levels are described herein. Networks within a floorplan can be operated at full capacity all day in an inefficient way when not adjusted due to traffic patterns and seasonality changes. Data related to the topology of the network, along with historical data can be utilized to generate predictions of various network needs. For example, the overall network throughput capacity needs may be predicted for a series of points in the future. An associated confidence level can be generated as well including one or more confidence intervals. These can be utilized to select a future need for the network and generate a corresponding sustainable network configuration for the network devices and / or their transceivers that can provide sufficient network needs while minimizing the overall power used. This can be automated over time once trust has been established.

Embodiments herein describe a method including receiving an initial chiplet layout, determining chiplet size for improving mask field utilization (MFU) using a plurality of first parameters, determining chiplet placement for improving gross modules per wafer (GMPW) using a plurality of second parameters, and generating an updated chiplet floorplan based on the determined chiplet size and the determined chiplet placement. Machine learning (ML) models are used to generate the optimized updated chiplet floorplan.

The invention relates to the technical field of electrical design, and discloses a method and a device for calculating the piping and wiring work amount of an electrical system loop, aiming at solving the problem of low efficiency and accuracy of the existing scheme, and the scheme mainly comprises the following steps: automatically extracting loop parameters and calculation parameters corresponding to each loop from a system diagram of the electrical system loop; constructing a mapping relation; constructing a bridge three-dimensional model of the building, and determining bridge primitives in the planar graph; automatically extracting pipeline primitives in the planar graph according to the primitives of the starting point distribution box, and marking the extracted pipeline primitives as required piping; determining a bridge starting point and a bridge ending point in the plane graph; determining an optimal bridge path between the bridge starting point and the bridge ending point based on an optimal path algorithm, and marking bridge primitives contained in the optimal bridge path as not needing piping; and according to the marked pipeline primitives and bridge primitives, calculating the piping and wiring work amount in combination with the corresponding calculation parameters. According to the invention, the efficiency and the accuracy of the piping and wiring work amount calculation are improved.