279 results about "Hierarchical design" patented technology

The present invention relates to a method for efficiently performing hierarchical design rules checks (DRC) and layout versus schematic comparison (LVS) on layout areas of an integrated circuit where cells overlap or where a cell and local geometry overlap. With the present invention, a hierarchical tree describes the integrated circuit's layout data including cells having parent-child relationships and including local geometry. The present invention performs efficient layout verification by performing LVS and DRC checking on the new portions of an integrated circuit design and layout areas containing overlapping cells. When instances of cells overlap, the present invention determines the overlap area using predefined data structures that divide each cell into an array of spatial bins. Each bin of a parent is examined to determine if two or more cell instances reside therein or if a cell instance and local geometry reside therein. Once overlap is detected, the areas of the layout data corresponding to the overlap areas are selectively flattened prior to proceeding to DRC and LVS processing. During selective flattening of the overlap areas, the hierarchical tree is traversed from the top cell down through intermediate nodes to the leaf nodes. Each time geometry data is located during the traversal, it is pushes directly to the top cell without being stored in intermediate locations. This provides an effective mechanism for selective flattening.

A method for modeling integrated circuit designs in a hierarchical design automation system which utilizes a block abstraction including therein set of all database objects (cells, nets, wires, vias, and blockages) that are necessary to achieve accurate placement, routing, extraction, simulation, and verification of the block's ancestors in the hierarchy.

A method of routing a random logic macro (RLM) that is used multiple times in a hierarchical VLSI design without having to route each individual instantiation independently. Once an RLM has been routed and timed it can be copied and reused in a physical design as is, and does not require any wiring changes. This method is an advantage over existing art because it conserves area, improves wireability, and reduces the time required for routing and timing each RLM instance. Furthermore, each RLM possesses the same timing and power characteristics, which improves overall circuit performance.

The invention discloses a high-precision dynamic map data processing system and method based on road side sensors. The high-precision dynamic map data processing system comprises a map data acquisition terminal and a high-precision map generation service terminal. The map data acquisition terminal provides a bulk of diversified map road original data for the high-precision map generation service terminal; the high-precision map generation service terminal comprises a map data processing module and a map generation visual module; the map data processing module is used for extracting road features from the map road original data and carrying out hierarchical design on all the road features, splicing information of the same road, completing road feature data fusion on the road feature aspect first, finally completing image splicing on the image aspect, and generating a road downward projection drawing in dependence on the splicing result; and the map generation visual module is used for marking road information on the downward projection drawing, the marked road information and the downward projection drawing commonly form map data of a high-precision map, visual editing is carried out on the map data, and a high-precision dynamic map is generated. According to the invention, the generation cost of the high-precision map can be reduced, and the high-precision dynamic map can be updated quickly.

Features are provided for graphically representing constraints on design objects in an Electronic Design Automation tool. A particular constraint on one or more circuit objects is displayed as a highlighted region that extends to each visible circuit object to which the constraint applies. Attributes of the highlighted region, such as density and thickness, may proportionally represent attributes of the constraint, such as a strength or distance specified by the constraint. The highlighted region is superimposed on or around circuit objects. The highlighted region may be a halo, which is a partially transparent region filled with a color. Multiple regions that represent the same type of constraint or relationship are connected by line segments, providing the ability to visualize groups of constrained objects, including groups that span levels of a hierarchical design. Intersecting highlighted regions are blended together using techniques such as alpha blending.

CAD software for automated circuit design provides improved display of hierarchical layout. Component placement perimeters are shown with "amoeba" characteristic for improved circuit floor-planning and analysis. Amoeba view of hierarchical design perimeter enables more intuitive observation of circuit floor-plan from actual component placement. Informational brevity conveyed by perimeters of hierarchies in design facilitates simpler interpretation of complex circuit layout, as well as distributed data access to remote sites through email or low-speed network.

A method for formulating an exposure dose for an electron beam on a resist film for a pattern of geometric shapes which compensates for electron scattering effects utilizing hierarchial design data which is preserved to as great as an extent as possible in the computation of the exposure dose. The exposure dose is corrected for both the forward scatter and backscatter effects of the electron beam in which the design data is modified for interactions of shapes which are affected only over the forward scatter range. In another version of the method, a multiple Gaussian approximation is used where the short term Gaussian terms are treated as the forward scatter terms and the long term Gaussian terms are treated as the back scatter terms.

The invention discloses a CDN bandwidth scheduling system comprising a CDN node, a monitoring center, a scheduling subsystem and a scheduling center, wherein the monitoring center obtains machine room quality information of the CDN node and sends the machine room quality information to the scheduling center; the scheduling center calculates a machine room bandwidth quota of each machine room according to obtained machine room cost information, the machine room quality information and service quality information; and the scheduling subsystem updates a scheduling strategy according to a user request number, user bandwidth flow and the machine room bandwidth quota sent by the scheduling center. According to the CDN bandwidth scheduling system, the scheduling center is set to achieve the decoupling of CDN bandwidth scheduling and service scheduling via a hierarchical design, the scheduling subsystem provides the scheduling of service demands, the scheduling center controls the bandwidth quota of the scheduling subsystem while taking both of the quality and the cost into account, and thus the overall quality and cost are optimal.

The present invention provides a systematic automated procedure for routing connections in display applications such as a network topology interface. In one embodiment, the invention first creates an “ideal routing” between two given nodes. The ideal routing includes three segments that join the nodes. If any obstructions exist on the original segments of the ideal routing then the procedure systematically reroutes the appropriate segments to achieve an efficient, visually cohesive and organized routing. The routing procedure operates at different layers, groups and subgroups of nodes. By using the procedure with a layered design it is possible to achieve fast, uniform and effective routing in very complex systems with many nodes and inter-node connections.

In one embodiment, a method of designing an integrated circuit is disclosed, including receiving a first partition block for a top level of a hierarchical design of an integrated circuit; analyzing each pin of the first partition block for an attribute associated with the pin indicating a timing exception; and if a timing exception other than false path is indicated then generating an internal timing pin in a first timing graph model of the first partition block for each timing exception, and adding a timing arc and a dummy arc coupled to the internal timing pin in the first timing graph model of the first partition block. The internal timing pin adds a timing exception constraint for each timing exception. Timing of the top level may then be analyzed with the first timing graph model to determine if timing constraints, including the added timing exception constraints, are met.

Embodiments of the present invention provide methods and apparatuses for implementing hierarchical design-for-test (DFT) logic on a circuit. The hierarchical DFT logic implements DFT circuitry that can be dedicated to a module, and which can configure DFT circuitry for multiple modules to share a sequential input signal and/or to share a sequential output signal. During operation, the DFT circuitry for a first module can propagate a bit sequence from the sequential input signal to the DFT circuitry of a second module, such that the bit sequence can include a set of control signal values for controlling the DFT circuitry, and can include compressed test vectors for testing the modules. Furthermore, the DFT circuitry for the second module can generate a sequential response signal, which combines the compressed response vectors from the second module and a sequential response signal from the DFT circuitry of the first module.

An integrated automatic test system of a on-board computer of a civilian airliner, which comprises a test controller, a test instrument collection, a switching system, and a signal interface device, wherein the test controller is connected with the test instrument collection and the switching system through an instrument control bus; the test instrument collection and the switching system are connected with the signal interface device; the signal interface device is used for being connected with a to-be-tested object of on-board electronic equipment of the to-be-tested civilian airliner; the test controller comprises a test module, a test management module, a test function library module, a driver module, and an operating system module; the test module, the test management module, the test function library module, the driver module, and the operating system module are classified into five levels during operation. The integrated automatic test system adopts the modularized design in the hardware architecture and the hierarchical design in the software architecture, so as to allow the modification and the extension of hardware and software to be more convenient, facilitate the improvement of resource reusability of the test system, and low the cost.

The invention discloses a system for simulating and training the program control of an air traffic control. The system comprises a simulation server, a comprehensive application server, a switchboard, a technology monitoring position, a training master control position, at least one training unit, an inner telephone and a display device. By using the system disclosed by the invention, the control on-duty environment can be realistically simulated, the united simulation training of an area, a zone and an airport can be realized, the working procedure of each link of the program control can be fully trained, the control process can be comprehensively understood by a control person, and the control program can be comprehensively mastered by the control person. According to the system disclosed by the invention, a network adopts a hierarchical design, the network design is simplified, the detection and the removing of primary fault are realized; and a dual-network design of a voice network and a data network is adopted, the training command transmission is reliable, the data traffic of the data network is simultaneously reduced to a large extent, and the low-delay and less-vibration performance of voice transmission is solved by the independent voice network. The invention also provides a training method of a single training mode, a control on-duty mode and a united control on-duty mode of the system for simulating and training the program control of the air traffic control.

A system and method are disclosed for legalizing a flat or hierarchical VLSI layout to meet multiple grid constraints and conventional ground rules. Given a set of ground rules with multiple grid constraints and a VLSI layout (either hierarchical or flat) which is layout-versus-schematic (LVS) correct but may not be ground rule correct, the system and method provide a legalized layout which meets the multiple grid constraints while maintaining LVS correctness and fixing the ground rule errors as much as possible with minimum layout perturbation from the input design. The system and method support multiple grid pitch constraints for hierarchical design, and provide for LVS correctness to be maintained while an on-grid solution possibly with some spacing violations.

The invention discloses a smart car provided with an Ethernet gateway with a back configuration function. The smart car comprises six CAN bus interfaces, four Ethernet interfaces and the Ethernet gateway with an integrated TBOX, the Ethernet gateway comprises a power supply module interface, an IO module interface, an RF front end, a MCU, an ARM7 Cortex, a CAN module interface, an Ethemet 100 BaseTX and an Ethemet Switch 100BaseT1; the Ethernet gateway has the back configuration function, and under the circumstance of ensuring that hardware is the same, gateway routing software is subjected tohierarchical design; when the signal requirements are changed, a requirement changing list is imported to generate an HEX file through configuration software, configuration information is downloadedto the gateway software to quickly respond to changes of the requirements, and it is avoided that software needs to be repeatedly developed and verified.

Tracing a short as a shortest path of explicit VLSI design component instances between two VLSI design component instances with different net names in a hierarchical design is a non-hierarchical problem. The method described in this document computes a shortest path of VLSI design leaf component instances containing at least one of the leaf design components causing the sort. To avoid exceeding available storage, the non-hierarchical instance information maintained during the process is pruned optimally. To achieve feasible performance, two methods to find "good" starting points are provided, based on geometrical distribution or based on connectivity information from the net build (if available).

A system, method and program product that utilizes flat pattern based L3GO elaboration in a hierarchical environment to create a nested conventional layout. A system is provide for processing a glyph layout to generate shapes for use in a VLSI (very large scale integrated circuit) design process, including: a hierarchical pattern search system that matches patterns from a pattern library to a set of glyph data, wherein the patterns have dependencies that cross hierarchical design boundaries; and a target shape generation system that selects patterns from a set of matching patterns and generates associated shapes.

The invention relates to a layered design method of a model-based automatic transmission software development platform. The software development platform is divided into three layers, namely a model application layer, a hardware abstraction layer and a bottom-layer driving layer, wherein the hardware abstraction layer is used for jointing the model application layer and the bottom-layer driving layer; an automatic transmission control strategy is characterized by modelling, emulating and testing by a model development tool, automatically generating C codes and converting the C codes into an application layer software module to form the model application layer; the model application layer carries out data exchange by using the hardware abstraction layer and realizes access of bottom-layer platform data and corresponding operation by a joint function; the bottom-layer driving layer carries out controller area network (CAN) driving, analogue/digital conversion, digital input and output, and own function and state monitoring of the platform; and the bottom-layer driving layer executes the corresponding operation by function call of the hardware abstraction layer, and processes and updates data in real time.

An integrated prototyping system (IPS) is proposed for verifying and validating an electronic system design (ESD) with hierarchical design elements (HDEs). The IPS has: a) A reprogrammable logic device (RPLD) having an emulation timing base and an RPLD-interface for programming and simulating HDEs under validation while transacting exchanging vectors. The RPLD is also switchably coupled to numerous external peripheral electronic devices (PED), b) An EDA simulator for simulating then verifying selected HDEs while transacting exchanging vectors. The EDA simulator also has a simulator interface; and c) An IPS controller bridging the RPLD and the EDA simulator. The IPS controller has an IPS executive for progressively verifying and validating the ESD. The IPS executive further includes a co-emulation software for jointly and simultaneously running the RPLD and the EDA simulator with an event-based synchronization scheme for interchanging exchanging vectors on demand between the RPLD and the EDA simulator.

The invention discloses a method and an apparatus for responding remote signals of remote receiving equipment. The method comprises the steps of integrating at least two remote controller protocols in a drive layer of remote signal receiving equipment; generating remote controller key code value mapping table in an application layer of the remote signal receiving equipment; decoding the remote signals by the drive layer according to the integrated remote controller protocols after the remote signal receiving equipment receives the remote signals, so as to obtain real key code value of the remote controller; then searching the mapping key code value corresponding to the real key code value in the remote controller key code value mapping table; and transmitting the mapping key code value to the application layer so as to execute a key function. With the hierarchical design of integrating a plurality of controller protocols in the drive layer and generating the remote controller key code value mapping table in the application layer, the apparatus can respond the remote signals with various protocols; and software in the drive layer is in no need of frequent modifications, so that the stability of the system is enhanced; and cost for software development and maintenance is reduced.

A system that routes nets within an integrated circuit. During operation, the system receives a representation for the integrated circuit, which includes block boundaries for physical partitions of the IC generated from a hierarchical design placement of the integrated circuit. The system then classifies each net in the integrated circuit based on the location of pins associated with the net. Next, the system generates routing constraints for each net based on the classification of the net and applies a feedthrough constraint to the physical partitions to restrict nets from feeding through physical partition boundaries. Finally, the system routes each net using the routing constraints for the net and the feedthrough constraints for the physical partitions. This routing is performed based on these block boundaries prior to finalizing the hierarchical design placement, thereby facilitating early detection of congestion or timing violations which can be corrected early in the design process.

The invention discloses a control system used for a power distribution terminal. The system includes a hardware platform layer, a driving layer, an operating system layer, an abstraction layer and an application layer. Unified scheduling is performed by a real-time operating system of the operating system layer. The abstraction layer includes a data engine module, a public service module and a debugging configuration module. The data engine module includes a real-time data sub-module and a historical data sub-module. The real-time data sub-module is used for data real-time storage and analysis of the power distribution terminal. The historical data sub-module is used for recording operation information formed by protection and measurement control function modules and the operation information is used for retrieval of the debugging configuration module. The public service module provides frequently used public interfaces to other modules. The application layer performs measurement control and protection on the power distribution terminal based on the public interfaces, the real-time database sub-module and the historical database sub-module. The control system used for the power distribution terminal performs a hierarchical design in a high cohesion and low coupling principle and data is separated from the application so that the system has the characteristics of being safe, highly efficient and reliable.