49 results about "Ground rule" patented technology

A method, system and program product that implements area minimization of a circuit design while respecting the explicit and implicit design constraints, in the form of ground rules and user intent. A longest path algorithm is used to generate a scaling factor. The scaling factor is used to reduce the size of the circuit design to the minimum legal size. The scaling may be followed by application of minpert analysis to correct any errors introduced by the scaling. The resulting design is shrunk (or expanded) with all elements shrinking (or growing) together by the same factor, and with the relative relationships of elements maintained. In addition, the invention is operational in the presence of a positive cycle, can be run with scaling that freezes the sizes of any structure or ground rule, and can be applied to technology migration.

A system and method are disclosed for legalizing a flat or hierarchical VLSI layout to meet multiple grid constraints and conventional ground rules. Given a set of ground rules with multiple grid constraints and a VLSI layout (either hierarchical or flat) which is layout-versus-schematic (LVS) correct but may not be ground rule correct, the system and method provide a legalized layout which meets the multiple grid constraints while maintaining LVS correctness and fixing the ground rule errors as much as possible with minimum layout perturbation from the input design. The system and method support multiple grid pitch constraints for hierarchical design, and provide for LVS correctness to be maintained while an on-grid solution possibly with some spacing violations.

A method of determining overlay error comprises creating a first and second layers of an integrated circuit, each having an active circuit feature and an adjacent kerf area. Each kerf area includes a first measurement feature separated from and corresponding substantially to the layer's active circuit feature. The circuit and kerf areas of the layers are substantially superimposed. The distance of separation between the active circuit feature and the layer kerf measurement feature in each layer in the direction of overlay error is the same. The second layer kerf measurement feature is displaced from the first layer kerf measurement feature in a direction perpendicular to the direction that the overlay error is to be determined. Overlay error is determined by measuring distance of separation in the direction of overlay error between the common points of reference of each of the first and second layer kerf measurement features.

An avalanche photodiode (APD) electro-magnetic radiation (EMR) detector for visible to near infrared wavelengths is described. The detector includes an EMR absorption region, a voltage biasing element, and a charge multiplication region. The EMR absorption region includes a substantially regular array of silver or aluminum nanoparticles embedded in a matrix material. The voltage biasing element is configured to apply a bias voltage to the matrix material such that electrical current is directly generated in the EMR absorption region based on a cooperative plasmon effect in the detector material when electro-magnetic radiation in the visible to near infrared wavelength range is incident upon the detector material, where the dominant mechanism for decay in the cooperative plasmon effect is non-radiative. The charge multiplication region is arranged relative to the EMR absorption region to avalanche multiply the electrical current generated in the EMR absorption region.

The invention relates to a method and a device for interactive control of a machine, whereby the operating parameters necessary for the working process of the machine are inputted into a data processing unit (12), for storing the operating parameters, using an input unit (10) with input fields in a form which guides the user. Working processes are thus carried out as a result of the inputs. A data set of the base rules for the working process of the machine is recorded in the data processing unit. A limited selection (11) of possible input choices is provided for the user by application of the data set based on the machine configuration and machine environment, which further comprise compatible parts for addition to the extant parts of a working process. Operator guidance is facilitated, whereby the user is provided with a limited selection (11), corresponding to the further parts of the process, on operating fields, by the input unit (10) on the surface (16) for manual input and/or for input using a manipulator (38).

The invention provides a method and structure for optimizing placement of redundant vias within an integrated circuit design. The invention first locates target vias by determining which vias do not have a redundant via. Then, the invention draws marker shapes on or adjacent to the target vias. The marker shapes are only drawn in a horizontal or vertical direction from each of the target vias. Next, the invention simultaneously expands all of the marker shapes in the first direction to a predetermined length or until the marker shapes reach the limits of a ground rule. During the expanding, different marker shapes will be expanded to different lengths. The invention determines which of the marker shapes were expanded sufficiently to form a valid redundant via to produce a first set of potential redundant vias and the invention eliminates marker shapes that could not be expanded sufficiently to form a valid redundant via. The invention repeats the foregoing processing in the direction perpendicular to the first. The invention can also be used to eliminate certain undesirable structures such as stacked vias or can be used to fix other problems such as insufficient via-to-via spacing. The invention then adds the redundant vias to the integrated circuit design, according to output produced by the optimizer.

An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.

A system and method of employing patterning process statistics to evaluate layouts for intersect area analysis includes applying Optical Proximity Correction (OPC) to the layout, simulating images formed by the mask and applying patterning process variation distributions to influence and determine corrective actions taken to improve and optimize the rules for compliance by the layout. The process variation distributions are mapped to an intersect area distribution by creating a histogram based upon a plurality of processes for an intersect area. The intersect area is analyzed using the histogram to provide ground rule waivers and optimization.

A design rule that determines a degree of overlap between two design elements in two adjoining levels by estimating a physical overlap area, or an “intersect area,” of corresponding structures in a semiconductor chip is provided. The estimation of the physical intersect area may factor in line edge biasing, critical dimension tolerance, overlay tolerance, and corner rounding to provide an accurate estimate of a physical area for each of the structures corresponding to the two design elements. The intersect area is employed as a metric to determine compliance with a ground rule, i.e., the ground rule is specified in terms of the intersect region. Other derived quantities such as electrical resistance, electromigration resistance, expected yield may be calculated from the intersect area, and may be advantageously employed to optimize the design data.

The invention provides a method and structure for optimizing placement of redundant vias within an integrated circuit design. The invention first locates target vias by determining which vias do not have a redundant via. Then, the invention draws marker shapes on or adjacent to the target vias. The marker shapes are only drawn in a horizontal or vertical direction from each of the target vias. Next, the invention simultaneously expands all of the marker shapes in the first direction to a predetermined length or until the marker shapes reach the limits of a ground rule. During the expanding, different marker shapes will be expanded to different lengths. The invention determines which of the marker shapes were expanded sufficiently to form a valid redundant via to produce a first set of potential redundant vias and the invention eliminates marker shapes that could not be expanded sufficiently to form a valid redundant via. The invention repeats the foregoing processing in the direction perpendicular to the first. The invention can also be used to eliminate certain undesirable structures such as stacked vias or can be used to fix other problems such as insufficient via-to-via spacing. The invention then adds the redundant vias to the integrated circuit design, according to output produced by the optimizer.

A high density, asymmetric, butted junction CMOS inverter, formed on an SOI substrate, may include: an asymmetric p-FET that includes a halo implant on only a source side of the p-FET; an asymmetric n-FET that includes a halo implant on only a source side of the n-FET; and a butted junction comprising an area of said SOI substrate where a drain region of the asymmetric n-FET and a drain region of the asymmetric p-FET are in direct physical contact. Asymmetric halo implants may be formed by a sequential process of covering a first FET of the CMOS inverter with an ion-absorbing structure and applying angled ion radiation to only the source side of the second FET, removing the ion-absorbing structure, covering the first FET with a second ion-absorbing structure, and applying angled ion radiation to only the source side of the second FET. A layout display of CMOS integrated circuit may require one ground rule for the high density, asymmetric butted junction CMOS inverter and another ground rule for other CMOS circuits.

Approaches are provided for fixing pin mismatches from swapping library cells in layout migration. Specifically, a method is provided that includes collecting information about a first technology pin from a library cell in a first technology. The method further includes swapping the library cell in the first technology with a library cell in a second technology. The method further includes collecting information about a second technology pin from the library cell in the second technology. The method further includes building a pin-mapping table that is configured to map the first technology pin to the second technology pin. The method further includes scaling a layout from the first technology to the second technology. The method further includes modifying the layout based on the pin-mapping table to match the at least one first technology pin to the at least one second technology pin while satisfying ground rules of the second technology.

Methods for producing self-aligned, self-assembled sub-ground-rule features without the need to use additional lithographic patterning. Specifically, the present disclosure allows for the creation of assist features that are localized and self-aligned to a given structure. These assist features can either have the same tone or different tone to the given feature.

The invention provides a method for processing a special-shaped hole on a metal by using femtosecond laser light. Processing of a circular hole and a special-shaped hole is performed on the same workstation; and the method is matched with a high-precision control system, so that the position accuracy of the circular hole in the special-shaped hole is ensured. Motion compounding is performed on a swinging shaft of an inching two-dimensional platform and a linear shaft of a five-axle platform, real-time control is performed on a laser shutter, and the basic rules that points construct lines, lines construct planes and planes construct a body are adopted, so that various special shapes can be processed by accurately controlling a laser beam tool.