70results about How to "Simplify sequence" patented technology

A method is proposed for coating an optoelectronic chip-on-board module including a flat substrate populated with one or more optoelectronic components having at least one primary optical arrangement and optionally at least one secondary optical arrangement. The optoelectronic chip-on-board module is coated with a transparent, UV-resistant, and temperature-resistant coating made of silicone by the following steps: (a) casting a liquid silicone into a mold open towards the top and having outer dimensions corresponding to or exceeding outer dimensions of the substrate; (b) inserting the substrate into the mold, wherein the optoelectronic component(s) are immersed completely into the silicone and a surface of the substrate contacts the silicone completely or the substrate immerses into the silicone at least partially with full surface contact; (c) curing and cross-linking the silicone with the optoelectronic component(s) and the substrate; and (d) removing the substrate from the mold with the coating of cured silicone.

A method is proposed for coating an optoelectronic chip-on-board module including a flat substrate populated with one or more optoelectronic components having at least one primary optical arrangement and optionally at least one secondary optical arrangement. The optoelectronic chip-on-board module is coated with a transparent, UV-resistant, and temperature-resistant coating made of silicone by the following steps: (a) casting a liquid silicone into a mold open towards the top and having outer dimensions corresponding to or exceeding outer dimensions of the substrate; (b) inserting the substrate into the mold, wherein the optoelectronic component(s) are immersed completely into the silicone and a surface of the substrate contacts the silicone completely or the substrate immerses into the silicone at least partially with full surface contact; (c) curing and cross-linking the silicone with the optoelectronic component(s) and the substrate; and (d) removing the substrate from the mold with the coating of cured silicone.

Improved sucker rod joints for down hole petroleum pumping applications are provided within the form factor of standard API sucker rods, such that existing inventory in suitable condition is fully usable in more demanding applications. The pin ends are selected or processed such as to provide preselected axial distance between a flat pin end and at least one reference surface, such as a threaded region or reference shoulder or both. The coupler is dimensioned such that the pin ends are in abutment either with each other or with opposite sides of an intervening torque washer in the central region, when the connection is made to a selected level of thread engagement. Furthermore, the engagement is such as to put the pin ends in compression and the coextensive length of coupler in tension. This increases frictional restraints and locks the elements together to resist fatigue failure upon cycling and to insure together with an anaerobic adhesive sealant, against back threading. This arrangement enables standard quality sucker rods to be employed in a configuration which is mechanically secure and highly resistant to tensile, bending and torsional forces, thus assuring a greater strength at the joint than in the rod itself, and resisting the effects of material fatigue arising from long term and stressful cycling operations.

Shifts in the apparent charge stored on a charge storing element of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent charge storing elements. To compensate for this coupling, the programming process for a given memory cell can take into account the target programmed state of one or more adjacent memory cell. The amount of programming is verified after each programming pulse and the standard verify level for the programming cell is dependent on the target state. The verify level is further offset lower dependent on the amount of perturbation from neighboring cells, determinable by their target states. The verify level is preferably virtually offset by biasing adjacent word lines instead of actually offsetting the standard verify level. For soft-programming erased cells, neighboring cells on both adjacent word lines are taken into account.