A gate wire including a gate line extending in the horizontal direction, and a gate
electrode is formed on an insulating substrate. A gate insulating layer is formed on the gate wire and covers the same. A
semiconductor pattern is formed on the gate insulating layer 30, and formed on the
semiconductor pattern are a data wire having a date line in the vertical direction, a source
electrode, a drain
electrode separated from the source electrode opposite the source electrode with respect to the gate electrode, and an align pattern located on both sides of the data line. A
passivation layer is formed on the data wire and the align pattern, and has contact holes exposing the drain electrode and an opening exposing the substrate between the data line and the align pattern. Here, the align pattern adjacent to the data line is exposed through the opening, and the
semiconductor pattern and the gate insulating layer are under-
cut. A pixel electrode connected to the drain electrode through the
contact hole is formed on the
passivation layer. Here, the opening is located between the data line and the pixel electrode. In this structure, misalignment occurring in the manufacturing process of a
thin film transistor panel for a
liquid crystal display is minimized, and stitch defects are prevented by uniformity forming a
coupling capacitance between the data line and the pixel electrode. Shorts between the data line and the pixel electrode are prevented by forming the opening between the data line and the pixel electrode.