535 results about "Wafer bonding" patented technology

The invention discloses a wafer bonding method, which comprises the following steps of: 1, providing a first wafer and a second wafer, the surface of the first wafer being provided with a microstructure with a high aspect ratio; step 2, cleaning the first wafer and the second wafer; step 3, performing vacuum drying treatment on the first wafer and the second wafer, wherein the vacuum pressure is controlled to be 0.1-10 Torr in the vacuum drying treatment process; step 4, carrying out pre-bonding on the first wafer and the second wafer to form a bonding body; and step 5, carrying out annealing treatment on the bonding body. Aiming at the problem of residual water in the pre-cleaning process in the bonding process of the micro-structure wafer with a high aspect ratio, the wafer is placed in a controllable vacuum environment, phase change boiling of liquid water under the condition of no heat input is realized, and the problem of high-temperature heat damage caused by an existing heating and baking method is effectively avoided.

The invention relates to a wafer chuck, a wafer bonding device and a wafer edge deformation compensation method. The wafer chuck comprises a supporting member which is provided with a circular surface for supporting a wafer and is divided into a first area and a second area, and the part, located in the second area, of the supporting member is elastic; the supporting piece is arranged at the top of the disc body, the disc body is provided with a cavity corresponding to the second area and an air entraining channel communicated with the cavity, the air entraining channel is communicated with the suction device, and the adsorption holes are communicated with the cavity; the cavity forms a positive pressure state and a negative pressure state under the action of the suction device, and in the positive pressure state, the part, located in the second area, of the supporting piece protrudes towards the side away from the cavity so as to drive the edge of the wafer to move towards the side away from the cavity; in a negative pressure state, the part, located in the second area, of the supporting piece is recessed towards the interior of the cavity so as to drive the edge of the wafer to move towards the inner side of the cavity. According to the invention, the initial deformation of the edge of the wafer can be compensated, so that the distortion of the edge area of the wafer after bonding is reduced.

According to the invention, the bonding strength between wafers in the semiconductor manufacturing process is improved through a simple structure. Provided is a vacuum chamber (14) for bonding semiconductor wafers (W1, W2) to each other, one using a silicon electrode (G1) and the other using a semiconductor wafer (W2) before bonding crystalline silicon circles (W1, W2) facing each other; after the silicon electrode G1 and the semiconductor wafer W2 are processed for the first time, the silicon electrode G1 is replaced by the bonding wafer G2, and then the bonding wafer G2 and the semiconductor wafer W2 are processed for the second time. Then, the pair of wafers W1 and W2, which are opposite to each other, are bonded together by electrostatic force in a vacuum environment.

The invention relates to the technical field of temporary wafer bonding, in particular to a high-precision wafer alignment device, and mainly solves the technical problem that a wafer alignment device is low in precision. The device comprises a rack, a visual mechanism, an adsorption platen, an XYZ three-axis platform, a rotating platform and an adjusting platform, the rack comprises a base and a portal frame, the visual mechanism is installed above a cross beam of the portal frame, the adsorption platen is fixed below the cross beam of the portal frame, the XYZ three-axis platform is installed on the base and located on the inner side of the portal frame, and the rotating platform is installed on the XYZ three-axis platform. The adjusting platform comprises a bottom plate, a top plate and leveling assemblies, the bottom plate is fixed to the rotating platform, and the leveling assemblies are connected between the bottom plate and the top plate and distributed at intervals in the circumferential direction. According to the device, on one hand, position calibration of the lower wafer and the upper wafer can be achieved, on the other hand, precision reduction caused by taking down, transferring and placing can be avoided, the precision of the upper wafer and the lower wafer when the upper wafer and the lower wafer are finally fixed can be guaranteed through cooperation of the two aspects, and therefore the process requirement is met.

Embodiments of the present disclosure provide a semiconductor device structure having vertically stacked complementary field effect transistors (CFETs). The CFETs are formed by bonding two substrates having semiconductor stacks formed thereon. A bonding structure is formed between the semiconductor stacks using wafer bonding technology. Embodiments of the resent disclosure enable the flexibility of choosing different N / P channel properties, provide a simple way to form the N / P channel isolation structure, and reduce potential leakage path and defects in stacked CFETs.

The invention provides a three-degree-of-freedom micro-motion bonding head for a wafer bonding machine, relates to the technical field of ultra-precision piezoelectric driving, and aims to solve the problems that a traditional bonding head structure is low in response speed and poor in multi-degree-of-freedom cooperative micro-motion stability. An external frame unit and an internal frame unit are fixedly assembled on the micropositioner main substrate; the external frame unit comprises an X-direction piezoelectric actuator, a Y-direction piezoelectric actuator, an X-direction balance weight, a Y-direction balance weight and a parallel guiding flexible hinge, wherein the X-direction balance weight and the Y-direction balance weight are symmetrically distributed, and the external frame unit is used for achieving X-direction linear motion and Y-direction linear motion. The internal frame unit comprises a Z-direction piezoelectric actuator, a wafer bonding head and a tandem decoupling flexible hinge, and is used for realizing Z-direction linear motion; the piezoelectric actuator is used as a driving element and is matched with the flexible hinge to form a guiding and transmission mechanism, three-degree-of-freedom micro-motion of the bonding head in space is achieved, and meanwhile the structural design is optimized to improve motion decoupling performance, compactness and adaptability of stroke and precision.

The invention provides a wafer bonding device and a wafer bonding method, and belongs to the technical field of photoelectron manufacturing. The bonding device comprises two pressing plates and buffer pads, wherein the buffer pads are arranged on two opposite plate surfaces of the two pressing plates. The problem of non-uniform pressure in the bonding process can be improved, and the yield of the subsequent process is improved.

A wafer-on-wafer formed memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. The memory die can be formed as one of many memory dies on a first semiconductor wafer. The logic die can be formed as one of many logic dies on a second semiconductor wafer. The first and second wafers can be bonded via a wafer-on-wafer bonding process. The memory and logic device can be singulated from the bonded first and second wafers.

The present disclosure relates to a multi-axis stage apparatus capable of significantly improving the precision of wafer bonding. The apparatus may include a base portion, a first driving device configured to vertically move at least a portion thereof in a third axis direction by a first distance with respect to the base portion, a second driving device formed on the first driving device and configured to vertically move at least a portion thereof in the third axis direction by a second distance, and an alignment stage connected to the second driving device and configured to align a first wafer chuck holding a first wafer such that the first wafer can be vertically moved in the third axis direction by a distance equal to the sum of the first and second distances.

A wafer-on-wafer bonded memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. A memory device formed on a memory die can include many global input / output lines and many arrays of memory cells. Each array of memory cells can include respective local input / output (LIO) lines coupled to a global input / output line. A logic device can be formed on a logic die. A bond, formed between the memory die and the logic die via a wafer-on-wafer bonding process, can couple the many global input / output lines to the logic device.

The invention provides a three-wafer bonding MEMS device and a preparation method thereof, the three-wafer bonding MEMS device comprises a first wafer, a second wafer, a third wafer, an insulating layer and a metal electrode, the first wafer comprises a plurality of first grooves, the bottom of each first groove is communicated with at least one silicon groove, and each silicon groove is filled with an insulating material; protruding silicon-silicon bonding platforms are arranged between the first grooves and inside the first grooves. The second wafer is connected with the first wafer through a silicon-silicon bonding platform, and a plurality of strip holes are formed in the second wafer; the third wafer comprises a plurality of second grooves; a limiting bulge can be arranged in the second groove; a raised eutectic bonding platform is arranged between the interior of the second groove and the second groove, and the third wafer is bonded with the second wafer; the insulating layer covers the first wafer; the plurality of metal electrodes are disposed on the insulating layer. According to the invention, the problem that the electrical parameters of the silicon-silicon bonding process cannot be tested and represented in the production and manufacturing of the MEMS device is solved.

The invention discloses a wafer reconstruction method and a reconstructed wafer. The wafer reconstruction method comprises the steps that an etching barrier layer is arranged on one side of a to-be-reconstructed wafer, the to-be-reconstructed wafer comprises a first substrate and a light-emitting functional layer arranged on the first substrate, and the etching barrier layer is arranged on the side, away from the first substrate, of the light-emitting functional layer; etching the wafer to be reconstructed to form a groove, wherein the depth of the groove extends to the etching barrier layer; cutting the etching barrier layer along the groove to form a plurality of LED wafers; bonding the LED wafer to a second substrate to form a reconstructed wafer; the size of the second substrate is larger than that of the first substrate. The manufacturing yield of the wafer with the larger size can be improved, and meanwhile the manufacturing cost of the wafer with the larger size is reduced.

The invention provides a method for detecting wafer bonding alignment deviation. The method comprises the steps that a preset number of metal test points are arranged on two wafers to be bonded according to preset coordinates, and every two metal test points on a first wafer and every two metal test points on a second wafer serve as a test loop; detecting the conduction condition of each group of test loops after the two wafers are bonded; and determining the bonding alignment deviation between the two wafers according to the conduction condition of each group of test loops. According to the invention, the detection precision of the wafer bonding alignment deviation can be improved.

A method includes bonding a first wafer to a second wafer, performing a trimming process on the first wafer, and depositing a sidewall protection layer contacting a sidewall of the first wafer. The depositing the sidewall protection layer includes depositing a high-density material in contact with the sidewall of the first wafer. The sidewall protection layer has a density higher than a density of silicon oxide. The method further includes removing a horizontal portion of the sidewall protection layer that overlaps the first wafer, and forming an interconnect structure over the first wafer. The interconnect structure is electrically connected to integrated circuit devices in the first wafer.

A method for overlay measurement is disclosed. The method includes receiving an image of a bonded wafer. The method includes generating, based on the image, a profile of the bonded wafer. The method includes adjusting, using the profile, an objective lens of a single-focus image-based infrared (IR) system to perform an overlay measurement of the bonded wafer.

The invention discloses a miniature integrated infrared gas sensor chip, which belongs to the technical field of sensors, and comprises a first wafer and a second wafer, and the first wafer and the second wafer are connected in a combination manner and form an optical gas chamber; a vent hole is formed above the first wafer, and a reflective film layer is plated on the inner wall of the optical gas chamber and is arranged to only allow infrared light emitted by the infrared light source to pass through; a periodic micro-nano structure is arranged in the optical gas chamber; the surface of the second wafer is covered with an insulating film layer, and an infrared light source and an infrared detector are arranged above the insulating film layer. An optical gas chamber is formed through double-wafer bonding, a periodic micro-nano structure is integrated to enhance interaction between infrared light and gas, environmental interference is suppressed in combination with a double-channel differential detector, and meanwhile stability and selectivity are improved through multi-layer structures such as a reflective film layer, a protective film layer and a composite insulating film layer. And finally, a miniaturized and high-sensitivity gas detection function is realized.

The embodiment of the invention provides a wafer bonding method, a manufacturing method of a gate-all-around transistor and a product. The wafer bonding method comprises the following steps: providing a semiconductor material donor wafer and a support wafer, forming a first dielectric layer on the support wafer, and forming a second dielectric layer on one side, to be bonded to the support wafer, of the semiconductor material donor wafer; performing chemical mechanical polishing on the first dielectric layer to form a first bonding surface, and performing chemical mechanical polishing on the second dielectric layer to form a second bonding surface; and bonding the support wafer and the semiconductor material donor wafer through the first bonding surface and the second bonding surface. The manufacturing method of the transistor comprises the following steps: thinning a target semiconductor material layer in a semiconductor material donor wafer; and defining a source region, a drain region and a channel region of the transistor, and enabling the channel region to be separated from the buried oxide layer and suspended. And depositing a gate dielectric layer, defining a gate region and depositing gate metal. And carrying out ion implantation and annealing. And opening holes in the source region and the drain region, and depositing a source region electrode and a drain region electrode.

The utility model relates to a megasonic cleaning device for wafer processing, and belongs to the technical field of wafer processing equipment. Wherein the upper rotating device is provided with a driving assembly and an infrared heater and is used for rotating and drying a wafer; the bonding device is provided with a pressure head with a pressure sensor and a driving mechanism, and pressure is applied to realize wafer bonding; the cleaning device comprises left and right swing arms and a cleaning nozzle and has megasonic cleaning and other functions; the buffer device supports and buffers the wafer; the lower rotating device drives the wafer to rotate; the alignment device, the vibration motor and the tilting device are matched, and wafer alignment is achieved after upper and lower wafers are cleaned and before bonding is completed; the up-and-down moving device adjusts the position of the wafer. According to the megasonic cleaning device, the megasonic technology is utilized, and efficient and accurate wafer cleaning can be ensured.

A method for manufacturing a semiconductor structure includes: forming a first bonding layer on a device substrate formed with a semiconductor device so as to cover the semiconductor device, wherein the first bonding layer includes a first metal oxide material in an amorphous state; forming a second bonding layer on a carrier substrate, wherein the second bonding layer includes a second metal oxide material in an amorphous state; conducting a surface modification process on the first bonding layer and the second bonding layer; bonding the device substrate and the carrier substrate to each other through the first and second bonding layers; and annealing the first and second bonding layers so as to convert the first and second metal oxide materials from the amorphous state to a crystalline state.

The invention discloses a low-temperature bonding method and a bonded wafer, and belongs to the technical field of wafer bonding. The method comprises the following steps of: (1) performing plasma enhanced chemical vapor deposition on a non-bonding surface of a substrate wafer and / or a piezoelectric wafer to form a SiO2 layer; (2) performing plasma activation treatment on the piezoelectric wafer and the substrate wafer; (3) cleaning and blow-drying the activated piezoelectric wafer and the substrate wafer, and forming an oxide layer with the thickness of at least 1.5 nm on the surface of the cleaned and blow-dried substrate wafer; (4) laminating the piezoelectric wafer obtained in the step (3) with a substrate wafer, and carrying out pre-bonding under 0.9 * 10 < 5 >-1.2 * 10 < 5 > Pa and the humidity of 50%-70%; and (4) annealing the pre-bonded wafer to obtain a bonded wafer. According to the method, the bonding strength can be effectively improved, defects such as holes are avoided, and the performance stability of the bonded wafer is improved.

In an embodiment, a bevel sealing system includes a dispensing chamber that includes a first chuck configured to support a workpiece, the workpiece including a first wafer bonded to a second wafer, where the first wafer and the second wafer include beveled edges, a sealant dispenser configured to apply sealant along a perimeter of a bonding interface between the first wafer and the second wafer, a first Charge-Coupled Device (CCD) camera configured to capture 2-dimensional (2D) images of edges of the workpiece, and a first laser edge profiler configured to measure and collect profile data of the edges of the workpiece.

According to the invention, the bonding strength between wafers in the semiconductor manufacturing process is improved through a simple structure. Provided is a semiconductor wafer bonding device 34 for bonding semiconductor wafers W1, W2 to each other, the semiconductor wafers W1, W2 being subjected to plasma treatment to activate the surfaces thereof, then being brought into a high vacuum state for a predetermined time, thereby polarizing the surface ions of the semiconductor wafers W1, W2, and bonding the semiconductor wafers W1, W2 to each other by applying a high-frequency power source 110 to the semiconductor wafers W1, W2. Ions move on the surfaces of the semiconductor wafers W1 and W2, so that the bonding strength between the semiconductor wafers W1 and W2 is improved.

Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.

A kind of circuit package structure based on three-dimensional heterogeneous laminated structure, the top layer edge of ceramic substrate is welded metal frame, the top layer of ceramic substrate is welded silicon MEMS substrate, the height of metal frame exceeds silicon MEMS substrate, the top layer of metal frame is welded metal cover plate, ceramic substrate, metal frame, metal cover plate form the cavity of airtight package, MEMS substrate is in the cavity, the top layer of ceramic substrate has pad, the bottom layer of silicon MEMS substrate has pad, all are welded internal BGA, the signal of ceramic substrate and silicon MEMS substrate is interconnected by internal BGA, the bottom layer of ceramic substrate has pad, and is welded external BGA, the signal of ceramic substrate is interconnected by external BGA and other substrate, ceramic substrate and silicon MEMS substrate are all stacked by multiple layers, have multiple vertical through holes and multiple horizontal wiring, each through hole is connected to any layer respectively, each wiring is on the surface or inside of multilayer board and is connected to any through hole respectively, silicon MEMS substrate is internally printed pattern and micro-bump using wafer bonding process.

The application discloses a wafer back contact type positioning and clamping fixing device and a wafer bonding method, and belongs to the technical field of wafer bonding. The wafer back contact type positioning and clamping fixing device comprises a bonding chamber, a lower suction disc, an upper pressing disc, a controller, a pressing driving mechanism, a positioning pressing rod, a clamping driving mechanism and flexible clamping paws. The lower end of the positioning pressing rod is in abutment with the upper end wall of the lower suction disc. The clamping driving mechanism is arranged on the two sides of the lower suction disc in a sliding mode. The flexible clamping paws are connected with the clamping driving mechanism. The flexible clamping paws are driven to slide along the radial direction of the lower suction disc by the clamping driving mechanism. The flexible clamping paws are used for clamping and fixing wafers. The inner circumferential wall of the flexible clamping paws is in abutment with the outer circumferential wall of the wafer. The limiting block is in abutment with the lower end wall of the edge of the wafer. The pressing driving mechanism and the clamping driving mechanism are electrically connected with the controller. The technical scheme of the application can avoid wafer surface pollution and damage, effectively improve the stability of the wafer bonding process, reduce the waste rate, save the cost, and has high market application and popularization value.

The present application provides a flip chip light emitting diode and a manufacturing method thereof. The flip chip light emitting diode comprises a transparent substrate, an epitaxial composite layer, a first conductive type electrode pad, a second conductive type electrode pad and a wafer bonding composite layer. The epitaxial composite layer is disposed on the transparent substrate. The first conductive type electrode pad is disposed on the transparent substrate and electrically connected to the epitaxial composite layer. The second conductive type electrode pad is disposed on the epitaxial composite layer and electrically connected to the epitaxial composite layer, and is located on the same horizontal plane as the first conductive type electrode pad on the same side of the transparent substrate. The wafer bonding composite layer comprises at least one titanium dioxide (TiO2) layer and at least one silicon dioxide (SiO2) layer, and is interposed between the epitaxial composite layer and the transparent substrate.

Techniques and / or systems are disclosed herein for forming a window cavity wafer that includes fabricating a window wafer by: providing a window wafer substrate having two faces; etching fiducials onto one or more faces of the window wafer substrate; and applying one or more optical coatings to on one or more faces of the window wafer substrate. Next, fabricating a spacer wafer separate from the window wafer by: providing a spacer wafer substrate having two faces; and forming an array of through-holes in the spacer wafer substrate. Then, bonding the spacer wafer to the window wafer to form the window cavity wafer; and forming discrete metal frames on a face of the window cavity wafer.

The invention provides a wafer bonding method and a wafer. The wafer bonding method comprises the following steps: S0, providing a first wafer and a second wafer; s1, detecting whether the edge of the first wafer and / or the second wafer has defects or not; s2, if the edge of the first wafer and / or the second wafer has defects, cutting the edge of the first wafer and / or the second wafer, and forming a notch in the edge of the first wafer and / or the second wafer; s3, a deposition process and a planarization process are alternately carried out on the gap for multiple times so as to fill the gap; and S4, bonding the first wafer and the second wafer to obtain a bonded wafer. According to the invention, through repeated alternate deposition and planarization, the gap is effectively filled, the flatness and shape of the wafer edge are ensured to meet the requirements of the subsequent process, and the deformation and fracture risks in the subsequent process are reduced.

The present disclosure provides an engineered epitaxial wafer of an ultra-thin GaN HEMT by wafer bonding and a manufacturing method thereof. According to an embodiment of the present invention, there is provided an engineered epitaxial wafer of an ultra-thin GaN HEMT by wafer bonding, comprising: a support substrate; an electrically insulating thin film region disposed on the support substrate; a buffer region disposed on the electrically insulating thin film region and containing Al(x)Ga(1-x)N (0≤x<1) doped with undoped carbon (C) and iron (Fe); a channel region disposed on the buffer region and containing Al(y)Ga(1-y)N (0≤y≤1); and a barrier region disposed on the channel region and containing Al(z)Ga(1-z)N (0<z<1) or In(w)Al(1-w)N (0<w<1).

A wafer on wafer on wafer and a chip on wafer on wafer structure and methods of forming the same are provided. In accordance with some embodiments, a first device wafer is bonded to a first carrier through wafer-on-wafer bonding and additional device wafers may subsequently be bonded to the first device wafer. A support wafer is then bonded to the top most device wafer and the first wafer may then be removed. The bonded wafer structure may then be singulated into individual semiconductor device packages. Through the wafer-on-wafer bonding process, the manufacturing cost and cycle time may be reduced.