769 results about "Wafer bonding" patented technology

The invention relates to the technical field of wafer bonding devices, in particular to a wafer bonding pressure control mechanism and method. The mechanism comprises a main driving unit and a bonding pressing rod linked with the main driving unit, the main driving unit drives the bonding pressing rod to move in the bonding pressure direction, bonding pressure is applied to a wafer through the bonding pressing rod, the bonding pressing rod is linked with the main driving unit through a pressure maintaining air cylinder, and the bonding pressing rod is arranged at the tail end of a piston rod of the pressure maintaining air cylinder; a displacement sensor is further included, the displacement change of the bonding pressing rod is detected through the displacement sensor, and the displacement sensor is electrically connected with the main driving unit. The main driving unit and the pressure maintaining air cylinder are combined to form a composite operation control system, the bonding pressure is controlled and adjusted by controlling the air pressure of the pressure maintaining air cylinder, and the stability of the bonding pressure is ensured.

The invention relates to the technical field of piezoelectric single-crystal filters, in particular to a filter based on a heterogeneous integrated piezoelectric single-crystal thin film and a preparation method, the filter comprises a Si substrate, a dry film, the piezoelectric single-crystal thin film, a SiO2 layer and a Si wafer are sequentially arranged on the Si substrate, metal balls are arranged on the Si wafer, the metal balls are connected with electrodes, and the electrodes are connected with the piezoelectric single-crystal thin film. And the electrode passes through the Si wafer and the SiO2 layer and is connected with the piezoelectric single crystal film. When the filter is prepared, bonding packaging can be performed after a cavity area is etched on a dry film, a resonance area is directly defined through a photoetching process, the influence of etching on the strength of the piezoelectric single crystal film is avoided, a silicon wafer bonding technology can be combined, double-sided packaging can be realized, and batch production is supported; in the process, only the electrode patterning step needs to be adjusted according to the type of the filter, and then the existing MEMS process integration is utilized, so that the preparation of the FBAR and the XBAR on the same production line is realized, the process compatibility is good, and the problems that the existing preparation method is poor in compatibility and is difficult to realize large-scale production are solved.

The invention discloses a wafer back contact type positioning and clamping fixing device and a wafer bonding method.The wafer back contact type positioning and clamping fixing device comprises a bonding cavity, a lower suction cup, an upper pressing disc, a controller, a pressing driving mechanism, a positioning pressing rod, a clamping driving mechanism and a flexible clamping jaw, and the lower end of the positioning pressing rod can abut against the upper end wall of the lower suction cup; the clamping driving mechanisms are arranged on the two sides of the lower suction cup in an up-down sliding mode, the flexible clamping jaws are connected with the clamping driving mechanisms, the clamping driving mechanisms drive the flexible clamping jaws to slide in the radial direction of the lower suction cup, the flexible clamping jaws are used for clamping and fixing a wafer, and the inner circumferential wall of each flexible clamping jaw can abut against the outer circumferential wall of the wafer. The limiting block can abut against the lower end wall of the edge of the wafer, and the pressing driving mechanism and the clamping driving mechanism are electrically connected with the controller. According to the technical scheme, the wafer surface can be prevented from being polluted and damaged, the stability of the wafer bonding process can be effectively improved, the rejection rate is reduced, the cost is saved, and the high market application and popularization value is achieved.

The invention discloses a wafer bonding method, which comprises the following steps of: 1, providing a first wafer and a second wafer, the surface of the first wafer being provided with a microstructure with a high aspect ratio; step 2, cleaning the first wafer and the second wafer; step 3, performing vacuum drying treatment on the first wafer and the second wafer, wherein the vacuum pressure is controlled to be 0.1-10 Torr in the vacuum drying treatment process; step 4, carrying out pre-bonding on the first wafer and the second wafer to form a bonding body; and step 5, carrying out annealing treatment on the bonding body. Aiming at the problem of residual water in the pre-cleaning process in the bonding process of the micro-structure wafer with a high aspect ratio, the wafer is placed in a controllable vacuum environment, phase change boiling of liquid water under the condition of no heat input is realized, and the problem of high-temperature heat damage caused by an existing heating and baking method is effectively avoided.

The invention relates to a wafer chuck, a wafer bonding device and a wafer edge deformation compensation method. The wafer chuck comprises a supporting member which is provided with a circular surface for supporting a wafer and is divided into a first area and a second area, and the part, located in the second area, of the supporting member is elastic; the supporting piece is arranged at the top of the disc body, the disc body is provided with a cavity corresponding to the second area and an air entraining channel communicated with the cavity, the air entraining channel is communicated with the suction device, and the adsorption holes are communicated with the cavity; the cavity forms a positive pressure state and a negative pressure state under the action of the suction device, and in the positive pressure state, the part, located in the second area, of the supporting piece protrudes towards the side away from the cavity so as to drive the edge of the wafer to move towards the side away from the cavity; in a negative pressure state, the part, located in the second area, of the supporting piece is recessed towards the interior of the cavity so as to drive the edge of the wafer to move towards the inner side of the cavity. According to the invention, the initial deformation of the edge of the wafer can be compensated, so that the distortion of the edge area of the wafer after bonding is reduced.

According to the invention, the bonding strength between wafers in the semiconductor manufacturing process is improved through a simple structure. Provided is a vacuum chamber (14) for bonding semiconductor wafers (W1, W2) to each other, one using a silicon electrode (G1) and the other using a semiconductor wafer (W2) before bonding crystalline silicon circles (W1, W2) facing each other; after the silicon electrode G1 and the semiconductor wafer W2 are processed for the first time, the silicon electrode G1 is replaced by the bonding wafer G2, and then the bonding wafer G2 and the semiconductor wafer W2 are processed for the second time. Then, the pair of wafers W1 and W2, which are opposite to each other, are bonded together by electrostatic force in a vacuum environment.

The invention provides a low-temperature bonding method for reducing surface damage and a bonding sheet thereof, and relates to the technical field of wafer bonding. In a high vacuum environment, the bonding surfaces of a first wafer and a second wafer which are to be bonded are subjected to first irradiation treatment by using a first atomic beam to obtain a first activation layer; s2, carrying out at least one second irradiation treatment on the bonding surface after the first irradiation treatment in the step S1 by adopting a second atomic beam to obtain a second activation layer; and carrying out ballasting bonding to obtain a bonding sheet. According to the low-temperature bonding method for reducing the surface damage, the bonding surface is activated in a gradient manner, so that the damage to the surface of the wafer caused by single activation can be reduced, the surface roughness is reduced, the probability of bubbles after bonding is reduced, and the bonding strength is improved.

The invention relates to the technical field of temporary wafer bonding, in particular to a high-precision wafer alignment device, and mainly solves the technical problem that a wafer alignment device is low in precision. The device comprises a rack, a visual mechanism, an adsorption platen, an XYZ three-axis platform, a rotating platform and an adjusting platform, the rack comprises a base and a portal frame, the visual mechanism is installed above a cross beam of the portal frame, the adsorption platen is fixed below the cross beam of the portal frame, the XYZ three-axis platform is installed on the base and located on the inner side of the portal frame, and the rotating platform is installed on the XYZ three-axis platform. The adjusting platform comprises a bottom plate, a top plate and leveling assemblies, the bottom plate is fixed to the rotating platform, and the leveling assemblies are connected between the bottom plate and the top plate and distributed at intervals in the circumferential direction. According to the device, on one hand, position calibration of the lower wafer and the upper wafer can be achieved, on the other hand, precision reduction caused by taking down, transferring and placing can be avoided, the precision of the upper wafer and the lower wafer when the upper wafer and the lower wafer are finally fixed can be guaranteed through cooperation of the two aspects, and therefore the process requirement is met.

Embodiments of the present disclosure provide a semiconductor device structure having vertically stacked complementary field effect transistors (CFETs). The CFETs are formed by bonding two substrates having semiconductor stacks formed thereon. A bonding structure is formed between the semiconductor stacks using wafer bonding technology. Embodiments of the resent disclosure enable the flexibility of choosing different N / P channel properties, provide a simple way to form the N / P channel isolation structure, and reduce potential leakage path and defects in stacked CFETs.

The invention relates to a heating and cooling system for wafer bonding equipment, which comprises a basic unit, a heating unit and a cooling unit, and is characterized in that the basic unit comprises an upper disc, a heating bin and a lower disc, and the heating bin is used for accommodating a wafer to be bonded and providing a vacuum environment for the wafer; the upper disc and the lower disc can be driven to be close to each other so as to apply set pressure to the wafer; an upper heater and a lower heater of the heating unit are used for heating the wafer in the axial direction, and an edge heater is used for carrying out heat compensation in the radial direction; an upper cooler and a lower cooler of the cooling unit are used for indirectly cooling the wafer; the wafer bonding device effectively improves heating uniformity and cooling efficiency in the wafer bonding process, can provide an accurate and effective vacuum environment for wafer bonding, and is simple in structure and easier to maintain and repair.

The invention discloses a wafer bonding strength testing method, which comprises the following steps of: cutting a bonded wafer into strip-shaped samples, adjusting a precise translation table to enable a laser head to be aligned with a bonding layer, scanning the bonding layer of the sample by using laser to obtain an inward initial crack, monitoring the position of the initial crack by using a microscope, and adjusting the precise translation table according to the position of the initial crack to test the bonding strength of the wafer. The method comprises the following steps: calibrating a crack to obtain a calibrated crack, adhering test pull rings to two sides of a sample with the calibrated crack, performing tension test on the pull rings to obtain a load-displacement curve of the sample, and calculating the bonding strength of the sample according to the load-displacement curve of the sample. According to the method, the submicron aligned preset cracks are processed through cutting and closed-loop calibration, and then the wafer bonding strength is quantitatively tested through a DCB method, so that the problem that the bonding strength of internal positions of wafers of a D2W bonding sample and a W2W bonding sample cannot be quantitatively tested is solved.

The invention provides a three-degree-of-freedom micro-motion bonding head for a wafer bonding machine, relates to the technical field of ultra-precision piezoelectric driving, and aims to solve the problems that a traditional bonding head structure is low in response speed and poor in multi-degree-of-freedom cooperative micro-motion stability. An external frame unit and an internal frame unit are fixedly assembled on the micropositioner main substrate; the external frame unit comprises an X-direction piezoelectric actuator, a Y-direction piezoelectric actuator, an X-direction balance weight, a Y-direction balance weight and a parallel guiding flexible hinge, wherein the X-direction balance weight and the Y-direction balance weight are symmetrically distributed, and the external frame unit is used for achieving X-direction linear motion and Y-direction linear motion. The internal frame unit comprises a Z-direction piezoelectric actuator, a wafer bonding head and a tandem decoupling flexible hinge, and is used for realizing Z-direction linear motion; the piezoelectric actuator is used as a driving element and is matched with the flexible hinge to form a guiding and transmission mechanism, three-degree-of-freedom micro-motion of the bonding head in space is achieved, and meanwhile the structural design is optimized to improve motion decoupling performance, compactness and adaptability of stroke and precision.

The invention relates to the technical field of optical fiber communication, in particular to a thin-film lithium niobate electro-optical modulator of a stepped electrode, which comprises a substrate, a buffer layer, an optical waveguide, a metal electrode and a transition layer, the optical waveguide is an X-shaped or Y-shaped cutting LN film, a traditional ridge-shaped structure is adopted, the optical waveguide is bonded to the thick SiO2 buffer layer on the substrate, the film can be prepared through various technologies such as ion implantation, wafer bonding and hot slicing, and in order to improve the electro-optical overlapping coefficient and reduce light absorption loss, a silicon dioxide transition layer is used for connecting the metal electrode and the optical waveguide. The metal electrode is of a stepped structure, the electrode can effectively reduce electrical loss and obtain high bandwidth, and the electrode is used for generating an electric field in the aspect of photoelectric efficiency; the electric field is used for changing the functional characteristics of the thin-film lithium niobate layer and further changing the optical transmission characteristics of the waveguide, so that electro-optical modulation is realized. Therefore, the problem that an existing electro-optical modulator is low in modulation efficiency is solved.

According to one aspect of the present invention, a wafer-to-wafer bonding structure is provided, comprising a wafer having a first test pad, a first bonding pad formed on the first test pad, and a first insulating layer, wherein the first bonding pad penetrates the first insulating layer. The structure may further comprise a wafer having a second test pad, a second bonding pad formed on the second test pad, and a second insulating layer, wherein the second bonding pad penetrates the second insulating layer. The structure may further comprise a polymer layer surrounding all side surfaces of the first bonding pad and all side surfaces of the second bonding pad, the polymer layer being arranged between the wafer and the wafer. In addition, the wafer and the wafer may be bonded together.

The invention provides a wafer bonding device and a wafer bonding method, and belongs to the technical field of photoelectron manufacturing. The bonding device comprises two pressing plates and buffer pads, wherein the buffer pads are arranged on two opposite plate surfaces of the two pressing plates. The problem of non-uniform pressure in the bonding process can be improved, and the yield of the subsequent process is improved.

A wafer-on-wafer formed memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. The memory die can be formed as one of many memory dies on a first semiconductor wafer. The logic die can be formed as one of many logic dies on a second semiconductor wafer. The first and second wafers can be bonded via a wafer-on-wafer bonding process. The memory and logic device can be singulated from the bonded first and second wafers.

The present disclosure relates to a multi-axis stage apparatus capable of significantly improving the precision of wafer bonding. The apparatus may include a base portion, a first driving device configured to vertically move at least a portion thereof in a third axis direction by a first distance with respect to the base portion, a second driving device formed on the first driving device and configured to vertically move at least a portion thereof in the third axis direction by a second distance, and an alignment stage connected to the second driving device and configured to align a first wafer chuck holding a first wafer such that the first wafer can be vertically moved in the third axis direction by a distance equal to the sum of the first and second distances.

A wafer-on-wafer bonded memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. A memory device formed on a memory die can include many global input / output lines and many arrays of memory cells. Each array of memory cells can include respective local input / output (LIO) lines coupled to a global input / output line. A logic device can be formed on a logic die. A bond, formed between the memory die and the logic die via a wafer-on-wafer bonding process, can couple the many global input / output lines to the logic device.

The invention provides a bonding layer of a carrier wafer, a preparation method of the bonding layer, a wafer bonding structure and a photon de-bonding method. The bonding layer comprises an inorganic medium layer and an inorganic heat conduction layer which are arranged on the surface of the transparent carrier in a stacked mode in the direction away from the surface of the transparent carrier. According to the invention, the laminated structure of the inorganic dielectric layer and the inorganic heat conduction layer is arranged on the surface of the transparent carrier, so that the wide spectrum absorption capability of the bonding layer is enhanced under the condition that the surface has relatively low roughness; the solar cell has the advantages of being high in photo-thermal conversion efficiency, extremely low in transmittance, high in high temperature resistance and chemical resistance and repeatable.

Embodiments of methods of die stacking are provided herein. In some embodiments, a method of die stacking using die-to-wafer bonding includes: bonding a plurality of first dies to a substrate by a hybrid bonding process; performing a selective silicon (Si) thinning process to reduce the thickness of the plurality of bonded first grains to form a plurality of thinned first grains; passivating the plurality of thinned first crystal grains to form a plurality of passivated thinned first crystal grains so as to protect the plurality of thinned first crystal grains; filling gaps between adjacent grains in the plurality of thinned first grains with a first filling material, wherein the plurality of passivated thinned first grains and the first filling material form a first layer; and forming a plurality of first conductive vias through the first layer to the substrate.

The invention provides a three-wafer bonding MEMS device and a preparation method thereof, the three-wafer bonding MEMS device comprises a first wafer, a second wafer, a third wafer, an insulating layer and a metal electrode, the first wafer comprises a plurality of first grooves, the bottom of each first groove is communicated with at least one silicon groove, and each silicon groove is filled with an insulating material; protruding silicon-silicon bonding platforms are arranged between the first grooves and inside the first grooves. The second wafer is connected with the first wafer through a silicon-silicon bonding platform, and a plurality of strip holes are formed in the second wafer; the third wafer comprises a plurality of second grooves; a limiting bulge can be arranged in the second groove; a raised eutectic bonding platform is arranged between the interior of the second groove and the second groove, and the third wafer is bonded with the second wafer; the insulating layer covers the first wafer; the plurality of metal electrodes are disposed on the insulating layer. According to the invention, the problem that the electrical parameters of the silicon-silicon bonding process cannot be tested and represented in the production and manufacturing of the MEMS device is solved.

The invention discloses a wafer reconstruction method and a reconstructed wafer. The wafer reconstruction method comprises the steps that an etching barrier layer is arranged on one side of a to-be-reconstructed wafer, the to-be-reconstructed wafer comprises a first substrate and a light-emitting functional layer arranged on the first substrate, and the etching barrier layer is arranged on the side, away from the first substrate, of the light-emitting functional layer; etching the wafer to be reconstructed to form a groove, wherein the depth of the groove extends to the etching barrier layer; cutting the etching barrier layer along the groove to form a plurality of LED wafers; bonding the LED wafer to a second substrate to form a reconstructed wafer; the size of the second substrate is larger than that of the first substrate. The manufacturing yield of the wafer with the larger size can be improved, and meanwhile the manufacturing cost of the wafer with the larger size is reduced.

The invention provides a method for detecting wafer bonding alignment deviation. The method comprises the steps that a preset number of metal test points are arranged on two wafers to be bonded according to preset coordinates, and every two metal test points on a first wafer and every two metal test points on a second wafer serve as a test loop; detecting the conduction condition of each group of test loops after the two wafers are bonded; and determining the bonding alignment deviation between the two wafers according to the conduction condition of each group of test loops. According to the invention, the detection precision of the wafer bonding alignment deviation can be improved.

A device includes a first set of modules configured for wafer shape correction and a second set of modules configured for wafer bonding. The first set of modules includes a metrology module configured to measure wafer shape data of a first wafer and a second wafer, including relative z-height values of the first wafer and the second wafer. A stressor film deposition module is configured to form a first stressor film on the first wafer. A stressor film modification module is configured to modify the first stressor film based on a first modification map that defines adjustments to internal stresses of the first wafer and is generated based on the wafer shape data. The second set of modules includes an alignment module configured to align the first wafer with the second wafer, and a bonding module configured to bond the first wafer to the second wafer.

A method includes bonding a first wafer to a second wafer, performing a trimming process on the first wafer, and depositing a sidewall protection layer contacting a sidewall of the first wafer. The depositing the sidewall protection layer includes depositing a high-density material in contact with the sidewall of the first wafer. The sidewall protection layer has a density higher than a density of silicon oxide. The method further includes removing a horizontal portion of the sidewall protection layer that overlaps the first wafer, and forming an interconnect structure over the first wafer. The interconnect structure is electrically connected to integrated circuit devices in the first wafer.

The invention discloses a wafer bonding strength characterization method, and relates to the field of wafer bonding tests.The method comprises the steps that a three-dimensional test model of interface fracture mechanics is built, the total deflection and shear modulus generated by a loading point in the test process are analyzed, and a compliance simulation calculation model corresponding to the three-dimensional test model is generated in combination with the crack length; optimizing the compliance simulation calculation model based on the actual model state of wafer bonding to obtain a compliance calculation model, and constructing an energy release rate calculation model in combination with the relationship between the compliance and the crack length; and loading the bonded sample by using a tensile machine, analyzing the peak load of the bonded sample according to the loading result, and obtaining the bonding strength of the bonded sample in combination with the compliance calculation model and the energy release rate calculation model. According to the method, the sample compliance calculation crack length obtained through experiments is substituted into the compliance calculation model and the energy release rate calculation model to obtain the bonding strength characterization result, the measurement method is simple, and the measurement result is more accurate.

The embodiment of the invention provides a wafer bonding structure and a manufacturing method thereof, a manufacturing method of a chip stacking structure and a packaging structure. The manufacturing method of the wafer bonding structure comprises the following steps: providing a first wafer and a second wafer; the first wafer and the second wafer comprise a plurality of chips; forming a first dielectric layer covering the first surfaces of the first wafer and the second wafer; forming a first conductive structure penetrating through the first dielectric layer; the first conductive structure is in contact with the side wall of the first dielectric layer and the top surface of the corresponding chip; a first height difference exists between the top surface of the first dielectric layer and the top surface of the first conductive structure; forming a second dielectric layer covering the top surface of the first dielectric layer; a second height difference exists between the top surface of the second dielectric layer and the top surface of the first conductive structure; the absolute value of the second height difference is greater than that of the first height difference.

The invention relates to the technical field of wafer bonding, in particular to a limiting column concentricity debugging system and a debugging method thereof. The debugging system comprises a carrying disc and at least two limiting columns, the limiting columns are arranged on the carrying disc in the circumferential direction of the carrying disc, each limiting column comprises a limiting key and a column body, a first limiting face and a second limiting face are arranged on each limiting key in a stepped mode, a first limiting space is defined by the first limiting faces, and a second limiting space is defined by the second limiting faces; the diameters of the first limiting space and the second limiting space are different, the first limiting space and the second limiting space are used for placing wafers, the diameters of the first limiting space and the second limiting space are adjustable, the lower end surface of the limiting key is a plane, the upper end surface of the cylinder is a plane, and the lower end surface of the limiting key can be in surface-to-surface contact with the upper end surface of the cylinder. The limiting key can move relative to the column body in the movement allowance range of the through hole, the limiting key can rotate, the limiting key can be applied to wafers with different diameters, and the application range of the limiting key is expanded.

The invention belongs to the technical field of semiconductor wafer process treatment, and particularly relates to a wafer bonding safety floating force application device and a use method thereof. A power source is fixed to a frame, a lead screw is connected with the output end of the power source, the lead screw is in threaded connection with a nut, the nut is fixedly connected with a sliding table plate, and an air cylinder is installed on the bottom face of the sliding table plate; the pressing disc body is connected with a cylinder rod of the air cylinder, and the supporting disc body is fixed to the bottom of the frame and located below the pressing disc body. A pipeline connector of the air cylinder is connected with the electric proportional valve, the electric proportional valve outputs fixed gas pressure needed by bonding to the air cylinder, and the pressing disc body is in pressing fit with the supporting disc body when the air cylinder is in a floating force application state. By adopting a mode of combining a rapid positioning structure and a floating force application structure, floating press fit of the bonding disc in the vacuum cavity is realized, the press fit adaptivity is improved, the control difficulty is reduced, the press fit force control precision is improved, the production safety is enhanced, and the production yield of the bonding process is further improved.

A method for overlay measurement is disclosed. The method includes receiving an image of a bonded wafer. The method includes generating, based on the image, a profile of the bonded wafer. The method includes adjusting, using the profile, an objective lens of a single-focus image-based infrared (IR) system to perform an overlay measurement of the bonded wafer.