1255 results about "Wafer bonding" patented technology

A method of fabricating a semiconductor device includes forming a memory cell array stack including a vertical stack of pad portions over a first substrate, forming first bonding pads each coupled to a different one of the pad portions in the vertical stack, forming control circuits including a plurality of sub-word line drivers over a second substrate, forming multi-layer level metal wiring coupled to the sub-word line drivers, forming second bonding pads coupled to the multi-layer level metal wiring, and performing a wafer bonding process for electrical coupling between the memory cell array stack and the control circuits.

A system includes a wafer shape metrology sub-system configured to perform one or more shape measurements on post-bonding pairs of wafers. The system includes a controller communicatively coupled to the wafer shape metrology sub-system. The controller receives a set of measured distortion patterns. The controller applies a bonder control model to the measured distortion patterns to determine a set of overlay distortion signatures. The bonder control model is made up of a set of orthogonal wafer signatures that represent the achievable adjustments. The controller determines whether the set of overlay distortion signatures associated with the measured distortion patterns are outside tolerance limits provides one or more feedback adjustments to the bonder tool.

The invention relates to the technical field of semiconductor manufacturing, and particularly discloses a turnover device and wafer bonding equipment, the turnover device comprises a support frame, a driving mechanism, a turnover clamping mechanism and a transmission mechanism; the supporting frame is arranged on the side wall of the vacuum chamber and located outside the vacuum chamber. The driving mechanism is arranged on the supporting frame; the turnover clamping mechanism is positioned in the vacuum chamber; the turnover clamping mechanism comprises a turnover mounting seat and a clamping assembly, and the clamping assembly is movably arranged on the turnover mounting seat; the transmission mechanism comprises an inner transmission shaft and an outer transmission shaft arranged outside the inner transmission shaft in a sleeving mode. The driving mechanism is completely arranged outside the vacuum chamber, and power is transmitted through the transmission mechanism, so that a mechanical structure in the vacuum chamber can be optimized, arrangement of components such as cables and a driving source in the vacuum chamber is reduced, the number of the components in the vacuum chamber is reduced, occupied space in the vacuum chamber is reduced, and meanwhile particle pollution is reduced.

The invention provides a wafer bonding device and a wafer bonding method, and relates to the technical field of semiconductor processing. The wafer bonding device comprises a carrying seat, a driving structure arranged on the carrying seat, and a target chuck and a bearing chuck which are arranged along the Z direction, at least one of the target chuck and the bearing chuck is in transmission connection with the driving structure, and the driving structure is configured to be capable of driving the target chuck and the bearing chuck to relatively move along the X-Y direction and the Z direction; a plurality of notches are formed in the edge of the target chuck; the carrying base is provided with a plurality of visual systems, the visual systems are located on the side, away from the bearing chuck, of the target chuck, the axial direction of the visual systems is consistent with the Z direction, the visual systems correspond to the notches one to one, and the visual systems are configured to shoot images, corresponding to the notches, of the wafers loaded on the target chuck and the bearing chuck. The wafer bonding device is good in wafer bonding quality, high in yield, small in size and small in occupied space.

Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises DRAM having bit-cells. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. In one example, the second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights. Ultra high-bandwidth is changed by placing the first die below the second die. The two dies are wafer-to-wafer bonded or coupled via micro-bumps.

Aspects of the present disclosure provide a wafer bonding system, which, for example, can include a wafer bonding tool configured to bond a first wafer and a second wafer to each other in accordance with a first wafer bonding recipe to produce a first post-bond wafer, a metrology tool integrated with the wafer bonding tool, and a tool controller coupled to the wafer bonding tool and the metrology tool. The metrology tool can be configured to measure a physical parameter of the first wafer. The physical parameter of the first wafer representing information relates to topographical features of the first wafer. The tool controller can have a model of a wafer bonding process. The model can include an input indicative of the physical parameter of the first wafer and configured to generate the first wafer bonding recipe based, at least in part, on the physical parameter of the first wafer.

A memory device includes a memory die bonded to a logic die via a wafer-on-wafer bond. A controller of the memory device that is coupled to the memory die can activate a row of the memory die. Responsive to activating the row, a sense amplifier stripe of the memory die can latch a first plurality of signals. A transceiver can route a second plurality of signals from the sense amplifier stripe to the logic die.

A ferroelectric memory chiplet in a multi-dimensional packaging. The multi-dimensional packaging includes a first die comprising a switch and a first plurality of input-output transceivers. The multi-dimensional packaging includes a second die comprising a processor, wherein the second die includes a second plurality of input-output transceivers coupled to the first plurality of input-output transceivers. The multi-dimensional packaging includes a third die comprising a coherent cache or memory-side buffer, wherein the coherent cache or memory-side buffer comprises ferroelectric memory cells, wherein the coherent cache or memory-side buffer is coupled to the second die via I / Os. The dies are wafer-to-wafer bonded or coupled via micro-bumps, copper-to-copper hybrid bond, or wire bond, Flip-chip ball grid array routing, chip-on-wafer substrate, or embedded multi-die interconnect bridge.

The invention belongs to the technical field of photoelectronics, and particularly relates to a wide-spectrum narrow-linewidth semiconductor mode-locked laser, and the collaboration of a saturable absorption region SA and a resonator is reflected in time domain-frequency domain dual optimization. And the resonator optimizes the frequency domain characteristics through nonlinear broadening, phase synchronization and mode purification. The SA adjusts a mode locking threshold value in real time through dynamic bias voltage, the pulse energy stability is ensured, dispersion management of the resonator balances the SPM and group velocity dispersion, spectrum splitting is avoided, and the dissipative soliton form is maintained. Besides, due to heterogeneous integration of the InP-based SA and the SiN-based resonator, wafer bonding of the InP-based SA and the SiN-based resonator is realized, high-efficiency energy transfer is realized through the low-loss conical waveguide, a high-performance frequency comb with a wide spectrum and a narrow pulse width is output, and the high-performance frequency comb can be widely applied to the fields of ultrafast optics, coherent light communication and precision spectroscopy.

The invention relates to the technical field of wafer bonding devices, in particular to a wafer bonding pressure control mechanism and method. The mechanism comprises a main driving unit and a bonding pressing rod linked with the main driving unit, the main driving unit drives the bonding pressing rod to move in the bonding pressure direction, bonding pressure is applied to a wafer through the bonding pressing rod, the bonding pressing rod is linked with the main driving unit through a pressure maintaining air cylinder, and the bonding pressing rod is arranged at the tail end of a piston rod of the pressure maintaining air cylinder; a displacement sensor is further included, the displacement change of the bonding pressing rod is detected through the displacement sensor, and the displacement sensor is electrically connected with the main driving unit. The main driving unit and the pressure maintaining air cylinder are combined to form a composite operation control system, the bonding pressure is controlled and adjusted by controlling the air pressure of the pressure maintaining air cylinder, and the stability of the bonding pressure is ensured.

The invention relates to the technical field of piezoelectric single-crystal filters, in particular to a filter based on a heterogeneous integrated piezoelectric single-crystal thin film and a preparation method, the filter comprises a Si substrate, a dry film, the piezoelectric single-crystal thin film, a SiO2 layer and a Si wafer are sequentially arranged on the Si substrate, metal balls are arranged on the Si wafer, the metal balls are connected with electrodes, and the electrodes are connected with the piezoelectric single-crystal thin film. And the electrode passes through the Si wafer and the SiO2 layer and is connected with the piezoelectric single crystal film. When the filter is prepared, bonding packaging can be performed after a cavity area is etched on a dry film, a resonance area is directly defined through a photoetching process, the influence of etching on the strength of the piezoelectric single crystal film is avoided, a silicon wafer bonding technology can be combined, double-sided packaging can be realized, and batch production is supported; in the process, only the electrode patterning step needs to be adjusted according to the type of the filter, and then the existing MEMS process integration is utilized, so that the preparation of the FBAR and the XBAR on the same production line is realized, the process compatibility is good, and the problems that the existing preparation method is poor in compatibility and is difficult to realize large-scale production are solved.

The invention discloses a double-wafer bonding clamping device and an application method thereof, and relates to the field of wafer bonding, the double-wafer bonding clamping device comprises a chuck, an upper chuck used for adsorbing an upper wafer, a lower chuck, a chassis seat and three clamping positioning mechanisms, the lower chuck is arranged at the bottom of the upper chuck, the chassis seat is arranged at the bottom of the lower chuck, and the three clamping positioning mechanisms are arranged on the chassis seat. A fixing part used for fixing the lower chuck is arranged on the chassis base, the three clamping and positioning mechanisms are arranged in a circumferential array shape with the axis of the lower chuck as the center, and each clamping and positioning mechanism comprises an air cylinder assembly, a Spacer-Clamp fixing base assembly, a Spacer assembly and a Clamp assembly. Through the spacing piece which can be fed in the horizontal direction, spacing clamping of the two wafers after the marking point alignment process is achieved, the upper wafer is pressed through the driving pressing wheel, alignment fixing between the upper wafer and the lower wafer is guaranteed, the wafer gap vacuumizing technology before bonding in the clamp can be achieved, and bubbles of a bonding glue layer are effectively avoided.

A memory device includes a memory die bonded to a logic die. A logic die that is bonded to a memory die via a wafer-on-wafer bonding process can receive signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and memory die. The logic die can also receive signals indicative of kernel data from local input / output (LIO) lines of the memory die and through the bond. The logic die can perform a plurality of operations at a plurality of vector-vector (VV) units utilizing the signals indicative of input data and the signals indicative of kernel data. The inputs and the outputs to the VV units can be configured based on a mode of the logic die.

The invention discloses a wafer-level low-temperature bonding process and a wafer bonding structure based on a smooth surface transfer method, which can realize wafer-level bonding in an air environment and under a low-temperature condition, and the bonding strength reaches the national military standard. According to the wafer-level low-temperature bonding process, firstly, a first bonding metal layer with the root mean square surface roughness smaller than 1 nm and the micron-level thickness is prepared through a transfer method; then, carrying out plasma treatment on the smooth first metal surface of the first bonding metal layer; and finally, heating and pressurizing bonding is carried out in an air environment, so that low-temperature wafer bonding is realized.

The invention discloses a wafer back contact type positioning and clamping fixing device and a wafer bonding method.The wafer back contact type positioning and clamping fixing device comprises a bonding cavity, a lower suction cup, an upper pressing disc, a controller, a pressing driving mechanism, a positioning pressing rod, a clamping driving mechanism and a flexible clamping jaw, and the lower end of the positioning pressing rod can abut against the upper end wall of the lower suction cup; the clamping driving mechanisms are arranged on the two sides of the lower suction cup in an up-down sliding mode, the flexible clamping jaws are connected with the clamping driving mechanisms, the clamping driving mechanisms drive the flexible clamping jaws to slide in the radial direction of the lower suction cup, the flexible clamping jaws are used for clamping and fixing a wafer, and the inner circumferential wall of each flexible clamping jaw can abut against the outer circumferential wall of the wafer. The limiting block can abut against the lower end wall of the edge of the wafer, and the pressing driving mechanism and the clamping driving mechanism are electrically connected with the controller. According to the technical scheme, the wafer surface can be prevented from being polluted and damaged, the stability of the wafer bonding process can be effectively improved, the rejection rate is reduced, the cost is saved, and the high market application and popularization value is achieved.

Embodiments of the present disclosure provide a semiconductor device structure having a vertically stacked complementary field effect transistor (CFET). The CFET is formed by bonding two substrates on which a semiconductor stack is formed. Bonding structures are formed between the semiconductor stacks using wafer bonding techniques. Embodiments of the present disclosure enable flexibility in selecting different N / P channel characteristics, provide a simple way to form N / P channel isolation structures, and reduce potential leakage paths and defects in stacking CFETs. The embodiment of the invention also relates to a semiconductor device and a manufacturing method thereof.

The invention provides a wafer bonding method, which comprises the following steps that a first silicon substrate is provided, a plurality of concave cavities are formed in a preset area of the first silicon substrate, the concave cavities are opened from the top surface of the first silicon substrate and extend downwards by a preset depth, and getter layers are formed on the bottom walls and the side walls of the concave cavities; providing a second silicon substrate, and directly bonding the first silicon substrate and the second silicon substrate; and annealing treatment. According to the invention, by introducing the activation treatment, the first silicon substrate and the second silicon substrate can realize high-quality bonding at a low temperature, and a strong bonding force is maintained. Meanwhile, a plurality of concave cavities filled with getter layers are formed in the first silicon substrate, and the getter layers are activated by adopting vacuum heating treatment, so that the getter layers can quickly and effectively absorb gases such as water vapor and the like generated on an interface in the low-temperature annealing process, the gases are effectively prevented from being accumulated at the bonding interface, cavities are effectively prevented from being formed, and the bonding quality of the semiconductor device is improved. And the reliability and the stability of direct bonding are further improved.

The present invention discloses a wafer bonding magnetic alignment method and device, the device includes at least an X-Y moving system, a bottom wafer bonding table, a magnetic sensor module, a bonding arm module, a device base and a frame. The method makes an alignment groove on the wafer through a semiconductor processing technology, and deposits a magnetic column of magnetic material in the groove. After magnetization, the magnetic column has a permanent magnetic property. The spatial magnetic field distribution in the wafer magnetic column is detected by a magnetic sensor to find the boundary or center of the magnetic column, thereby realizing the detection of wafer position information. Compared with the traditional optical alignment method, the magnetic sensor does not need to calibrate the position, and the alignment is performed when the distance between the two wafers is in the micron level. After alignment, there is no need to move the alignment again, and direct bonding is performed, which improves the efficiency and accuracy of wafer bonding.

Provided in the present invention are an alignment method and apparatus for wafer bonding. A plurality of image collection apparatuses are located on the same side of a wafer to be bonded and have the same collection direction. The alignment method comprises: transferring a first wafer to a predetermined position of a first motion platform, and then fixing the first motion platform; making a plurality of image collection apparatuses perform focused imaging on the first wafer, and using a preset algorithm to determine position coordinates of the first wafer; transferring a second wafer to a predetermined position of a second motion platform, such that the first wafer and the second wafer face each other, wherein the position of the second motion platform is parallel to the position of the first motion platform; making the plurality of image collection apparatuses perform focused imaging on the second wafer, so as to determine position coordinates of the second wafer; adjusting the second motion platform on the basis of the position coordinates of the first wafer and the position coordinates of the second wafer, such that the position of the second wafer is aligned and coincides with the position of the first wafer in an axial direction of the wafers; and adjusting the second motion platform in the axial direction of the wafers, such that the two wafers approach each other for bonding.

The invention discloses a wafer bonding method, which comprises the following steps of: 1, providing a first wafer and a second wafer, the surface of the first wafer being provided with a microstructure with a high aspect ratio; step 2, cleaning the first wafer and the second wafer; step 3, performing vacuum drying treatment on the first wafer and the second wafer, wherein the vacuum pressure is controlled to be 0.1-10 Torr in the vacuum drying treatment process; step 4, carrying out pre-bonding on the first wafer and the second wafer to form a bonding body; and step 5, carrying out annealing treatment on the bonding body. Aiming at the problem of residual water in the pre-cleaning process in the bonding process of the micro-structure wafer with a high aspect ratio, the wafer is placed in a controllable vacuum environment, phase change boiling of liquid water under the condition of no heat input is realized, and the problem of high-temperature heat damage caused by an existing heating and baking method is effectively avoided.

The invention relates to a wafer chuck, a wafer bonding device and a wafer edge deformation compensation method. The wafer chuck comprises a supporting member which is provided with a circular surface for supporting a wafer and is divided into a first area and a second area, and the part, located in the second area, of the supporting member is elastic; the supporting piece is arranged at the top of the disc body, the disc body is provided with a cavity corresponding to the second area and an air entraining channel communicated with the cavity, the air entraining channel is communicated with the suction device, and the adsorption holes are communicated with the cavity; the cavity forms a positive pressure state and a negative pressure state under the action of the suction device, and in the positive pressure state, the part, located in the second area, of the supporting piece protrudes towards the side away from the cavity so as to drive the edge of the wafer to move towards the side away from the cavity; in a negative pressure state, the part, located in the second area, of the supporting piece is recessed towards the interior of the cavity so as to drive the edge of the wafer to move towards the inner side of the cavity. According to the invention, the initial deformation of the edge of the wafer can be compensated, so that the distortion of the edge area of the wafer after bonding is reduced.

According to the invention, the bonding strength between wafers in the semiconductor manufacturing process is improved through a simple structure. Provided is a vacuum chamber (14) for bonding semiconductor wafers (W1, W2) to each other, one using a silicon electrode (G1) and the other using a semiconductor wafer (W2) before bonding crystalline silicon circles (W1, W2) facing each other; after the silicon electrode G1 and the semiconductor wafer W2 are processed for the first time, the silicon electrode G1 is replaced by the bonding wafer G2, and then the bonding wafer G2 and the semiconductor wafer W2 are processed for the second time. Then, the pair of wafers W1 and W2, which are opposite to each other, are bonded together by electrostatic force in a vacuum environment.

A semiconductor device has a first substrate and a first semiconductor layer formed over the first substrate. A second substrate is disposed over a surface of the first semiconductor layer opposite the first substrate. The first semiconductor layer and second semiconductor layer can be silicon carbide or cubic silicon carbide. The first substrate and a portion of the first semiconductor layer are removed to reduce defects in the first semiconductor layer. A second semiconductor layer is formed over a remaining portion of the first semiconductor layer. A third semiconductor layer is disposed over the second semiconductor layer. The third semiconductor layer can be silicon. The third semiconductor layer can be disposed over the second semiconductor layer by direct wafer bonding. An electrical component is formed within the third semiconductor layer. The electrical component can be a power MOSFET, IGBT, CTIGBT, diode, and thyristor.

A semiconductor device includes a backside power rail over a bulk semiconductor material, a first bonding dielectric layer over the backside power rail, a first transistor level over the first bonding dielectric layer, a second bonding dielectric layer over the first transistor level, and a second transistor level over the second bonding dielectric layer. The first transistor level includes first channel structures having a first epitaxially grown semiconductor material. The second transistor level includes second channel structures having a second epitaxially grown semiconductor material. The backside power rail is spaced apart from the first transistor level by a first bonding dielectric layer. The first transistor level is spaced apart from the second transistor level by the second bonding dielectric layer.

The invention provides a low-temperature bonding method for reducing surface damage and a bonding sheet thereof, and relates to the technical field of wafer bonding. In a high vacuum environment, the bonding surfaces of a first wafer and a second wafer which are to be bonded are subjected to first irradiation treatment by using a first atomic beam to obtain a first activation layer; s2, carrying out at least one second irradiation treatment on the bonding surface after the first irradiation treatment in the step S1 by adopting a second atomic beam to obtain a second activation layer; and carrying out ballasting bonding to obtain a bonding sheet. According to the low-temperature bonding method for reducing the surface damage, the bonding surface is activated in a gradient manner, so that the damage to the surface of the wafer caused by single activation can be reduced, the surface roughness is reduced, the probability of bubbles after bonding is reduced, and the bonding strength is improved.

A semiconductor wafer bonding tool is provided. The semiconductor wafer bonding tool can be used to perform a wafer-wafer bonding between a first semiconductor wafer and a second semiconductor wafer. The semiconductor wafer bonding tool includes a wafer bonding chuck configured to support a first semiconductor wafer at a first side. A plurality of discrete actuators are disposed at the first side of the wafer bonding chuck. Respective actuators of the plurality of discrete actuators are capable of displacing independently of one another. The respective actuators can be displaced based on one or more characteristics of the first semiconductor wafer or the second semiconductor wafer. In doing so, an improved wafer-wafer bonding process can be implemented.

The invention relates to the technical field of wafer processing, and discloses a wafer bonding machine for grinding and polishing, the wafer bonding machine comprises a fixing mechanism, a fixing assembly is fixedly arranged in the fixing mechanism, and a closing assembly is fixedly arranged on the inner wall of the fixing mechanism. The plurality of arc-shaped plates are in a stacked state, when the arc-shaped plates rotate, the center positions of the plurality of arc-shaped plates form a circular clamping area, the area clamps and limits the side wall of a wafer at the top of the microporous ceramic vacuum chuck, and when the wafer is clamped and limited, the side wall of the wafer at the top of the microporous ceramic vacuum chuck is clamped and limited. The wafer is guaranteed to be located at the center position of the micropore ceramic vacuum suction cup through pushing of the multiple arc-shaped plates, then the micropore ceramic vacuum suction cup generates adsorption force, and under the influence of the adsorption force and side wall clamping force, it is guaranteed that the device can conduct clamping and adsorption treatment on wafers of different specifications.

The invention relates to the technical field of temporary wafer bonding, in particular to a high-precision wafer alignment device, and mainly solves the technical problem that a wafer alignment device is low in precision. The device comprises a rack, a visual mechanism, an adsorption platen, an XYZ three-axis platform, a rotating platform and an adjusting platform, the rack comprises a base and a portal frame, the visual mechanism is installed above a cross beam of the portal frame, the adsorption platen is fixed below the cross beam of the portal frame, the XYZ three-axis platform is installed on the base and located on the inner side of the portal frame, and the rotating platform is installed on the XYZ three-axis platform. The adjusting platform comprises a bottom plate, a top plate and leveling assemblies, the bottom plate is fixed to the rotating platform, and the leveling assemblies are connected between the bottom plate and the top plate and distributed at intervals in the circumferential direction. According to the device, on one hand, position calibration of the lower wafer and the upper wafer can be achieved, on the other hand, precision reduction caused by taking down, transferring and placing can be avoided, the precision of the upper wafer and the lower wafer when the upper wafer and the lower wafer are finally fixed can be guaranteed through cooperation of the two aspects, and therefore the process requirement is met.

The invention belongs to the field of semiconductor processing and manufacturing, and provides a temporary bonding and de-bonding method, a composite substrate preparation method and a wafer manufacturing method.The temporary bonding and de-bonding method comprises the steps that silicon oxide layers are formed on two silicon substrates; the silicon oxide layer is subjected to ion implantation, hydrofluoric acid treatment and plasma activation, temporary bonding of the two silicon substrates is realized through hydrophilic bonding, and a temporary bonding interface is cracked through de-bonding annealing, so that de-bonding is realized. According to the method, a bonding medium does not need to be used, the thermal properties of the two substrates can be kept consistent, and warping and breaking are effectively avoided; temporary bonding is high in strength and good in stability, the functional substrate can be greatly thinned through the method, and therefore the composite substrate is prepared or the method is further used for manufacturing a multi-layer wafer bonding structure.

Embodiments of the present disclosure provide a semiconductor device structure having vertically stacked complementary field effect transistors (CFETs). The CFETs are formed by bonding two substrates having semiconductor stacks formed thereon. A bonding structure is formed between the semiconductor stacks using wafer bonding technology. Embodiments of the resent disclosure enable the flexibility of choosing different N / P channel properties, provide a simple way to form the N / P channel isolation structure, and reduce potential leakage path and defects in stacked CFETs.