72 results about "Wafer bonding" patented technology

The present application provides a flip chip light emitting diode and a manufacturing method thereof. The flip chip light emitting diode comprises a transparent substrate, an epitaxial composite layer, a first conductive type electrode pad, a second conductive type electrode pad and a wafer bonding composite layer. The epitaxial composite layer is disposed on the transparent substrate. The first conductive type electrode pad is disposed on the transparent substrate and electrically connected to the epitaxial composite layer. The second conductive type electrode pad is disposed on the epitaxial composite layer and electrically connected to the epitaxial composite layer, and is located on the same horizontal plane as the first conductive type electrode pad on the same side of the transparent substrate. The wafer bonding composite layer comprises at least one titanium dioxide (TiO2) layer and at least one silicon dioxide (SiO2) layer, and is interposed between the epitaxial composite layer and the transparent substrate.

Techniques and / or systems are disclosed herein for forming a window cavity wafer that includes fabricating a window wafer by: providing a window wafer substrate having two faces; etching fiducials onto one or more faces of the window wafer substrate; and applying one or more optical coatings to on one or more faces of the window wafer substrate. Next, fabricating a spacer wafer separate from the window wafer by: providing a spacer wafer substrate having two faces; and forming an array of through-holes in the spacer wafer substrate. Then, bonding the spacer wafer to the window wafer to form the window cavity wafer; and forming discrete metal frames on a face of the window cavity wafer.

The present disclosure provides an engineered epitaxial wafer of an ultra-thin GaN HEMT by wafer bonding and a manufacturing method thereof. According to an embodiment of the present invention, there is provided an engineered epitaxial wafer of an ultra-thin GaN HEMT by wafer bonding, comprising: a support substrate; an electrically insulating thin film region disposed on the support substrate; a buffer region disposed on the electrically insulating thin film region and containing Al(x)Ga(1-x)N (0≤x<1) doped with undoped carbon (C) and iron (Fe); a channel region disposed on the buffer region and containing Al(y)Ga(1-y)N (0≤y≤1); and a barrier region disposed on the channel region and containing Al(z)Ga(1-z)N (0<z<1) or In(w)Al(1-w)N (0<w<1).

A wafer on wafer on wafer and a chip on wafer on wafer structure and methods of forming the same are provided. In accordance with some embodiments, a first device wafer is bonded to a first carrier through wafer-on-wafer bonding and additional device wafers may subsequently be bonded to the first device wafer. A support wafer is then bonded to the top most device wafer and the first wafer may then be removed. The bonded wafer structure may then be singulated into individual semiconductor device packages. Through the wafer-on-wafer bonding process, the manufacturing cost and cycle time may be reduced.

The present invention relates to a multi-axis stage apparatus capable of significantly improving the precision of wafer bonding, a wafer bonding method using the apparatus, and a wafer bonding apparatus. The apparatus includes a base, an alignment stage configured to align a first wafer held by a first wafer chuck, a first driving device positioned between the base and the alignment stage and configured to vertically move the alignment stage with low precision, and a second driving device also positioned between the base and the alignment stage and configured to vertically move the alignment stage with high precision. The second driving device may include a flexure hinge, at least a portion of which is configured to distribute load. By combining coarse and fine vertical movement control and supporting structures based on flexure mechanics, the apparatus enables precise multi-axis alignment and bonding of wafers.

This invention provides a method for eliminating bonding interface defects, a module for eliminating bonding interface defects, a semiconductor device processing apparatus, and a computer-readable storage medium. The method for eliminating bonding interface defects includes the following steps: locating at least one bubble defect on the bonding interface of a grain-wafer bond; and applying a pulsed high-energy beam from the grain side of the bonding interface to the at least one bubble defect to form at least one venting micro-via penetrating the corresponding grain above the bubble defect, wherein the peak power of the pulsed high-energy beam is not less than 10 kW, and its single-pulse energy is not greater than 1 mJ.

The application relates to the field of mice, and discloses an optoelectronic chip and a mouse. The optoelectronic chip comprises a packaging piece, a lead frame, a patch element and a circuit wafer. The lead frame is partially arranged in the packaging piece. The lead frame has a first surface and a second surface. The patch element is arranged on the first surface of the lead frame. The circuit wafer is arranged on the second surface of the lead frame. The circuit wafer is connected with the lead frame through a wire. According to the application, the patch element is integrated on the first surface of the lead frame, and the circuit wafer is arranged on the second surface of the lead frame to form a double-layer layout structure. The patch welding process and the circuit wafer bonding process are independently implemented on the two working surfaces of the lead frame. The mouse function modules are highly integrated. When the mouse is produced, only a single packaging chip is used to replace the original discrete element layout. The mouse circuit board design complexity is greatly simplified, and the mouse manufacturer saves high-precision patch equipment.

A semiconductor package assembly process that uses a self-aligned die-to-wafer bonding process that aligns interconnects of a semiconductor die with corresponding interconnects of a wafer. A surface preparation process assists in the accurate alignment of the die and the wafer. The surface preparation process serves to define a liquid confinement region that helps ensure accurate alignment. Additionally, the surface preparation process helps ensure that the bonding surfaces of the wafer and the die are smooth and free of debris, which enhances the quality of the bonds between the interconnects of each component. When the surfaces of the wafer and the die have been prepared, the self-aligned die-to-wafer bonding process utilizes surface tension to align the interconnects of the die with the interconnects of the wafer.

This utility model discloses an upper imprinting device and a vacuum nanoimprinting equipment with an airbag structure, including: an upper imprinting mold frame, an airbag assembly, an airbag driving device, an airbag vacuuming device, and a cavity vacuuming device. The upper imprinting mold frame is driven by the upper mold frame driving device, and the upper imprinting mold frame has an upper cavity. The airbag assembly is placed in the upper cavity and includes: an upper locking ring plate, a lower locking ring plate, and an airbag. The upper and lower locking ring plates are concentrically arranged and connected to each other, and the edge of the airbag is clamped between the upper and lower locking ring plates. Under the action of the airbag vacuuming device and the cavity vacuuming device, a vacuum pressure difference is formed inside and outside the airbag, and the airbag expands outward, applying downward pressure to the center area of ​​the wafer, causing the wafer to deform accordingly. This utility model achieves deformation of the center area of ​​the wafer by expanding and applying pressure under vacuum pressure difference, thereby improving the accuracy of wafer bonding with the motherboard and the imprinting yield.

A semiconductor package assembly process uses a self-aligning die-to-wafer bonding process that aligns interconnects of a semiconductor die with corresponding interconnects of a wafer. A surface preparation process assists in the accurate alignment of the die and the wafer. The surface preparation process is used to define a liquid confinement area that helps ensure accurate alignment. Additionally, the surface preparation process helps ensure that the bonding surfaces of the wafer and the die are smooth and free from debris, which enhances a bond quality between the interconnects of each component. When the surfaces of the wafer and the die have been prepared, the self-aligning die-to-wafer bonding process utilizes surface tension to align the interconnects of the die with the interconnects of the wafer.

The application provides a wafer bonding alignment device for bonding a first wafer to a second wafer, comprising a hot plate, a spacer mechanism, an alignment mechanism, a plurality of limiting grooves pointing to the center of the hot plate are arranged on the side of the hot plate; the alignment mechanism comprises a flexible alignment assembly, a floating plate and a third driving mechanism; the floating plate is transversely provided with a guide support, the guide support forms a guide surface towards the hot plate, the flexible alignment assembly comprises a positioning assembly, a rolling body guided by the guide surface and a resisting assembly; the floating plate is driven to move up and down by the third driving mechanism, the rolling body slides under the guidance of the guide surface, the positioning assembly moves radially to expand and contract along the limiting grooves, so as to perform alignment on the edges of the first wafer and the second wafer before the first wafer and the second wafer are at least attached. The application significantly improves the wafer concentricity alignment effect, eliminates the transverse error generated in the secondary alignment process, and avoids the phenomenon of wrinkles and local missing of the bonding glue.

A memory die is bonded to a logic die on a wafer by die-to-wafer bonding. The logic die may include surface metal pads having first planar horizontal surfaces located within a horizontal plane including a bonding interface and located within an area not overlapping with an area of the memory die. Alternatively or additionally, electrically conductive paths may be present between sense amplifiers in the logic die and first bit lines in the memory die. The electrically conductive paths may include second bit lines located in the logic die and laterally extending from within an area overlapping with the area of the memory die to an area not overlapping with the area of the memory die in a plan view. One or more memory die can be attached to the logic die.

This application relates to a multi-axis platform device that can significantly improve the accuracy of wafer bonding, a wafer bonding method using the multi-axis platform device, and a wafer bonding apparatus. The multi-axis platform device includes a base, an alignment platform, a first driving element, and a second driving element. The alignment platform is used to align a first wafer held in a first wafer chuck. The first driving element is disposed between the base and the alignment platform and is used to coarsely move the alignment platform in the vertical direction. The second driving element is disposed between the base and the alignment platform and is used to finely move the alignment platform in the vertical direction. The second driving element includes a flexible hinge, at least a portion of which is used to distribute the load. By combining coarse and fine vertical movement control with a support structure based on a flexible mechanism, the multi-axis platform device can achieve precise multi-axis alignment and bonding of wafers.

In wafer-to-wafer bonding, a first die is bonded to a second die at a bonding interface. Various configurations of capacitors are placed along an inner portion of an edge seal of the bonded dies to detect a discontinuity in the bonding interface. These configurations include interdigitated capacitors, which can be horizontally or vertically oriented, parallel-digitated capacitors, and pillars forming a parameter around the dies with conductive portions offset from the pillar and extending inside the dies. Other configurations can be used.

A multi-die semiconductor assembly integrates a manually-designed full-custom compute die with a peripheral die providing input / output, memory, power, and clock resources through a hybrid-bonded electrical connection comprising chip-to-chip, chip-to-wafer, or wafer-to-wafer bonding. The compute die operates without bond pads, standard-cell libraries, or automated synthesis, and the assembly functions independently of qualified digital or analog intellectual-property resources for the compute-die process node. Dense hybrid-bonded conductive paths carry both signal and power, enabling early functional hardware at advanced nodes before design-library availability while sustaining high activation bandwidth for transformer-class inference workloads.

Technology is disclosed herein for a memory device with multiple dies bonded together. The memory device may be referred to herein as an integrated memory assembly. The integrated memory assembly has a control semiconductor die and two or more memory semiconductor dies. In one embodiment, each memory semiconductor die has a memory structure having blocks of memory cells. Bit lines extend over the respective memory structure. In one embodiment the integrated memory assembly has what is referred to herein as a “separate bit line architecture”. The separate bit line architecture allows the control semiconductor die to control a memory operation in parallel in the two memory semiconductor dies. Moreover, the separate bit line architecture allows for good scaling of a memory device with multiple dies bonded together.

The application discloses a manufacturing method of a high-speed back-illumination photodiode integrated with a micro-lens, and comprises the following steps: step 1, preparation of wafer front surface technology and marking; step 2, wafer bonding; step 3, wafer back surface thinning; step 4, wafer back surface photoetching: S41, wafer back surface glue coating; S42, pre-alignment; S43, turning on an infrared light source of a projection scanning photoetching machine to obtain a correction parameter value; S44, step-by-step exposure; S45, repeating step S44 until exposure of all exposure fields is completed; and step 5, silicon lens forming. The manufacturing method combines high-precision alignment in the projection scanning photoetching machine with an infrared penetration optical system, is used for compensating for nonlinear deformation of a thin wafer after bonding, and thus realizes a manufacturing method of sub-micron level accurate overlay of front and back surface patterns of an optoelectronic device.

This invention provides a wafer bonding assembly and wafer bonding equipment, relating to the field of wafer bonding technology. The wafer bonding assembly includes: a fixture and multiple spacers; the fixture holds a wafer to be bonded; when the wafer is placed on the fixture, the fixture surrounds the wafer; the multiple spacers are spaced apart circumferentially along the fixture; a first end of each spacer is connected to the fixture, and a second end of each spacer is provided with a support portion, which is located between two wafers when the wafer is placed on the fixture; wherein the total area of ​​the multiple support portions is greater than or equal to a first threshold; the first threshold is: the area of ​​the support portion corresponding to the maximum stress that the part with the lowest yield strength in the support portion can withstand when the support portion is pulled out from between the two wafers.

The application relates to an image recognition method, device and system for wafer bonding. The method according to some embodiments of the application comprises: providing a template image; detecting edges in the template image; screening the detected edges to obtain an outer edge of a template region in the template image; and measuring the position of the template region in the template image. Compared with the prior art, the application can automatically screen the template region in the template image, and can also obtain highly consistent templates for multiple cameras, thereby improving the image recognition accuracy.

This invention provides a flip-chip type light-emitting diode and a method for manufacturing the same that improve light extraction efficiency and simplify the manufacturing process. [Solution] The flip-chip light-emitting diode includes a transparent substrate 208, an epitaxial composite layer, a first conductivity type electrode pad 211, a second conductivity type electrode pad 212, and a wafer bonding composite layer. The epitaxial composite layer is mounted on the transparent substrate and includes a first compound semiconductor layer 204, a light-emitting layer 203, and a second compound semiconductor layer 202. The first conductivity type electrode pad is mounted on the transparent substrate and electrically connected to the epitaxial composite layer. The second conductivity type electrode pad is mounted on the epitaxial composite layer, electrically connected to the epitaxial composite layer, and is located on the same side of the transparent substrate at the same height as the first conductivity type electrode pad. The wafer bonding composite layer includes at least one titanium dioxide (TiO2) layer 206 and at least one silicon dioxide (SiO2) layer 207.

The present invention provides a material joining method, material joining apparatus, and joined body that can prevent poor conductivity and increased connection resistance when joining a first material and a second material. [Solution] The method comprises: an activation step in which, in a vacuum environment and with the plasma lit, a processing gas containing hydrogen is supplied to reduce the oxide films Oe1 and Oe2 formed on the electrode portions Ze1 and Ze2 of the first material Z1 and the second material Z2 to remove the oxide films Oe1 and Oe2, and activate the surfaces of the non-electrode portions Zi1 and Zi2 of the first material Z1 and the second material Z2; and a joining step in which, after the activation step, in a vacuum environment and with the plasma lit, or immediately after the vacuum environment and the plasma is turned off, the electrode portion Ze1 of the first material Z1 and the electrode portion Ze2 of the second material Z2, and the non-electrode portion Zi1 of the first material Z1 and the non-electrode portion Zi2 of the second material Z2 are joined together so that they come into contact with each other.

The inventive concept provides an image sensor including a step having a slope shape and an image sensor including the wafer-to-wafer bonding structure. The image sensor includes a first substrate including a pixel array, a first multilayer wiring, a first insulation layer formed on a first junction surface to pass through the first insulation layer and a second substrate on the first substrate, wherein the second substrate includes a logic circuit, a second multilayer wiring, a second insulation layer on a second junction surface opposite to the first junction surface and a second metal pad passing through the second insulation layer, and a second step formed in the second junction surface engages with a first step formed in the first junction surface in a symmetrical slope shape to form direct bonding between the first substrate and the second substrate.

A wafer hybrid bonding structure and method includes: a first wafer having a first functional surface, a first dielectric structure located on the first functional surface, and a first conductive structure located within the first dielectric structure. The first dielectric structure includes a first dielectric layer, and the first conductive structure includes a first conductive layer and a first metal barrier layer located on the surface of the first conductive layer. A second wafer bonded to the first wafer has a second functional surface. A second dielectric structure located on the second functional surface and a second conductive structure located within the second dielectric structure, the second conductive structure including a second conductive layer, wherein the first conductive structure and the second conductive structure are bonded to each other, and the first dielectric structure and the second dielectric structure are bonded to each other, which can reduce the diffusion of metal from the first conductive layer to the second dielectric structure, thereby improving the reliability of the device.

A processing method for a bonded wafer in which a first wafer and a second wafer are bonded, includes forming a ring-shaped modified layer by focusing and applying a laser beam adjacently inside a chamfered portion formed on an outer periphery of a first wafer; facilitating removal of the chamfered portion by supplying a liquid that weakens a bonding force to an interface between the first wafer and a second wafer bonded together in the chamfered portion and allowing the liquid to penetrate into the interface until the chamfered portion is removable; and grinding the first wafer of the bonded wafer held such that the second wafer faces a chuck table of a griding apparatus, thereby thinning the first wafer and removing the chamfered portion.

This invention discloses an antistatic substrate-free wafer bonding film and its preparation method, belonging to the field of thin film technology. The film contains antistatic nanoneedle composite microspheres and Schiff base corrosion inhibitor complexes. The two work synergistically to endow the wafer bonding film with excellent mechanical strength, antistatic properties, and corrosion resistance, and also have thermal conductivity, which can be applied to wafers and extend the service life of the wafer bonding film. The antistatic nanoneedle composite microspheres and Schiff base corrosion inhibitor complexes form a functionally complementary and structurally synergistic filler system in the matrix. The one-dimensional structure of the nanoneedles can act as a reinforcing phase, inhibiting the initiation of internal cracks in the film layer and improving the tensile strength of the film layer. The Schiff base structure can coordinate with the copper and zinc in the antistatic nanoneedle composite microspheres, firmly anchoring the Schiff base corrosion inhibitor complexes to the surface of the nanoneedle microspheres, allowing the corrosion inhibition sites to be evenly distributed in the film layer with the nanoneedle microspheres, improving the long-term effectiveness and uniformity of corrosion inhibition performance.

This invention belongs to the field of communication automation technology and discloses a system and method for intelligent optimization of HBM bonding process for ultra-fine stacking. Addressing the process pain points of ultra-fine stacked HBM bonding, this invention constructs three core modules: micro-nano-level modification and control of the bonding interface, precise adaptation of the wafer bonding force field, and intelligent correction of micro-deformation after bonding. These modules cover the entire process of HBM bonding, from interface preprocessing and dynamic bonding to post-processing shape control. By employing core technologies such as precise construction of micro-nano textures of the bonding interface, multi-dimensional adaptation of the bonding force field of heterogeneous wafers, and real-time measurement and correction of micro-deformation of the bonding wafer, it overcomes the technical bottlenecks of traditional HBM bonding processes, including "weak interface bonding force, poor bonding force field adaptability, and difficulty in correcting micro-deformation after bonding." This achieves strong bonding of the HBM bonding interface, dynamic force field matching during the bonding process, and precise correction of micro-deformation of the wafer after bonding, significantly improving the bonding yield, interface interconnect reliability, and stacking accuracy of ultra-fine stacked HBM, and adapting to the packaging requirements of HBM5 and subsequent ultra-fine stacked high-bandwidth memory chips.

The embodiment of the invention provides a wafer binding method and device based on a double-workbench photoetching machine, the double-workbench photoetching machine comprises an exposure machine table and a control device for controlling the operation of the photoetching machine, the exposure machine table comprises two workbenches, the method is applied to the control device, and the method comprises the following steps: obtaining historical operation data, determining a cut-off historical wafer according to the historical operation data, determining a first workbench for a workbench corresponding to the cut-off historical wafer, obtaining an arrangement sequence of each to-be-processed target wafer, determining a first to-be-processed target wafer, determining a second workbench as a workbench corresponding to the first to-be-processed target wafer, and determining the second to-be-processed target wafer as a second workbench corresponding to the second to-be-processed target wafer; and according to a mode that the first workbench and the second workbench alternately correspond to each other, determining a workbench corresponding to each to-be-processed target wafer after the first to-be-processed target wafer, and binding each to-be-processed target wafer with the corresponding workbench. Based on the method provided by the invention, the productivity of the photoetching machine can be improved.

A memory die is bonded to a logic die on a wafer by die-to-wafer bonding. The logic die may include surface metal pads having first planar horizontal surfaces located within a horizontal plane including a bonding interface and located within an area not overlapping with an area of the memory die. Alternatively or additionally, electrically conductive paths may be present between sense amplifiers in the logic die and first bit lines in the memory die. The electrically conductive paths may include second bit lines located in the logic die and laterally extending from within an area overlapping with the area of the memory die to an area not overlapping with the area of the memory die in a plan view. One or more memory die can be attached to the logic die.

The utility model belongs to sensing equipment technical field relates to a pressure sensing device, including shell and cooperation setting on the shell upper cover, the shell and upper cover form the accommodation space between, be provided piezoelectric wafer in the accommodation space, piezoelectric wafer and shell fixedly bond between, and piezoelectric wafer and shell still have the lug between connection, the shell has the recess portion with piezoelectric wafer coaxial setting in, and the convex part correspondingly piezoelectric wafer circumferential setting, piezoelectric wafer fixedly bond on the convex part, the lug one side and piezoelectric wafer bond, the other side and the convex rib on the shell corresponding connection. The utility model can improve the voltage of knock feedback, and its feedback highest voltage is about 10V, has simple structure, and it is convenient to assemble, stable performance, effect is improved obviously and so on advantage.