4 results about "Three dimensional integration" patented technology

A device comprises a first interconnect structure, a second interconnect structure, a stacked complementary transistor structure, a first contact, and a second contact. The stacked complementary transistor structure is disposed between the first and second interconnect structures. The stacked complementary transistor structure comprises a first transistor of a first type, and a second transistor of a second type which is opposite the first type. The first contact connects a first source / drain element of the first transistor to the first interconnect structure. The second contact connects a first source / drain element of the second transistor to the second interconnect structure. The first and second contacts are disposed in alignment with each other.

This invention provides a multimodal transport path planning method and a dedicated sorting robot based on a medium-to-large cargo sorting robot. The method includes: identifying the center of gravity offset and rotational inertia tensor of the target medium-to-large cargo based on detected data to construct a three-dimensional overturning risk field with the robot's center of mass as the origin; mapping the three-dimensional overturning risk field to the interior of a three-dimensional multimodal transport spatiotemporal network, and assigning corresponding safety margin values ​​to each spatiotemporal node by combining the equipment parameters, communication time windows, and dynamic load states of each transport node; using a spatiotemporal A* algorithm for path search, and retaining only spatiotemporal nodes with safety margin values ​​greater than a preset margin threshold as path nodes during the search process; and performing three-dimensional integration processing on each path node to generate a multimodal transport path adapted to the target medium-to-large cargo. This invention can significantly improve path planning efficiency.

Three-dimensional integrated circuit (3DIC) structures and methods of forming the same are provided. A 3DIC structure includes a semiconductor package, a first package substrate, a molded underfill layer and a thermal interface material. The semiconductor package is disposed over and electrically connected to the first package substrate through a plurality of first bumps. The semiconductor package includes at least one semiconductor die and an encapsulation layer aside the semiconductor die. The molded underfill layer surrounds the plurality of first bumps and a sidewall of the semiconductor package, and has a substantially planar top surface. The CTE of the molded underfill layer is different from the CTE of the encapsulation layer of the semiconductor package. The thermal interface material is disposed over the semiconductor package.

Conductive vias for 3D integration may be formed during or after assembly to couple dies or die stacks. In one example, such conductive vias may extend through the dies or die stacks and through an interface with conductive bumps, without terminating on the bumps. Bypassing conductive bumps with a conductive via may enable improved performance, power delivery, and thermal management. In one example, an assembly includes a first IC structure (such as a substrate, interposer, or other IC structure) and a second IC structure (such as a die or die stack) over the first IC structure. The assembly includes an interface layer between the first IC structure and the second IC structure, where the interface layer includes a plurality of conductive bumps. A conductive via extends through the interface layer with the bumps and is coupled with a conductive element of the first IC structure.