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2 results about "Three dimensional integration" patented technology

A multimodal transport path planning method based on a large and medium-sized sorting robot and a special sorting robot

PendingCN122353636ASimulationThree dimensional integration
This invention provides a multimodal transport path planning method and a dedicated sorting robot based on a medium-to-large cargo sorting robot. The method includes: identifying the center of gravity offset and rotational inertia tensor of the target medium-to-large cargo based on detected data to construct a three-dimensional overturning risk field with the robot's center of mass as the origin; mapping the three-dimensional overturning risk field to the interior of a three-dimensional multimodal transport spatiotemporal network, and assigning corresponding safety margin values ​​to each spatiotemporal node by combining the equipment parameters, communication time windows, and dynamic load states of each transport node; using a spatiotemporal A* algorithm for path search, and retaining only spatiotemporal nodes with safety margin values ​​greater than a preset margin threshold as path nodes during the search process; and performing three-dimensional integration processing on each path node to generate a multimodal transport path adapted to the target medium-to-large cargo. This invention can significantly improve path planning efficiency.
Owner:DANBACH ROBOT JIANGXI INC

Conductive vias for three dimensional integration

Conductive vias for 3D integration may be formed during or after assembly to couple dies or die stacks. In one example, such conductive vias may extend through the dies or die stacks and through an interface with conductive bumps, without terminating on the bumps. Bypassing conductive bumps with a conductive via may enable improved performance, power delivery, and thermal management. In one example, an assembly includes a first IC structure (such as a substrate, interposer, or other IC structure) and a second IC structure (such as a die or die stack) over the first IC structure. The assembly includes an interface layer between the first IC structure and the second IC structure, where the interface layer includes a plurality of conductive bumps. A conductive via extends through the interface layer with the bumps and is coupled with a conductive element of the first IC structure.
Owner:INTEL CORP