High-reliability TSV (Through Silicon Via) technique based on SOI (Silicon-On-Insulator) substrate

Abstract

The invention provides a high-reliability TSV technique based on a SOI substrate. According the technique, the existing silicon-silicon dioxide-silicon sandwich structure of the SOI substrate is not damaged, but three-dimensional integration of the SOI substrate is directly performed, so that each layer of the formed three-dimensional integrated device is provided with a buried oxide layer. The three-step etching technology is adopted to replace the existing single-step etching technology in the traditional SOI TSV technique. The method comprises the following steps: firstly etching top layer silicon, secondly etching the buried oxide layers, and at last etching bottom layer silicon, wherein the etching window of the top layer silicon is larger than that of the buried layers and the bottom layer silicon to form a horizontal etching margin on the buried oxide layer interface. The high-reliability TSV technique can avoid potential safety hazards such as the increase of electric leakage possibility and the reduction of withstand voltage, increase the possibility of the three-dimensional integrated device, greatly improve the performance of the SOI three-dimensional integrated device, and is high in the reliability.

Description

technical field [0001] The invention relates to the technical field of microelectronics. Background technique [0002] SOI devices have the characteristics of good radiation resistance, high temperature resistance, high voltage and low leakage. However, most of the TSV process methods based on SOI substrates fail to give full play to the radiation resistance, high temperature resistance, high voltage and low leakage of SOI substrates. and other advantages. As described in the document "An SOI-based three-dimensional integrated circuit technology (IEEE international SOI conference proceedings)", the TSV process method based on the SOI substrate used will make the buried oxide layer thinner when thinning the back of the wafer. As a corrosion barrier layer, all the underlying silicon is removed by chemical mechanical polishing and etching, so as to form an ultra-thin wafer with only the top silicon and buried oxide layer left. bonding (see figure 1 ). It can be seen that du...

AI Technical Summary

Problems solved by technology

Due to the existence of the "Notching" structure, it will be difficult to make subsequent insulation layers, barrier layers / seed layers, and through-hole metallization on the side walls of the through-holes. There will be potential safety hazards such as increased leakage and reduced withstand voltage, which will seriously affect the performance and performance of SOI three-dimensional integrated devices. reliability

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