595 results about "Microelectronics" patented technology

The invention discloses a power source power optimization method, system and device of a copper wire system and a storage medium, and relates to the technical field of bonding copper wire production, and the method comprises the following steps: building an intelligent bonding copper wire system simulation model, obtaining virtual parameters based on the intelligent bonding copper wire system simulation model, and optimizing the virtual parameters; the optimized virtual parameters are applied to actual bonding equipment, and the actual power and the bonding effect of the bonding equipment are collected. According to the intelligent bonding copper wire system, the energy efficiency can be remarkably improved through power optimization of a power source, in the field of semiconductor packaging and microelectronic manufacturing, a traditional bonding process often depends on fixed power setting, the setting cannot adapt to different working conditions and material characteristics, energy loss and unstable bonding quality are caused, and the energy efficiency is affected. By optimizing the power of the power supply in real time, the method reduces unnecessary power consumption, reduces the production cost, and improves the bonding quality at the same time.

Advanced flat metals for microelectronics are provided. While conventional processes create large damascene features that have a dishing defect that causes failure in bonded devices, example systems and methods described herein create large damascene features that are planar. In an implementation, an annealing process creates large grains or large metallic crystals of copper in large damascene cavities, while a thinner layer of copper over the field of a substrate anneals into smaller grains of copper. The large grains of copper in the damascene cavities resist dishing defects during chemical-mechanical planarization (CMP), resulting in very flat damascene features. In an implementation, layers of resist and layers of a second coating material may be applied in various ways to resist dishing during chemical-mechanical planarization (CMP), resulting in very flat damascene features.

The invention relates to the field of microelectronic manufacturing, and discloses a high-performance monocrystalline silicon nano wafer manufacturing process which comprises the following steps: preparing a monocrystalline silicon wafer, and obtaining a high-quality monocrystalline silicon wafer through fine cutting, chemical mechanical polishing and surface residual stress elimination treatment; multi-stage cleaning and surface treatment are carried out, and surface pollutants are removed through combination of molecular chromatography, electric field assisted ultrasonic cleaning and low-temperature plasma cleaning; and manufacturing a nano structure, and forming a complex nano structure by adopting multi-stage electron beam lithography, segmented reactive ion etching and self-adaptive deep etching regulation and control. The surface quality, the mechanical strength and the electrical property of the wafer are remarkably improved through the technologies of refined monocrystalline silicon wafer preparation, multi-stage cleaning, advanced nanostructure manufacturing, self-adaptive heat treatment and the like; and through surface functionalization and multi-layer high-precision packaging, the environmental tolerance and long-term reliability of the nanostructure are enhanced.

Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.

Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.

The invention relates to a microelectronic device surface defect detection method based on improved YOLOv9, and the method comprises the steps: collecting a microelectronic device surface image, forming a microelectronic device surface image sample set after defect classification and marking, carrying out data enhancement to obtain an expanded data set, and dividing the expanded data set into a training set, a verification set and a test set; an efficient multi-scale attention mechanism module is introduced into a backbone network backbone of the YOLOv9 model, and a microelectronic device surface defect detection model based on the improved YOLOv9 is constructed; training the microelectronic device surface defect detection model based on the improved YOLOv9 by using the training samples in the training set to obtain an optimized microelectronic device surface defect detection model; and obtaining a to-be-detected microelectronic device image, inputting the to-be-detected microelectronic device image into the optimized microelectronic device surface defect detection model for detection, and outputting a detection classification result. The problem that the defect detection effect under small samples and small targets is poor can be solved, and the accuracy of microelectronic device surface defect detection is improved.

A microelectronics package comprises a substrate comprising at least two conductive layers that are separated by a first dielectric. At least one island comprising a magnetic material is embedded within the dielectric between the two conductive layers. An inductor structure extends within a via in the at least one island. The via extends between the two conductive layers. The inductor structure comprises a conductive wall along a sidewall of the via, and wherein the conductive wall surrounds a second dielectric and is electrically coupled to the two conductive layers.

The invention discloses a power MOSFET and a preparation method thereof, and belongs to the technical field of microelectronics. The power MOSFET comprises a substrate layer, an AlN buffer layer, a Ga2O3 buffer layer and a Ga2O3 epitaxial layer which are arranged from bottom to top, wherein the top surface of the Ga2O3 epitaxial layer is provided with a groove, and an oxide isolation layer is arranged in the groove; the drain electrode is arranged on one side of the Ga2O3 epitaxial layer and is adjacent to the oxide isolation layer; the source electrode is arranged in the middle area of the other side of the Ga2O3 epitaxial layer; second grooves are formed in the two sides of the source electrode; a NiO layer and an insulated gate dielectric layer are arranged on the second groove from bottom to top; a gate electrode with a non-planar gate structure is arranged on the insulated gate dielectric layer; and a gap part around the second groove and the gate electrode is filled with a first oxide isolation layer. Through structural design and material selection, the problems of serious heat dissipation and gate electrode electric leakage of existing similar devices are solved, and the voltage withstanding performance of the device is improved.

The invention belongs to the field of microelectronics, and particularly relates to a full-transparent HfO2-based ferroelectric capacitor and a preparation method and application thereof, and the full-transparent HfO2-based ferroelectric capacitor comprises a substrate, a bottom electrode, a ferroelectric medium layer and a top electrode which are sequentially stacked from bottom to top. Insertion layers are respectively arranged between the ferroelectric medium layer and the bottom electrode and between the ferroelectric medium layer and the top electrode. And the intercalation layer is a TiOx intercalation layer. Compared with the prior art, the defects that in the prior art, the ferroelectric performance of a transparent ferroelectric device is poor, a high annealing temperature is needed, and then the thermal budget requirement of a back-end process is not met are overcome; the TiOx intercalation layers are introduced to the two sides of the ferroelectric dielectric layer, so that the grain orientation is improved, the annealing temperature can be reduced to 400 DEG C, and the method can be compatible with a back-end process.

The invention relates to the technical field of microelectronics, and discloses a processing method of a passive chip for magnetic field energy collection, which comprises the following steps: S1, providing a chip with a flexible substrate, and depositing a first dielectric layer on the surface of the substrate to isolate the substrate from a coil; s2, forming a three-dimensional spiral coil structure on the dielectric layer by adopting a three-dimensional micro-nano processing technology, wherein the coils are stacked layer by layer in an asymmetric spiral form along a direction perpendicular to the substrate; and S3, in the forming process of the coil, a multi-wire-harness cross arrangement design is used, so that the inductance increment of a unit area is maximized. Through the design of the three-dimensional spiral coils and the asymmetric coils, the limitation of a traditional planar coil structure on magnetic field coupling and induction efficiency is broken through, the three-dimensional spiral coils are arranged in a multi-layer mode in the vertical direction, magnetic flux coupling between the coils is tighter, and the inductance value and the induced electromotive force are remarkably improved.

The invention belongs to the field of microelectronics, and particularly relates to a preparation method and application of a ferroelectric diode based on a scandium-doped aluminum nitride thin film, and the ferroelectric diode is prepared through the following steps: S1, growing an adhesion layer on a substrate through magnetron sputtering; s2, growing a bottom electrode on the adhesion layer through magnetron sputtering; s3, growing a ferroelectric film on the bottom electrode through magnetron co-sputtering at room temperature; s4, coating photoresist on the ferroelectric film, and exposing and developing; s5, growing a top electrode on the exposed and developed ferroelectric film through magnetron sputtering; and S6, stripping to obtain the ferroelectric diode. Compared with the prior art, the method has the advantages that the problems of high preparation temperature of the Al1-xScxN layer and large thickness of the Al1-xScxN layer in the prior art are solved, the ferroelectric diode memory of the scandium-doped aluminum nitride film is prepared at room temperature for the first time, and compatibility with a CMOS (complementary metal oxide semiconductor) process is better realized.

The invention provides a multilayer substrate via hole electrothermal coupling model construction method considering temperature change parameter change, and relates to the technical field of microelectronics. Comprising the following steps: constructing a # imgabs0 # lumped parameter equivalent circuit model corresponding to a multi-layer substrate via hole structure according to a size parameter, a material parameter and a multi-layer equivalent circuit network cascade mode of the multi-layer substrate via hole structure; constructing an equivalent thermal circuit model corresponding to the multi-layer substrate via hole structure according to the size parameters, the material parameters and the temperature nodes between the adjacent layers of the multi-layer substrate via hole structure; and connecting the # imgabs1 # lumped parameter equivalent circuit model with the equivalent thermal circuit model by utilizing a hardware description language, and establishing a multilayer substrate via hole electrothermal coupling model, so as to obtain the steady-state temperature of the substrate via hole by utilizing the multilayer substrate via hole electrothermal coupling model. Therefore, the temperature change of the via hole can be accurately obtained, the occupied computing resource + is less, and the computing time is shorter.

The invention discloses a Ga2O3 heterojunction beta irradiation battery with a multi-groove radioactive source, relates to the technical field of microelectronics, and solves the problems of low energy utilization rate and low energy conversion efficiency of a Ga2O3 nuclear battery radioactive source in the prior art. The battery comprises a filling type multi-groove radioactive source; the Ga2O3 heterojunction diode unit sequentially comprises a P-type ohmic contact electrode, a P-type NiO ion implantation region, an N-type Ga2O3 low-doped epitaxial layer, an N-type Ga2O3 high-doped substrate and an N-type ohmic contact electrode from top to bottom; a multi-T-type radioactive isotope source layer in the filling type multi-groove radioactive source is arranged above the P-type NiO ion implantation region and forms radiation energy coupling with the Ga2O3 heterojunction diode unit; the groove type structure is filled with the radioactive source, the energy deposition of the radioactive source entering the semiconductor conversion device is greatly increased, and the energy conversion efficiency of the Ga2O3 beta irradiation battery is improved.

The invention provides a preparation method of a ferroelectric film. The preparation method comprises the following steps: providing a first stress layer; depositing a hafnium elementary substance and a zirconium elementary substance on the first stress layer through a magnetron sputtering process to form a ferroelectric alloy layer; the ferroelectric alloy layer is oxidized, crystal defects and crystal phase transformation stress are generated in the ferroelectric alloy layer through heat released in the oxidation process, and a ferroelectric oxidation layer is formed; performing graphical processing on the ferroelectric oxide layer, and depositing a stress material in a graphical processing area of the ferroelectric oxide layer to form a second stress layer; and carrying out rapid thermal annealing treatment on a composite layer formed by the first stress layer, the ferroelectric alloy layer and the second stress layer to promote the crystalline phase of the ferroelectric alloy layer to be converted into a ferroelectric orthogonal phase so as to obtain the ferroelectric film. The invention also provides an application of the preparation method in a microelectronic device.

The invention relates to the technical field of microelectronics, and discloses a small and special electric machine armature defect detection method based on improved YOLOv11n, which comprises the following steps: S1, acquiring small and special electric machine armature defect image data; s2, constructing an armature defect network model, wherein an original YOLOv11n model structure is improved by constructing a C3K2-MA module; a lightweight feature extraction module is used to replace a convolution module in a trunk feature extraction and down-sampling process, and a down-sampling module is improved; the CIoU of the original YOLOv11n model is improved by using DIOU, so that the model precision is improved, and a loss function is improved; s3, using the training set and the test set obtained in the step S1 to train through the armature defect network model constructed in the step S2; and S4, using the trained armature defect network model to carry out field detection on the armature defects of the small and special electric machine. According to the invention, a partial multi-scale feature aggregation module C3K2-MA is provided, the detection capability of different scale targets is significantly improved, and the detection precision is improved.

The invention relates to the technical field of microelectronics, semiconductors and communication, and discloses a radio frequency switch chip, and the circuit structure of the radio frequency switch chip comprises a transformer type differential inductor T-L1, a transformer type differential inductor T-L2, a capacitor C1, an NMOS transistor M1, an NMOS transistor M2, a gate resistor RG1, and a gate resistor RG2. The radio frequency switch chip provided by the invention adopts a differential structure, so that the parasitic inductance effect of a grounding key and a wire during packaging and testing can be eliminated, and the insertion loss and the isolation performance are improved; compared with a single-end port, the lower impedance of the differential port is more beneficial to improving the power capacity of the switch; the differential structure allows the transformer type differential inductor to use differential signal characteristics, the equivalent quality factor of the inductor is improved, and the circuit performance is improved; the differential structure can improve the linearity of the circuit, especially the second-order intermodulation effect; the differential structure can be compatible with a modern silicon-based CMOS radio frequency system, and an additional balun is not needed for signal conversion.

The invention discloses a K-band amplitude-limiting low-noise amplifier, and belongs to the technical field of radio frequency microelectronics. The circuit comprises an input matching module, a diode amplitude limiting module, an inter-stage matching module, a low-noise amplification module and an output matching module which are cascaded in sequence, the input matching module is used for realizing impedance matching between a radio frequency signal input end and the diode amplitude limiting module and transmitting a radio frequency signal; the diode amplitude limiting module is used for limiting the amplitude of the radio frequency signal and transmitting the radio frequency signal; the inter-stage matching module is used for realizing impedance matching between the diode amplitude limiting module and the low-noise amplification module; the low-noise amplification module is used for carrying out amplification processing on the radio frequency signal after amplitude limiting and transmitting the radio frequency signal; and the output matching module is used for realizing impedance matching between the low-noise amplification module and the radio frequency signal output end and outputting the amplified radio frequency signal. According to the invention, the amplitude of the input signal can be limited, so that the amplitude is kept in a bearable range of the low-noise amplification circuit, and the stability and reliability of the whole system are ensured.

The invention discloses a low-voltage domain and over-voltage domain compatible BGR circuit, and belongs to the technical field of microelectronics. The circuit comprises divider resistors R1, R2 and R3 and voltage stabilizing capacitors C1-C4, the divider resistors R1, R2 and R3 are used for providing bias voltage for N1, N5, N6, P5, P6, P7 and P11, the N1, N5 and N6 are deep N-well MOS tubes, and P1, N1, N2, N3, N4 and R4 form a starting circuit; when the power supply voltage is 2.3 V-5. 5V, the 3.3 V device is used for realizing the design of the low-power-consumption BGR, and the functions that the low-voltage device is not punctured and the service life of the low-voltage device is not attenuated when the low-voltage device is applied to an over-voltage working condition, and the performance of the device is not reduced in a low-voltage environment are realized.

The invention provides a preparation method of a conductive toughened self-lubricating polyimide composite material, and relates to the field of hybrid multi-scale nano composite materials. The material is prepared from the following raw materials: polyimide, a surfactant, a lubricant, a conductive agent and a dispersing agent. The preparation method of the material comprises the following steps: stably dispersing graphite and carbon nanotubes in a liquid medium by utilizing the amphipathy of graphene oxide, uniformly mixing the graphite and the carbon nanotubes with polyimide slurry, freezing, soaking, self-assembling to form a three-dimensional continuous carbon nano network, and finally carrying out compression molding on a hot press. The conductive toughened polyimide composite material is prepared by the method which is simple, convenient, efficient, wide in applicability and convenient for industrial production, the impact resistance and the high-temperature self-lubricating performance of the conductive toughened polyimide composite material can be remarkably improved while static electricity is dissipated, and the application range of the polyimide composite material in the fields of aerospace, new energy automobiles, electronics, microelectronics and the like is widened.

A nanowire bonding interconnect for fine-pitch microelectronics is provided. Vertical nanowires created on conductive pads provide a debris-tolerant bonding layer for making direct metal bonds between opposing pads or vias. Nanowires may be grown from a nanoporous medium with a height between 200-1000 nanometers and a height-to-diameter aspect ratio that enables the nanowires to partially collapse against the opposing conductive pads, creating contact pressure for nanowires to direct-bond to opposing pads. Nanowires may have diameters less than 200 nanometers and spacing less than 1 μm from each other to enable contact or direct-bonding between pads and vias with diameters under 5 μm at very fine pitch. The nanowire bonding interconnects may be used with or without tinning, solders, or adhesives. A nanowire forming technique creates a nanoporous layer on conductive pads, creates nanowires within pores of the nanoporous layer, and removes at least part of the nanoporous layer to reveal a layer of nanowires less than 1 μm in height for direct bonding.

The invention discloses a pulse modulation plasma jet generation method and application thereof, and particularly relates to the field of microelectronics, and the method comprises the following steps: I, constructing a multidisciplinary association database, modulating a high-voltage pulse power supply, and optimizing pulse waveform parameters at the same time; iI, pulse voltage is applied through a high-voltage electrode to generate plasma jet, a coupling simulation model is established, and the evolution process of the plasma jet is simulated; according to the method, the requirement of manual operation can be reduced, subjective deviation and information loss are avoided, the robustness of resisting environmental interference is improved, and the method can adapt to the high-speed and high-precision process requirement; the testing of invalid parameter combinations can be avoided, the searching capability is improved, the experiment or simulation frequency is reduced, the anti-interference capability of the jet system on working condition fluctuation is improved, and the maintenance frequency is reduced.

The invention discloses a broadband power amplifier with an output reconfigurable network, and relates to the technical field of microelectronics, the broadband power amplifier with the output reconfigurable network adopts a three-stage amplification circuit with a gate width ratio of 1: 2: 8, and signal pre-amplification and gain improvement are realized through the first two stages of amplifiers; the last-stage eight-tracheid parallel structure outputs saturated power under high-voltage power supply and realizes power additional efficiency; the output reconfigurable network is controlled by a first switch and a second switch, the first switch is turned off and the second switch is turned on in a high-power mode, so that a compensation microstrip line is grounded to form a fundamental wave matching branch knot, the loss of a harmonic suppression network is avoided, and high-efficiency output is guaranteed; in a low-power mode, the first switch is switched on, the second switch is switched off, the first LC resonance unit and the second LC resonance unit jointly form a band-stop filtering network, secondary and third harmonic impedance is adjusted to be in a near-short-circuit state, so that generation of higher harmonics is restrained, phase distortion is offset through the compensation microstrip line, and the integrity of fundamental wave signals is maintained.

The invention relates to the technical field of microelectronics, in particular to a unimolecular memristor based on a viologen derivative and a preparation method of the unimolecular memristor. The unimolecular memristor based on the viologen derivative comprises an electrode pair and an organic functional molecule, and the organic functional molecule is selected from the viologen derivative and assembled between the electrode pair through an amide condensation reaction. According to the organic functional molecule provided by the invention, functional modification is performed on the basis of a viologen molecular structure, so that an energy barrier of reversible oxidation-reduction reaction of a viologen unit is effectively reduced, and the performance of the single-molecule memristor is remarkably improved; meanwhile, the on-off ratio of the device is also improved by one order of magnitude. According to the preparation method provided by the invention, the stability and repeatability of a monomolecular device can be ensured, and the conductive stability and durability of the molecular junction of the organic functional molecule are effectively improved. The method is simple and convenient to operate, reaction conditions are easy to control, and large-scale production of molecular devices is facilitated.

A load sensing assembly for a medical implant is disclosed. The medical implant may include an upper surface, a side surface, a bottom surface, and a cavity housing various sensors and microelectronics. In other embodiments, the medical implant may include a port that is accessible through at least one of the bottom surface, side surface, and the upper surface. The port may be configured to receive an electronics assembly, package, or hermetically sealed enclosure. The electronics package may have a size and shape generally corresponding to the port. In various embodiments, electronic components and sensors may be powered by a local power source. In various embodiments, sensors may be chosen from: accelerometers, gyroscope, strain gauge, pressure sensor, pH sensor, impedance sensor, optical sensor, and / or a temperature sensor. In various embodiments, the medical implant may be chosen from: an interbody spinal implant, a pedicle screw, a connector, and / or a cross-link.

Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects are provided. An example optical interconnect joins first and second optical conduits. A first direct oxide bond at room temperature joins outer claddings of the two optical conduits and a second direct bond joins the inner light-transmitting cores of the two conduits at an annealing temperature. The two low-temperature bonds allow photonics to coexist in an integrated circuit or microelectronics package without conventional high-temperatures detrimental to microelectronics. Direct-bonded square, rectangular, polygonal, and noncircular optical interfaces provide better matching with rectangular waveguides and better performance. Direct oxide-bonding processes can be applied to create running waveguides, photonic wires, and optical routing in an integrated circuit package or in chip-to-chip optical communications without need for conventional optical couplers. An example wafer-level process fabricates running waveguides, optical routing, and direct-bonded optical interconnects for silicon photonics and optoelectronics packages when two wafers are joined.

The invention relates to a printed circuit board welding spot temperature cycle acceleration test profile design method, which takes welding spots on an aging test board carrying a test device as research objects, and utilizes simulation software to carry out finite element simulation on a target circuit board under multiple groups of temperature cycle stress conditions. A plurality of groups of fatigue life are calculated through an Engelmaier fatigue life model in combination with a simulation result, the fatigue life obtained through calculation is substituted into a Coffin-Manson acceleration model for fitting calculation of an acceleration factor calculation formula, finally, the acceleration factor calculation formula is utilized, required acceleration time is substituted into the formula for calculation to obtain actual condition design acceleration test section parameters, and the acceleration test section parameters are calculated according to the actual condition design acceleration test section parameters. The obtained acceleration test profile can complete the temperature cycle acceleration test of the printed circuit board within a given time, and the process of the method is as shown in Figure 8. The method belongs to the technical field of reliability evaluation of microelectronics and components.

The invention belongs to the field of microelectronics, and particularly relates to a ferroelectric capacitor, a preparation method thereof and a three-dimensional ferroelectric memory array, and the ferroelectric capacitor comprises a substrate, a bottom electrode, a ferroelectric dielectric layer, a deoxidizing layer and a top electrode which are sequentially arranged from bottom to top; the ferroelectric medium layer is an Hf < 1-x > Zr < x > O < 2 > layer, 0 lt; xlt; the Hf-rich composition is realized by controlling the Hf: Zr super-cycle ratio of atomic layer deposition; the thickness of the ferroelectric medium layer is 1-6 nm, and the thickness of the bottom electrode is 0.1-5 nm. Compared with the prior art, the problems of polarization characteristic degradation caused by thinning of the ferroelectric layer in the hafnium-based ferroelectric capacitor and crosstalk in the FeRAM in the prior art are solved. According to the scheme, the oxygen vacancy concentration is accurately adjusted to inhibit the formation of a non-ferroelectric phase, so that the ultra-thin ferroelectric film can still maintain relatively high remanent polarization while the size is reduced, a storage window is effectively improved, and the wake-up requirement is reduced.

The invention provides an ultraviolet light synaptic device based on gallium nitride-gallium oxide heterojunction and a preparation method thereof, and relates to the technical field of microelectronics, the ultraviolet light synaptic device based on gallium nitride-gallium oxide heterojunction is extremely sensitive to ultraviolet light, has successfully simulated various characteristics of biological synapses, and can be applied to the field of biological synapses. Wherein the characteristics comprise persistent photoconductive effect (PPC), double-pulse facilitation (PPF) and plasticity of transition from short-term memory (STM) to long-term memory (LTM); moreover, the gallium nitride-gallium oxide heterojunction structure can prolong the optical sensing mechanism, reduce the energy consumption of a synaptic event and increase the synaptic plasticity. In addition, the ultraviolet synaptic device has the advantages of simple preparation, high sensitivity, good stability and the like, and is very suitable for industrial production.

The invention relates to a method for pyrolyzing graphene by etching a SiC surface through metal Ag nanoparticles and application, and belongs to the technical field of two-dimensional material patterning. According to the method, SiC pyrolytic graphene with a metal nano Ag film growing on the surface is placed in a closed confined container, vacuum high-temperature annealing is carried out, and metal Ag nano particles can etch a graphene layer in the volatilization process. The confinement type annealing etching technology is simple and effective, has no requirement on the surface polarity of the SiC substrate, is expected to promote large-scale uniform patterning preparation of SiC pyrolytic graphene, and provides guidance and reference values for practical application of a two-dimensional material in the field of microelectronics.

A method produces a microelectronics device by hybrid bonding of individual chips onto a handle wafer, of the Die-to-Wafer type, includes a flow protocol for thinning the rear substrate of the chips. The flow protocol includes a pre-thinning grinding of the rear substrate of the individual chips once they have been attached to the wafer. This grinding is preceded by the formation of a protective layer protecting the trenches formed by the spaces between the attached individual chips. Next, a rectification etching rectifies the height of the rear substrate of each of the attached individual chips, via chemical wet etching, to eliminate the Total Thickness Variation. This etching is selective with respect to an etch-stop element contained in the respective substrates of the attached chips and which is used to stop the etching at a level that is substantially uniform for each of the chips.