1248 results about "Copper metal" patented technology

Metal films are deposited with uniform thickness and excellent step coverage. Copper metal films were deposited on heated substrates by the reaction of alternating doses of copper(I) NN′-diisopropylacetamidinate vapor and hydrogen gas. Cobalt metal films were deposited on heated substrates by the reaction of alternating doses of cobalt(II) bis(N,N′-diisopropylacetamidinate) vapor and hydrogen gas. Nitrides and oxides of these metals can be formed by replacing the hydrogen with ammonia or water vapor, respectively. The films have very uniform thickness and excellent step coverage in narrow holes. Suitable applications include electrical interconnects in microelectronics and magnetoresistant layers in magnetic information storage devices.

A method for processing substrate to form a semiconductor device is disclosed. The substrate includes an etch stop layer disposed above a metal layer. The method includes etching through the etch stop layer down to the copper metal layer, using a plasma etch process that utilizes a chlorine-containing etchant source gas, thereby forming etch stop layer openings in the etch stop layer. The etch stop layer includes at least one of a SiN and SiC material. Thereafter, the method includes performing a wet treatment on the substrate using a solution that contains acetic acid (CH3COOH) or acetic acid / ammonium hydroxide (NH4OH) to remove at least some of the copper oxides. Alternatively, the copper oxides may be removed using a H2 plasma. BTA passivation may be optionally performed on the substrate.

A method for forming a copper bump for flip chip bonding having improved oxidation resistance and thermal stability including providing a copper column having a thickness of at least about 40 microns overlying a metallurgy including an uppermost copper metal layer and a lowermost titanium layer the lowermost titanium layer in contact with an exposed copper bonding pad portion surrounded by a passivation layer; and, selectively depositing at least one protective metal layer over the copper column according to an electrolytic deposition process.

A catalyst for hydrogenated synthesis of glycol with oxalate and a preparation method for the catalyst belong to the glycol preparation technical field. The catalyst of the present invention uses the copper metal as the main active component, and zinc as the promoter, and is manufactured with the method of deposition. A carrier of the catalyst is the modified silica sol. The select content of the copper metal is 5 to 45 percent of the carrier weight, and the optimal content of the copper metal is 10 to 40 percent. The content of zinc metal is 0.1 to 15 percent of the carrier weight, and the optimal content of zinc metal is 1 to 8.0 percent. The select specific surface area of the carrier is 90-350m2 / g, and the optimal is 150-300m2 / g. Proven by experiments, the catalyst is provided with the very high reaction activity and glycollate selectivity in the reaction to synthesize glycollate with oxalate and hydrogen Moreover, the catalyst is provided with the long usable life and the stable reaction performance, and can be easily controlled.

Disclosed is a semiconductor device comprising a thin film transistor and wirings connected to the thin film transistor, in which the thin film transistor has a channel formation region in an oxide semiconductor layer, and a copper metal is used for at least one of a gate electrode, a source electrode, a drain electrode, a gate wiring, a source wiring, and a drain wiring. The extremely low off current of the transistor with the oxide semiconductor layer contributes to reduction in power consumption of the semiconductor device. Additionally, the use of the copper metal allows the combination of the semiconductor device with a display element to provide a display device with high display quality and negligible defects, which results from the low electrical resistance of the wirings and electrodes formed with the copper metal.

A metal oxide is deposited on a substrate in a semiconductor fabrication metallization process is patterned and subsequently reduced to a more conductive form, such as elemental metal. The metal oxide is reduced by exposure to at least one reducing agent or current that is capable of removing oxygen from the metal oxide. Copper oxide, for example, can be dry etched for patterning prior to reduction to copper metal, and the patterned copper used as an ECD seed layer.

Compositions useful in microelectronic device manufacturing for surface preparation and / or cleaning of wafer substrates such as microelectronic device precursor structures. The compositions can be employed for processing of wafers that have, or are intended to be further processed to include, copper metallization, e.g., in operations such as surface preparation, pre-plating cleaning, post-etching cleaning, and post-chemical mechanical polishing cleaning of microelectronic device wafers. The compositions contain (i) alkanolamine, (ii) quaternary ammonium hydroxide and (iii) a complexing agent, and are storage-stable, as well as non-darkening and degradation-resistant in exposure to oxygen.

Disclosed is a semiconductor device comprising a thin film transistor and wirings connected to the thin film transistor, in which the thin film transistor has a channel formation region in an oxide semiconductor layer, and a copper metal is used for at least one of a gate electrode, a source electrode, a drain electrode, a gate wiring, a source wiring, and a drain wiring. The extremely low off current of the transistor with the oxide semiconductor layer contributes to reduction in power consumption of the semiconductor device. Additionally, the use of the copper metal allows the combination of the semiconductor device with a display element to provide a display device with high display quality and negligible defects, which results from the low electrical resistance of the wirings and electrodes formed with the copper metal.

A catalyst for hydrogenated synthesis of glycollate with oxalate and a preparation method for the catalyst belong to the glycollate preparation technical field. The catalyst of the present invention uses the copper metal as the main active component, and silver as the promoter, and is manufactured with the method of immersion. A carrier of the catalyst is the modified silica sol. The select content of the copper metal is 5 to 45 percent of the carrier weight, and the optimal content of the copper metal is 10 to 40 percent. The content of silver metal is 0.1 to 15 percent of the carrier weight, and the optimal content of silver metal is 1 to 8.0 percent. The select carrier is the silica sol with a double peak pore distribution structure and the specific surface area of the carrier is 100-300m2 / g; and the optimal specific surface area of the carrier is 120-240m2 / g. The present invention settles the problem of applying a Cr / Cu catalyst in the oxalate gas-phase catalytic hydrogenation. Proven by experiments, the catalyst is provided with the very high reaction activity and glycollate selectivity in the reaction to synthesize glycollate with oxalate and hydrogen Moreover, the catalyst is provided with the long usable life and the stable reaction performance, and can be easily controlled.

A precursor composition for the deposition and formation of an electrical feature such as a conductive feature. The precursor composition advantageously has a low viscosity enabling deposition using direct-write tools. The precursor composition also has a low conversion temperature, enabling the deposition and conversion to an electrical feature on low temperature substrates. A particularly preferred precursor composition includes copper metal for the formation of highly conductive copper features.

A method comprises forming a barrier layer for copper metallization, selectively forming a silicon film on a surface of copper wiring formed on the main surface of a semiconductor substrate, and reacting the silicon film with a non-copper metal and / or nitrogen to form a barrier layer in a self-aligned manner relative to the copper wiring. In the method, the capacitance increase in the copper wirings formed is prevented, and the barrier layer formed has a satisfactory barrier property of protecting the copper wirings.

A precursor composition for the deposition and formation of an electrical feature such as a conductive feature. The precursor composition advantageously has a viscosity of at least about 1000 centipoise and can be deposited by screen printing. The precursor composition also has a low conversion temperature, enabling the deposition and conversion to an electrical feature on low temperature substrates. A particularly preferred precursor composition includes silver and / or copper metal for the formation of highly conductive features.

A process of electrodepositing high purity copper in a via in a silicon substrate to form a through-silicon-via (TSV), including immersing the silicon substrate into an electrolytic bath in an electrolytic copper plating system in which the electrolytic bath includes an acid, a source of copper ions, a source of ferrous and / or ferric ions, and at least one additive for controlling physical-mechanical properties of deposited copper; and applying an electrical voltage for a time sufficient to electrodeposit high purity copper to form a TSV, in which a Fe+2 / Fe+3 redox system is established in the bath to provide additional copper ions to be electrodeposited by dissolving copper ions from a source of copper metal.

Process for producing a copper-containing aqueous solution, in which a copper mass is dissolved in the presence of air in an aqueous leach liquor containing monoethanolamine and an acid, wherein the amount of acid equivalents is between 0.05 and about 0.7 times the equivalents of monoethanolamine, and wherein the rate of copper dissolution into the aqueous leach liquor is greater than about 4.3 grams of copper per liter of leach liquor per hour until a product having at least about 80 grams per liter is obtained.

A method for metallizing a via feature in a semiconductor integrated circuit device substrate, wherein the semiconductor integrated circuit device substrate comprises a front surface, a back surface, and the via feature and wherein the via feature comprises an opening in the front surface of the substrate, a sidewall extending from the front surface of the substrate inward, and a bottom. The method comprises contacting the semiconductor integrated circuit device substrate with an electrolytic copper deposition chemistry comprising (a) a source of copper ions and (b) a leveler compound, wherein the leveler compound is a reaction product of a dipyridyl compound and an alkylating agent; and supplying electrical current to the electrolytic deposition chemistry to deposit copper metal onto the bottom and sidewall of the via feature, thereby yielding a copper filled via feature.

The present invention provides a copper oxide-containing composition that includes copper oxide nanoparticles and one or more heteroatom donor ligands bonded to the surface of the nanoparticles, where x and y are numbers having a ratio that is equal to the ratio of the average number of M atoms to the average number of 0 atoms in the nanoparticles. The nanoparticles are stabilized by the one or more heteroatom donor ligands which act as a protective layer that cap the surface of the nanoparticles. The present invention also provides a solution of the copper oxide nanoparticles that may be applied to a substrate and then subsequently reduced to copper metal. Finally, the invention provides a method of preparing the copper oxide nanoparticles.

Novel copper alkoxide compound based ink formulations and their chemical syntheses are disclosed. The method of using the ink formulations to print conducting copper metal lines with standard ink jet printing and curing at <150° C. is also disclosed.

A process of electrodepositing high purity copper in a via in a silicon substrate to form a through-silicon-via (TSV), including immersing the silicon substrate into an electrolytic bath in an electrolytic copper plating system in which the electrolytic bath includes an acid, a source of copper ions, a source of ferrous and / or ferric ions, and at least one additive for controlling physical-mechanical properties of deposited copper; and applying an electrical voltage for a time sufficient to electrodeposit high purity copper to form a TSV, in which a Fe+2 / Fe+3 redox system is established in the bath to provide additional copper ions to be electrodeposited by dissolving copper ions from a source of copper metal.

The invention discloses a lithium battery with novel current collectors and a preparation method of the lithium battery with the novel current collectors. The lithium battery comprises a positive pole piece, a diaphragm and a negative pole piece. The positive pole piece comprises a novel positive pole current collector in a multi-layer structure, the positive pole current collector comprises a first plastic film, and each of upper and lower surfaces of the first plastic film is coated with a first adhesion reinforcement layer, an aluminum metal plating layer and a first antioxidant layer sequentially. The negative pole piece comprises a novel negative pole current collector in a multi-layer structure, the negative pole current collector comprises a second plastic film, and each of upper and lower surfaces of the second plastic film is coated with a second adhesion reinforcement layer, a copper metal plating layer and a second antioxidant layer sequentially. The preparation method includes: laminating the positive pole piece, the diaphragm and the negative pole piece, packaging through aluminum-plastic films, injecting an appropriate amount of electrolyte, and subjecting the aluminum-plastic films to hot-press packaging. The lithium battery has advantages that light weight, energy density improvement and cost reduction of the battery can be realized, and copper / aluminum plating layers are less prone to shedding and oxidization.

An on-chip decoupling capacitor (106) and method of fabrication. The decoupling capacitor (106) is integrated at the top metal interconnect level (104) and includes surface protection layer (109) for the copper metal (104b) of the top metal interconnect.

A method is disclosed for metallizing a substrate comprising an interconnect feature in the manufacture of a microelectronic device, wherein the interconnect feature comprises a bottom, a sidewall, and a top opening having a diameter, D. The method comprises the following steps: depositing a barrier layer on the bottom and the sidewall of the interconnect feature, the barrier layer comprising a metal selected from the group consisting of ruthenium, tungsten, tantalum, titanium, iridium, rhodium, and combinations thereof; contacting the substrate comprising the interconnect feature comprising the bottom and sidewall having the barrier layer thereon with an aqueous composition comprising a reducing agent and a surfactant; and depositing copper metal onto the bottom and the sidewall of the interconnect feature having the barrier layer thereon.

The invention discloses a method for preparing graphene. The method comprises the following steps of: after heating a substrate loaded with a copper metal layer to a bulk phase melting point and above the bulk phase melting point of copper in the flowing anaerobic and anhydrous atmosphere, introducing a carbon-containing compound into a system to perform chemical vapor deposition to obtain the graphene on the surface of the copper metal layer after the deposition. According to the method, the graphene with various shapes is prepared by introducing inert gases under a liquid state copper catalyst. The method is easy and convenient to operate and high in quality of products, and can be used for large-scale production. The shapes of the graphene can be regulated and controlled by regulating a concentration ratio of the inert gases to carbon-containing substances and hydrogen.

A polishing composition for chemical mechanical polishing of semiconductor wafers having a copper metal circuit includes, an aqueous composition having a pH of under 5.0, and polyacrylic acid having a number average molecular weight of about 20,000-150,000, or blends of high and low number average molecular weight polyacrylic acids.

The invention relates to a metal material surface coating process, in particular to a metal material surface copper imitation wire drawing process. The technical problem to be solved by the invention is to overcome the defects of the prior art and provide the metal material surface copper imitation wire drawing process with good copper imitation effect, strong copper metal texture, long light-keeping and color-keeping time and easy scale production. The technical proposal is as follows: the copper imitation wire drawing process comprises the following steps of: 1) carrying out conventional chemical pretreatment on the surface of a metal material and leading the metal surface to be clean, smooth and flat; 2) electrostatic spraying a transparent red outdoor powder coating or a pure transparent outdoor powder coating containing pigments; and 3) using a thermal-sensitive transfer paper with copper imitation bottom color of deep sky blue or black straight stripes for carrying out thermal transfer and obtaining the copper imitation wire drawing effect, wherein the straight-silkiness stripes with the color phase of deep sky blue or black silkiness straight textures are printed on the thermal-sensitive transfer paper with the copper imitation bottom color of deep sky blue or black straight stripes, the bottom color of the copper imitation color is light red purple or red purple or light yellow. In addition to the advantages, the copper imitation wire drawing process is more conductive to environmental protection.

The invention discloses chemical mechanical polishing liquid for polishing low-k dielectric materials, which comprises abrasive particles, corrosion inhibitor, oxidizer and water, and is characterized in comprising at least an accelerator agent. The polishing liquid of the invention has a high removing speed of low k dielectric material under lower pressure, and also has the a high removing speed of the other materials such as copper metal (Cu), silicon oxide (Teos), Tantalum metal (Ta) / Tantalum nitride (TaN) blocking layers, etc.

The invention discloses an electronic packaging material. The electronic packaging material is characterized by comprising a matrix and a reinforcement, wherein the matrix is made of aluminum, copper, aluminum alloy or copper alloy, the reinforcement is of graphene accounting for 0.5-30% of total mass percentage, and the graphene has 1-20 layers of tiny plates the area of each which is 1-5000 mu m<2> or plates the area of each which is more than 1mm<2>; and the aluminum or copper metal comprises Cr, Fe, Ti, W, B or Mo element, the content of the Cr, Fe, Ti, W, B or Mo element is 0.05-1%. The electronic packaging material has the advantages of being high-heat conductivity, high-strength, low-density, environment-friendly and good in machineable property; and as the electronic packaging material, the composite has excellent property and good application prospects.

A method for analyzing accelerant of electroplated copper includes placing copper electrode in electrolyte containing organic additives to let copper electrode absorb accelerant containing sulphur, using pure water to wash copper electrode absorbed with sulphur compound then placing copper electrode into deposit-electrolyte containing polyethylene glycol and chlorine ion and carrying out cathode circulation VA scan to deposit down copper metal, carrying out integration on obtained polarization curve to prepare out detection line. The deposit-electrolyte used in said method is also disclosed.

A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, the cap layer may be formed by an in-situ deposition process in which a process gas comprising germanium, arsenic, tungsten, or gallium is introduced, thereby forming a copper-metal cap layer. In another embodiment, a copper-metal silicide cap is provided. In this embodiment, silane is introduced before, during, or after a process gas is introduced, the process gas comprising germanium, arsenic, tungsten, or gallium. Thereafter, an optional etch stop layer may be formed, and a second dielectric layer may be formed over the etch stop layer or the first dielectric layer.