986 results about "Power semiconductor device" patented technology

The invention relates to the technical field of sintering evaluation, in particular to a power semiconductor device packaging sintering evaluation method and device based on image analysis. The method comprises the following steps: obtaining a multi-source heterogeneous monitoring image set of a semiconductor device, carrying out multi-modal space corresponding relation identification, carrying out global registration precision compensation, and constructing a multi-modal space registration image matrix; carrying out multi-level voxelization analysis reconstruction based on the multi-modal space registration image matrix, carrying out structure deviation mapping modeling, and constructing a sintering three-dimensional structure deviation distribution map; and performing multi-directional defect detection according to the multi-modal space registration image matrix, performing defect cascade failure modeling, and constructing a multi-defect structure integrity association network. According to the method, accurate three-dimensional sintering structure defect analysis is realized, the quality of the sintering structure is quantified in all directions, and intelligent optimization and rapid iteration of a sintering process are promoted.

A heterojunction device having at least three terminals, the at least three terminals comprising a high voltage terminal, a low voltage terminal and a control terminal. The heterojunction device further comprises at least one main power heterojunction transistor, an auxiliary gate circuit comprising at least one first low-voltage heterojunction transistor, a pull-down circuit comprising a capacitor and a charging path for the capacitor. The heterojunction device further comprises at least one monolithically integrated component, wherein the capacitor is configured to provide an internal rail voltage for the at least one monolithically integrated component.

The invention relates to the technical field of semiconductor packaging, in particular to a batch dust-free packaging device for power semiconductor devices and a using method of the batch dust-free packaging device for the power semiconductor devices, and the batch dust-free packaging device comprises a plastic packaging machine main body, a plastic packaging mold and a side frame, an upper plastic packaging mold and a lower plastic packaging mold are installed at the upper end and the lower end of the plastic packaging machine body respectively, a side frame is fixedly connected to one side of the plastic packaging machine body, a cleaning roller storage box is installed on one side of the side frame, and an electric push rod and an air supply and negative pressure unit are arranged in the cleaning roller storage box. Three-step dust-free cleaning of blowing, sucking and shaking is automatically carried out on a mold cavity after each time of plastic packaging; during air blowing, air is expanded and cooled twice through a conical barrel, the mold is synchronously cooled, and stubborn particles are stripped; negative pressure is formed on the surface of the cotton layer during air suction, and all residual scraps are sucked away; after cleaning is finished, the roller body returns to the storage box, the blocking block collides with the toothed plate to enable the roller body to jolt at high frequency, and attachments are shaken off into the box and are sealed and collected.

The invention discloses a double-sided heat dissipation common drain module packaging structure, and belongs to the technical field of power semiconductor device packaging. The module comprises a common drain electrode upper copper layer, two drain electrode copper terminals, two power chips, two source electrode copper blocks, two L-shaped source electrode lower copper layers, two driving grid electrode copper terminals, two driving source electrode copper terminals and a bonding wire. Drain electrodes of the two power chips are welded on the common drain electrode upper copper layer, and source electrodes of the two power chips are respectively welded with the L-shaped source electrode lower copper layer through source electrode copper blocks. And the bonding wire is connected with the grid electrode and the source electrode of the chip and the driving copper terminal to realize Kelvin connection. Thermal resistance is reduced through a double-sided heat dissipation structure, parasitic inductance is reduced through a three-dimensional commutation loop, power density and reliability are improved, and the common drain geminate transistor is suitable for common drain geminate transistor application in a battery management system.

The invention provides an IGBT (Insulated Gate Bipolar Translator) turn-off time measuring method, system, equipment and medium, and belongs to the field of power semiconductor device testing technology and state monitoring, and the method comprises the following steps: firstly, selecting 20% Vdc and 80% Vdc as turn-off initial measuring points, secondly, carrying out first error correction by adopting a linear estimation method, and finally, carrying out second error correction by adopting a linear estimation method; performing linear fitting on the voltage difference Vce data through a least square method to obtain initial turn-off time; and finally, aiming at systematic deviation caused by inherent concavity and convexity characteristics of the voltage curve, performing secondary error correction by adopting a convex hull algorithm, acquiring a lower envelope line of the ic-tOFF relation curve through an Andriw algorithm, and identifying and eliminating the problem of Overestimation of the turn-off time based on a convex hull accurate point set. According to the invention, accurate measurement of the turn-off time of the IGBT under the condition of low sampling rate is realized, the hardware cost is significantly reduced, and a reliable technical basis is provided for IGBT state monitoring and life prediction.

The embodiment of the invention discloses a semiconductor device service life evaluation method based on a power cycle test and related equipment, and the method comprises the steps: dividing semiconductor devices produced by the same factory in the same batch into two parts, and executing a second-level power cycle test on one part, a millisecond-level power cycle test is firstly executed on the other part, and then a second-level power cycle test is executed on the other part; establishing a first life model according to one test result, and establishing a second life model according to the other test result; and calculating a third life model corresponding to the millisecond power cycle test according to the first life model and the second life model, and performing life evaluation on the semiconductor device according to the third life model. By adopting the embodiment of the invention, the reliability assessment requirement of the power semiconductor device in the future can be met, and the aims of accelerating aging and meeting the actual working condition can be fulfilled, so that an important reference significance is provided for the research of the reliability test of the device and the assessment of the actual life.

The invention discloses a gallium nitride power device and a preparation method thereof, and relates to a power semiconductor device, in order to simplify a forming process of a multilayer field plate, the invention provides the gallium nitride power device which is provided with a plurality of dielectric layers rising in a step shape, and a step-shaped side edge is formed on the side surface of each dielectric layer; according to the method provided by the invention, no matter how many layers of the field plates are, field plate deposition only needs to be carried out once, etching can be carried out twice and two layers of field plates can be formed during photoetching each time, the number of layers of the field plates can be increased without increasing the complexity and cost of the process, and the manufacturing cost of the field plates can be reduced. The electric field distribution between the gate metal and the drain metal of the device is more uniform, and the breakdown voltage and the reliability of the device are improved.

The invention relates to power semiconductor device on-line monitoring and power electronic system control, in particular to a SiC MOSFET conduction current extraction circuit and method, high-frequency oscillation interference is effectively suppressed through a second-order passive RC filter circuit, a measurement error less than or equal to 1.5% is realized within a current range of 50A-300A in combination with an accurate mathematical model established by a depth symbol optimization algorithm, and the measurement accuracy is improved. The requirement of the intelligent gate driver on high-precision current feedback is met, and the measurement precision is remarkably improved; the pulse width direct analysis technology is adopted, a traditional active integrator and a digital decoding link are omitted, the system response delay is smaller than or equal to 500 ns, microsecond-level over-current protection can be supported, the response speed and the real-time performance are optimized, and the system safety in a high-frequency application scene is remarkably improved.

The utility model provides a power semiconductor device, comprising a substrate which comprises a body region and a drift region which are arranged at an interval; the first well region is formed in the body region; the substrate leading-out region is formed in the body region, the first well region and the substrate leading-out region are arranged at intervals, the substrate leading-out region comprises a polycrystalline silicon body, the polycrystalline silicon body extends into the body region from the surface of the body region, and the vertical size of the polycrystalline silicon body is larger than the junction depth of the first well region; the first dielectric layer is arranged on the outer side of the polycrystalline silicon body, and the first well region and the polycrystalline silicon body are separated by the first dielectric layer; the second well region is formed in the drift region; the gate dielectric layer is arranged on the surface of the drift region, the gate dielectric layer is located between the body region and the second well region, and the gate dielectric layer is separated from the second well region; and the polysilicon gate layer is arranged on the surfaces of the gate dielectric layer, the drift region, the substrate and the body region. Without increasing the lateral dimension of the semiconductor device, the withstand voltage between the source electrode and the substrate can be improved.

An inverter includes a housing and a heat dissipation apparatus. The housing may include a first cavity and a second cavity, and a power semiconductor device is disposed in the first cavity. The second cavity has a first air inlet and a first air outlet, and a magnetic component is disposed in the second cavity. The heat dissipation apparatus includes a radiator and a first fan. The radiator includes an evaporator and a condenser that are connected to each other. The evaporator is disposed in the second cavity. The power semiconductor device is in thermally conductive contact with the evaporator, to dissipate heat for the power semiconductor device. The first fan is disposed in the second cavity, an air inlet side of the first fan faces the first air inlet, and an air outlet side of the first fan faces the first air outlet.

Power semiconductor devices and power semiconductor device packages are provided. In one example, a power semiconductor device package includes a submount and a semiconductor die on the submount. In some examples, the semiconductor die includes a metallization structure, a first passivation layer on the metallization structure, a buffer layer on the first passivation layer, a second passivation layer on the buffer layer, and a polyimide layer directly on the second passivation layer. In some examples, the second passivation layer includes the same material as the first passivation layer.

A bidirectional crosstalk suppression driving circuit suitable for a wide bandgap power semiconductor device comprises a push-pull circuit and a crosstalk suppression auxiliary circuit, the push-pull circuit is connected with the crosstalk suppression auxiliary circuit, and the crosstalk suppression auxiliary circuit is connected with a grid electrode and a source electrode of the power semiconductor device. The push-pull circuit is used for generating a driving voltage signal to drive a power semiconductor device. When the power semiconductor device is subjected to positive crosstalk, positive voltage is generated through a negative voltage capacitor in the crosstalk suppression auxiliary circuit, and the influence of negative overvoltage generated on a driving resistor when the positive crosstalk occurs is reduced; when the power semiconductor device is subjected to negative crosstalk, gate equivalent driving impedance is reduced through an RD auxiliary branch in the crosstalk suppression auxiliary circuit, and reverse overvoltage caused by negative crosstalk is reduced. The circuit has compatibility and economical efficiency, and is simple in structure and easy to operate. The method is of great significance in improving the turn-on and turn-off reliability of a power semiconductor device and guaranteeing stable operation of a system.

The invention belongs to but not limited to the technical field of power semiconductor packaging, and discloses a packaging structure of a power semiconductor device. The power module comprises a lead frame, a plastic package body, a base island, a bonding wire and a semiconductor chip assembly, a first power unit and a second power unit are integrated, the first unit comprises two driving ICs, six IGBTs and six FRD chips, the second unit comprises two driving ICs and six MOS chips, 46 pins are provided, and functions are clearly divided. All the IC chips and the FRD chips are arranged on the same base island, the back faces of the chips are welded to the base island, and the front faces of the chips are connected with pins in a standard mode through bonding wires. The structure solves the problems of complex packaging layout, disordered connection and the like in the prior art, can drive the compressor and the fan respectively, realizes high integration level and compact layout, shortens an electric connection path, reduces parasitic parameters, reduces the overall size and cost, and improves reliability and engineering compatibility.

The invention relates to the technical field of heat dissipation of power semiconductor devices, in particular to a ceramic heat dissipation carrier plate, a preparation method thereof and a power semiconductor device. The ceramic heat dissipation carrier plate of the present invention comprises: a ceramic substrate; the first bonding layer is arranged on one side of the ceramic substrate; the metal circuit layer is arranged on the first bonding layer; the second bonding layer is arranged on the other side of the ceramic substrate; the metal heat dissipation layer is arranged on the second bonding layer; a porous structure is arranged in the metal heat dissipation layer; the first bonding layer and the second bonding layer are formed in a magnetron sputtering mode. According to the ceramic heat dissipation carrier plate, the porous structure is arranged in the metal heat dissipation layer, the ultrathin combination layer is formed through magnetron sputtering, thermal expansion mismatch between metal and ceramic is remarkably reduced, residual stress and warping are effectively restrained, meanwhile, the heat conduction path is shortened, the cavity defect is eliminated, and the heat dissipation efficiency is improved. Therefore, collaborative improvement of high heat dissipation efficiency and long-term reliability is realized in a high-voltage, high-temperature and high-vibration environment.

The invention discloses a power semiconductor board-level test system and method, and belongs to the technical field of power semiconductor device test. According to the system, a reactive aging test and a dynamic characteristic test are creatively integrated on a single test platform, and the problems of low efficiency and high cost of a traditional substation test are solved through modular design. The system comprises a multifunctional test head arranged at a test station and capable of being connected with a power terminal and a signal terminal of a power module at the same time; the reactive load loop is formed by a three-phase adjustable reactor; the high-precision signal acquisition module comprises a flexible current probe and a differential voltage probe; the oscilloscope realizes multi-channel synchronous acquisition; and accurate control is realized based on the main control board card of the FPGA. According to the testing method, Vge, Vce, Ic and other parameters are collected in real time in the reactive aging process, online monitoring of dynamic characteristics is achieved through a current triggering mechanism, and a fault recording function is achieved.

The invention relates to the technical field of semiconductor testing, in particular to a power semiconductor device testing method, system and equipment and a storage medium, and the method comprises the steps: collecting the current temperature data of a to-be-tested device in real time, and comparing the current temperature data with a test target temperature value, so as to judge whether the target temperature is too high or too low; the real-time feedback data is compared with the target value to judge whether the heating operation or the cooling operation should be executed, so that control guidance is provided for temperature adjustment; after the heating or cooling operation is judged to be carried out, the electric heating unit and the electric cooling unit are driven to carry out dynamic adjustment, so that the temperature of the device is stabilized in a minimum fluctuation interval near the target temperature, and the stability of the test temperature is ensured; after it is confirmed that the temperature is stabilized in the target range, the test unit is triggered to apply excitation to the to-be-tested device in a specific mode, test errors generated due to temperature fluctuation or the fact that the target temperature is not reached are eliminated, and test results of different batches and different times have high comparability.

The application provides a high-voltage direct-hanging energy storage equipment energy storage submodule test system and test method, comprising: a current generator, which generates test current using a cascaded full-bridge structure and can reduce the harmonic content of the output voltage of the current generator based on carrier phase shift or carrier layering modulation; an energy storage submodule to be tested; a current controller for controlling the current generator to adjust the test current; a submodule controller for controlling the energy storage submodule to be tested to adjust the state of charge and voltage of the submodule; and an energy storage system parameter model for outputting reference signals for current control and state of charge control to the current controller and the submodule controller, respectively. The application can test the energy storage submodule in accordance with the actual system operation condition without building a complete energy storage system and effectively reduces the requirements of the test circuit for the switching frequency of the power semiconductor device, the filter and the direct current power supply.

An example power semiconductor device includes a silicon carbide semiconductor structure. The example power semiconductor device includes at least one heterodoped layer in the silicon carbide semiconductor structure. In some implementations, the heterodoped layer includes a first layer having a first dopant concentration of a first conductivity type in a range of about 1×1017 / cm3 to about 2×1021 / cm3. The heterodoped layer includes a second layer having a second dopant concentration of the first conductivity type that is less than the first dopant concentration of the first layer. The semiconductor structure includes a drift region, wherein the drift region has a third dopant concentration of the first conductivity type. The third dopant concentration is less than the first dopant concentration.

The invention relates to a cyclic aging test device for a power semiconductor device with a three-level three-phase bridge twin-dragging structure, which comprises a three-phase bridge test unit, a host control board and a slave control board, and is characterized in that the three-phase bridge test unit comprises a host three-phase bridge, a slave three-phase bridge and a three-phase inductive load with the same three-phase bridge structure; the three-phase bridge is connected with a power semiconductor device; the direct current ends of the host three-phase bridge and the slave three-phase bridge are connected in parallel, and the same group of direct current power supply Vdc supplies power to the host three-phase bridge and the slave three-phase bridge; the alternating current ends of the host three-phase bridge and the slave three-phase bridge are interconnected through the three-phase inductive load to form a twin-trawling structure; the slave control panel controls the voltage output of the three-phase bridge arm as the target of the current closed-loop control of the host control panel, and the host control panel simulates the actual working state of the power semiconductor device by adjusting a control strategy. The device has the beneficial effects that various real working conditions are simulated, and the cyclic aging test of the system-level AC type power semiconductor device is realized.

The invention relates to the technical field of power semiconductor device preparation, and discloses a preparation parameter optimization method, device and equipment of a power semiconductor device and a medium, the method comprises the following steps: obtaining various characterization data and current preparation parameters of the power semiconductor device, the current preparation parameters being process parameters adopted by the current preparation of the power semiconductor device; cue words are obtained, the cue words are used for indicating the direction in which the target model analyzes the representation data and used for indicating the optimization direction of the current preparation parameters, and the target model is a large language model in which a reinforcement learning algorithm is introduced; the various representation data, the current preparation parameters and the cue words are input into a target model to be analyzed and optimized, target preparation parameters of the power semiconductor device are obtained, and the target preparation parameters are predicted technological parameters enabling the performance of the power semiconductor device to be optimal in the optimization direction. Preparation parameters can be optimized in real time, and the method adapts to changes of new device structures and processes.

A power semiconductor device includes a semiconductor structure comprising an active region, an encapsulation material on the semiconductor structure, and a plurality of adhesion features in or on the semiconductor structure along an interface with the encapsulation material. The interface is laterally between the active region and at least one edge of the semiconductor structure. Related devices and fabrication methods are also discussed.

The invention provides a silicon substrate gallium nitride power semiconductor device and a preparation method thereof, and relates to the technical field of semiconductors. The device comprises a first silicon substrate layer, a second substrate layer, a substrate electrode and a gallium nitride device layer, the second substrate layer comprises a laminated structure which is periodically arranged; the laminated structure sequentially comprises a substrate functional layer and a second silicon substrate layer from bottom to top; wherein the first silicon substrate layer and the second silicon substrate layer adopt a first type of doping, and the substrate functional layer adopts a second type of doping, so that a bipolar doped substrate structure is formed. Based on this, when the silicon substrate gallium nitride power semiconductor device is in a high-voltage reverse bias state, at least one PN junction in the bipolar doped substrate structure can be in a reverse bias state due to the potential difference between the lower substrate electrode and the drain electrode of the silicon substrate gallium nitride power semiconductor device; and the breakdown voltage of the silicon substrate gallium nitride power semiconductor device in the vertical direction is further improved.

The invention belongs to the technical field of power semiconductor devices. The invention provides a SiC MOSFET surge current transient electrothermal coupling failure modeling method. A real packaging three-dimensional structure model is established, and material parameters are defined; dividing grids, constructing a current and solid heat transfer module, applying surge waveform data and realizing real-time coupling; carrying out transient solution to obtain temperature data, extracting a hot spot area and comparing thermodynamic critical parameters of the material; and establishing a multi-class failure mechanism model, and outputting a failure prediction result and reliability evaluation. The method is high in structural reduction degree, transient temperature rise and hot spot distribution can be accurately simulated, the problems that modeling is not accurate, transient electrothermal coupling analysis is lacked and a real failure mode cannot be reflected in the prior art are solved, the failure position, mode and threshold value can be accurately predicted, the method is suitable for reliability evaluation under the multi-surge condition, and the method is suitable for popularization and application. And the method has engineering application value and research significance.

The invention relates to the technical field of semiconductor devices, and discloses a wide bandgap power semiconductor device and a preparation method thereof. The method comprises: providing a substrate layer of a first conductivity type; forming a first doped region which is deep into the substrate layer and comprises a plurality of doped layers which are sequentially nested from outside to inside, wherein the doping concentrations of the plurality of doped layers are sequentially increased from outside to inside; forming a second doped region in the doped layer on the innermost side of the first doped region; forming an isolation layer on the first surface; forming a control electrode on the isolation layer; forming a first electrode on the first surface; a second electrode is formed on the second surface of the substrate layer. According to the invention, the first doped region which is located between the substrate layer and the second doped region and has the doping concentration gradually increased from outside to inside is formed through a mode of multiple times of ion implantation, so that transverse electric field constraint is constructed, transverse depletion of a channel region and a short channel effect under the condition of large voltage are inhibited, the channel width is reduced, and the performance of the device is improved. And the device performance and reliability are improved.

A power semiconductor device includes a semiconductor structure comprising an active region, and a plurality of stress relief trenches in the semiconductor structure laterally between the active region and at least one edge of the semiconductor structure. The stress relief trenches respectively comprise opposing sidewalls and a dielectric material and / or a semiconductor material therebetween, and do not contribute to electrical conduction between first and second terminals of the power semiconductor device. Related devices and fabrication methods are also discussed.

A power semiconductor module may comprise a common drain pad, a first power semiconductor device on a first region of the common drain pad, a second power semiconductor device on a second region of the common drain pad, a molding layer surrounding lateral parts of the first power semiconductor device and the second power semiconductor device on a peripheral region of the common drain pad, a common gate pad on the first power semiconductor device and the second power semiconductor device, and a source pad on the first power semiconductor device and the second power semiconductor device. The source pad may surround at least two outer lateral parts of the common gate pad.

Power semiconductor packages are provided. In one example, the power semiconductor package includes a first semiconductor die, a second semiconductor die, and a submount having a first side and a second side opposing the first side. The first semiconductor die is coupled to the first side of the submount, and the second semiconductor die is coupled to the second side of the submount.

The invention provides a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) integrated with an SCR (Selective Catalytic Reduction) and a manufacturing method thereof, and relates to the technical field of power semiconductor devices, the device is integrated with a PNPN four-layer structure consisting of a P + region, an N-type epitaxial layer, a P-type body region and an N + source region between a grid electrode and a source electrode, and the P + region is in metal ohmic contact with the source electrode. Through collaborative design of the distance and the doping concentration of the P + region and the N + source region, the forward and reverse trigger voltage thresholds of the PNPN structure can be accurately matched with the asymmetric driving window of the electric control main drive. The structure is arranged on the outer edge of a cellular area or a terminal area, and is electrically isolated from an active area, a field plate is arranged to suppress false triggering, ohmic contact is optimized to accelerate turn-off, and it is ensured that holding current is higher than parasitic latch triggering current, so that rapid and reliable discharge and self-protection of bidirectional surge between a gate and a source are achieved on the premise that the performance of a main device is not affected, and the reliability of the device is improved. And the gate oxide reliability is obviously improved.

The invention relates to the technical field of power semiconductor devices, and discloses a trench MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device integrated with a junction control diode and a method. A P-type well region is arranged on the first N-type epitaxial layer, a source contact region is arranged on the P-type well region, and an N-type buffer region is arranged at the bottom of the P-type well region; the N-type buffer region penetrates through the source electrode contact region and the P-type well region and goes deep into the trench MOSFET region of the first N-type epitaxial layer. According to the invention, the junction-controlled freewheeling diode is integrated at the side of the shield grid, so that the conduction voltage drop of the diode during freewheeling is reduced, and the reverse recovery time is greatly shortened. A high-turn-on-voltage diode is additionally arranged at the bottom of the shielding grid, the turn-on voltage is bipolar conduction, self-turn-on conduction is achieved under extreme working conditions such as surge, and the reliability of the device is improved. And the shielding grid electrode can form an electric field shielding effect during reverse voltage withstanding, so that electric field clamping at the bottom of the true grid electrode is realized.

The invention discloses a method and equipment for determining the aging degree of a power semiconductor device and a medium, and relates to the technical field of semiconductor device reliability detection, and the method comprises the steps: taking a composite data sequence as input, constructing an electrothermal bidirectional recurrent neural network model, carrying out the temperature compensation of electrical characteristic data, and generating a pure aging signal; performing time domain and frequency domain analysis on the pure aging signal, extracting a drift rate, a drift acceleration and a stable drift value, and performing vectorization processing to form an aging feature vector; comparing the aging feature vector with the multi-dimensional threshold interval one by one, and judging a corresponding aging degree grade according to a comparison result; and displaying the aging degree grade in real time, storing and generating an aging degree grade historical record, calculating an aging trend value, comparing the aging trend value with an aging warning threshold value, and triggering an early warning signal when the aging trend value exceeds the aging warning threshold value. According to the invention, the accuracy, stability and credibility of the whole aging degree determination process are improved.