1655 results about "Power semiconductor device" patented technology

Disclosed in the present invention are a grid-connect control method and apparatus for a grid-connect inverter. The method comprises: on the basis of a control structure of a grid-connect inverter in a dp domain, passing a deviation signal of a power outer loop through power outer loop controllers, so as to generate reference values of a current inner loop, and comparing the reference values of the current inner loop with an actual output current, so as to obtain error signals, wherein the control structure comprises a PQ power control outer loop and a current control inner loop, and the actual output current is obtained by means of performing phase tracking, on the basis of a synchronous reference frame phase-locked loop, on the voltage of a point of common coupling; and adjusting the error signals by means of a current inner loop controller, so as to generate modulation signals, performing pulse width modulation (PWM) on the modulation signals, so as to generate an on-off signal of an inverter bridge power semiconductor device, and controlling the state of connection and disconnection between the grid-connect inverter and a power grid on the basis of the on-off signal. In the present embodiment, the connection and disconnection between a grid-connect inverter and a power grid are controlled, so as to improve the stability of the grid-connect inverter in weak power grids.

The invention discloses a power semiconductor device aging on-line diagnosis method, which relates to the field of power electronics, and comprises the following steps: integrating an intelligent sensor and an aging test circuit, and establishing a multi-physics field coupling simulation model; based on the multi-physics field coupling simulation model, evaluating the aging state of the current device to obtain the health index of the device; based on the multi-dimensional data matrix, constructing an anomaly detection model, and outputting an anomaly detection result; predicting the failure probability and the remaining service life of the semiconductor device according to an abnormal detection result; generating a maintenance suggestion based on the predicted failure probability and remaining useful life of the semiconductor device; according to the method, the maintenance suggestion is generated according to the prediction result, the user is guided to take preventive maintenance measures in time, the accuracy of aging state evaluation is improved, the timeliness of fault early warning is enhanced, and economic losses and technical risks caused by sudden faults are reduced.

The invention provides a packaging and sintering evaluation method and device for a power semiconductor device, and the method comprises the steps: carrying out the non-destructive scanning through a high-frequency acoustic microtechnique, carrying out the correction through combining with a temperature-sound velocity relation model, achieving the real-time monitoring of a sintering process, and solving a problem that the transient change cannot be captured. Through frequency domain conversion and an improved inverse Fourier transform algorithm, precise reconstruction of the microstructure of the sintering interface is realized, and the limitation that the microstructure is difficult to evaluate in the prior art is overcome. Based on the reconstructed microstructure, a detailed three-dimensional geometric model is established, and time domain finite element analysis is performed, so that comprehensive thermal stress evolution data is obtained, and the defect of surface information of a traditional method is overcome. And quantitative evaluation is carried out by using the multi-dimensional feature space and the preset discrimination model, so that comprehensive analysis of the sintering quality is realized, and the defect of lack of comprehensive quantitative evaluation capability is overcome. Through organic combination of the steps, the accuracy and comprehensiveness of packaging and sintering evaluation are remarkably improved.

The invention belongs to the technical field of semiconductors, and discloses a SiC power semiconductor module with low parasitic parameters and a preparation method. Comprising a SiC power semiconductor chip, a SiC power semiconductor chip substrate cushion block, a positive electrode power terminal, a negative electrode power terminal, an output power terminal, a positive electrode side middle layer cushion block, a positive electrode side ceramic decoupling capacitor, a positive electrode side substrate middle layer cushion block, a negative electrode side middle layer cushion block, a negative electrode side ceramic decoupling capacitor and a negative electrode side substrate middle layer cushion block. A first copper-clad ceramic substrate, a third copper-clad ceramic substrate, a fourth copper-clad ceramic substrate, a second copper-clad ceramic substrate, a first commutation loop middle copper layer and a second commutation loop middle copper layer; according to the invention, a commutation path is provided for the SiC power semiconductor device by using the middle layer copper of the laminated copper-clad ceramic substrate, the concept of mutual inductance offset of double commutation loops is innovatively introduced, and the parasitic inductance of the module is further reduced.

The invention provides a packaging and sintering control method and device for a power semiconductor device, and the method comprises the steps: achieving the monitoring of a dynamic stress field of a chip and a substrate interface through an embedded pressure sensing array, and obtaining the real-time stress distribution data. And in combination with a material characteristic database, multivariable collaborative optimization is performed on sintering process parameters, so that dynamic adjustment of the parameters is realized. The temperature and pressure curves of all the areas of the sintering platform are dynamically adjusted according to the optimized technological parameters by means of the micro induction heating element and the piezoelectric actuator, and refined self-adaptive multi-area sintering control is achieved. The sintering interface is subjected to real-time nondestructive testing, the interface quality index is obtained and serves as a feedback parameter to be input into the optimization process, closed-loop control is formed, and the accuracy of the sintering process is improved. The problems of uneven stress distribution and inconsistent bonding strength in the prior art are solved through a comprehensive real-time monitoring and dynamic regulation and control method, and the packaging quality and reliability of the power semiconductor device are remarkably improved.

The utility model relates to the technical field of power semiconductor devices, and discloses a super-junction VDMOS device resistant to static breakdown, which comprises a drain electrode and a grid electrode, an N + substrate is deposited on the upper surface of the drain electrode, a buffer layer is arranged above the N + substrate, a first N-epitaxial layer grows on the upper surface of the buffer layer, and a second N-epitaxial layer grows on the lower surface of the buffer layer. A first N-epitaxial layer is grown on the substrate, a P-region is formed in the first N-epitaxial layer through ion implantation diffusion, a second N-epitaxial layer grows on the first N-epitaxial layer, highly-doped P columns are arranged on the two sides in the second N-epitaxial layer, a heavily-doped region hole potential barrier region is arranged on one side of each P column, and a lightly-doped region hole potential well region is arranged on the lower side of one side of each P column. According to the VDMOS device, the thickness of the gate dielectric layer is increased, the total thickness of the gate dielectric layer is 100 nm, the single-particle shrinkage-through effect of the VDMOS device can be effectively improved, the gate dielectric layer is composed of 20 nm silicon dioxide and 80 nm trisilicon nitride, the single-particle shrinkage-through resistance characteristic of the device is further improved, and under the same gate voltage, gate-source electric leakage is reduced.

A power semiconductor device includes a semiconductor layer structure comprising a drift region of a first conductivity type, and a gate trench extending into the drift region. The gate trench includes sidewalls and a bottom surface therebetween. A bottom shielding structure of a second conductivity type is provided under the bottom surface of the gate trench. First and second support shielding structures of the second conductivity type extend into the drift region on opposing sides of the gate trench and are spaced apart from the sidewalls thereof. A material composition, distance of extension into the drift region relative to a surface of the semiconductor layer structure, and / or dopant concentration of the bottom shielding structure may be different from that of the first and second support shielding structures. Related devices and fabrication methods are also discussed.

The invention relates to the technical field of sintering evaluation, in particular to a power semiconductor device packaging sintering evaluation method and device based on image analysis. The method comprises the following steps: obtaining a multi-source heterogeneous monitoring image set of a semiconductor device, carrying out multi-modal space corresponding relation identification, carrying out global registration precision compensation, and constructing a multi-modal space registration image matrix; carrying out multi-level voxelization analysis reconstruction based on the multi-modal space registration image matrix, carrying out structure deviation mapping modeling, and constructing a sintering three-dimensional structure deviation distribution map; and performing multi-directional defect detection according to the multi-modal space registration image matrix, performing defect cascade failure modeling, and constructing a multi-defect structure integrity association network. According to the method, accurate three-dimensional sintering structure defect analysis is realized, the quality of the sintering structure is quantified in all directions, and intelligent optimization and rapid iteration of a sintering process are promoted.

The invention provides a reconfigurable series-parallel connection network type converter with high overcurrent capacity and a construction method, and belongs to the technical field of power electronic directional power converters. Comprising the following steps of: respectively connecting two corresponding ports of two asymmetric half-bridge modules, symmetric half-bridge modules or H-bridge modules through two bridge type bidirectional switches or reverse series bidirectional switches, and connecting a group of two non-corresponding ports of the modules through a third bridge type bidirectional switch or reverse series bidirectional switch; according to the converter example, two corresponding ports of two H-bridge modules are connected through two bridge type bidirectional switches respectively, and a group of two non-corresponding ports of the two H-bridge modules are connected through a third bridge type bidirectional switch; on the basis that the number of modules is not increased, the overcurrent capacity of the grid-forming type converter is remarkably improved, and the saturation problem of magnetic elements such as a power semiconductor device and a filter inductor is avoided; the system is modularized, simple in structure, malleable and easy to standardize.

A heterojunction device having at least three terminals, the at least three terminals comprising a high voltage terminal, a low voltage terminal and a control terminal. The heterojunction device further comprises at least one main power heterojunction transistor, an auxiliary gate circuit comprising at least one first low-voltage heterojunction transistor, a pull-down circuit comprising a capacitor and a charging path for the capacitor. The heterojunction device further comprises at least one monolithically integrated component, wherein the capacitor is configured to provide an internal rail voltage for the at least one monolithically integrated component.

The invention belongs to the technical field of power semiconductor device life prediction, and particularly relates to a SiC MOSFET life prediction method based on gate oxide layer aging. The method comprises the following steps: firstly, acquiring a real threshold voltage sequence under different working conditions through a SiC MOSFET accelerated aging test, and preprocessing the real threshold voltage sequence; then, a life prediction model is constructed based on the conditional generative adversarial network, and the life prediction model comprises a generator, a common discriminator, a conditional discriminator, a coding network and a reverse recovery network; enabling the working condition as a condition label and the preprocessed real threshold voltage sequence to sequentially pass through a coding network and a reverse recovery network to obtain a real threshold voltage sequence embedded with the working condition; using the working condition as a condition label and a randomly generated Gaussian noise sequence to pass through a generator to obtain an analog threshold voltage sequence embedded with the working condition; inputting the real threshold voltage sequence and the simulation threshold voltage sequence with the embedded working conditions into a common discriminator and a condition discriminator at the same time for discrimination; and finally, training the life prediction model, and generating a threshold voltage sequence under an expected working condition by using a trained generator. According to the method, the service life of the SiC MOSFET under different working conditions can be predicted offline, and the method is more applicable.

A semiconductor device comprises a silicon carbide based semiconductor layer structure that comprises a drift region having a first conductivity type and an implanted region having a second conductivity type on the drift region. First and second gate trench sections extend into the semiconductor layer structure. A first maximum depth into the semiconductor layer structure of a first portion of the implanted region that is between the first gate trench section and the second gate trench section is different than a second maximum depth into the semiconductor layer structure of a second portion of the implanted region that extends downwardly underneath the first gate trench section.

The utility model relates to a power semiconductor device, in particular to a power semiconductor device, an upper P-type cover layer and a lower P-type cover layer are designed, the high doping concentration of the first P-type cover layer at the lower layer ensures that the threshold voltage of the device can reach a higher value, and the opportunity that an enhanced device is mistakenly opened is reduced; the doping concentration of the upper second P-type cover layer decreases progressively from bottom to top in the vertical direction and decreases progressively from the middle to the left edge and the right edge in the horizontal direction, the doping concentration of the surface corner position is low, when the grid electrode is pressed in the forward direction, the depletion region of the surface corner is deep, the formed peak electric field is low, the design reduces the leakage current of the grid electrode, and the reliability of the grid electrode is improved. And the breakdown voltage and the reliability of the gate are improved.

The invention provides a power semiconductor device which comprises a cellular area, a transition area and a terminal area, and the transition area is located between the cellular area and the terminal area of the device. The bottoms of the device cellular region, the transition region and the terminal region are jointly provided with a first conductive type substrate, a first conductive type epitaxial layer located above the first conductive type substrate and a first conductive type buffer layer located in the first conductive type epitaxial layer; under the application of large current, as the cellular region is the region with the maximum area proportion in the chip, if breakdown can occur in the cellular region, the current is discharged through the cellular region, and the robustness of the device is greatly improved; on the basis of ensuring the withstand voltage of the terminal region, the breakdown point is transferred to the large-area cellular region by adjusting the widths of the transition region and the N / P column of the terminal region and optimizing the electric field distribution of the terminal region, so that the EAS performance of the device is improved, the reverse withstand voltage characteristic of the device is optimized, the charge balance sensitivity of the terminal region of the device is reduced, and the robustness of the device is improved.

The invention provides an E-Comp and PTC two-in-one power semiconductor device, and relates to the technical field of semiconductor devices, the E-Comp and PTC two-in-one power semiconductor device comprises a substrate, a wafer, a plastic package body, a plurality of power pins and signal pins, the wafer is arranged on the substrate, the power pins and the signal pins are electrically connected with the substrate and the wafer respectively, a heat dissipation surface is arranged on one side, away from the wafer, of the substrate, and the heat dissipation surface is arranged on the other side, away from the wafer, of the substrate. And the substrate and the wafer outside the heat dissipation surface coated by the plastic package body, and one ends of the power pins and the signal pins far away from the substrate extend to the outside of the plastic package body. According to the vehicle-mounted air conditioner, the power semiconductor device is connected with the electric compressor and the PTC heater through the power pins, the refrigerating function and the heating function of the vehicle-mounted air conditioner can be integrated together, the integration degree of the power semiconductor device is improved, E-Comp compression refrigerating control and heating control of the PTC heater are achieved through the same power semiconductor device, the occupied space is reduced, and the vehicle-mounted air conditioner is convenient to use. The space utilization rate is improved, and the cost is reduced.

The invention relates to the technical field of power semiconductor devices, in particular to a power semiconductor device with a shield gate trench structure and a manufacturing method thereof, and the power semiconductor device comprises a drain electrode located at the bottom, an N + substrate located on the upper end face of the drain electrode, an N-drift region located on the upper end face of the N + substrate, a P-type body region located on the upper end face of the N-drift region, and a source electrode located at the top. By introducing the nano-composite super-junction shielding structure, optimizing the shape and the size of the groove and integrating the micro-nano fin structure and the reconfigurable self-adaptive shielding grid structure, the electric field distribution in the device can be remarkably improved, and the nano-particles in the nano-composite super-junction shielding structure, the P columns and the N columns have a synergistic effect; the reconfigurable self-adaptive shield grid structure adjusts the electric field in real time according to the working state, and the measures effectively relieve the groove electric field aggregation effect, so that the electric field distribution is more uniform, and the breakdown voltage and reliability of the device are improved.

The invention relates to the technical field of semiconductor packaging, in particular to a batch dust-free packaging device for power semiconductor devices and a using method of the batch dust-free packaging device for the power semiconductor devices, and the batch dust-free packaging device comprises a plastic packaging machine main body, a plastic packaging mold and a side frame, an upper plastic packaging mold and a lower plastic packaging mold are installed at the upper end and the lower end of the plastic packaging machine body respectively, a side frame is fixedly connected to one side of the plastic packaging machine body, a cleaning roller storage box is installed on one side of the side frame, and an electric push rod and an air supply and negative pressure unit are arranged in the cleaning roller storage box. Three-step dust-free cleaning of blowing, sucking and shaking is automatically carried out on a mold cavity after each time of plastic packaging; during air blowing, air is expanded and cooled twice through a conical barrel, the mold is synchronously cooled, and stubborn particles are stripped; negative pressure is formed on the surface of the cotton layer during air suction, and all residual scraps are sucked away; after cleaning is finished, the roller body returns to the storage box, the blocking block collides with the toothed plate to enable the roller body to jolt at high frequency, and attachments are shaken off into the box and are sealed and collected.

The utility model provides an adjustable pulse generator. The adjustable pulse generator comprises an input unit, a control unit and a driving circuit, the input unit is used for receiving a PWM signal parameter value input by a user; the control unit is used for outputting a PWM signal with a preset frequency and a preset duty ratio based on a PWM signal parameter value input by a user; and the driving circuit is used for modulating the PWM signal output by the control unit so as to drive the power semiconductor device to be tested. According to the adjustable pulse generator provided by the invention, parameters such as the frequency and the duty ratio of the pulse signal are adjustable, the circuit structure is simple, the cost is relatively low, and the size of a test tool is reduced.

A semiconductor device comprises a silicon carbide based semiconductor layer structure that includes a drift layer having a first conductivity type, a gate trench that extends to a first depth into an upper surface of the semiconductor layer structure, a gate electrode in the gate trench, a support shield trench that extends to a second depth into the upper surface of the semiconductor layer structure, where the second depth is less than the first depth, and a source metallization layer on the upper surface of the semiconductor layer structure and extending into the support shield trench.

The invention belongs to the field of power semiconductor devices, and discloses a dynamic current-sharing layout design method and system for a multi-chip parallel power module, and the method comprises two aspects of main power loop layout and wiring and driving loop layout and wiring. A main power loop is designed in a vertical commutation manner, and parallel chip source electrodes and drain electrodes are designed in an integrated manner, so that quasi-common-source-electrode inductors of the chips are consistent and integrated, and parallel dynamic current sharing of multiple gallium nitride chips is facilitated; wiring of the driving loop is in vertical commutation and is vertical to the main power loop, mutual inductance of the power loop to the driving loop is basically zero, and parallel dynamic current sharing of gallium nitride chips is facilitated; when the design is met and grid leading-out ends and Kelvin source leading-out ends of the four chips are symmetrical about the symmetry axis of the main power loop, the mutual inductance of the main power loop to a part of wiring from a drive to each chip grid is equal, and the mutual inductance of the main power loop to a wiring from a Kelvin source to a drive ground of each chip is also equal. And an excellent gallium nitride multi-chip parallel dynamic current sharing effect can be realized.

The invention discloses a trench-type power semiconductor device with a gate protrusion structure and a preparation method thereof. The preparation method comprises the following steps: depositing an epitaxial layer on a silicon substrate; sequentially preparing a silicon dioxide cushion layer, a first mask layer and a second mask layer on the epitaxial layer; etching to form a gate trench; forming a gate oxide layer; depositing grid polycrystalline silicon; removing the grid polycrystalline silicon on the surface of the first mask layer through chemical mechanical grinding; etching to remove the first mask layer, and adjusting the morphology of the grid polycrystalline silicon on the silicon platform region; forming a body region and a source region through ion implantation; and preparing a source region contact hole and a tungsten bolt. According to the invention, the grid protrusion structure is formed in the preparation process of the groove type power semiconductor device, the problem that the channel electric leakage is increased after the polycrystalline silicon is etched is solved, the grid resistance is reduced by increasing the cross sectional area of the grid polycrystalline silicon, the switching speed and the linear region capability are improved, and the device performance is optimized.

A semiconductor device comprises a semiconductor layer structure comprising a drift region having a first conductivity type, a well region having a second conductivity type on the drift region, and a first JFET region having the first conductivity type, and a gate trench extending into the semiconductor layer structure. An upper surface of the first JFET region is positioned below the gate trench. A first conductivity dopant concentration of the first JFET region exceeds a first conductivity dopant concentration of the drift region.

The invention belongs to the technical field of radiators, and particularly relates to a radiator for a power semiconductor and an assembling method thereof. The radiator comprises a heat dissipation bottom plate, a heat dissipation plate and a heat dissipation shell, the heat dissipation bottom plate is used for connecting the power semiconductor device and the heat dissipation plate, the heat dissipation bottom plate and the heat dissipation plate form a heat dissipation bottom plate-heat dissipation plate combination body through a vacuum brazing or pressure sintering process, and the heat dissipation bottom plate-heat dissipation plate combination body is reliably connected with the heat dissipation shell; the heat dissipation bottom plate is made of a material with a thermal expansion coefficient similar to that of the power semiconductor device; a window is arranged on the heat dissipation bottom plate, a protruding part is arranged at the position, corresponding to the window, of the heat dissipation plate, and the protruding part of the heat dissipation plate penetrates through the window to make contact with the power semiconductor device. According to the radiator, the titanium alloy or the tungsten copper alloy with the thermal expansion coefficient similar to that of the power semiconductor device is adopted as the heat dissipation bottom plate, and the protruding parts on the heat dissipation plate penetrate through the windows of the heat dissipation bottom plate to be in direct contact with the power semiconductor device, so that the heat dissipation efficiency can be improved.

The invention discloses a semiconductor device critical breakdown characteristic simulation method based on a hybrid finite volume method. The method comprises the following steps: firstly, carrying out geometric modeling on a device, and carrying out mesh generation; then, the quality of the grids is judged, an FBM method is adopted for the grids with the good quality, and a CVFEM method is adopted for the grids with the poor quality to discretize a drift-diffusion equation set; and then, solving the discrete drift-diffusion equation set system by adopting a full-coupling Newton iteration method, and realizing the optimization of the boost numerical simulation process by adopting an automatic boost strategy and an initial value extrapolation method. And finally, obtaining physical field information of a power semiconductor device (LDMOS) under different external bias voltages, calculating terminal current through a post-processing method, and obtaining an I-V characteristic curve of the device after the avalanche breakdown effect is considered. The method has good numerical calculation precision, numerical stability and grid adaptability, and the complete benchmarking with the solution precision of an international advanced semiconductor simulation tool Sentaur TCAD is realized.

The invention provides a manufacturing method of a semiconductor structure, which is applied to the technical field of semiconductors. According to the invention, before the second conductive layer is formed, the ion implantation process is carried out on the substrate, so that the first ion implantation region is formed in the substrate below the deep trench, and the second ion implantation region is synchronously formed in the substrate at two sides of the deep trench, thereby saving an ion implantation process. The conduction type of the first ion implantation region (located between the control gate and the drain electrode) is opposite to that of the substrate, so that carriers can be mutually depleted, and the purpose of increasing a depletion region and the breakdown voltage is achieved; and then a second conductive layer is formed and deposited in the deep trench, and a control gate in a special shape is formed by combining a first conductive layer on the side wall of the deep trench, so that the purposes of reducing the overlapping area between the control gate and a drain electrode, reducing the gate-drain capacitance of the power semiconductor device, reducing the switching loss and finally improving the switching speed are achieved.

The invention discloses a dynamic reverse bias test method and system for a power semiconductor device, and relates to the technical field of power semiconductor device testing, and the method comprises the steps: obtaining a test parameter of a tested device, and carrying out the test circuit configuration based on the test parameter of the tested device; performing a dynamic reverse bias test based on the configured test circuit to obtain a test result; and analyzing and evaluating a test result. According to the method, the accuracy and reliability of a test result are improved, a solid foundation is provided for a subsequent dynamic reverse bias test, potential problems of the device can be found in time, it is ensured that the test result has an actual reference value, real-time data support is provided for subsequent evaluation and analysis, the performance state of the device can be accurately judged, and the reliability of the device is improved. The safety of the test process is ensured, the integrity and sufficiency of the test are ensured, and misjudgment caused by insufficient test is avoided.

The invention discloses a double-sided heat dissipation common drain module packaging structure, and belongs to the technical field of power semiconductor device packaging. The module comprises a common drain electrode upper copper layer, two drain electrode copper terminals, two power chips, two source electrode copper blocks, two L-shaped source electrode lower copper layers, two driving grid electrode copper terminals, two driving source electrode copper terminals and a bonding wire. Drain electrodes of the two power chips are welded on the common drain electrode upper copper layer, and source electrodes of the two power chips are respectively welded with the L-shaped source electrode lower copper layer through source electrode copper blocks. And the bonding wire is connected with the grid electrode and the source electrode of the chip and the driving copper terminal to realize Kelvin connection. Thermal resistance is reduced through a double-sided heat dissipation structure, parasitic inductance is reduced through a three-dimensional commutation loop, power density and reliability are improved, and the common drain geminate transistor is suitable for common drain geminate transistor application in a battery management system.

The invention discloses a high-temperature test method for a power semiconductor device, and relates to the technical field of quantum thermal control, and the method comprises the steps: collecting a temperature field and surface conductivity data of an edge region of the power semiconductor device in real time, and synchronously applying an electric stress of a specified working voltage to the power semiconductor device; an internal thermal displacement field is reconstructed based on the temperature field, a calibration thermal displacement field is generated, and the topological number of the edge area is calculated in combination with the surface conductivity data; generating a thermal failure risk distribution map according to the spatial position of the peak value of the thermodynamic entropy yield, and locking a high-entropy variable power dense region; and the electric stress applying direction is dynamically adjusted in association with the high-entropy variable power dense area, and a thermal failure diagnosis report is output after a full-period high-temperature test is completed. According to the method, submicron-level real-time positioning of the thermodynamic entropy generation peak value under the high-temperature working condition is achieved through collaborative mapping of the quantized calibration thermal displacement field and the tensor field of the classic temperature gradient.

The invention provides an IGBT (Insulated Gate Bipolar Translator) turn-off time measuring method, system, equipment and medium, and belongs to the field of power semiconductor device testing technology and state monitoring, and the method comprises the following steps: firstly, selecting 20% Vdc and 80% Vdc as turn-off initial measuring points, secondly, carrying out first error correction by adopting a linear estimation method, and finally, carrying out second error correction by adopting a linear estimation method; performing linear fitting on the voltage difference Vce data through a least square method to obtain initial turn-off time; and finally, aiming at systematic deviation caused by inherent concavity and convexity characteristics of the voltage curve, performing secondary error correction by adopting a convex hull algorithm, acquiring a lower envelope line of the ic-tOFF relation curve through an Andriw algorithm, and identifying and eliminating the problem of Overestimation of the turn-off time based on a convex hull accurate point set. According to the invention, accurate measurement of the turn-off time of the IGBT under the condition of low sampling rate is realized, the hardware cost is significantly reduced, and a reliable technical basis is provided for IGBT state monitoring and life prediction.

The invention discloses a power semiconductor device continuous switch test circuit and method, and relates to the field of power electronics, and the test circuit comprises a current generator which is used for generating a test current; the voltage balance module is used for generating test voltage; the auxiliary module is connected with the current generator and the voltage balance module and is used for providing test voltage and test current required in a continuous switching state for the power semiconductor device T1 to be tested; the capacitor discharging module is used for controlling the magnitude of voltage connected to the two ends of the power semiconductor device T1 to be tested; wherein the voltage balance module comprises a power semiconductor device Tc2 and a capacitor C1; the power semiconductor device Tc2 controls the capacitor C1 to apply voltage to the inductor L in the auxiliary module, and the voltage at the two ends of the inductor L is balanced. According to the application, the continuous switching condition simulation of the power semiconductor device T1 to be tested is met, and voltage and current stress decoupling is realized, so that a voltage source does not need higher voltage stress, and the requirement on a power supply is reduced.