267results about How to "Increase the on-resistance" patented technology

A converter circuit and related technique for providing high power density power conversion includes a reconfigurable switched capacitor transformation stage coupled to a magnetic converter (or regulation) stage. The circuits and techniques achieve high performance over a wide input voltage range or a wide output voltage range. The converter can be used, for example, to power logic devices in portable battery operated devices.

A power semiconductor device includes a plurality of trenches formed within a semiconductor body, each trench including one or more electrodes formed therein. In particular, according to embodiments of the invention, the plurality of trenches of a semiconductor device may include one or more gate electrodes, may include one or more gate electrodes or one or more source electrodes, or may include a combination of both gate and source electrodes formed therein. The trenches and electrodes may have varying depths within the semiconductor body.

A stereo class-D audio system includes a first die including four monolithically integrated NMOS high-side devices and a second a second die including four monolithically integrated PMOS low-side devices. The audio system also includes a set of electrical contacts for connecting the high and low-side devices to components within the a stereo class-D audio system, the set of electrical contacts including at least one supply contact for connecting the drains of the high-side devices to a supply voltage (V_cc) and at least one ground contact for connecting the drains of the low-side devices to ground, the electrical contacts also including respective contacts for each source of the high and low-side devices allowing the source of each high-side device to be connected to the source of a respective low-side device to form two H-bridge circuits.

In a semiconductor device in which a diode and a high electron mobility transistor are incorporated in the same semiconductor chip, a compound semiconductor layer of the high electron mobility transistor is formed on a main surface (first main surface) of a semiconductor substrate of the diode, and an anode electrode of the diode is electrically connected to an anode region via a conductive material embedded in a via hole (hole) reaching a p⁺ region which is the anode region of the main surface of the semiconductor substrate from a main surface of the compound semiconductor layer.

In a semiconductor device including a gate electrode buried in a trench of the device, the trench is constructed by a first opening with a uniform width the same as that of an upper portion of the first opening and a second opening beneath the first opening with a width larger than the uniform width. A bottom of a base region adjacent to the trench is adjacent to the second opening.

There is a need for turning off a transistor in a power supply switch circuit irrespective of relative potential relationship between a contact power supply terminal and an internal power supply line and making it possible to decrease an on-resistance of an MOS transistor without increasing the size of the MOS transistor constituting the power supply switch circuit. The power supply switch circuit is comprised of two PMOS transistors whose gate terminals connect with two pull-up circuits. A charge pump circuit generates a negative voltage and is connected to a pull-down circuit. The pull-down circuit is connected to the gate terminals in common. During a contactless operation, the pull-up circuit short-circuits one gate terminal to a contact power supply terminal VDD and the other gate terminal to an internal power supply line VDDA. During a contact operation, the pull-up circuit supplies both gate terminals with a negative voltage from the charge pump circuit.

Improved highly reliable power RFP structures and fabrication and operation processes. The structure includes plurality of localized dopant concentrated zones beneath the trenches of RFPs, either floating or extending and merging with the body layer of the MOSFET or connecting with the source layer through a region of vertical doped region. This local dopant zone decreases the minority carrier injection efficiency of the body diode of the device and alters the electric field distribution during the body diode reverse recovery.

In a manufacturing method of a semiconductor device, first, a first semiconductor layer, a second semiconductor layer, and a p-type third semiconductor layer are sequentially epitaxially grown on a substrate. After that, the third semiconductor layer is selectively removed. Then, a fourth semiconductor layer is epitaxially grown on the second semiconductor layer. Then, a gate electrode is formed on the third semiconductor layer.

The invention discloses a synchronous rectification control method and circuit, and the method comprises a plurality of working steps. At a later working stage of synchronous rectification, a drain-source voltage rises to a closed-loop threshold voltage along with the decrease of a current, and a grid-source voltage starts to decrease, thereby enabling conduction resistance to increase. Through enabling a drain-source voltage of a synchronous rectification tube to be close to a reference voltage, the drain-source voltage remains equal to the closed-loop threshold voltage. Therefore, the drain-source voltage remains unchanged in a later period of synchronous rectification conduction, and primary side detection is enabled to be more accurate. Meanwhile, a grid-source switching-off threshold voltage is used for judging the switching-off time, thereby guaranteeing that the synchronous rectification tube is precisely switched off at a moment of current zero crossing.

The invention relates to the field of a radio frequency power device, and discloses a radio frequency SOI LDMOS device with close body contact. The device comprises bottom layer silicon, an embedding oxidation layer, top layer silicon, a P region an N region, a gate oxidation layer, a polysilicon gate layer, a gate poly-silicide layer, a gate electrode, a silicon nitride side wall, an N drift region, a drain region, a drain region silicide layer, a drain electrode, a source region, a body contact region, a body region, a source region silicide layer and a source electrode. The radio frequency LDMOS device is manufactured on an SOI substrate, and forms the close body contact which is in short circuit with the source region by utilizing a heavily doped region in the same form as the P region; the source/body, a drain/body and the gate and the electrodes are interconnected by the silicide; a plurality of gate bars are connected in parallel in the forked mode so as to improve the driving capability of the device; a method for adjustment, back-gate injection, N region injection and N drift region injection, which is compatible with the CMOS process, is designed; and a method for hiding the silicide in the N drift region, which is compatible with the CMOS process, is designed.

The invention discloses an LDMS (Laterally Diffused Metal Oxide Semiconductor) device with a stepped multiple discontinuous filed plate and a manufacturing method for the LDMS device. The LDMS device comprises a semiconductor body, wherein the semiconductor body comprises a semiconductor substrate region, a semiconductor epitaxial layer and a semiconductor medium layer which are sequentially arranged from bottom to top; a grid extending along a channel and at least two field plates are arranged in the semiconductor medium layer; at least two field plates are sequentially arranged in a horizontal direction from the grid to a leakage-drift region; a first field plate adjacent to the grid horizontally extends in the leakage-drift region; field plates which are not adjacent to the grid are respectively in a horizontal strip shape; the distance between every two field plates is greater than zero; the distance between a second field plate adjacent to the first field plate and the leakage-drift region is greater than the distance between a horizontally-extending part of the first field plate and the leakage-drift region; and the distance between other horizontal strip field plates and the leakage-drift region is gradually increased. According to the LDMS device disclosed by the invention, the contradiction between source and drain breakdown voltage and the optimal requirement of a conducting resistor is relieved and the performance of the LDMS device is improved.

A method for manufacturing a semiconductor device includes the steps of: forming, on a principal face of a substrate, a semiconductor layer including a first semiconductor region of a first conductivity type; and forming, in the semiconductor layer, a trench having a bottom located in the first semiconductor region. The method further includes a step of forming a trench bottom impurity region being of a second conductivity type and covering the bottom of the trench by performing annealing to cause part of the semiconductor layer corresponding to an upper corner portion of the trench to move to be placed on the bottom of the trench.

A process for manufacturing a semiconductor device of the trench variety with reduced feature sizes and improved characteristics which process includes forming a termination structure having a field oxide disposed in a recess below the surface of the semiconductor die in which the active elements of the device are formed, and forming source regions after the major thermal steps have been performed.

The invention discloses a power supply and a power supply system with multiple power supplies. The power supply is used for receiving an electric energy of an input voltage and generating an output voltage and an output current. The power supply comprises a power convertor, an output protecting circuit and a control unit, wherein the power convertor is used for receiving the electric energy of the input voltage and generating an inner output voltage; the output protecting circuit is connected with an output end of the power convertor and comprises a plurality of switch circuit sets in parallel connection; the output protecting circuit is used for limiting a current direction of the output current under an switch-on/off action of the switch circuit sets; the control unit is electrically connected with the output protecting circuit; and the control unit is used for outputting a plurality of control signals for respectively controlling the switch circuit sets, wherein at least two control signals are included and are used for respectively controlling at least two switch circuit sets to switch off at different moments. The power supply provided by the invention can be used for increasing power supply efficiency under the normal running of the power supply and the production cost is lower.

A semiconductor device includes a semiconductor substrate, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a first semiconductor region of the first conductivity type, a second semiconductor region of the second conductivity type, a gate insulating film, and a gate electrode. The semiconductor device further includes, in a region of the first semiconductor layer across or adjacent to a p-n junction therein that does not overlap the second semiconductor region in a plan view except lateral edges thereof, a lifetime killer region having lifetime killers implanted therein.

A high voltage LDMOS transistor according to the present invention includes at least one P-field block in the extended drain region of the N-well. The P-field blocks form junction-fields in the N-well for equalizing the capacitance of parasitic capacitors between the drain region and the source region and fully deplete the drift region before breakdown occurs. A higher breakdown voltage is therefore achieved and the N-well having a higher doping density is thus allowed. The source region and P-field blocks enclose the drain region, which makes the LDMOS transistor self-isolated.

The subject matter disclosed herein relates to super-junction (SJ) power devices and, more specifically, to edge termination techniques for SJ power devices. A semiconductor super-junction (SJ) device includes one or more epitaxial (epi) layers having a termination region disposed adjacent to an active region. The termination region includes a plurality of vertical pillars of a first and a second conductivity-type, wherein, moving outward from the active region, a respective width of each successive vertical pillar is the same or smaller. The termination region also includes a plurality of compensated regions having a low doping concentration disposed directly between a first side of each vertical pillar of the first conductivity-type and a first side of each vertical pillar of the second conductivity-type, wherein, moving outward from the active region, a respective width of each successive compensated region is the same or greater.