771 results about "Switched capacitor" patented technology

The invention discloses a frequency division control radio frequency power supply solid-state impedance matcher and a method thereof, and aims to solve the problems that a traditional mechanical impedance matcher is slow in response, low in adjustment precision and difficult to adapt to a dynamic load. According to the system, an all-solid-state impedance matcher is adopted, impedance dynamic adjustment is achieved through a matching network composed of an adjustable inductance module and a switched capacitor module, closed-loop control is constructed in combination with a radio frequency signal detection module and a digital signal processor, and a frequency division control strategy is adopted, and the high-frequency band realizes high-precision matching through a control strategy of coarse adjustment of the adjustable inductance module and fine adjustment of the switched capacitor module. The device has the advantages of high response speed, wide frequency band coverage and the like, and is particularly suitable for industrial plasma application scenes with remarkable dynamic impedance characteristics.

A system and method are used to maintain a variance in feedback factors of an amplifier between the first and second phases either below a threshold value or within a specified range. The system includes the amplifier and first through third capacitances. The amplifier is coupled between an input node and an output node that operates during first and second phases of operation. The first capacitance is coupled across the amplifier and between the input node and the output node during the first and second phases of operation. The second capacitance is coupled to the input node during the first phase of operation. The third capacitance is coupled to one of the input and output nodes during one or both of the first and second phases of operation.

The invention relates to the technical field of artificial intelligence, and discloses a charging pile operation state management method and system based on artificial intelligence, and the method comprises the steps: constructing a dual-input single-output DC-DC conversion control circuit structure based on an input power supply, a main power switching device, a three-winding coupling inductor and a switched capacitor unit; calculating a switch time sequence control signal based on a double-input single-output DC-DC conversion control circuit structure; detecting the running state of the charging pile to obtain a multi-dimensional quantized data set, and performing data coding to obtain a standard data information sequence; performing multi-dimensional feature value extraction and fault position identification on the standard data information sequence to obtain a fault positioning result; according to the fault positioning result and the switch time sequence control signal, closed-loop regulation control is carried out on the power device conduction time sequence and the clamping circuit parameters, stable direct-current output voltage is obtained, the voltage conversion efficiency is improved, the accuracy of fault recognition is improved, and the misjudgment rate is reduced.

The invention relates to a modular commutation type converter operation test system, which comprises an energy complementing device, a soft start circuit, a load reactor, a sampling device and a centralized control device, and is characterized in that the energy complementing device comprises a plurality of direct current output ends, and each direct current output end is correspondingly connected with a test object switch capacitor module, so that energy complementing is carried out on each test object switch capacitor module independently. Under the control of the centralized control device, the energy complementing device is combined with the soft start circuit, so that the test object switch capacitor module and the test object H-bridge valve string are subjected to soft start charging operation, various different working conditions of the modular commutation type converter can be simulated, and the operation test of the modular commutation type converter can be realized according to set test parameters and operation test parameters. Through the scheme, the twin-dragging experiment of the test object switch capacitor module and the test object H-bridge valve string in the modular reversing converter can be realized, so that the blank of the MCC operation test platform is filled, and the product design capability and quality of the MCC are improved.

A multiphase buck converter that includes smart two-phase power stages for reducing switching losses. Each of the smart power stages includes a first high side switch, a second high side switch, a first low side switch, a second low side switch, a switching capacitor, a first inductor, and a second inductor. The exemplary multiphase buck converter includes two such smart power stages and a multiphase controller for generating PWM signals for driving the two smart power stages synchronously.

A power supply circuit has a first node, a second node, a DC-DC converter that includes a switched capacitor, generates an output voltage based on an input voltage supplied from the first node, and outputs the output voltage from the second node, and a regulator that is connected in parallel to the DC-DC converter between the first node and the second node and controls an output current flowing to the second node based on a reference voltage lower than the input voltage.

An apparatus as discussed herein can be configured to include a first analog-to-digital converter operative to convert a first analog voltage into a first digital signal; a digital-to-analog converter operative to convert the first digital signal into a second analog voltage; a switched capacitor circuit coupled to the digital-to-analog converter, the switched capacitor circuit is operative to store a sample of the second analog voltage; and a second analog-to-digital converter operative to convert an analog error voltage into a second digital signal, the analog error voltage based on a difference between the sample of the second analog voltage received from the switched capacitor circuit and a sample of the first analog voltage.

The invention discloses a CMOS analog multiplier circuit, the circuit comprises a current-to-voltage circuit and a multiplier sub-circuit connected with the current-to-voltage circuit, an OSC circuit in the multiplier sub-circuit receives an input voltage VB and a reference voltage VREF and generates a two-phase non-overlapping clock signal group, a voltage-to-current A circuit converts a voltage VA into a current iA, and the current iA is connected with the OSC circuit. The switched capacitor integrating circuit inputs a sampling voltage to the voltage-to-current B circuit and integrates a difference current is of a current iA and a current iB to realize multiplication, the voltage-to-current B circuit converts a sampling voltage signal into the current iB, and the current-to-voltage circuit converts the current iB into an output voltage Vo as a multiplier operation result. Through combination of modular design, a current mode method and a switched capacitor method and high-precision current conversion and integration processes, an efficient and accurate multiplication simulation function is realized, a THD enhancement function is introduced through multiplexing design, and circuit performance is further optimized.

A switched capacitor converter includes an auxiliary circuit, a first branch and a second branch, the auxiliary circuit is connected between the first branch and the second branch, all power transistors of the first branch and the second branch are primary power transistors, and the auxiliary circuit transfers a charge or electric charges on one of the first branch and the second branch to another of the first branch and the second branch during a dead time when the primary power transistors are turned off, so as to the primary power transistors turn on at zero voltage and reduce a switching loss.

The invention relates to a three-winding coupling inductor bipolar output high-gain DC-DC converter, which is characterized in that a coupling inductor and switched capacitor boosting technology is introduced into a three-level Boost bipolar output converter, and bipolar output voltages Uo1 and Uo2 are controlled by adjusting the turn ratio of the coupling inductor and the duty ratio of a switch; and the input and output power is changed by adjusting the resistance value of the output load. The DC-DC converter is low in input current ripple, high in voltage gain and low in switching tube voltage stress, and bipolar output voltage can be flexibly adjusted through the duty ratio and the coupling inductor turn ratio.

A Hybrid Switched Capacitor Converter (HSCC) topology is presented that is suitable for high conversion ratio Point-of-Load (PoL) applications. The topology specifically targets 48V to 1V power delivery in space-based high-performance computing systems, where size and weight are important considerations, along with device de-rating for radiation tolerance. One implementation merges an initial 2:1 switched capacitor conversion stage with a symmetric dual inductor hybrid (SDIH) conversion stage, reaping benefits of both. The SDIH stage offers reduced component count and an excellent switch stress figure of merit, while the initial 2:1 voltage reduction stage significantly reduces the volume of flying capacitors, enabling compact size and low weight.

The invention provides a series-parallel switched capacitor converter. The series-parallel switched capacitor converter comprises a voltage source, a switch module, a plurality of charge transfer modules, voltage detection modules and a series switching module, wherein the voltage detection modules are in one-to-one correspondence with the charge transfer modules; the first output end of each charge transfer module is connected with the first input end of the voltage detection module, the second output end of the last charge transfer module is connected to the negative electrode of the voltage source, the second output end of each charge transfer module is connected to the second output end of the series switching module, and the control end of each charge transfer module is connected with the first output end of the series switching module; the second input end of each voltage detection module is connected to the positive electrode of the voltage source, and the output end is connected with the control end of the series switching module; the voltage detection module detects the voltage of the charge transfer module and generates a voltage detection signal; the series switching module switches the driving mode of the charge transfer module in the series energy storage state to a voltage driving mode or a current driving mode according to the voltage detection signal, thereby improving the charging stability.

The invention belongs to the technical field of power management, and particularly relates to a double-phase DC-DC topological structure with a current multiplier. The invention is characterized in that a current multiplier and a switched capacitor SC buck are embedded on the basis of the traditional multiphase buck, the inductive current and the RMS current of a buck power device are greatly reduced, the current stress is transferred to a charge pump structure of a low-voltage and low-FoM-value device, and the voltage stress is retained in a high-voltage device of the buck. And high conversion efficiency is realized through a strategy that the charge pump and the buck share current and voltage stress respectively. Meanwhile, due to the fact that the switched capacitor has extremely low output impedance, and the circuit is compatible with a loop control strategy of a traditional multi-phase buck, the transient response speed is also remarkably improved. The idea of the invention can be linearly expanded from typical two-phase buck to N-phase buck, so that the topological structure of the invention has universality.

The invention discloses a low-power-consumption small-area on-chip temperature sensor based on an MOS tube and a method thereof. Comprising a temperature sensing circuit and an analog-to-digital conversion circuit which are connected with each other, the temperature sensing circuit is used for generating a voltage signal related to the temperature and outputting the voltage signal to the analog-to-digital conversion circuit to achieve digital quantization of the temperature, and the output end of a CTAT branch is connected to the input end of a switched capacitor amplifier through a buffer. The output end of the switched capacitor amplifier is connected to the non-inverting input end of the comparator, the output end of the PTAT branch is connected to the inverting input end of the comparator, the output end of the comparator is connected with the input end of the successive approximation logic unit, and the output end of the successive approximation logic unit is connected to the switched capacitor amplifier. According to the temperature sensing circuit structure, the problem of power supply sensitivity existing when voltage is generated is effectively solved, reference signals do not need to be additionally generated in the quantization process, and the problem of error accumulation is avoided.

The invention discloses a low-noise and high-precision analog front-end circuit for biological signal acquisition. The low-noise and high-precision analog front-end circuit comprises a chopping capacitance coupling type instrument amplifier circuit, a switched capacitor type programmable gain amplifier circuit and a Sigma-Delta analog-to-digital converter modulator circuit. T-type capacitance feedback, chopping modulation and programmable technologies are introduced on the basis of an existing amplifier, and the low-noise and programmable gain functions of the pre-amplifier are achieved. Through the three-order one-bit quantized feed-forward chopping type Sigma-Delta modulator, the signal to noise ratio and the effective bit number of the signal are improved. Compared with the prior art, the analog front-end circuit not only has the capability of changing the gain multiple according to the bio-electricity signal, but also has the low-noise and high-precision signal processing effect, and the problems that a traditional analog front-end circuit is large in noise and low in signal processing precision are solved. In addition, the biological signal acquisition-oriented circuit provided by the invention can also be used in other analog front ends, such as an audio processor and the like, and is wide in application range.

The invention discloses an ultra-wideband circulator based on a periodic modulation topology circuit, and belongs to the technical field of microwave and radio frequency nonreciprocal circuits. The working bandwidth range of the circulator is widened, and non-reciprocal transmission is achieved through non-magnetic materials. A time sequence control unit is respectively connected with a Floquet topology circuit layer, a clock signal driving module, a reset signal driving module and a start signal driving module; the Floquet topology circuit layer is respectively connected with a first coupling port, a second coupling port and a third coupling port; the other ends of the first coupling port, the second coupling port, the third coupling port, the clock signal driving module, the reset signal driving module and the starting signal driving module are respectively grounded; the Floquet topology circuit layer adopts a six-layer parallel network structure, and each layer of network structure comprises a coupling capacitor and three N-type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) switches. The advantages of the switched capacitor structure are utilized, and the signal processing capacity which is high in integration level, small in size and capable of breaking through delay-bandwidth limitation is achieved.

According to an aspect, there is provided an all-digital phase-locked loop, ADPLL, for a radio receiver, transmitter or transceiver. The ADPLL comprises a time-to-digital converter for generating a digital time signal based on an external reference clock signal and a feedback signal, a switched capacitor digitally controlled oscillator, SC-DCO, for generating a radio frequency signal used as the feed-back signal, a phase-locked loop for controlling the SC-DCO based on the digital time signal for achieving a phase and frequency lock and digital processing means. The digital processing means are configured to maintain, in at least one memory, a lookup table defining a plurality of switching configurations of the SC-DCO corresponding to a plurality of frequencies of the radio frequency signal and to cause the phase-locked loop controller to adjust the switching configuration of the SC-DCO according to the lookup table.

A power amplifier includes a main switched capacitor power amplifier (SCPA), a peak SCPA, and a shunt inductor. The main SCPA is electrically coupled to a load. The peak SCPA is in parallel with the main SCPA and electrically coupled to the load. The shunt inductor is electrically coupled between the peak SCPA and the load.

The invention relates to a clock delay circuit for reducing interleaving distortion of a time interleaving pipeline ADC, and belongs to the field of analog-to-digital converters. Comprising a four-channel time-interleaved sampling switched capacitor array, an allowance amplifier module and four groups of delay control circuits, the four-channel time-interleaved sampling switched capacitor array comprises four sampling switched capacitor arrays which are connected in parallel; the four sampling switch capacitor arrays connected in parallel are all communicated with the allowance amplifier module; each group of delay control circuits is correspondingly connected with one sampling switch capacitor array; the delay control circuit comprises a clock generation circuit and a programmable current source array; the programmable current source array is connected with the clock generation circuit; the output end of the clock generation circuit is connected with the corresponding sampling switch capacitor array; according to the invention, the effect of reducing interleaving distortion in the four-channel time-interleaving pipeline analog-to-digital converter is realized, and the performance of the whole analog-to-digital converter is further improved.

A switch control method is applied to a hybrid voltage converter including a switched capacitor unit and a freewheeling unit. The method including obtaining the output current of the hybrid voltage converter, when the output current is greater than a first current threshold, controlling the switches in the hybrid voltage converter to operate in parallel conduction mode, when the output current is less than the first current threshold, controlling the switches in the hybrid voltage converter to operate in sequential conduction mode. When the switches operate in parallel conduction mode, N switches in the switched capacitor unit are controlled to turn on and off with the same duty cycle and a phase shift of 360 / N degrees. When the switches operate in sequential conduction mode, each switch in the switched capacitor unit is controlled to conduct individually with the same duty cycle in sequence.

The invention discloses a gallium nitride hybrid switched capacitor voltage converter with a high step-down ratio, which belongs to the technical field of switching power supplies and comprises an input filtering module, a switched capacitor module group, a half-bridge module group and an output filtering module which are connected in sequence, the switched capacitor module group comprises a plurality of switched capacitor modules which are connected in parallel, the half-bridge module group comprises a plurality of half-bridge modules which are connected in parallel, and the switched capacitor modules and the half-bridge modules are in one-to-one correspondence and work in corresponding preset switching periods; the output filtering module comprises a plurality of output filtering inductors, and the output filtering inductors are correspondingly connected with the half-bridge modules. Through innovation of the topological structure, the buck ratio higher than that of a traditional Buck converter under the same duty ratio is achieved, input current and output voltage ripples are further improved through a multi-phase interleaving parallel control mode, wide bandgap devices are reasonably selected for the innovatively-designed topological structure, and therefore the output current and output voltage ripples are improved. And the circuit is more suitable for kilowatt-level switching power supply equipment.

Switched capacitor power converter circuitry configured to receive an input voltage and to output an output voltage, the switched capacitor power converter circuitry comprising: a switch network; a flying capacitor coupled to the switch network; and an output capacitor coupled to an output node of the switch network, wherein the switched capacitor power converter circuitry is operable in: a first mode in which the switch network operates at a fixed duty cycle; and a second mode in which the switch network operates at a variable duty cycle based on a predetermined flying capacitor charging threshold and a predetermined flying capacitor discharging threshold.

A fully differential switched capacitor amplifier receives a differential analog signal from a differential input terminal, amplifies the differential analog signal, and outputs an amplified signal from a differential output terminal. The fully differential switched capacitor amplifier includes: a sampling capacitor that respectively samples the differential analog signal input from the differential input terminal; a differential input switch connected to a path for inputting the differential analog signal between the differential input terminal and the sampling capacitor; a fully differential amplifier that amplifies the differential analog signal input to the sampling capacitor; and a differential input resistor connected between the differential input switch and the sampling capacitor.

The invention discloses a zero-input current ripple wide-gain DC-DC converter and a control method, the zero-input current ripple wide-gain DC-DC converter comprises a zero-ripple boost unit and a voltage multiplication unit which are connected in sequence, and the zero-ripple boost unit comprises a first inductor, a second inductor, a third capacitor, a fourth capacitor, a first power switch and a third diode; the voltage multiplication unit comprises a first capacitor, a second capacitor, a first diode, a second diode, a third diode, a third inductor and a second power switch. By introducing the zero-ripple boost unit, the zero-input ripple characteristic is realized while the voltage gain is improved, and meanwhile, the voltage multiplication unit is introduced, so that the structure has a function similar to that of a switched capacitor and optimizes the energy circulation of the switched capacitor; therefore, the voltage gain of the converter is further improved, and the voltage and current stress of the semiconductor device is reduced.

The invention relates to the technical field of radio frequency integrated circuits, and discloses a low-noise voltage-controlled oscillator circuit which comprises a source electrode following low-noise bias circuit with digital calibration, a source electrode following low-noise bias circuit with digital calibration, a source electrode following low-noise bias circuit with digital calibration and a source electrode following low-noise bias circuit with digital calibration, the cross-coupled amplifier array is composed of a plurality of units, and the source electrode of the cross-coupled amplifier array suppresses low-frequency noise through a resistance-capacitance feedback network and receives a digital amplitude calibration signal so as to dynamically adjust the number of working units and stabilize the output amplitude; the amplitude self-calibration loop consists of digital logic and a peak detector; the switched capacitor unit array is provided with stable direct-current bias; and a wide linear variable capacitor array driven by the stepped bias voltage. Through deep fusion of digital and analog technologies, the phase noise is remarkably reduced, the linear tuning range is widened, the amplitude stability is ensured, the power consumption is reduced, and the method is particularly suitable for a high-performance radio frequency communication chip of the Internet of Things.

The invention relates to a convolution calculation unit and a sensor internal processing circuit, and the convolution calculation unit comprises a Gilbert multiplication circuit which is used for carrying out the voltage multiplication of a differential voltage of a processed image pixel value and a differential voltage of a weight of a convolution kernel; and the switched capacitor circuit is used for carrying out weighted calculation on the voltage multiplication result. The output bandwidth of the Gilbert multiplier is optimized on the basis of the Gilbert multiplier, the stability and the accuracy of the system are improved, the power consumption of the system can be further reduced by adopting the switched capacitor circuit to carry out weighting operation on the signal, the work and the turn-off of the system can be controlled by utilizing a time signal, and the power consumption of the system is reduced. And the system hardly consumes energy in a static state.

The invention discloses a load transient detection circuit of a COT Buck, a corresponding COT Buck and a switching power supply. The load transient detection circuit comprises an input end, three resistors connected in series, two comparators and a switched capacitor sampling hold circuit, wherein the input end is grounded after passing through the three resistors in sequence. A node between the input end and the first resistor and a node between the second resistor and the third resistor are connected to the input ends of the first comparator and the second comparator through a switched capacitor sampling hold circuit structure. Valley voltage information and peak voltage information of inductive current are obtained through the switched capacitor sampling hold circuit, whether a load is transiently changed or not is judged by comparing inductive current ripples with a valley value and a peak value, and it is guaranteed that the switching power supply has appropriate transient detection trigger threshold voltage under any load. According to an output signal of the load transient detection circuit, the COT Buck can increase the turn-on or turn-off time so as to enhance the transient response speed.

The invention provides a resistor resistance value high-precision measuring circuit. The resistor resistance value high-precision measuring circuit comprises a chip power supply end, a grounding end, a current mirror circuit, an operational amplifier circuit, a current starvation type oscillator circuit and a switched capacitor circuit, wherein the switched capacitor circuit is controlled by the output frequency of the current starvation type oscillator circuit and can be equivalent to a resistor with a resistance value related to the output frequency; an equivalent resistor and a to-be-measured resistor which is arranged outside the chip and is connected with the signal input port are driven by the current mirror image circuit, and two obtained voltages related to the to-be-measured resistor and the equivalent resistor are output to the operational amplifier circuit for comparison. According to the current hunger type oscillator circuit, accurate resistance value measurement can be achieved, the influence of non-idealities such as the working voltage, temperature drift and threshold drift of the high-precision resistance value measurement circuit on accurate measurement of the to-be-measured resistance value is small, and the circuit structure is simple.

The invention provides a novel high-gain DC-DC converter based on a photovoltaic panel and a DC bus, and relates to the technical field of power electronics and control thereof. Comprising an input stage of a conventional SEPIC converter; the boosting unit is composed of an impedance network and a switched capacitor network, the impedance network comprises external inductors connected in series and capacitors and diodes connected in series with the external inductors, and the impedance characteristic of the input side is adjusted through the combination of the capacitors, the diodes and the inductors; the switched capacitor network comprises a capacitor and a diode which are connected in series, and charge transfer and voltage multiplication are achieved through charging and discharging of the capacitor and unilateral conductivity of the diode. The load unit realizes voltage conversion and stable output through the synergistic effect of an impedance network and a switched capacitor network in the boost unit.

A three-phase wireless electric energy transmission device disclosed by the present invention comprises a three-phase inverter, a three-phase switch capacitor, a coil magnetic field coupling structure and a rectifier, the coil magnetic field coupling structure comprises a primary coil and a secondary coil which are arranged in mirror symmetry, the primary coil is provided with two layers, each layer comprises a three-phase coil, each phase coil occupies a 120-degree angle range of the circumference, and the rectifier is connected with the primary coil and the secondary coil. The two layers of coils form a staggered angle, each phase of switched capacitor of the three-phase switched capacitor comprises a first capacitor branch and a second capacitor branch which are arranged in parallel, the first capacitor branch is provided with a first capacitor, and the second capacitor branch comprises a second capacitor and a switch module which are arranged in series; the switch module adjusts the equivalent capacitance value of the second capacitor branch through the duty ratio and adjusts the transmission power of the three-phase wireless power transmission device. The invention further discloses a load power adjusting method of the three-phase wireless power transmission device, the transmission efficiency can be kept unchanged within the adjusting range, and soft switching can be achieved within the adjusting range.