1035 results about "Switched capacitor" patented technology

The invention discloses a frequency division control radio frequency power supply solid-state impedance matcher and a method thereof, and aims to solve the problems that a traditional mechanical impedance matcher is slow in response, low in adjustment precision and difficult to adapt to a dynamic load. According to the system, an all-solid-state impedance matcher is adopted, impedance dynamic adjustment is achieved through a matching network composed of an adjustable inductance module and a switched capacitor module, closed-loop control is constructed in combination with a radio frequency signal detection module and a digital signal processor, and a frequency division control strategy is adopted, and the high-frequency band realizes high-precision matching through a control strategy of coarse adjustment of the adjustable inductance module and fine adjustment of the switched capacitor module. The device has the advantages of high response speed, wide frequency band coverage and the like, and is particularly suitable for industrial plasma application scenes with remarkable dynamic impedance characteristics.

The present invention discloses a boost converter power stage circuit, comprising: an organic light-emitting diode power management integrated circuit unit, a switched capacitor converter, and a boost converter, wherein, a flying capacitor is used to boost the voltage of the inductor to twice the voltage, and then the positive voltage of the output voltage source is boosted, and then use the switched capacitor converter to output the voltage in order to obtain the conversion of the negative voltage.

A switched capacitor converter can include a switched capacitor stage comprising a flying capacitor and a ladder of three switching devices. A first switching device can be connected between a DC input of the switched capacitor converter and an AC bus. A second switching device is connected between the DC input and a third switching device. The third switching device can be connected between the second switching device and ground. The flying capacitor can be connected between the AC bus and a junction of the second switching device and the third switching device. The switched capacitor converter can further include an inverter stage having an input coupled to the AC bus and an output that delivers an AC voltage.

A system and method are used to maintain a variance in feedback factors of an amplifier between the first and second phases either below a threshold value or within a specified range. The system includes the amplifier and first through third capacitances. The amplifier is coupled between an input node and an output node that operates during first and second phases of operation. The first capacitance is coupled across the amplifier and between the input node and the output node during the first and second phases of operation. The second capacitance is coupled to the input node during the first phase of operation. The third capacitance is coupled to one of the input and output nodes during one or both of the first and second phases of operation.

The invention relates to the technical field of artificial intelligence, and discloses a charging pile operation state management method and system based on artificial intelligence, and the method comprises the steps: constructing a dual-input single-output DC-DC conversion control circuit structure based on an input power supply, a main power switching device, a three-winding coupling inductor and a switched capacitor unit; calculating a switch time sequence control signal based on a double-input single-output DC-DC conversion control circuit structure; detecting the running state of the charging pile to obtain a multi-dimensional quantized data set, and performing data coding to obtain a standard data information sequence; performing multi-dimensional feature value extraction and fault position identification on the standard data information sequence to obtain a fault positioning result; according to the fault positioning result and the switch time sequence control signal, closed-loop regulation control is carried out on the power device conduction time sequence and the clamping circuit parameters, stable direct-current output voltage is obtained, the voltage conversion efficiency is improved, the accuracy of fault recognition is improved, and the misjudgment rate is reduced.

The invention relates to a modular commutation type converter operation test system, which comprises an energy complementing device, a soft start circuit, a load reactor, a sampling device and a centralized control device, and is characterized in that the energy complementing device comprises a plurality of direct current output ends, and each direct current output end is correspondingly connected with a test object switch capacitor module, so that energy complementing is carried out on each test object switch capacitor module independently. Under the control of the centralized control device, the energy complementing device is combined with the soft start circuit, so that the test object switch capacitor module and the test object H-bridge valve string are subjected to soft start charging operation, various different working conditions of the modular commutation type converter can be simulated, and the operation test of the modular commutation type converter can be realized according to set test parameters and operation test parameters. Through the scheme, the twin-dragging experiment of the test object switch capacitor module and the test object H-bridge valve string in the modular reversing converter can be realized, so that the blank of the MCC operation test platform is filled, and the product design capability and quality of the MCC are improved.

A multiphase buck converter that includes smart two-phase power stages for reducing switching losses. Each of the smart power stages includes a first high side switch, a second high side switch, a first low side switch, a second low side switch, a switching capacitor, a first inductor, and a second inductor. The exemplary multiphase buck converter includes two such smart power stages and a multiphase controller for generating PWM signals for driving the two smart power stages synchronously.

A power supply circuit has a first node, a second node, a DC-DC converter that includes a switched capacitor, generates an output voltage based on an input voltage supplied from the first node, and outputs the output voltage from the second node, and a regulator that is connected in parallel to the DC-DC converter between the first node and the second node and controls an output current flowing to the second node based on a reference voltage lower than the input voltage.

The invention provides a wide-input-range voltage-adjustable resonant DC-DC converter, and the converter comprises a voltage adjusting stage which is connected with an input end, and is configured to work at a first frequency, and carries out the magnetizing and demagnetizing control of a power inductor in the voltage adjusting stage; the resonant switched capacitor topology circuit is connected to the tail end of the inductor in the voltage regulating stage, a high-low level switching node is formed at the joint, the switched capacitor topology circuit comprises a plurality of resonant tank units, and the plurality of resonant tank units work at a second resonant frequency; therefore, the voltage at the high-low level switching node is switched between the high-power value and the low-power value of the specific output voltage, and the soft switching of the switched capacitor topology circuit is realized.

An apparatus as discussed herein can be configured to include a first analog-to-digital converter operative to convert a first analog voltage into a first digital signal; a digital-to-analog converter operative to convert the first digital signal into a second analog voltage; a switched capacitor circuit coupled to the digital-to-analog converter, the switched capacitor circuit is operative to store a sample of the second analog voltage; and a second analog-to-digital converter operative to convert an analog error voltage into a second digital signal, the analog error voltage based on a difference between the sample of the second analog voltage received from the switched capacitor circuit and a sample of the first analog voltage.

The invention discloses a CMOS analog multiplier circuit, the circuit comprises a current-to-voltage circuit and a multiplier sub-circuit connected with the current-to-voltage circuit, an OSC circuit in the multiplier sub-circuit receives an input voltage VB and a reference voltage VREF and generates a two-phase non-overlapping clock signal group, a voltage-to-current A circuit converts a voltage VA into a current iA, and the current iA is connected with the OSC circuit. The switched capacitor integrating circuit inputs a sampling voltage to the voltage-to-current B circuit and integrates a difference current is of a current iA and a current iB to realize multiplication, the voltage-to-current B circuit converts a sampling voltage signal into the current iB, and the current-to-voltage circuit converts the current iB into an output voltage Vo as a multiplier operation result. Through combination of modular design, a current mode method and a switched capacitor method and high-precision current conversion and integration processes, an efficient and accurate multiplication simulation function is realized, a THD enhancement function is introduced through multiplexing design, and circuit performance is further optimized.

A switched capacitor converter includes an auxiliary circuit, a first branch and a second branch, the auxiliary circuit is connected between the first branch and the second branch, all power transistors of the first branch and the second branch are primary power transistors, and the auxiliary circuit transfers a charge or electric charges on one of the first branch and the second branch to another of the first branch and the second branch during a dead time when the primary power transistors are turned off, so as to the primary power transistors turn on at zero voltage and reduce a switching loss.

The embodiment of the invention provides a charging method, the method is applied to a first terminal device to charge a second terminal device, the first terminal device comprises a battery, a first switched capacitor circuit and a wired charging interface, and the first switched capacitor circuit is electrically connected between the battery and the wired charging interface. The wired charging interface is connected with the second terminal device through an OTG data line, and the method comprises the following steps: in response to a reverse charging mode of the first terminal device selected by a user, determining that the first terminal device is a main device for providing electric energy in OTG connection; and controlling the first switched capacitor circuit to increase a first output voltage of the battery to a second output voltage, and outputting the second output voltage to the wired charging interface so as to transmit the second output voltage to the second terminal device through the OTG data line. According to the charging method provided by the invention, the charging power of reverse charging can be improved, the efficiency of reverse charging is higher, and the problem of heating during reverse charging is reduced.

The invention relates to a three-winding coupling inductor bipolar output high-gain DC-DC converter, which is characterized in that a coupling inductor and switched capacitor boosting technology is introduced into a three-level Boost bipolar output converter, and bipolar output voltages Uo1 and Uo2 are controlled by adjusting the turn ratio of the coupling inductor and the duty ratio of a switch; and the input and output power is changed by adjusting the resistance value of the output load. The DC-DC converter is low in input current ripple, high in voltage gain and low in switching tube voltage stress, and bipolar output voltage can be flexibly adjusted through the duty ratio and the coupling inductor turn ratio.

A comparator-based switched-capacitor circuit has a first input terminal, a second input terminal, a first output terminal, and a second output terminal, and includes an analog-to-digital converter (ADC), a decoder, and a switch-capacitor network. The ADC is coupled to the first input terminal and the second input terminal and includes a plurality of comparators. The decoder is coupled to the ADC. The switch-capacitor network includes a comparator, a first current source, a second current source, a plurality of switches, and a plurality of capacitors. The first current source is coupled to the comparator and the first output terminal. The second current source is coupled to the comparator and the second output terminal. The voltage of the first output terminal and the voltage of the second output terminal do not exceed a target range.

The invention discloses a high-side series drive sodium battery protection method and system, and relates to the technical field of battery protection, and the method comprises the steps: collecting the data information of each monomer of a sodium battery pack through a sensor, and carrying out the preprocessing; judging based on the preprocessed data, and starting balancing operation; a PWM signal with a fixed frequency is generated to control the on and off of the MOSFET switch; and the duty ratio and the frequency of the PWM signal are adjusted in real time by monitoring the voltage fluctuation of the resonant capacitor. Through an active equalization mode of the switched capacitor, efficient equalization of voltage in the battery pack is realized, energy loss and heating are reduced, and the service life of the battery is prolonged. According to the invention, a high-side protection framework is adopted, so that the system can keep stable communication even when battery protection is triggered, and the overall safety and stability are improved; the system integrates a self-developed chip master control module and SOC calculation and fault diagnosis functions, can monitor the battery state in real time and perform intelligent management, and significantly improves the reliability and expansibility of the system.

A Hybrid Switched Capacitor Converter (HSCC) topology is presented that is suitable for high conversion ratio Point-of-Load (PoL) applications. The topology specifically targets 48V to 1V power delivery in space-based high-performance computing systems, where size and weight are important considerations, along with device de-rating for radiation tolerance. One implementation merges an initial 2:1 switched capacitor conversion stage with a symmetric dual inductor hybrid (SDIH) conversion stage, reaping benefits of both. The SDIH stage offers reduced component count and an excellent switch stress figure of merit, while the initial 2:1 voltage reduction stage significantly reduces the volume of flying capacitors, enabling compact size and low weight.

The invention provides a series-parallel switched capacitor converter. The series-parallel switched capacitor converter comprises a voltage source, a switch module, a plurality of charge transfer modules, voltage detection modules and a series switching module, wherein the voltage detection modules are in one-to-one correspondence with the charge transfer modules; the first output end of each charge transfer module is connected with the first input end of the voltage detection module, the second output end of the last charge transfer module is connected to the negative electrode of the voltage source, the second output end of each charge transfer module is connected to the second output end of the series switching module, and the control end of each charge transfer module is connected with the first output end of the series switching module; the second input end of each voltage detection module is connected to the positive electrode of the voltage source, and the output end is connected with the control end of the series switching module; the voltage detection module detects the voltage of the charge transfer module and generates a voltage detection signal; the series switching module switches the driving mode of the charge transfer module in the series energy storage state to a voltage driving mode or a current driving mode according to the voltage detection signal, thereby improving the charging stability.

The invention belongs to the technical field of power management, and particularly relates to a double-phase DC-DC topological structure with a current multiplier. The invention is characterized in that a current multiplier and a switched capacitor SC buck are embedded on the basis of the traditional multiphase buck, the inductive current and the RMS current of a buck power device are greatly reduced, the current stress is transferred to a charge pump structure of a low-voltage and low-FoM-value device, and the voltage stress is retained in a high-voltage device of the buck. And high conversion efficiency is realized through a strategy that the charge pump and the buck share current and voltage stress respectively. Meanwhile, due to the fact that the switched capacitor has extremely low output impedance, and the circuit is compatible with a loop control strategy of a traditional multi-phase buck, the transient response speed is also remarkably improved. The idea of the invention can be linearly expanded from typical two-phase buck to N-phase buck, so that the topological structure of the invention has universality.

The invention discloses a low-power-consumption small-area on-chip temperature sensor based on an MOS tube and a method thereof. Comprising a temperature sensing circuit and an analog-to-digital conversion circuit which are connected with each other, the temperature sensing circuit is used for generating a voltage signal related to the temperature and outputting the voltage signal to the analog-to-digital conversion circuit to achieve digital quantization of the temperature, and the output end of a CTAT branch is connected to the input end of a switched capacitor amplifier through a buffer. The output end of the switched capacitor amplifier is connected to the non-inverting input end of the comparator, the output end of the PTAT branch is connected to the inverting input end of the comparator, the output end of the comparator is connected with the input end of the successive approximation logic unit, and the output end of the successive approximation logic unit is connected to the switched capacitor amplifier. According to the temperature sensing circuit structure, the problem of power supply sensitivity existing when voltage is generated is effectively solved, reference signals do not need to be additionally generated in the quantization process, and the problem of error accumulation is avoided.

The invention discloses a low-noise and high-precision analog front-end circuit for biological signal acquisition. The low-noise and high-precision analog front-end circuit comprises a chopping capacitance coupling type instrument amplifier circuit, a switched capacitor type programmable gain amplifier circuit and a Sigma-Delta analog-to-digital converter modulator circuit. T-type capacitance feedback, chopping modulation and programmable technologies are introduced on the basis of an existing amplifier, and the low-noise and programmable gain functions of the pre-amplifier are achieved. Through the three-order one-bit quantized feed-forward chopping type Sigma-Delta modulator, the signal to noise ratio and the effective bit number of the signal are improved. Compared with the prior art, the analog front-end circuit not only has the capability of changing the gain multiple according to the bio-electricity signal, but also has the low-noise and high-precision signal processing effect, and the problems that a traditional analog front-end circuit is large in noise and low in signal processing precision are solved. In addition, the biological signal acquisition-oriented circuit provided by the invention can also be used in other analog front ends, such as an audio processor and the like, and is wide in application range.

The invention discloses an ultra-wideband circulator based on a periodic modulation topology circuit, and belongs to the technical field of microwave and radio frequency nonreciprocal circuits. The working bandwidth range of the circulator is widened, and non-reciprocal transmission is achieved through non-magnetic materials. A time sequence control unit is respectively connected with a Floquet topology circuit layer, a clock signal driving module, a reset signal driving module and a start signal driving module; the Floquet topology circuit layer is respectively connected with a first coupling port, a second coupling port and a third coupling port; the other ends of the first coupling port, the second coupling port, the third coupling port, the clock signal driving module, the reset signal driving module and the starting signal driving module are respectively grounded; the Floquet topology circuit layer adopts a six-layer parallel network structure, and each layer of network structure comprises a coupling capacitor and three N-type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) switches. The advantages of the switched capacitor structure are utilized, and the signal processing capacity which is high in integration level, small in size and capable of breaking through delay-bandwidth limitation is achieved.

According to an aspect, there is provided an all-digital phase-locked loop, ADPLL, for a radio receiver, transmitter or transceiver. The ADPLL comprises a time-to-digital converter for generating a digital time signal based on an external reference clock signal and a feedback signal, a switched capacitor digitally controlled oscillator, SC-DCO, for generating a radio frequency signal used as the feed-back signal, a phase-locked loop for controlling the SC-DCO based on the digital time signal for achieving a phase and frequency lock and digital processing means. The digital processing means are configured to maintain, in at least one memory, a lookup table defining a plurality of switching configurations of the SC-DCO corresponding to a plurality of frequencies of the radio frequency signal and to cause the phase-locked loop controller to adjust the switching configuration of the SC-DCO according to the lookup table.

A power amplifier includes a main switched capacitor power amplifier (SCPA), a peak SCPA, and a shunt inductor. The main SCPA is electrically coupled to a load. The peak SCPA is in parallel with the main SCPA and electrically coupled to the load. The shunt inductor is electrically coupled between the peak SCPA and the load.

A method for determining temperature of a chip, includes generating a first voltage and a second voltage using a pair of bipolar-junction transistors, and generating a third voltage using another bipolar-junction transistor. When a most recent bit of a bitstream is a logic-zero, the difference between the first and second voltages is sampled using a switched-capacitor input-sampling circuit, and a difference between the first and second voltages is integrated, to produce a proportional-to-absolute-temperature voltage. The proportional-to-absolute-temperature voltage is quantized to produce a next bit of the bitstream. When the most recent bit of the bitstream is a logic-one, the third voltage is sampled using the switched-capacitor input-sampling circuit, and the third voltage is integrated, to produce a complementary-to-absolute-temperature voltage. The complementary-to-absolute-temperature voltage is quantized to produce a next bit of the bitstream. The bitstream is filtered and decimated to produce an output code representative of the temperature of the chip.

A photovoltaic (PV) system may include a plurality of PV modules connected in series, each PV module of the plurality of PV modules being configured to harvest solar energy, and output the harvested solar energy as direct current (DC); at least one inverter connected to the plurality of PV modules, the at least one inverter configured to, receive the DC output by the plurality of PV modules, and convert the DC output into alternating current (AC); each PV module of the plurality of PV modules includes at least one capacitor configured to store the harvested solar energy; and processing circuitry configured to, monitor a charging voltage of the at least one capacitor, and control the DC output of the PV module based on the monitored charging voltage of the at least one capacitor.

A system for measuring parasitic capacitance coupling between adjacent first communication transmission line and second communication transmission line is disclosed. The system including: a parasitic tolerant capacitive based coupling measurement circuit (CBCM), the CBCM including: a capacitive auto-zeroing buffer configured to bias the second communication transmission line and displace coupling charge transferred from the first communication transmission line to a switched capacitor storage element; a capacitive trans-impedance amplifier configured to integrate displaced coupling charge onto an output voltage node; and a comparator configured to switch states once the capacitive trans-impedance amplifier integration has surpassed a reference trippoint.

The invention relates to a clock delay circuit for reducing interleaving distortion of a time interleaving pipeline ADC, and belongs to the field of analog-to-digital converters. Comprising a four-channel time-interleaved sampling switched capacitor array, an allowance amplifier module and four groups of delay control circuits, the four-channel time-interleaved sampling switched capacitor array comprises four sampling switched capacitor arrays which are connected in parallel; the four sampling switch capacitor arrays connected in parallel are all communicated with the allowance amplifier module; each group of delay control circuits is correspondingly connected with one sampling switch capacitor array; the delay control circuit comprises a clock generation circuit and a programmable current source array; the programmable current source array is connected with the clock generation circuit; the output end of the clock generation circuit is connected with the corresponding sampling switch capacitor array; according to the invention, the effect of reducing interleaving distortion in the four-channel time-interleaving pipeline analog-to-digital converter is realized, and the performance of the whole analog-to-digital converter is further improved.

The invention provides a switched capacitor converter circuit control time sequence method, device and equipment, a medium and a program product, and the method comprises the steps: disconnecting a switch connected to a power end and an output end during the conversion from series connection to parallel connection, and cutting off a current path between the power end and the output end; the flying capacitors are sequentially connected in parallel between the output end and the ground from the output end; when parallel connection is converted into series connection, a current path between the flying capacitors and the output end is cut off firstly, then the flying capacitors are sequentially connected in series from the power end, and finally the power end is closed to be connected with the series switch of the uppermost flying capacitor, so that a series access from the power end to the output end is formed. According to the invention, the damage risk of the power tubes in the switched capacitor converter and the voltage withstanding requirement of part of the power tubes are reduced, and the conversion efficiency is further improved.

The invention relates to a fully differential input dynamic latch comparator applied to a flash ADC (Analog to Digital Converter). The fully differential input dynamic latch comparator comprises a non-overlapping clock, a preamplifier, a dynamic latch comparator, an RS trigger and a switched capacitor module. The two-phase non-overlapping clock module is used for generating clocks clk1 and clk2 and respective early turn-off clocks clk1a and clk2a. And the pre-amplifier module is used for summing and amplifying the input differential signal and the reference voltage of the comparator. And the dynamic latch comparator module is used for comparing the output of the pre-amplifier to obtain a final result. The RS trigger is used for latching a comparison result for a half period, and the input end of the amplifier and the input end of the comparator are connected to the capacitor formed by the MOS tube to reduce kickback noise.