881results about "Oscillations generators" patented technology

An output drive circuit includes: a totem-pole output including: a high-side transistor (HST) with drain and source, an output stage power supply voltage applied to the drain, the source connected to the first node (N1); and a low-side transistor with source and drain, a ground voltage applied to the source, the drain connected to N1; and a bootstrap part including a capacitor supplying charge to a gate of HST when on, the charge being charged when HST is off, and one terminal of the bootstrap part connected to N1, the output drive circuit further including: a first transistor (T1) that conducts when HST is to be on, T1 connected between a drive circuit power supply voltage and the gate of HST; and a second transistor conducting when HST is to be turned on, the second transistor connected between the other terminal of the capacitor and HST gate.

A temperature control device includes a temperature detector, a difference operation unit, a controller, a saturation processing circuit unit, a rewritable storage unit, and a conversion unit. The difference operation unit operates a digital value corresponding to a difference value between a detected temperature value and a target temperature. The controller calculates a manipulated variable using the digital value operated by the difference operation unit. The saturation processing circuit unit includes a digital circuit to limit an output value of the controller to a pre-set upper limit value. The rewritable storage unit stores the upper limit value read from a storage area of the rewritable storage unit and input into the saturation processing circuit unit. The conversion unit converts the output value of the saturation processing circuit unit into an analog signal to output the converted value as a control command value to the heater.

The invention provides a design method and system of a high-speed RC clock system. The system comprises a high-speed RC oscillator, a reference clock module, a clock calibration module, a trigger module and a state machine module. The method comprises the following steps of: controlling a calibration process through a state machine module, counting a high-frequency clock signal by taking a theoretical count value as a reference after a clock calibration module is triggered, judging whether the frequency has deviation or not and the direction of the deviation according to a counting result, performing stepping adjustment on a calibration value, and performing frequency adjustment on a high-speed RC oscillator. And circularly executing the calibration step until the counting result falls into an allowable error range. A phase-locked loop circuit does not need to be additionally arranged, high and low temperature calibration in the production stage does not need to be introduced, the chip design complexity, the manufacturing cost and the production test cost can be effectively reduced, meanwhile, high precision and stability of clock signals are ensured, and output of a low-cost, high-frequency and high-precision RC clock is achieved.

An electronic device may include wireless circuitry having an oscillator. The oscillator can include a first transistor having a source-drain terminal coupled to a tail node, a second transistor having a source-drain terminal coupled to the tail node, a first coil having a first terminal coupled to the tail node and having a second terminal coupled to a power supply line, and a second coil inductively coupled to the first coil. The first and second coils can be part of a balun. The balun can be coupled to a tunable capacitance. The tunable capacitance can include multiple differential switchable capacitor circuits. The balun and the tunable capacitance can form a balun phase noise filter configured to reduce a phase noise associated with the oscillator.

Technologies directed to a frequency multiplier circuit of a customer terminal (CT) for doubling and tripling a frequency of a local oscillator are described. One communication device includes a local oscillator (LO) to generate a first differential signal having a first frequency and a frequency multiplier circuit to generate a second differential signal having a second frequency that is double the first frequency or a third differential signal having a third frequency that is triple the first frequency. The frequency multiplier circuit includes a variable capacitance circuit that is programmable to one of multiple capacitances and a variable inductance circuit that is programmed to a first inductance for the second differential signal and to a second inductance for the third differential signal.

The invention relates to the technical field of radio frequency integrated circuits, and discloses a low-noise voltage-controlled oscillator circuit which comprises a source electrode following low-noise bias circuit with digital calibration, a source electrode following low-noise bias circuit with digital calibration, a source electrode following low-noise bias circuit with digital calibration and a source electrode following low-noise bias circuit with digital calibration, the cross-coupled amplifier array is composed of a plurality of units, and the source electrode of the cross-coupled amplifier array suppresses low-frequency noise through a resistance-capacitance feedback network and receives a digital amplitude calibration signal so as to dynamically adjust the number of working units and stabilize the output amplitude; the amplitude self-calibration loop consists of digital logic and a peak detector; the switched capacitor unit array is provided with stable direct-current bias; and a wide linear variable capacitor array driven by the stepped bias voltage. Through deep fusion of digital and analog technologies, the phase noise is remarkably reduced, the linear tuning range is widened, the amplitude stability is ensured, the power consumption is reduced, and the method is particularly suitable for a high-performance radio frequency communication chip of the Internet of Things.

The invention discloses a low-cost precise time keeping method, system and device based on a gating circulation unit, and relates to the technical field of power grid measurement. The method is executed when the synchronous phasor measurement device cannot receive external signals, and comprises the following steps: monitoring operation parameters which influence the frequency stability of an internal crystal oscillator of the phasor measurement unit in real time; calculating a current frequency error of the crystal oscillator in real time by using a crystal oscillator frequency drift prediction model based on a gated cycle unit network based on the operation parameters; generating a time correction amount according to the current frequency error; and applying the time correction to a local clock of the phasor measurement unit to compensate the frequency drift of the crystal oscillator so as to realize accurate time keeping. According to the invention, through accurate prediction of crystal oscillator errors and lightweight software compensation, the synchronous phasor measurement device adopting a low-cost crystal oscillator can also realize long-time high-precision time keeping, the hardware cost is obviously reduced, and the reliability of power grid monitoring during the Beidou / GPS lock losing period is improved.

The invention relates to the technical field of radio frequency integrated circuits, and discloses a dynamic bias C-type voltage-controlled oscillator based on a CMOS (complementary metal oxide semiconductor) process, the voltage-controlled oscillator adopts a C-type structure, a cross-coupled network adds two resistors and a capacitor on the basis of a cross-coupled transistor, a circuit works in the C type by adjusting bias voltage at a resistor end, and the voltage-controlled oscillator works in the C type. The C-type voltage-controlled oscillator, a tail current source, a variable capacitance network, a switched capacitor array and a fixed LC resonance network form a core structure of the C-type voltage-controlled oscillator capable of numerical control tuning and voltage-controlled tuning, so as to determine the working frequency of the circuit and realize numerical control and voltage-controlled tuning functions; and the operational amplifiers with two bandwidth modes are introduced, so that the problem of difficult oscillation starting is solved, and the oscillation starting speed and the phase noise performance in a stable state are considered at the same time.

Piezoelectric materials, particularly ones with high quality factor used for mechanical antenna implementations, are sensitive to environmental conditions including temperature swings, humidity, vibration. Under the varying environmental conditions, the resonant frequency of the piezoelectric antenna can drift, and this results in the dampened piezoelectric radiator performance due to the mismatch between RF source' excitation frequency and piezoelectric antenna's resonant frequency. The frequency drift can be detrimental to the operation of the communication system that involves piezoelectric transmitter / receiver as a system component. In embodiments, the piezoelectric antennas may be integrated into a crystal oscillator to lock a drive frequency of the piezoelectric antennas to a resonant frequency of the piezoelectric antennas.

The invention belongs to the field of integrated circuits, and particularly relates to a high-Q-value quick-start crystal oscillator based on an MLP neural network. A neural network is used for replacing a complex phase synchronization hardware circuit in a traditional energy injection technology. Firstly, working state parameters of a crystal oscillator are collected in real time through a state collection module; then mapping the received real-time digital information into a corresponding output instruction through a trained MLP neural network model, and further controlling an energy injection module to inject an energy signal in the same phase as crystal oscillation; along with gradual increase of the oscillation amplitude, when the oscillation amplitude reaches a threshold value, the MLP neural network control model outputs an injection stopping instruction, switches the switch state, and submits the instruction to the negative resistance oscillation circuit to maintain steady-state oscillation and output a stable oscillation signal. According to the invention, the low complexity and high robustness are taken into account while quick starting is realized, and a solution is provided for the application of the high-Q-value crystal oscillator in a low-delay and low-power-consumption scene.

The invention discloses a voltage-controlled oscillator and a sub-sampling phase-locked loop, and relates to the technical field of phase-locked loops. The voltage-controlled oscillator comprises two negative resistance transistors and a three-layer coil structure; the three layers of coil structures are respectively a drain coil, a grid coil and a source coil from outside to inside; the gate coil and the drain coil are both of an octagonal structure, and the source coil is of a splayed structure; the drain coil, the source coil and the grid coil are all provided with center taps, the center tap of the source coil is connected with a power voltage module, the center tap of the drain coil is grounded, and the connection point of the center tap of the source coil and the power voltage module and the connection point of the center tap of the drain coil and the ground are located on the same side of the drain coil. And the two negative resistance transistors are positioned on the other side of the drain coil. According to the invention, automatic alignment of second harmonics in a wide frequency range is realized. And meanwhile, an extra chip area is not increased.

A frequency multiplier includes an oscillator and a harmonic generator. The oscillator has a resonant cavity and a negative resistance unit. The negative resistance unit includes a feedback capacitor and a parasitic capacitor. The feedback capacitor and the parasitic capacitor collectively provide negative resistance for the resonant cavity. The harmonic generator is configured to generate a harmonic signal based on a fundamental frequency signal taken as input. The oscillator is electrically connected to the harmonic generator, and is configured to receive the harmonic signal, and to output an intrinsic signal with the resonant cavity. A frequency of the intrinsic signal is a multiple of a frequency of the fundamental frequency signal.

The invention discloses a Colpitts voltage-controlled oscillator based on harmonic tuning, which comprises a differential driving module and a differential resonant cavity, and is characterized in that the differential driving module outputs a differential current signal and is used for providing a differential resonant current for the differential resonant cavity; the differential resonant cavity is used for converting an input differential current signal into a differential voltage signal, and the differential resonant cavity inputs the differential voltage signal into the differential driving module and provides a differential driving voltage for the differential driving module; wherein the differential resonant cavity has two differential-mode impedance peaks and one common-mode impedance peak, and the working frequency of the differential-mode impedance peak working at a high frequency band is increased to about two times based on a coupling effect among own inductors and a synergistic effect of frequency tuning and impedance matching; and meanwhile, the frequency corresponding to the common-mode impedance peak is one to three times of the frequency corresponding to the differential-mode impedance peak, so that the phase noise of the oscillator can be better suppressed, and more excellent comprehensive performance is realized under the condition of realizing higher working frequency.

Oscillator circuitry is provided that includes a pair of n-type transistors coupled to a first tail node, a pair of p-type transistors coupled to a second tail node, a first tail coil coupled to the first tail node, and a tunable magnetic coupling circuit magnetically coupled to the first tail coil. The oscillator can further include a load inductor, a load capacitor, a second tail coil coupled to the second tail node and magnetically coupled to the tunable magnetic coupling circuit, and a tunable capacitor having a first terminal coupled to the first tail node and having a second terminal coupled to the second tail node. The tunable magnetic coupling circuit can include a first coupling coil magnetically coupled to the first tail coil, a second coupling coil magnetically coupled to the second tail coil, and a programmable resistor coupled to the first and second coupling coils in a loop.

A clock integrated circuit (100) is provided. The clock integrated circuit includes: a first clock generator (110) which includes a crystal oscillator (XTAL) configured to generate a first clock signal (fxo); and a second clock generator (120) which includes a resistance-capacitance (RC) oscillator (121) and a first frequency divider (122), and is configured to: generate a second clock signal (fRTC)using the first frequency divider (122) based on a clock signal (fRCO) output from the RC oscillator (121); perform a first calibration operation for adjusting a frequency division ratio of the first frequency divider (122) to a first frequency division ratio based on the first clock signal (fxo) ; and perform a second calibration operation for adjusting the first frequency division ratio to a second frequency division ratio based on a sensed temperature.

Devices and methods may include receiving a square wave having a frequency at an input of a harmonic-cancellation (HC) sine-wave generator; receiving a clock signal having a clock frequency at a clock input of the HC sine-wave generator; generating one or more delayed square waves based on the received square wave and the clock signal using one or more delay components of the HC sine-wave generator; and amplitude-scaling the square wave and the one or more delayed square waves using a plurality of taps of the HC sine-wave generator to produce a plurality of amplitude-scaled square waves. The method may include adding the plurality of amplitude-scaled square waves using summing circuitry of the HC sine-wave generator to produce a sine wave having tone at the frequency with suppressed signal strength at selected harmonics of the frequency of the square wave at an output terminal of the HC sine-wave generator.

To provide a spin wave excitation detection structure that has a high strength structure, a high spin wave intensity that can be excited, and a wide frequency bandwidth of the spin wave that can be excited.SOLUTION: A spin wave excitation detection structure that excites and detects spin waves includes a support substrate, a conductive film provided on the support substrate, an insulating magnetic film provided on the conductor film, and a conductor wire provided on the insulating magnetic film.SELECTED DRAWING: Figure 1

In one example, an RF oscillator system includes a laser source configured to emit laser light, a housing, a crystalline microresonator disposed within the housing, and a photonic integrated circuit disposed within the housing, the photonic integrated circuit including an optical waveguide network and configured to generate a clock signal based on the laser light. The RF oscillator system may further include at least one photonic wirebond configured to couple the laser light between the optical waveguide network and the crystalline microresonator via evanescent coupling; laser control circuitry disposed within the housing and configured to lock a frequency of the laser light to a resonance of the microresonator to generate the clock signal; and a direct digital synthesizer disposed within the housing and configured to produce a tunable oscillator signal based on the clock signal.

Oscillator. The present invention provides an oscillator in which external heat is less likely to be transmitted to a vibrating element, and which has stable frequency characteristics. The oscillator has: an outer package; an inner package housed in the outer package and fixed to the outer package via a heat-insulating member; a vibrating element housed in the inner package; a temperature sensor; a first circuit element including an oscillation circuit that causes the vibrating element to oscillate and generates an oscillation signal that is temperature-compensated based on the temperature sensor, the first circuit element being housed in the inner package; and a second circuit element fixed to the outer package and including a frequency control circuit that controls the frequency of the oscillation signal.

A voltage-controlled oscillator (VCO) circuit is provided. The VCO includes: a first dual-core VCO including a first oscillator core and a second oscillator core; a second dual-core VCO including a third oscillator core and a fourth oscillator core, wherein the first and second dual-core VCOs are disposed side-by-side; first switches configured to connect or disconnect the first and second dual-core VCOs from each other; and second switches configured to connect or disconnect the first and second oscillator from each other, and to connect or disconnect the third and fourth oscillator cores from each other.

A phase shifter including: an upconversion mixer configured to receive a local oscillator (LO) signal having a LO frequency, and configured to receive and multiply a radio frequency (RF) input signal with the LO signal to produce a modulated signal having two sidebands around the LO frequency, an intermediate IF sideband having frequency below the LO and an image sideband; a filter connected to and configured to receive the modulated signal from the upconversion mixer and to attenuate a range of frequencies corresponding to the image sideband to select and output the intermediate frequency (IF) sideband signal; and a downconversion mixer configured to receive and multiply the IF sideband signal with a phase shifted LO signal to produce an output signal including a phase shifted version of the RF input signal.

This application provides a frequency multiplier, including an oscillator and a harmonic generator. The oscillator includes a resonant cavity and a negative resistance unit. The harmonic generator is configured to generate a harmonic signal based on an input fundamental frequency signal. The oscillator is electrically connected to the harmonic generator, and is configured to receive the harmonic signal, and output an intrinsic signal by using the resonant cavity. A frequency of the intrinsic signal is a multiple of a frequency of the fundamental frequency signal. The negative resistance unit includes a feedback capacitor and a parasitic capacitor. The feedback capacitor and the parasitic capacitor collectively provide negative resistance for the resonant cavity. This application further provides a wireless communication device. Therefore, according to the frequency multiplier and the wireless communication device provided in this application, energy efficiency of the frequency multiplier may be improved, thereby optimizing a balance between bandwidth, energy efficiency, and power consumption of the frequency multiplier.

The present invention relates to a radio transmitter (200) for operating a radio transmission system (100), preferably an SRD radio transmission system, between at least one radio transmitter (200), preferably between a plurality of radio transmitters (200), and a radio receiver (300) operating as a base station, wherein the respective radio transmitter (200) sends a telegram in the form of a data packet or a plurality of successively sent partial data packets to the radio receiver (300) at specific transmission times, each as a burst or bursts, wherein the respective radio transmitter (200) has a quartz crystal (201) which generates an oscillation for a timer, on the basis of which the timer determines the start and / or end times of the transmission of the respective burst, wherein the quartz crystal (201) is characterized by a quartz error profile (F1) which determines the original temperature dependence of the quartz error of the quartz crystal (201).To solve the problem of providing a radio transmitter that allows for the time-accurate transmission of telegrams even when its hardware does not enable alignment with the transmission frequency or carrier frequency of the radio signal, compensation means for the quartz error of the quartz crystal (201) are provided, which change, in particular shift, the quartz error curve (F1).

A circuit for reducing a temperature-induced frequency drift in a voltage to current (V2I) converter based voltage-controlled oscillator (VCO) for at least one wide band phase-locked loop (PLL), the circuit includes a V2I resistor node of the V2I converter, the V2I resistor node being at one end of a resistor, the VCO, and a current controlled oscillator (CCO), and the circuit is configured to provide a fixed offset current to the V2I resistor node to cause at least one V2I output current to have a value conversely proportional to absolute temperature (CTAT), the at least one V2I output current being output by the V2I converter, and mirror the at least one V2I output current to the CCO to reduce the temperature-induced frequency drift at a lower frequency band of the VCO.

A resonator including: a resonator plate having a thickness, and a surface having a maximum length and a width, wherein the resonator plate is a ZT-cut quartz, and a frame including a C-shaped portion having a first arm and a second arm extending at least partially about the lateral edges of the resonator plate and wherein each of the first arm and second arm is connected to the resonator plate by means of tethers.

A crystal oscillation chip including a casing and a crystal oscillation piece is provided. The crystal oscillation piece is disposed in the casing. The crystal oscillation piece includes a flat substrate, two electrodes and two conductive silver glues, the two electrodes are respectively disposed on two opposite main surfaces of the flat substrate. The flat substrate includes at least one notch. The notch is disposed at a side surface of the flat substrate and is recessed along a direction vertical from the side surface and toward an interior of the flat substrate. A height of the notch is the same as a thickness of the flat substrate, and two conductive silver glues connect the flat substrate and the casing.

This spin current magnetization rotational type magnetoresistive element includes a magnetoresistive effect element having a first ferromagnetic metal layer having a fixed magnetization orientation, a second ferromagnetic metal layer having a variable magnetization orientation, and a non-magnetic layer sandwiched between the first ferromagnetic metal layer and the second ferromagnetic metal layer, and spin-orbit torque wiring which extends in a direction that intersects the stacking direction of the magnetoresistive effect element, and is connected to the second ferromagnetic metal layer, wherein the electric current that flows through the magnetoresistive effect element and the electric current that flows through the spin-orbit torque wiring merge or are distributed in the portion where the magnetoresistive effect element and the spin-orbit torque wiring are connected.

The application discloses a quartz crystal oscillator base sealing method and belongs to the technical field of components and elements. The technical key point is that the upper cover and the base with a KV ring are sealed by a rolling electrode. The resistance of the upper cover is R1, the surface resistance of the KV ring of the base with the KV ring is R2, the resistances of the upper cover and the base on two sides are R5 and R6 respectively, and the maximum output power of the rolling electrode is P max . P max , R1, R5, R6 and R2 need to satisfy the following conditions: P max ·[1+R2 / (R5+R6)] ‑1 ·[1+(R5+R2+R6) / R1] ‑1 is greater than or equal to [P 热阈值 ]. [P 热阈值 ] represents the heat power threshold of the resistances of the upper cover and the base on two sides during the sealing of the rolling electrode. The technical scheme can improve the air tightness of the quartz crystal oscillator.

The invention relates to the field of integrated circuits, in particular to a K-band voltage-controlled oscillator based on a noise circulation structure, a phase-locked loop and a chip. The voltage-controlled oscillator comprises an oscillation circuit and a tuning circuit. The oscillating circuit comprises an upper resonant cavity formed by a basic oscillating circuit adopting a noise circulation structure and a lower resonant cavity formed by a noise suppression circuit adopting a Colpitts structure. The oscillating circuit adopts two groups of cross-coupled negative resistors, namely NMOS and PMOS, the cross-coupled negative resistors adopt a capacitance-coupled noise circulation structure, the PMOS adopts a Colpitts structure, and the cross-coupled negative resistors are connected through a tail inductor so as to improve phase noise and power consumption of the circuit. The tuning circuit adopts a variable capacitor which is connected to the oscillation circuit and is composed of a numerical control capacitor array and / or a self-adjusting capacitor circuit; and the capacitance value of the variable capacitor is adjusted to realize fine adjustment of the oscillation frequency. According to the invention, the problem that a traditional oscillator with a noise circulation structure is difficult to realize comprehensive optimization of phase noise and power consumption can be solved.

A bias circuit may generate one or more bias outputs for a crystal oscillator. The bias circuit may include a first current mirror, a second current mirror, and a third current mirror. A capacitor may be coupled between the second current mirror and the third current mirror. In operation, a first bias output may be generated by a third current mirror, and a second bias output may be generated by a second current mirror. The first bias output and the second bias output may be coupled to a crystal oscillator.