648results about "Multiple input and output pulse circuits" patented technology

An interface circuit includes a reference voltage generation circuit to generate a reference voltage, a differential voltage signal generation circuit to convert send data input in sending data into a pair of differential voltage signals and output the pair of differential voltage signals based on the reference voltage generated by the reference voltage generation circuit, a receiver to convert a pair of differential voltage signals input in receiving data and output received data, and a receiver test circuit to perform a sensitivity test of the receiver, the receiver test circuit having a resistance circuit to generate a pair of differential voltage signals having a potential difference being necessary for the sensitivity test of the receiver.

The disclosure relates to an electronic circuit to verify the integrity of a switch. The circuit comprises a voltage comparator and decoupling switch. The decoupling switch configured receive the driving signal having a first logic value to enable the monitoring of the comparison voltage and is configured to receive the monitoring enable signal having a first logic value to command the opening of the decoupling switch. The electronic circuit is configured to generate the output monitoring signal having a first logic value in an event that the switch is an open circuit and having a second logic value in an event that the switch is a short circuit.

The invention provides a wheel speed detection device and a chip system. The wheel speed detection device comprises a first comparator, a second comparator and a signal analyzer, the first comparator and the second comparator are respectively configured with different reference voltages, and the input end of the first comparator and the input end of the second comparator are used for receiving voltage signals generated by the same wheel speed sensor; and the signal analyzer is used for analyzing the wheel speed information according to the first comparison signal output by the first comparator and the second comparison signal output by the second comparator. Thus, the input signal is subjected to multi-threshold judgment by using a double-comparator structure, so that sensor signals of different current levels can be identified and analyzed uniformly, and compatible processing of sensor signals of multiple protocols is realized. Therefore, the problem that the overall system cost is increased due to hardware redundancy and system complexity increase in a traditional scheme is avoided, and the universality and the integration capacity of the interface module are effectively improved in a low-cost mode.

An integrated circuit includes a first multiplexer, a second multiplexing-input, a first clocked comparator, and a second clocked comparator. A first input node is connected to a first multiplexing-input of the first multiplexer, a first multiplexing-input of the second multiplexer, a first comparing-input of the first clocked comparator, and a first comparing-input of the second clocked comparator. A second input node is connected to a second multiplexing-input of the first multiplexer and a second multiplexing-input of the second multiplexer. An output of the first multiplexer is connected to second comparing-input of the first clocked comparator, and an output of the second multiplexer is connected to a second comparing-input of the second clocked comparator. The integrated circuit also includes an offset control circuit connected to a comparator-output of the first clocked comparator and a comparator-output of the second clocked comparator.

A latch comparator is disclosed. The latch comparator includes a first reservoir capacitor; a preamplifier including first and second transistors respectively connected to first and second inputs, the first and second transistors selectably connectable to a first terminal of the first reservoir capacitor, and third and fourth transistors respectively connected to the first and second inputs, the third and fourth transistors selectably connectable to a second terminal of the first reservoir capacitor; and a latch, including a first portion serially connected between the first and third transistors and connected to a first output, and a second portion serially connected between the second and fourth transistors and connected to a second output.

The invention relates to the technical field of interface circuits, in particular to a multi-mode switching detection circuit for a Type-C interface, which is used for realizing peripheral type identification and automatic switching between a USB host mode and a DP input mode on a single Type-C interface. The circuit comprises an interface detection unit connected with a Type-C female seat interface, a voltage comparison unit, a main control processor chip, a mode discrimination unit and a control output unit. The voltage comparison unit carries out resistance voltage division and threshold comparison on CC pin voltage, two levels are formed at a detection node and sent to the main control processor chip, and USB equipment and DP source equipment are distinguished by the mode judgment unit. The control output unit controls the USB host power supply control circuit and the DP input chip power supply circuit, establishes a USB data channel in a USB host mode, and establishes a DP-to-video channel in a DP input mode. The circuit realizes rapid peripheral identification and mode automatic switching based on hardware, and is simple in structure, low in cost, high in response speed and high in system stability.

The invention discloses a high-voltage positive and negative pulse detection circuit, which relates to the technical field of signal conditioning, and is characterized in that a voltage division circuit is responsible for attenuating input pulse signals, a switching diode is responsible for rectification and inputting positive and negative pulse signals into corresponding conditioning circuits respectively, and a charging circuit is responsible for maintaining pulse width characteristics of the signals; and the steepness of the signal edge is ensured by the comparator, and FPGA identification can be realized. Uncertain high-voltage pulse signals can be processed, and application scenes are diversified. The edge characteristic, pulse width and pulse direction of the pulse signal can be identified, and the signal processing capability is prominent.

The invention discloses a single-pin trimming circuit, which relates to the technical field of analog circuit design and comprises a comparator module, a first input end of the comparator module is connected to a single pin, a second input end of the comparator module is connected to a reference voltage, and the comparator module is used for comparing an input voltage of the single pin with the reference voltage and outputting a comparison signal; the input end of the time sequence decoding module is connected to the output end of the comparator module, and the time sequence decoding module is configured as follows: a, the logic state of a trimming position is judged according to the duration time of the pulse in the comparison signal; and b, addressing different trimming positions according to the number of pulses in the comparison signal, and further generating a multi-position trimming control signal through a series of pulse signals input by the single pin. Accurate control of a multi-bit fuse trimming circuit in a chip is realized by using single-pin resources.

The invention belongs to the technical field of integrated circuits, and particularly relates to a dynamic comparator suitable for a low-voltage high-speed analog-to-digital converter, the dynamic comparator adopts a three-stage latch circuit structure to realize rapid comparison of weak input signals so as to generate corresponding digital signals, and the method specifically comprises the following steps of: in a pre-amplification stage, pre-amplification is carried out; the positive feedback effect of the cross-coupled transistor pair is utilized to efficiently convert a tiny input voltage difference (lt; 10mV) into a recognizable voltage difference, and then through two-stage regeneration of the main latch module and the auxiliary latch module, a logic level is quickly output to complete quantization judgment. The auxiliary latch stage is additionally arranged on the basis of a traditional cross coupling latch circuit, the working speed of the comparator is effectively increased under the condition that only small area overhead is introduced, and the probability that the dynamic comparator has a metastable state is greatly reduced.

The invention relates to a trigger unit. The trigger unit comprises a first comparison feedback circuit, a first clock gating circuit, a master latch and a slave latch assembly, the first comparison feedback circuit is used for detecting a signal hopping state of an external input signal according to a first output signal output by the output end of the main latch, and generating a corresponding first state feedback signal, so that the first clock gating circuit generates a corresponding first gating clock signal according to the first state feedback signal and a reference clock signal, and sends the first gating clock signal to the second clock gating circuit; under the condition that the first gating clock signal is valid, the main latch is controlled to update the first output signal according to the external input signal; the state switching opportunity of the main latch can be accurately controlled, and unnecessary clock flipping in the trigger and transistor switching activity caused by the unnecessary clock flipping are effectively reduced, so that dynamic power consumption related to a clock network and dynamic power consumption generated by flipping of nodes in a data path are effectively reduced.

An input / output (I / O) sensor is provided for a multi-IC (Integrated Circuit) module. The I / O sensor includes: a signal input, configured to receive a data signal from an interconnected part of an IC of the multi-IC module; and a time duration measurement circuit, configured to measure a time duration between a first time, at which the data signal is at a first level, and a second time, at which the data signal is at a second level, different from the first level. The sensor may be incorporated into an I / O block, an IC, and / or a multi-IC module. An I / O sensor which includes a controller configured to measure duty cycle distortion of a multi-phase clock is also disclosed.

A comparator is disclosed. The comparator includes an amplifier circuit, a latch circuit, and a boost circuit. The amplifier is configured to amplify a difference between the first and second differential inputs during an active phase of the comparator. The latch circuit includes first and second transistors, respectively coupled to first and second differential amplifier outputs, and configured to respectively drive first and second legs of the latch circuit during the active phase. The boost circuit includes first and second boost transistors respectively coupled to the first and second differential amplifier outputs, and configured to respectively provide a first supplemental current to the first differential output of the latch circuit and a second supplemental current to the second differential output of the latch circuit.

The invention belongs to the technical field of digital-analog hybrid integrated circuits, and particularly relates to a high-precision low-power-consumption dynamic comparator circuit suitable for an SAR ADC (Synthetic Aperture Radar Analog to Digital Converter). The high-precision low-power-consumption dynamic comparator circuit is designed by adopting two-stage pre-amplification and a latch structure, a first-stage pre-amplification circuit A1 is a gain amplification stage, and a second-stage pre-amplification circuit A2 is a gain amplification stage; the effects of simplifying the circuit structure, reducing power consumption and eliminating kickback noise are achieved by adopting a dynamic operational amplifier of a cross-coupled load, the second-stage pre-amplification circuit A2 serves as an extra gain stage, an output signal from the first-stage pre-amplification circuit A1 can be quickly amplified by adopting a cross-coupled load structure, and the kickback noise is eliminated. The third-stage latch circuit A3 improves the speed of the comparator, the latch adopts a dynamic structure and is controlled by a dynamic clock, the latch does not work during resetting, and the static power consumption of the comparator is reduced.

The embodiment of the invention provides a hysteresis comparator circuit and a hysteresis comparator, the hysteresis comparator circuit comprises an open-loop operational amplifier circuit, the open-loop operational amplifier circuit is used for receiving a reference input and a comparison input, and determining a comparison output according to the reference input and the comparison input; the current feedback control circuit is connected with the open-loop operational amplifier circuit and used for controlling hysteresis current to be input to the open-loop operational amplifier circuit according to the comparison output, and the open-loop operational amplifier circuit feeds back and adjusts hysteresis voltage under the action of the hysteresis current; the bias voltage providing circuit is connected with the open-loop operational amplifier circuit and used for providing bias voltage for the open-loop operational amplifier circuit, and the bias voltage is used for controlling on-off of the open-loop operational amplifier circuit. The hysteresis comparator solves the technical problems that the hysteresis amount in the hysteresis comparator in the prior art is influenced by the power supply voltage and the hysteresis window is asymmetric.

The invention discloses a gain amplification circuit and a gain amplifier, and relates to the field of signal processing, the gain amplification circuit is characterized in that a sampling capacitor module in an integrator accesses a differential input signal, the sampling capacitor module is connected with an integrating capacitor module, the integrating capacitor module further accesses a differential output signal, and the sampling capacitor module is used for sampling the differential input signal; the integrating capacitor module is used for carrying out integration and amplification based on the differential input signal and the differential output signal obtained through sampling; the differential input end of the comparator is connected with the differential output end of the integrator, and the comparator is used for generating a differential output signal; the differential input end of the feedback network is connected with the differential output end of the comparator, and the differential output end of the feedback network is connected with the differential feedback end of the integrator. The gain amplification circuit multiplexes part of circuits in the integrator and is realized in a switched capacitor mode, so that quiescent current does not need to be independently provided for the gain amplification circuit, meanwhile, voltage sampling and amplification can be completed, and the overall circuit power consumption is reduced.

A comparator circuit includes a matching capacitor in series with a first switching device and a second switching device. The first and second switching devices are in parallel between the matching capacitor and a reference voltage. The comparator circuit further includes a sampling capacitor in series with a third switching device and a fourth switching device. The third switching device is in series between the sampling capacitor and a DAC, and the fourth switching device is in series between the sampling capacitor an input voltage. The comparator circuit further includes a comparator having an inverting input terminal and a non-inverting input terminal. The inverting input terminal is capacitively coupled to the matching capacitor and the non-inverting input terminal is capacitively coupled to the sampling capacitor. The comparator circuit further includes a fifth switching device and a sixth switching device in series between the matching capacitor and the sampling capacitor.

A clock selector circuit (1) comprises a first input for receiving a first input clock signal (CLK1) having a first frequency, and a second input for receiving a second input clock signal (CLK2) having a second frequency, the second frequency differing from the first frequency by a frequency offset. The clock selector circuit (1) further comprises a clock output for outputting an output clock signal (CLK_OUT), a phase difference detector (7) and switching circuitry (5, 6). The phase difference detector (7) is configured to detect when a phase difference, over time, between the first input clock signal (CLK1) and the second input clock signal (CLK2), determined using a predetermined type of clock edge, being either a rising edge or a falling edge, crosses zero, and to signal this zero crossing to the switching circuitry (5, 6). The switching circuitry (5, 6) is configured, in response to receiving a zero-crossing signal from the phase difference detector (7), to detect an edge of opposite type to the predetermined type in the first input clock signal (CLK1) or in the second input clock signal (CLK2), and, in response to detecting said edge of opposite type, to switch the output clock signal (CLK_OUT) between the first input clock signal (CLK1) and the second input clock signal (CLK2).

This invention discloses a rapid offset voltage calibration device for dynamic comparators, primarily addressing the problems of long calibration cycles and poor calibration accuracy in existing comparator offset calibration techniques. The device includes a comparator, a calibration voltage control circuit, a calibration control logic circuit, and a calibration input circuit. In calibration mode, the comparator outputs the comparison result. The calibration control logic circuit stores and processes the comparison result and outputs different control signals to the calibration voltage control circuit based on the number of consecutive comparisons. The calibration voltage control circuit adjusts the step size of the calibration voltage according to the different control signals and transmits this information to the calibration transistor in the calibration input circuit. The calibration transistor in the calibration input circuit rapidly calibrates the comparator's offset voltage to the convergence range as the calibration voltage changes. This invention dynamically adjusts the calibration step size, reduces the comparison and compensation cycle, and improves calibration speed while maintaining calibration accuracy. It can be used for calibrating dynamic comparators.

To provide a wireline receiver with improved timing and associated margins. [Solution] A wireline receiver comprising a data sampler sa0, a first edge sampler sa1, a second edge sampler sa2, a base phase detection circuit 222, an additional phase detection circuit 224, a clock circuit 240, and a phase shift circuit 250, wherein the data sampler, the first edge sampler, and the second edge sampler, when triggered by the data clock, the first edge clock, and the second edge clock, respectively, sample and compare the receiver signal to determine whether the receiver signal exceeds the data threshold level, the first threshold level, and the second threshold level, thereby providing a basis for phase detection. In response to phase detection, the clock circuit provides the first edge clock and the data clock, and the phase shift circuit provides the second edge clock by phase shift.

The invention discloses a low-noise low-power-consumption cascade input comparator which comprises a pre-amplification stage and a latch stage, the pre-amplification stage is used for amplifying a pair of differential signals input from the outside, the amplified differential signals are obtained and output to the latch stage, and the latch stage is used for latching the amplified differential signals. The latch stage is used for keeping a latch state and outputting a differential comparison result, the pre-amplification stage is used for inputting a pair of differential signals by arranging a three-stage cascade structure consisting of three pairs of input geminate transistors, and is used for preventing all connection nodes of the pre-amplification stage and the latch stage from being completely discharged to the ground by arranging a pair of cross coupling geminate transistors, so that charge storage is realized; the circuit has the advantages of low input reference noise, no consumption of a large amount of extra area and power consumption, small area and low power consumption.

The application provides a comparator and a decision feedback equalization circuit, comprising a first input circuit, which is used for generating a first differential signal according to an input signal and a first reference signal under the control of a control signal; a first positive feedback circuit, which is used for accelerating the difference between the first differential signal; a second input circuit, which is used for generating a second differential signal according to the input signal and a second reference signal under the control of the control signal; wherein the first reference signal is greater than the second reference signal; a second positive feedback circuit, which is used for accelerating the difference between the second differential signal; and an output circuit, which is connected with the output end of the first input circuit and is used for amplifying and latching the voltage signal of the output end of the first input circuit or the voltage signal of the output end of the second input circuit in a regeneration stage to output a comparison result. The response rate of the comparator in the application is high, the power consumption is small, the working voltage is low and the inter-symbol interference can be eliminated.

The invention discloses a continuous time current comparator capable of outputting maximum current and minimum current. The continuous time current comparator comprises eight groups of cascode current mirrors consisting of NMOS (N-channel Metal Oxide Semiconductor) transistors N1-N20 and PMOS (P-channel Metal Oxide Semiconductor) transistors P1-P8, the drain electrode of the PMOS tube P2 is connected with the drain electrode of the NMOS tube N5 and the drain electrode of the NMOS tube N7 at the same time, the drain electrode of the PMOS tube P6 is connected with the drain electrode of the NMOS tube N11 and the drain electrode of the NMOS tube N13 at the same time, and the drain electrode of the PMOS tube P8 is connected with the drain electrode of the NMOS tube N17; a to-be-compared current Ia is input from the drain electrode of the NMOS transistor N1, and a to-be-compared current Ib is input and then is divided into two paths which respectively flow to the drain electrode of the NMOS transistor N3 and the drain electrode of the NMOS transistor N9; the drain electrode of the NMOS tube N19 outputs the maximum current Imax, and the drain electrode of the NMOS tube N15 outputs the minimum current Imin. After currents Ia and Ib to be compared are input, the maximum current Imax and the minimum current Imin corresponding to the currents Ia and Ib are output through current copying, summation and difference operation of the cascode current mirror, and the maximum current Imax and the minimum current Imin are both continuous analog current signals.

An integrated circuit (100A) includes an H-bridge circuit (102) having a first output node (OUT1) for coupling to the high-side terminal of an inductor (103) and a second output node (OUT2) for coupling to the low-side terminal of the inductor. A current-sensing FET (SNS-DRV) is coupled between a current source (110) and a lower supply voltage to provide a reference current (Itrip), including a peak current limit at the sensing node. A current-sensing comparator (104) has a first input coupled to the sensing node, a second input coupled to the second output node, and an output (113) coupled to send an output signal to a driver control circuit. A FET linearity detection circuit (112) is coupled to receive the gate voltage (LS2) of an active low-side power FET (Mls2) and has an output (CMP EN) coupled to enable the current-sensing comparator when the active low-side power FET operates in the linear region.

This invention relates to the field of integrated circuit technology and discloses a three-stage positive feedback comparator circuit and electronic device based on fast timing. The circuit includes a first-stage positive feedback module, a second-stage triggering and clocking module, a second-stage positive feedback amplification module, and a third-stage positive feedback latching module. By employing a three-stage positive feedback structure, this invention places the corresponding differential signal nodes in the same feedback loop at each stage, significantly enhancing the comparator's amplification rate and metastability suppression capability. Furthermore, by introducing a fast timing control mechanism, the second-stage amplification, clock reset generation, and third-stage latching operations can be executed in parallel, effectively shortening the critical path delay and significantly improving the overall comparison speed. The electronic device includes the aforementioned comparator circuit. This invention effectively solves the bottlenecks of traditional comparators in terms of speed and reliability and is suitable for high-speed, high-precision data conversion systems.

The invention discloses an integrated circuit and a method for operating the integrated circuit. The integrated circuit comprises a first multiplexer, a second multiplexing input, a first time control comparator and a second time control comparator. The first input node is connected to a first multiplexing input of the first multiplexer, a first multiplexing input of the second multiplexer, a first comparison input of the first time control comparator and a first comparison input of the second time control comparator. The second input node is connected to a second multiplexing input of the first multiplexer and a second multiplexing input of the second multiplexer. The output of the first multiplexer is connected to the second comparison input of the first time control comparator, and the output of the second multiplexer is connected to the second comparison input of the second time control comparator. The integrated circuit also includes an offset control circuit connected to a comparator output of the first clocked comparator and a comparator output of the second clocked comparator.

The invention discloses an LVDS (Low Voltage Differential Signaling) receiving circuit with a wide common-mode input range. The LVDS receiving circuit comprises a common-mode conversion circuit, a main comparator circuit, a secondary comparison circuit and a logical judgment circuit, the common-mode conversion circuit is used for converting an external wide common-mode input differential signal into a signal with constant common-mode voltage and no attenuation of the differential signal; the main comparator circuit identifies the converted differential signal to complete differential-to-single-ended data conversion; the secondary comparator circuit is composed of two low-speed comparators; and the logic judgment circuit judges the output of the main comparator and the window comparator to ensure that the output of the input end of the circuit group is a constant level under the short circuit and disconnection conditions, so that the function of dynamic failure protection of the circuit is realized. The wide common-mode input circuit can realize discrimination of wide common-mode input signals ranging from-4V to 5V, and has a dynamic failure protection function.

A comparator-based switched-capacitor circuit (SC circuit) has a first output terminal and a second output terminal, which output a first output signal and a second output signal, respectively. The comparator-based SC circuit includes a switch-capacitor network, a first current source, a second current source, and a compensation circuit. The first current source is coupled to the switch-capacitor network and the first output terminal. The second current source is coupled to the switch-capacitor network and the second output terminal. The compensation circuit is coupled to the first output terminal and the second output terminal and configured to generate a first and second voltage differences corresponding respectively to the first and second output signals and apply the first and second voltage differences to the second and first output terminals, respectively.

Provided are a control circuit, a semiconductor memory device, and a control method thereof that are capable of efficiently estimating the amount of delay between a first signal and a second signal and generating an output signal according to the amount of delay. [Solution] The control circuit 30 comprises a delay line section 31 to which a start signal start_tdc is input, the delay line section including a plurality of delay units U1 to U8 connected in series; a detection section 32 to which an end signal end_tdc is input, the detection section detecting, when an end signal is input after the start signal is input to the delay line section, the number of delay units among the plurality of delay units through which the start signal has passed before the end signal is input; and a control section 33 that controls the transmission path of the start signal in the delay line section so that the number of delay units through which the start signal has passed before the start signal is output from the delay line section is equal to the number of delay units detected by the detection section.

This application relates to a daisy chain clock distribution system and discloses a circuit (100a) comprising a first power converter (108a) having a first voltage input (110a) and a first output (116a or 117a). The circuit (100a) further comprises a second power converter (108b) having a second voltage input (110b) coupled to the first voltage input (110a), a clock input (112b), and a second output (116b or 117b). A phase shifter (118b) is coupled between the first output (116a or 117a) and the clock input (112b) of the second power converter (108b).

Systems and methods for data transmission are disclosed. The system can include a phase test circuit including a difference detection circuit, a low pass filter circuit, and a reference comparison circuit. The difference detection circuit can be configured to produce an output signal having a duty cycle corresponding to a phase difference between a first input signal and a second input signal. The low pass filter circuit can be connected to an output of the difference detection circuit, and the reference comparison circuit can be configured to compare an output signal of the low pass filter circuit to a threshold.