1519results about "Multiple input and output pulse circuits" patented technology

An interface circuit includes a reference voltage generation circuit to generate a reference voltage, a differential voltage signal generation circuit to convert send data input in sending data into a pair of differential voltage signals and output the pair of differential voltage signals based on the reference voltage generated by the reference voltage generation circuit, a receiver to convert a pair of differential voltage signals input in receiving data and output received data, and a receiver test circuit to perform a sensitivity test of the receiver, the receiver test circuit having a resistance circuit to generate a pair of differential voltage signals having a potential difference being necessary for the sensitivity test of the receiver.

A clock generation apparatus includes a counter configured to count transitions in a locally generated clock signal when a data signal is received from a 1-wire serial bus, a latch configured to capture an output of the counter and to provide a latched output representative of the transitions counted in the locally generated clock signal while a synchronization pattern is received in the data signal, a flipflop and a comparator configured to drive a decision signal to a first signaling state when the output of the counter matches the latched output and to drive the decision signal to a second signaling state when the output of the counter does not match the latched output. The flipflop has an output that changes signaling state in response to an edge in the decision signal. The counter is reset when the decision signal is driven to the first signaling state.

An injection-locked oscillator includes a plurality of delay elements, two or more voltage control circuits, a phase comparator and a controller. The plurality of delay elements is connected in a loop and coupled to a global power supply. Each delay element has an input driven by a preceding stage and an output that drives a next stage. Each voltage control circuit couples one of the plurality of delay elements to the global power supply. The phase comparator is coupled to in-phase and quadrature outputs of the injection-locked oscillator. The controller is coupled to an output of the phase comparator and is configured to drive control inputs of the two or more voltage control circuits. The control input of each voltage control circuit determines a level of a voltage drop across the each voltage control circuit.

The invention relates to a PCB over-temperature protection device, method and equipment, and relates to the technical field of servers, the device comprises at least one control circuit and a complex programmable logic device CPLD, and the control circuit comprises a thermistor and at least one voltage comparator; the thermistor is arranged in a monitoring area of a printed circuit board (PCB) and is used for converting the temperature of the monitoring area into a target voltage signal; the forward input end of the voltage comparator receives a target voltage signal, the reverse input end of the voltage comparator receives a reference voltage signal corresponding to the voltage comparator, and the voltage comparator is used for outputting a high level when the target voltage signal is higher than the reference voltage signal; the CPLD comprises a plurality of input pins respectively corresponding to the voltage comparators, each input pin is electrically connected with the output end of the corresponding voltage comparator, and the CPLD is used for triggering over-temperature protection operation corresponding to the input pin when the high level is received through the input pin, so that the timeliness of PCB over-temperature protection is improved.

Provided are a display drive circuit and a display device capable of curbing fluctuation of a signal line voltage. A display drive circuit includes a ramp wave voltage generation circuit that generates a ramp wave voltage whose voltage level changes with time, and a signal line voltage generation circuit that holds the voltage level of the ramp wave voltage at a timing corresponding to a signal level of a pixel signal and generates a signal line voltage. The ramp wave voltage generation circuit includes an amplifier that outputs the ramp wave voltage, a load circuit arranged on a feedback path of the amplifier, and a current generation circuit that controls a current flowing through the load circuit such that the ramp wave voltage matches a reference voltage.

A clock monitor circuit detects departures from expected values for clock period, clock high time duration, or clock low time duration. A delay line of the clock monitor circuit is composed of delay portions of delay cells. Each delay cell also has a comparator portion with logic to compare aspects of the monitored clock signal to corresponding expected values, and to output a failure detection signal indicating whether the expected values are met. Expected values may be read from a fuse set. The delay of the delay line may be programmatically adjusted. The clock monitor circuit may be combined with a circuit that detects narrow glitches in the monitored clock signal. Devices and systems with one or more monitored clock signals, and methods of clock signal monitoring, are also described.

A readout circuit includes a comparator having a first input coupled to receive a ramp signal from a ramp generator and a second input coupled to receive an analog image data signal from one of a plurality of bitlines. The comparator is configured to generate a comparator output in response to a comparison of the ramp signal and the analog image data signal. A sampling circuit has a first input coupled to receive a sampling control signal and a second input coupled to receive the comparator output. The sampling circuit is configured to generate a sampling output. A counter has a first input coupled to receive a counter control signal and a second input coupled to receive one of the comparator output and a signal from the sampling circuit. The readout circuit is configured to perform correlated multiple sampling (CMS) calculations or non-CMS calculations in response to the sampling output.

The disclosure relates to an electronic circuit to verify the integrity of a switch. The circuit comprises a voltage comparator and decoupling switch. The decoupling switch configured receive the driving signal having a first logic value to enable the monitoring of the comparison voltage and is configured to receive the monitoring enable signal having a first logic value to command the opening of the decoupling switch. The electronic circuit is configured to generate the output monitoring signal having a first logic value in an event that the switch is an open circuit and having a second logic value in an event that the switch is a short circuit.

The invention belongs to the field of analog integrated circuit design and integrated systems, and particularly relates to a programmable dead time control circuit for a high-voltage half-bridge driver. Comprising a dead zone time selection circuit (100), a multi-selection mode circuit module and a dead zone logic control circuit (105) which are connected in sequence, and the multi-selection mode circuit module comprises an overlapped input mode circuit (101), an equal ratio input mode circuit (102), a fixed mode input circuit (103) and a dead zone forbidden mode circuit (104) which are connected in parallel. According to the invention, the control of four kinds of dead time can be completed on one driving circuit, so that the circuit can freely control the magnitude of the output dead time without other external structures.

The invention discloses a CMOS analog multiplier circuit, the circuit comprises a current-to-voltage circuit and a multiplier sub-circuit connected with the current-to-voltage circuit, an OSC circuit in the multiplier sub-circuit receives an input voltage VB and a reference voltage VREF and generates a two-phase non-overlapping clock signal group, a voltage-to-current A circuit converts a voltage VA into a current iA, and the current iA is connected with the OSC circuit. The switched capacitor integrating circuit inputs a sampling voltage to the voltage-to-current B circuit and integrates a difference current is of a current iA and a current iB to realize multiplication, the voltage-to-current B circuit converts a sampling voltage signal into the current iB, and the current-to-voltage circuit converts the current iB into an output voltage Vo as a multiplier operation result. Through combination of modular design, a current mode method and a switched capacitor method and high-precision current conversion and integration processes, an efficient and accurate multiplication simulation function is realized, a THD enhancement function is introduced through multiplexing design, and circuit performance is further optimized.

A class D amplifier circuit receives an analog audio signal with a first reference voltage as its center level, and outputs an output pulse signal having a duty cycle that corresponds to the analog audio signal. A bias circuit generates a second reference voltage having a voltage level obtained as a division of the first reference voltage and the power supply voltage. A periodic voltage generating circuit of the class D amplifier circuit generates a periodic voltage having a triangle waveform or otherwise a sawtooth waveform having an amplitude that corresponds to the second reference voltage.

The present disclosure provides an alternating current (AC) / direct current (DC) voltage detection circuit, which includes a rising edge trigger circuit and a detection and output circuit connected to an output terminal of the rising edge trigger circuit. When the operating voltage is higher than the preset voltage, the determination circuit activates the detection and output circuit to detect the change of the operating voltage and the target flip.

Comparator circuitry for power converters. In an example, a circuit includes a comparator having a first comparator input, a second comparator input, and a comparator output, the comparator coupled to a supply terminal. The circuit further includes a first transistor coupled between a boot terminal and the first comparator input and having a control terminal coupled to a switching terminal, and a second transistor coupled between the boot terminal and the second comparator input and having a control terminal coupled to the switching terminal. Also, a third transistor is coupled between the supply terminal and the second comparator input, and a voltage reference generator is coupled to the supply terminal and to a control terminal of the third transistor.

The invention provides a wheel speed detection device and a chip system. The wheel speed detection device comprises a first comparator, a second comparator and a signal analyzer, the first comparator and the second comparator are respectively configured with different reference voltages, and the input end of the first comparator and the input end of the second comparator are used for receiving voltage signals generated by the same wheel speed sensor; and the signal analyzer is used for analyzing the wheel speed information according to the first comparison signal output by the first comparator and the second comparison signal output by the second comparator. Thus, the input signal is subjected to multi-threshold judgment by using a double-comparator structure, so that sensor signals of different current levels can be identified and analyzed uniformly, and compatible processing of sensor signals of multiple protocols is realized. Therefore, the problem that the overall system cost is increased due to hardware redundancy and system complexity increase in a traditional scheme is avoided, and the universality and the integration capacity of the interface module are effectively improved in a low-cost mode.

Flash analog to digital converters and other types of integrated circuits having multiple comparators may employ calibration methods and firmware to efficiently compensate the various offset voltages of the multiple comparators. One illustrative integrated circuit includes: multiple comparators each configured to provide a comparator output signal indicating whether an input signal exceeds a reference voltage by more than an offset voltage, the multiple comparators including a current comparator and a previous comparator; and a controller configured to perform a search to select a calibration setting for each of the comparators in turn, the controller determining an initial search window for the current comparator based on a calibration setting selected for the previous comparator.

The embodiment of the invention discloses a comparison circuit, a decision feedback equalizer and a communication interface, the comparison circuit comprises a first-stage comparator and a second-stage comparator, the first-stage comparator carries out comparison sampling on an input signal and a reference signal, obtains and amplifies a potential difference between the input signal and the reference signal, and outputs the potential difference between the input signal and the reference signal; and the secondary comparator receives the pre-amplified potential difference and performs secondary comparison sampling on the pre-amplified potential difference to obtain a target signal. Therefore, according to the comparison circuit provided by the embodiment of the invention, the first-stage comparator can work at a relatively low conversion rate through a biphase sampling principle, the comparison efficiency of the second-stage comparator is improved through pre-amplification of the first-stage comparator, and meanwhile, physical separation of input and output of the comparison circuit is realized; according to the embodiment, direct coupling paths between input and output are reduced, input end interference caused by output changes is reduced, meanwhile, biphase sampling is based on discrete time type sampling, the bandwidth and gain requirements are reduced, and eye pattern distortion is avoided.

Load disconnect techniques for boost converters. In an example, a power converter includes a driver circuit, a control circuit, and a comparator circuit. During normal boost operation (VIN<VOUT), the comparator circuit disables the control circuit and enables the driver circuit, which in turn fully turns on a high-side switching element during high-side on-phase. In contrast, during start-up operation or an output short-to-ground condition (VIN≥VOUT), the comparator circuit disables the driver circuit and enables the control circuit, which in turn controls the gate voltage of the high-side switching element, so the current through the switching element is regulated, and the switching node voltage is regulated to about a threshold voltage higher than VIN. In this manner, the comparator circuit controls the driver circuit and the control circuit, which in turn allow the boost converter to operate in a normal fashion even when VIN is higher than VOUT.

The invention discloses a hysteresis comparator circuit capable of externally setting a threshold value, which comprises an input voltage ui, a positive and negative threshold voltage preset circuit, comparators A1, A2 and A3 and an A3 in-phase end voltage bias circuit, an output voltage uo, + / -Vcc and + Vcc are connected with-Vcc through a resistor R1, potentiometers P1 and P2 which are connected in parallel, a resistor R2 and form the positive and negative threshold voltage preset circuit, the sliding end of P1 is connected with the anti-phase end of A1, and the sliding end of P2 is connected with the anti-phase end of A3. The sliding end of the P2 is connected with the anti-phase end of the A2, the voltage ui is connected with the in-phase ends of the operational amplifier A1 and the operational amplifier A2 at the same time, the output end of the A1 is connected with the in-phase end of the operational amplifier A3 through the R3, the output end of the operational amplifier A2 is connected with the in-phase input end of the operational amplifier A3 through the resistor R4, the anti-phase input end of the operational amplifier A3 is connected with the working ground, and the output end of the operational amplifier A3 is connected with the in-phase input end of the operational amplifier A3 through the resistor R5. And the output end of the operational amplifier A3 outputs the output voltage uo.

The invention discloses a high-voltage power supply high-selection circuit and a control method thereof, the high-voltage power supply high-selection circuit comprises a floating power supply generation circuit, a high-voltage floating comparator circuit, inverters INV1-INV4, a high-voltage PMOS tube PDM5 and a high-voltage PMOS tube PDM6, the floating power supply generation circuit generates a floating high voltage HVDD and a floating low voltage HVSS, two inputs of the high-voltage floating comparator circuit are respectively connected with input signals V1 and V2, and the high-voltage floating comparator circuit is connected with the high-voltage PMOS tube PDM5 and the high-voltage PMOS tube PDM6. The inverters INV1-INV4 generate two inverted signals A and B according to an output signal of the high-voltage floating comparator circuit, a high-voltage power supply end of the high-voltage floating comparator circuit, a source electrode of the high-voltage PMOS tube PDM5 and a source electrode of the high-voltage PMOS tube PDM6D are connected with a floating high voltage HVDD, and a low-voltage power supply end of the high-voltage floating comparator circuit is connected with a floating low voltage HVSS. According to the invention, the high-voltage power supply high-selection circuit is realized.

An integrated circuit includes a first multiplexer, a second multiplexing-input, a first clocked comparator, and a second clocked comparator. A first input node is connected to a first multiplexing-input of the first multiplexer, a first multiplexing-input of the second multiplexer, a first comparing-input of the first clocked comparator, and a first comparing-input of the second clocked comparator. A second input node is connected to a second multiplexing-input of the first multiplexer and a second multiplexing-input of the second multiplexer. An output of the first multiplexer is connected to second comparing-input of the first clocked comparator, and an output of the second multiplexer is connected to a second comparing-input of the second clocked comparator. The integrated circuit also includes an offset control circuit connected to a comparator-output of the first clocked comparator and a comparator-output of the second clocked comparator.

A ripple voltage detector circuit comprises a pulse generator, a direct current-to-direct current (DC-DC) converter coupled to the pulse generator, and a first control loop coupled to the pulse generator and the DC-DC converter. The first control loop is configured to measure an output voltage of the DC-DC converter, determine an output ripple voltage of the output voltage, determine a ripple coefficient based on the output ripple voltage, determine a reference peak inductor current based on the ripple coefficient, and determine a peak value of an inductor current during a switching cycle, and transition a switching state of the DC-DC converter based on the reference peak inductor current and the peak value of the inductor current.

A multi-phase clock signal generating circuit, configured to generate a plurality of output clock signals with different phases, comprising: a charge pump, configured to generate a control voltage according to a reference clock signal and a target clock signal; a delay circuit, comprising a delay chain with a plurality of delay units, configured to generate a plurality of candidate clock signals and the target clock signal according to the control voltage; and a phase selecting circuit, configured to select at least two of the candidate clock signals as the output signals.

A latch comparator is disclosed. The latch comparator includes a first reservoir capacitor; a preamplifier including first and second transistors respectively connected to first and second inputs, the first and second transistors selectably connectable to a first terminal of the first reservoir capacitor, and third and fourth transistors respectively connected to the first and second inputs, the third and fourth transistors selectably connectable to a second terminal of the first reservoir capacitor; and a latch, including a first portion serially connected between the first and third transistors and connected to a first output, and a second portion serially connected between the second and fourth transistors and connected to a second output.

A circuit for detecting metastability in an asynchronous successive approximation register analog-to-digital converter; wherein the dual output comparator is arranged to receive a first input signal and a second input signal, compare the first input signal with the second input signal, and drive one of the first comparison signal and the second comparison signal to a set state based on the comparison. When the first comparison signal is in the set state, the first output end is in the set state. When the second comparison signal is in the set state, the second output end is in the set state. If a predetermined duration elapses after the dual output comparator starts comparison, and if both the first comparison signal and the second comparison signal are in a reset state, the control logic outputs a set state at both the first output and the second output. This allows the metastability of the comparator to be detected in the asynchronous SAR ADC. The control logic may effectively terminate the comparison if a predetermined duration is reached. In other words, the control logic may overwrite the comparator output to provide a defined output indicative of metastability.

The invention discloses an oscillation circuit. The oscillating circuit comprises a charging and discharging module, an energy storage module, a self-zeroing comparison module and an output module; the self-return-to-zero comparison module comprises a storage unit and an output unit; the charging and discharging module is connected with the energy storage module, and the charging and discharging module is used for charging and discharging the energy storage module according to the power supply voltage, so that the energy storage module outputs a triangular wave signal; the storage unit is connected with a first threshold voltage, a second threshold voltage and an offset voltage of the output unit, and the output unit is used for outputting a comparison signal based on a comparison result of the triangular wave signal and the first threshold voltage when the feedback voltage is at a second level and outputting a comparison signal based on a comparison result of the triangular wave signal and the first threshold voltage when the feedback voltage is at a first level. Outputting a comparison signal based on a comparison result of the triangular wave signal and the second threshold voltage; and the output module is connected with the self-return-to-zero comparison module, the feedback voltage is accessed to the output module, and the output module is used for outputting an oscillation signal according to the comparison signal and the feedback voltage. According to the technical scheme, the reliability and the stability of the oscillation circuit are improved.

An electronic device includes a first sample circuit configured to generate a first sampling signal by sampling an input signal in response to edges of a clock signal, a first comparator configured to generate a first logic decision signal by comparing a voltage level of the first sampling signal with a reference voltage level, an analog bang-bang phase detector configured to generate a first detection signal by executing an exclusive OR (XOR) operation on successive samples of the first logic decision signal, and a digitally controlled oscillator configured to vary a frequency of the clock signal according to the first detection signal.

The invention discloses a direct-current solid-state circuit breaker with a voltage limiting protection circuit and a control method thereof. The direct-current solid-state circuit breaker comprises a solid-state switch module, the solid-state switch module comprises a first sub-module and a second sub-module which are the same, and each of the first sub-module and the second sub-module comprises a SiC JFET device J, capacitors C, Cgd and Cgs, a comparator U, an MOSFET device Q, a resistor Rg and resistors ra and rb; the first end of Rg is used for receiving a driving signal, and the second end of Rg is connected to the grid electrode of J after being connected with the first end of C, the second end of Cgd and the first end of Cgs; the second end of ra and the first end of rb are connected as a comparison voltage sampling point; the first end of ra is connected to the first end of Cgd and the drain electrode of J; the second end of the rb is connected to the second end of the Cgs, the source electrode of the Q and the source electrode of the J; the second end of C is connected to the drain electrode of Q; the output end of U is connected to the grid electrode of Q; the anode input of U is comparison voltage, and the cathode input is reference voltage; the source electrode of the first sub-module J is connected to the drain electrode of the second sub-module J.

An adhesive may include an adhesive structure and an adhesive composition. The adhesive structure may include a graft copolymer. The adhesive composition may include at least about 1 wt. % and not greater than 40 wt. % of a macromonomer component for a total weight of the adhesive composition, at least about 50 wt. % and not greater than about 98 wt. % of a (meth)acrylic based polymeric component A for a total weight of the adhesive composition, and at least about 0.1 wt. % and not greater than about 30 wt. % of a tackifier component for a total weight of the adhesive composition. The macromonomer component may have a weight-average molecular weight of at least 1000 g / mol and a glass transition temperature (Tg) of at least about 40° C. The (meth)acrylic based polymeric component A may have a glass transition temperature (Tg) of not greater than about 20° C.

The invention relates to the technical field of interface circuits, in particular to a multi-mode switching detection circuit for a Type-C interface, which is used for realizing peripheral type identification and automatic switching between a USB host mode and a DP input mode on a single Type-C interface. The circuit comprises an interface detection unit connected with a Type-C female seat interface, a voltage comparison unit, a main control processor chip, a mode discrimination unit and a control output unit. The voltage comparison unit carries out resistance voltage division and threshold comparison on CC pin voltage, two levels are formed at a detection node and sent to the main control processor chip, and USB equipment and DP source equipment are distinguished by the mode judgment unit. The control output unit controls the USB host power supply control circuit and the DP input chip power supply circuit, establishes a USB data channel in a USB host mode, and establishes a DP-to-video channel in a DP input mode. The circuit realizes rapid peripheral identification and mode automatic switching based on hardware, and is simple in structure, low in cost, high in response speed and high in system stability.

The invention discloses a dynamic comparator and a voltage calibration method thereof, relates to the field of dynamic comparators, and is used for improving the comparison precision of the dynamic comparator in a mode of not sacrificing the power consumption and the efficiency of the dynamic comparator. A kickback noise suppression circuit is connected to a tail current tube of an input geminate transistor to adjust the switching time of a clock signal, a calibration crystal geminate transistor is connected to a regeneration node of the input geminate transistor, and a reference voltage is adjusted through a resistor string DAC to calibrate an offset voltage. The kickback noise is effectively suppressed by adjusting the slew rate of the clock signal of the tail current tube, the calibration speed is increased through the two-stage resistor string DAC, the crystal pair tube is controlled and calibrated by multiplexing the adjusted clock signal, and the calibration precision is improved.