107results about "Multiple input and output pulse circuits" patented technology

An interface circuit includes a reference voltage generation circuit to generate a reference voltage, a differential voltage signal generation circuit to convert send data input in sending data into a pair of differential voltage signals and output the pair of differential voltage signals based on the reference voltage generated by the reference voltage generation circuit, a receiver to convert a pair of differential voltage signals input in receiving data and output received data, and a receiver test circuit to perform a sensitivity test of the receiver, the receiver test circuit having a resistance circuit to generate a pair of differential voltage signals having a potential difference being necessary for the sensitivity test of the receiver.

This application relates to a daisy chain clock distribution system and discloses a circuit (100a) comprising a first power converter (108a) having a first voltage input (110a) and a first output (116a or 117a). The circuit (100a) further comprises a second power converter (108b) having a second voltage input (110b) coupled to the first voltage input (110a), a clock input (112b), and a second output (116b or 117b). A phase shifter (118b) is coupled between the first output (116a or 117a) and the clock input (112b) of the second power converter (108b).

Systems and methods for data transmission are disclosed. The system can include a phase test circuit including a difference detection circuit, a low pass filter circuit, and a reference comparison circuit. The difference detection circuit can be configured to produce an output signal having a duty cycle corresponding to a phase difference between a first input signal and a second input signal. The low pass filter circuit can be connected to an output of the difference detection circuit, and the reference comparison circuit can be configured to compare an output signal of the low pass filter circuit to a threshold.

An actuator driving device includes a driving coil that generates a driving force with first and second voltages; and a control unit, which sets one of the first and second voltages to a first pulse, sets the other one to a second pulse, and performs at least one of: a first control for modulating one pulse width of the first and second pulses with a change amount larger than that of the other pulse width so that a pulse width of ON time of the second pulse is within a pulse width of ON time of the first pulse; and a second control for modulating one pulse width of the first and second pulses with a change amount larger than that of the other pulse width so that the pulse width of the first pulse in ON time is within the pulse width of the second pulse in ON time.

This invention discloses a dynamic comparator for a successive approximation analog-to-digital converter (ADC), relating to the field of comparator technology. The dynamic comparator includes: a cascaded pre-amplifier circuit and a latch circuit; the pre-amplifier circuit includes at least a differential input pair of transistors, a positive feedback loop, and a first tail current source; the differential input pair is used to receive external differential input signals; the positive feedback loop and the first tail current source are both connected to the differential input pair; the first tail current source includes three NMOS transistors connected in parallel; the three NMOS transistors connected in parallel are used to dynamically bias the differential input pair; the positive feedback loop is connected between the two signal output nodes of the pre-amplifier circuit; the positive feedback loop is used to increase the gain of the pre-amplifier circuit. This invention addresses the problems of large footprint and difficult offset calibration in existing successive approximation ADCs.

This invention provides a comparator circuit with latching function and its control method. The comparator circuit with latching function uses an initial voltage provided by a pre-comparison module. The initial voltage is dynamically adjusted based on the input comparison voltage to generate a first current variable. This first current variable is converted into a control voltage, and a first comparison result is output based on the control voltage. The first comparison result is compared and positive feedback latched by the latching module to obtain a second comparison result. This comparator circuit with latching function, designed for low-to-medium precision and low-frequency applications, replaces the redundant design and related bias circuits of multi-stage operational amplifier cascades with a pre-comparison module. The common-mode voltage bias is integrated into the structure of the pre-comparison module, simplifying the circuit structure. This comparator circuit does not interfere with the preceding or following circuits, reducing process sensitivity.

The utility model discloses a biological electricity stimulation circuit based on digital potentiometer, including PWM signal module and electric stimulation module, PWM signal module is used to produce first PWM signal and second PWM signal, and first PWM signal and second PWM signal are the PWM signal of each other time sequence phase inverse, electric stimulation module includes first digital potentiometer U8 and second digital potentiometer U9, one end of first digital potentiometer U8 is connected with first PWM signal through triode Q7, and the other end of first digital potentiometer U8 is connected with first port J1 through triode Q8, one end of second digital potentiometer U9 is connected with first port J1 through triode Q6, and the other end of second digital potentiometer U9 is connected with triode Q8 after triode Q9 and ground, and second PWM signal is connected with second port J2. Through two inverse PWM signals to control comparator, cooperate two digital potentiometers, form loop, realize positive and negative pulse formula's bidirectional current output, be favorable to simplify circuit, reduce cost.

The application discloses a random number conversion system based on a self-calibration magnetic tunnel junction and a working method thereof, and the system comprises a magnetic tunnel junction, a magnetic tunnel junction random writing module, a pre-charge sensing amplification module and a real-time feedback calibration module; the magnetic tunnel junction is a source of physical randomness of the system, and the resistance state of the magnetic tunnel junction randomly flips based on thermal fluctuation; the output end of the magnetic tunnel junction random writing module is connected with the magnetic tunnel junction; the input end of the pre-charge sensing amplification module is connected with the magnetic tunnel junction; the real-time feedback calibration module comprises a period counter, a flip counter and a digital comparator; the input end of the flip counter is connected with the output end of the pre-charge sensing amplification module; the output end of the digital comparator is connected with the input end of the magnetic tunnel junction random writing module, and the flip current of the magnetic tunnel junction random writing module is dynamically adjusted. The application solves the problem of flip probability deviation of a traditional true random number generator caused by process deviation and environmental temperature fluctuation.

The invention discloses a high-speed voltage comparator which is additionally provided with an edge quick response circuit, and then when an input signal of the comparator jumps from a low level to a high level or from the high level to the low level, the edge quick response circuit is switched to the edge quick response circuit. The edge quick response circuit controls the voltage quick change of the control ends of the pull-up device and the pull-down device in the comparator, and accelerates the switching process of the pull-up device and the pull-down device, so that the comparator can finish level judgment more quickly. According to the invention, the response speed of the comparator can be optimized on the premise that the circuit power consumption and the circuit complexity are not obviously increased.

A clock monitoring circuit includes a clock enable signal generator configured to generate an ultra-high frequency clock enable signal based on a clock enable control signal and a reference clock signal, and an ultra-high frequency detector configured to generate an ultra-high frequency determination signal indicating whether a selection clock signal is an ultra-high frequency signal, based on the selection clock signal, the ultra-high frequency clock enable signal, and the reference clock signal.

This invention discloses a wide-range high-voltage signal comparison circuit. The key technical points of the circuit are: the comparison circuit includes a first branch and a second branch each containing a Schottky diode; a third branch and a fourth branch composed of n Schottky diodes connected in series; a first voltage divider branch; a second voltage divider branch; and a comparator. The outputs of the first and third branches are connected to form a first node, and the outputs of the second and fourth branches are connected to form a second node. The first node is connected to the first voltage divider branch, and after voltage division, it is connected to the positive input terminal of the comparator. The second node is connected to the second voltage divider branch, and after voltage division, it is connected to the negative input terminal of the comparator. The comparison circuit designed in this invention operates directly between the high-voltage power supply and global ground, which not only avoids the layout design difficulties caused by multiple power supply grounds but also effectively improves comparison accuracy.

Disclosed are circuits for dynamically configuring configurable micro-architectural circuits based on associated operating point indicators.

A signal detection circuit (400) includes a signal input terminal (402), a rectifier circuit (404), a comparator circuit (406); a current source (408), and a comparator output terminal (412). The rectifier circuit (404) is coupled to the signal input terminal (402) and configured to receive an input signal and generate a rectified signal based on the input signal. The comparator circuit (406) is coupled to the rectifier circuit (404) and configured to receive a common mode signal and generate a difference current based on a difference of the common mode signal and the rectified signal. The current source (408) is coupled to the comparator circuit (406) and configured to generate a reference current. The comparator output terminal (412) is configured to provide an output signal based on a difference of the reference current and the difference current.

An output detection and pulse generation circuit is disclosed. The output detection and pulse generation circuit includes a comparison circuit configured to receive first data to be transmitted to a logic circuit according to a first clock signal and generate a comparison signal by comparing the first data with second data transmitted to the logic circuit in a first phase, and a control signal generation circuit configured to output the comparison signal generated in the first phase as a control signal for controlling activation or deactivation of the logic circuit according to a second clock signal in a second phase.

A semiconductor device according to this disclosure includes: a comparator circuit; a counter circuit; and a latch circuit that stores a count value of the counter circuit at a timing when an output signal of the comparator circuit changes, the counter circuit includes: a multiphase signal generator; and a plurality of flip-flop circuits including a first-stage flip-flop and second-stage and subsequent flip-flops, the first-stage flip-flop takes in an inverted signal of an output signal of a flip-flop in a final stage and each of the second-stage and subsequent flip-flops takes in an output signal of a flip-flop in a preceding stage in synchronization with each of the plurality of clock signals, and an output signal of each of the plurality of flip-flop circuits is output as a count signal of the count value.

This disclosure relates to an amplifier circuit, a comparator including the comparator, and a semiconductor device using the comparator. The comparator includes an amplifier circuit and a latch circuit. The amplifier circuit generates a first amplified signal and a second amplified signal based on a clock signal, an input signal, and a reference voltage. The latch circuit generates a first output signal and a second output signal based on the clock signal, the first amplified signal, and the second amplified signal.

An apparatus including a comparator and a plurality of replica current sources. The comparator outputs a control voltage onto an output line upon comparing a midpoint voltage with a feedback voltage. The control voltage indicates whether the feedback voltage is higher or lower than the midpoint voltage. Each of the replica current sources draws a supply voltage from a supply line. A replica current source enters into an inactive state in response to an enable signal being in a deactivating state. Upon entering the inactive state, the replica current source ceases drawing the control voltage from the output line.

A multi-stream cross correlator for spiking neural networks, where each stream contains significant stochastic content. At least one event occurs, with a fixed temporal relationship across at least two streams. Each stream is treated as a Frame Of Reference (FOR), and subject to an adjustable delay based on comparison to the Other streams. For each spike of the FOR, a timing analysis, relative to the last and current FOR spikes, is completed by comparing Post and Pre accumulators. Also, a new timing analysis is begun, with the current FOR spike, by restarting the production of Post and Pre weighting functions, the values of which are accumulated, upon the occurrence of each Other spike, until a next FOR spike. A one-spike delay unit can be used, if time-neutral conflict resolution is used. The average spike rate of the FOR can be determined and used for the Post and Pre weighting functions.

The application discloses a low-offset comparator for inhibiting sampling signal attenuation, relates to the technical field of analog and mixed signal integrated circuit design, and is used for solving the problems of sampling signal amplitude attenuation caused by input parasitic capacitance and sampling capacitance voltage division of a pre-amplification stage of a comparator in the prior art and deterioration of ADC linearity and dynamic range caused by the problems. The low-offset comparator comprises a sample-and-hold enhancement circuit and a subsequent processing circuit, the sample-and-hold enhancement circuit is connected between a sample-and-hold circuit and the subsequent processing circuit, the subsequent processing circuit comprises a pre-amplification stage with an input transistor pair, the sample-and-hold enhancement circuit comprises an input capacitance neutralization network, the input capacitance neutralization network is connected between a differential input end and a differential output end of the pre-amplification stage, is used for generating a feedback capacitance opposite to inherent gate-drain capacitance effect of the input transistor pair, and thus effectively reduces the input capacitance of the pre-amplification stage at a sampling node of the sample-and-hold circuit.

The application provides a control circuit and a control device. The control circuit comprises: a current sampling module, which is connected to both ends of a shunt to collect a first voltage signal on the shunt; an amplification module, which is used for amplifying the first voltage signal to obtain a second voltage signal and transmitting the second voltage signal to a signal processing module; the signal processing module is used for generating a corresponding first target control signal or a second target control signal according to the second voltage signal and a first reference voltage signal or a second reference voltage signal, and outputting the first target control signal or the second target control signal to a driving module; the driving module is used for generating a driving signal according to the first target control signal or the second target control signal, and outputting the driving signal to an ignition device, wherein the driving signal is used for driving the ignition device to ignite an explosion device in an intelligent fuse. In this way, the control mode for the ignition device is increased, so that the intelligent fuse can adapt to complex environments.

A differential signaling circuit is provided. The differential signaling circuit includes: a differential amplifier configured to generate differential signals; a first signal path circuit; a second signal path circuit; a phase control circuit configured to receive the differential signals having a common phase, output DC signals having a common level in a first operating period, and transmit the differential signals to the first signal path circuit and the second signal path circuit, respectively, in a second operating period; and a duty ratio correction circuit connected between the first signal path circuit and the second signal path circuit, and configured to control duty ratios of the differential signals to be equal to each other in the second operating period.

A drive circuit can calculate an optimal phase adjustment amount by passing a current through an external load. The drive circuit includes a control circuit that outputs a first AC signal and a second AC signal from an AC signal source, and a reference voltage generation circuit that has a differential amplifier generating a first AC voltage from the first AC signal and outputs the first AC voltage to one end of an external load. It also includes a voltage-current conversion circuit that supplies an AC current to the external load from the second AC signal, and a comparator connected across both ends of the external load. The comparator compares the first AC voltage at one end of the external load with the second AC voltage at the other end of the external load and changes the output voltage when the first and second AC voltages are inverted.

This application provides a calibration method and system for a multiphase quadrature clock, relating to the technical field of clock calibration. Each phase of the multiphase quadrature clock is passed through a first low-pass filter to obtain a first DC voltage. Based on a comparison between the first DC voltage and a first reference voltage, the rise time and / or fall time control word of the buffer for that phase clock is adjusted until the first DC voltage equals the first reference voltage. Then, the clock edges of two adjacent phases are sequentially input to a logic gate module to generate pulse signals. These pulse signals are passed through a second low-pass filter to obtain a second DC voltage. Based on a comparison between the second DC voltage and a second reference voltage, the delay control word of the buffer for at least one of the two clock edges is adjusted until the second DC voltage equals the second reference voltage, thereby achieving phase deviation calibration between the clock edges of adjacent phases. The solution provided in this application has the advantage of achieving accurate calibration.

A continuous time comparator, comprising a first Field Effect Transistor, FET, (Mn1) arranged for receiving a first input signal, and a second FET (Mn2) arranged for receiving a second input signal, two branches, a first of said two branches comprises a first transistor (Mp1) and a second of said two branches comprises a second transistor (Mp2), wherein said first of said two branches is connected to said first FET (Mn1) and wherein said second of said two branches is connected to said second FET (Mn2), a first dynamic clamp circuitry connected in parallel over said first branch, wherein said first dynamic clamp circuitry is arranged to dynamically clamp a voltage at a gate of a first output transistor (Mp4), and a second dynamic clamp circuitry connected in parallel over said second branch, wherein said second dynamic clamp circuitry is arranged to dynamically clamp a voltage at a gate of a second output transistor (Mp3), said first and second output transistors (Mp3, Mp4) for providing an output of said comparator and for providing an inverting output of said comparator.

The application provides an interface circuit and an electronic device. The interface circuit comprises a comparison module configured to output a first switching signal when a common-mode voltage of a differential input signal is less than a preset voltage, and output a second switching signal when the common-mode voltage of the differential input signal is not less than the preset voltage. A negative voltage generation module is configured to output a negative voltage according to the first switching signal, and output a ground voltage according to the second switching signal. An amplification module is configured to amplify the differential input signal according to the negative voltage or the ground voltage. A conversion module is configured to convert the differential input signal into a digital signal as an output of the interface circuit. When the common-mode voltage of the differential input signal is less than the preset voltage, the negative voltage generation module outputs the negative voltage as a reference potential end of the amplification module, thereby improving the common-mode equivalent voltage value of the differential input signal at the input end of the amplification module, so that the differential input signal is stable in gain and low in power consumption during high-speed transmission, and can accurately transmit data.

This invention discloses a slope detection circuit, relating to the field of integrated circuit technology. The circuit includes: a signal detection circuit, a comparison feedback circuit, and a charge discharge circuit. The output terminal of the signal detection circuit is connected to the inverting input terminal of the comparison feedback circuit, and the output terminal of the comparison feedback circuit is connected to the control terminal of the charge discharge circuit and an external bus chip. The signal detection circuit is used to convert the slope of the input signal into a voltage change at the detection node, generating a voltage change signal. The comparison feedback circuit is used to receive the voltage change signal and, based on the voltage change signal, generate a rising edge detection signal or a falling edge detection signal. The charge discharge circuit is used to discharge the charge accumulated at the detection node in response to the rising edge detection signal or the falling edge detection signal.