1134results about "Multiple input and output pulse circuits" patented technology

An interface circuit includes a reference voltage generation circuit to generate a reference voltage, a differential voltage signal generation circuit to convert send data input in sending data into a pair of differential voltage signals and output the pair of differential voltage signals based on the reference voltage generated by the reference voltage generation circuit, a receiver to convert a pair of differential voltage signals input in receiving data and output received data, and a receiver test circuit to perform a sensitivity test of the receiver, the receiver test circuit having a resistance circuit to generate a pair of differential voltage signals having a potential difference being necessary for the sensitivity test of the receiver.

Provided are a display drive circuit and a display device capable of curbing fluctuation of a signal line voltage. A display drive circuit includes a ramp wave voltage generation circuit that generates a ramp wave voltage whose voltage level changes with time, and a signal line voltage generation circuit that holds the voltage level of the ramp wave voltage at a timing corresponding to a signal level of a pixel signal and generates a signal line voltage. The ramp wave voltage generation circuit includes an amplifier that outputs the ramp wave voltage, a load circuit arranged on a feedback path of the amplifier, and a current generation circuit that controls a current flowing through the load circuit such that the ramp wave voltage matches a reference voltage.

The disclosure relates to an electronic circuit to verify the integrity of a switch. The circuit comprises a voltage comparator and decoupling switch. The decoupling switch configured receive the driving signal having a first logic value to enable the monitoring of the comparison voltage and is configured to receive the monitoring enable signal having a first logic value to command the opening of the decoupling switch. The electronic circuit is configured to generate the output monitoring signal having a first logic value in an event that the switch is an open circuit and having a second logic value in an event that the switch is a short circuit.

The invention discloses a CMOS analog multiplier circuit, the circuit comprises a current-to-voltage circuit and a multiplier sub-circuit connected with the current-to-voltage circuit, an OSC circuit in the multiplier sub-circuit receives an input voltage VB and a reference voltage VREF and generates a two-phase non-overlapping clock signal group, a voltage-to-current A circuit converts a voltage VA into a current iA, and the current iA is connected with the OSC circuit. The switched capacitor integrating circuit inputs a sampling voltage to the voltage-to-current B circuit and integrates a difference current is of a current iA and a current iB to realize multiplication, the voltage-to-current B circuit converts a sampling voltage signal into the current iB, and the current-to-voltage circuit converts the current iB into an output voltage Vo as a multiplier operation result. Through combination of modular design, a current mode method and a switched capacitor method and high-precision current conversion and integration processes, an efficient and accurate multiplication simulation function is realized, a THD enhancement function is introduced through multiplexing design, and circuit performance is further optimized.

A class D amplifier circuit receives an analog audio signal with a first reference voltage as its center level, and outputs an output pulse signal having a duty cycle that corresponds to the analog audio signal. A bias circuit generates a second reference voltage having a voltage level obtained as a division of the first reference voltage and the power supply voltage. A periodic voltage generating circuit of the class D amplifier circuit generates a periodic voltage having a triangle waveform or otherwise a sawtooth waveform having an amplitude that corresponds to the second reference voltage.

The present disclosure provides an alternating current (AC) / direct current (DC) voltage detection circuit, which includes a rising edge trigger circuit and a detection and output circuit connected to an output terminal of the rising edge trigger circuit. When the operating voltage is higher than the preset voltage, the determination circuit activates the detection and output circuit to detect the change of the operating voltage and the target flip.

The invention provides a wheel speed detection device and a chip system. The wheel speed detection device comprises a first comparator, a second comparator and a signal analyzer, the first comparator and the second comparator are respectively configured with different reference voltages, and the input end of the first comparator and the input end of the second comparator are used for receiving voltage signals generated by the same wheel speed sensor; and the signal analyzer is used for analyzing the wheel speed information according to the first comparison signal output by the first comparator and the second comparison signal output by the second comparator. Thus, the input signal is subjected to multi-threshold judgment by using a double-comparator structure, so that sensor signals of different current levels can be identified and analyzed uniformly, and compatible processing of sensor signals of multiple protocols is realized. Therefore, the problem that the overall system cost is increased due to hardware redundancy and system complexity increase in a traditional scheme is avoided, and the universality and the integration capacity of the interface module are effectively improved in a low-cost mode.

Flash analog to digital converters and other types of integrated circuits having multiple comparators may employ calibration methods and firmware to efficiently compensate the various offset voltages of the multiple comparators. One illustrative integrated circuit includes: multiple comparators each configured to provide a comparator output signal indicating whether an input signal exceeds a reference voltage by more than an offset voltage, the multiple comparators including a current comparator and a previous comparator; and a controller configured to perform a search to select a calibration setting for each of the comparators in turn, the controller determining an initial search window for the current comparator based on a calibration setting selected for the previous comparator.

The embodiment of the invention discloses a comparison circuit, a decision feedback equalizer and a communication interface, the comparison circuit comprises a first-stage comparator and a second-stage comparator, the first-stage comparator carries out comparison sampling on an input signal and a reference signal, obtains and amplifies a potential difference between the input signal and the reference signal, and outputs the potential difference between the input signal and the reference signal; and the secondary comparator receives the pre-amplified potential difference and performs secondary comparison sampling on the pre-amplified potential difference to obtain a target signal. Therefore, according to the comparison circuit provided by the embodiment of the invention, the first-stage comparator can work at a relatively low conversion rate through a biphase sampling principle, the comparison efficiency of the second-stage comparator is improved through pre-amplification of the first-stage comparator, and meanwhile, physical separation of input and output of the comparison circuit is realized; according to the embodiment, direct coupling paths between input and output are reduced, input end interference caused by output changes is reduced, meanwhile, biphase sampling is based on discrete time type sampling, the bandwidth and gain requirements are reduced, and eye pattern distortion is avoided.

Load disconnect techniques for boost converters. In an example, a power converter includes a driver circuit, a control circuit, and a comparator circuit. During normal boost operation (VIN<VOUT), the comparator circuit disables the control circuit and enables the driver circuit, which in turn fully turns on a high-side switching element during high-side on-phase. In contrast, during start-up operation or an output short-to-ground condition (VIN≥VOUT), the comparator circuit disables the driver circuit and enables the control circuit, which in turn controls the gate voltage of the high-side switching element, so the current through the switching element is regulated, and the switching node voltage is regulated to about a threshold voltage higher than VIN. In this manner, the comparator circuit controls the driver circuit and the control circuit, which in turn allow the boost converter to operate in a normal fashion even when VIN is higher than VOUT.

The invention discloses a high-voltage power supply high-selection circuit and a control method thereof, the high-voltage power supply high-selection circuit comprises a floating power supply generation circuit, a high-voltage floating comparator circuit, inverters INV1-INV4, a high-voltage PMOS tube PDM5 and a high-voltage PMOS tube PDM6, the floating power supply generation circuit generates a floating high voltage HVDD and a floating low voltage HVSS, two inputs of the high-voltage floating comparator circuit are respectively connected with input signals V1 and V2, and the high-voltage floating comparator circuit is connected with the high-voltage PMOS tube PDM5 and the high-voltage PMOS tube PDM6. The inverters INV1-INV4 generate two inverted signals A and B according to an output signal of the high-voltage floating comparator circuit, a high-voltage power supply end of the high-voltage floating comparator circuit, a source electrode of the high-voltage PMOS tube PDM5 and a source electrode of the high-voltage PMOS tube PDM6D are connected with a floating high voltage HVDD, and a low-voltage power supply end of the high-voltage floating comparator circuit is connected with a floating low voltage HVSS. According to the invention, the high-voltage power supply high-selection circuit is realized.

An integrated circuit includes a first multiplexer, a second multiplexing-input, a first clocked comparator, and a second clocked comparator. A first input node is connected to a first multiplexing-input of the first multiplexer, a first multiplexing-input of the second multiplexer, a first comparing-input of the first clocked comparator, and a first comparing-input of the second clocked comparator. A second input node is connected to a second multiplexing-input of the first multiplexer and a second multiplexing-input of the second multiplexer. An output of the first multiplexer is connected to second comparing-input of the first clocked comparator, and an output of the second multiplexer is connected to a second comparing-input of the second clocked comparator. The integrated circuit also includes an offset control circuit connected to a comparator-output of the first clocked comparator and a comparator-output of the second clocked comparator.

A ripple voltage detector circuit comprises a pulse generator, a direct current-to-direct current (DC-DC) converter coupled to the pulse generator, and a first control loop coupled to the pulse generator and the DC-DC converter. The first control loop is configured to measure an output voltage of the DC-DC converter, determine an output ripple voltage of the output voltage, determine a ripple coefficient based on the output ripple voltage, determine a reference peak inductor current based on the ripple coefficient, and determine a peak value of an inductor current during a switching cycle, and transition a switching state of the DC-DC converter based on the reference peak inductor current and the peak value of the inductor current.

A multi-phase clock signal generating circuit, configured to generate a plurality of output clock signals with different phases, comprising: a charge pump, configured to generate a control voltage according to a reference clock signal and a target clock signal; a delay circuit, comprising a delay chain with a plurality of delay units, configured to generate a plurality of candidate clock signals and the target clock signal according to the control voltage; and a phase selecting circuit, configured to select at least two of the candidate clock signals as the output signals.

A latch comparator is disclosed. The latch comparator includes a first reservoir capacitor; a preamplifier including first and second transistors respectively connected to first and second inputs, the first and second transistors selectably connectable to a first terminal of the first reservoir capacitor, and third and fourth transistors respectively connected to the first and second inputs, the third and fourth transistors selectably connectable to a second terminal of the first reservoir capacitor; and a latch, including a first portion serially connected between the first and third transistors and connected to a first output, and a second portion serially connected between the second and fourth transistors and connected to a second output.

A circuit for detecting metastability in an asynchronous successive approximation register analog-to-digital converter; wherein the dual output comparator is arranged to receive a first input signal and a second input signal, compare the first input signal with the second input signal, and drive one of the first comparison signal and the second comparison signal to a set state based on the comparison. When the first comparison signal is in the set state, the first output end is in the set state. When the second comparison signal is in the set state, the second output end is in the set state. If a predetermined duration elapses after the dual output comparator starts comparison, and if both the first comparison signal and the second comparison signal are in a reset state, the control logic outputs a set state at both the first output and the second output. This allows the metastability of the comparator to be detected in the asynchronous SAR ADC. The control logic may effectively terminate the comparison if a predetermined duration is reached. In other words, the control logic may overwrite the comparator output to provide a defined output indicative of metastability.

The invention discloses a direct-current solid-state circuit breaker with a voltage limiting protection circuit and a control method thereof. The direct-current solid-state circuit breaker comprises a solid-state switch module, the solid-state switch module comprises a first sub-module and a second sub-module which are the same, and each of the first sub-module and the second sub-module comprises a SiC JFET device J, capacitors C, Cgd and Cgs, a comparator U, an MOSFET device Q, a resistor Rg and resistors ra and rb; the first end of Rg is used for receiving a driving signal, and the second end of Rg is connected to the grid electrode of J after being connected with the first end of C, the second end of Cgd and the first end of Cgs; the second end of ra and the first end of rb are connected as a comparison voltage sampling point; the first end of ra is connected to the first end of Cgd and the drain electrode of J; the second end of the rb is connected to the second end of the Cgs, the source electrode of the Q and the source electrode of the J; the second end of C is connected to the drain electrode of Q; the output end of U is connected to the grid electrode of Q; the anode input of U is comparison voltage, and the cathode input is reference voltage; the source electrode of the first sub-module J is connected to the drain electrode of the second sub-module J.

The invention relates to the technical field of interface circuits, in particular to a multi-mode switching detection circuit for a Type-C interface, which is used for realizing peripheral type identification and automatic switching between a USB host mode and a DP input mode on a single Type-C interface. The circuit comprises an interface detection unit connected with a Type-C female seat interface, a voltage comparison unit, a main control processor chip, a mode discrimination unit and a control output unit. The voltage comparison unit carries out resistance voltage division and threshold comparison on CC pin voltage, two levels are formed at a detection node and sent to the main control processor chip, and USB equipment and DP source equipment are distinguished by the mode judgment unit. The control output unit controls the USB host power supply control circuit and the DP input chip power supply circuit, establishes a USB data channel in a USB host mode, and establishes a DP-to-video channel in a DP input mode. The circuit realizes rapid peripheral identification and mode automatic switching based on hardware, and is simple in structure, low in cost, high in response speed and high in system stability.

The invention discloses a dynamic comparator and a voltage calibration method thereof, relates to the field of dynamic comparators, and is used for improving the comparison precision of the dynamic comparator in a mode of not sacrificing the power consumption and the efficiency of the dynamic comparator. A kickback noise suppression circuit is connected to a tail current tube of an input geminate transistor to adjust the switching time of a clock signal, a calibration crystal geminate transistor is connected to a regeneration node of the input geminate transistor, and a reference voltage is adjusted through a resistor string DAC to calibrate an offset voltage. The kickback noise is effectively suppressed by adjusting the slew rate of the clock signal of the tail current tube, the calibration speed is increased through the two-stage resistor string DAC, the crystal pair tube is controlled and calibrated by multiplexing the adjusted clock signal, and the calibration precision is improved.

The invention provides a high-integration-level signal reading module for a neutron proportional counter tube, and belongs to the technical field of neutron detection, the high-integration-level signal reading module comprises stacked double-layer circuit boards, and the upper circuit board and the lower circuit board are connected through pin interfaces; the upper circuit board is provided with a signal processing circuit which is used for reading, amplifying, discriminating and shaping signals of the neutron proportional counter tube. The lower-layer circuit board is provided with a positive and negative dual-power-supply support circuit which provides + / -3.3 V power supply support for the signal processing circuit of the upper-layer circuit board. The module supplies power through the lower-layer power panel, and the lower-layer circuit board supplies positive and negative power to the upper-layer circuit board after completing power conversion. Signals are input through the IPX interface of the upper-layer circuit board and are output through the other IPX interface after being processed. The charge sensitive pre-amplifier, the broadband voltage amplifier, the pulse discriminator circuit, the pulse shaping circuit and the power management module are integrated in the same module, so that the real integrated design is realized.

The invention provides a relaxation oscillator, a chip and an electronic device, the relaxation oscillator comprises a bias module, a first generation module, a first comparator, a second generation module, a second comparator and a control logic module, the first generation module and the second generation module alternately enter a first working mode and a second working mode, in the first working mode, the first comparator is connected with the second comparator, and in the second working mode, the second comparator is connected with the control logic module. The non-inverting input end inputs a reference voltage, when the voltage of the inverting input end rises from a preset initial voltage to the reference voltage, a discharge signal is output, so that the voltage of the inverting input end drops, and when the voltage of the inverting input end drops to the reference voltage, the discharge signal is stopped being output, so that the voltage of the inverting input end is kept as the reference voltage; in the second working mode, the reference voltage is input into the inverted input end, the first comparator or the second comparator is grounded and reset at the non-inverted input end until the voltage of the non-inverted input end reaches the reference voltage, and the first output signal or the second output signal is correspondingly output.

The invention discloses a high-voltage positive and negative pulse detection circuit, which relates to the technical field of signal conditioning, and is characterized in that a voltage division circuit is responsible for attenuating input pulse signals, a switching diode is responsible for rectification and inputting positive and negative pulse signals into corresponding conditioning circuits respectively, and a charging circuit is responsible for maintaining pulse width characteristics of the signals; and the steepness of the signal edge is ensured by the comparator, and FPGA identification can be realized. Uncertain high-voltage pulse signals can be processed, and application scenes are diversified. The edge characteristic, pulse width and pulse direction of the pulse signal can be identified, and the signal processing capability is prominent.

The invention discloses a single-pin trimming circuit, which relates to the technical field of analog circuit design and comprises a comparator module, a first input end of the comparator module is connected to a single pin, a second input end of the comparator module is connected to a reference voltage, and the comparator module is used for comparing an input voltage of the single pin with the reference voltage and outputting a comparison signal; the input end of the time sequence decoding module is connected to the output end of the comparator module, and the time sequence decoding module is configured as follows: a, the logic state of a trimming position is judged according to the duration time of the pulse in the comparison signal; and b, addressing different trimming positions according to the number of pulses in the comparison signal, and further generating a multi-position trimming control signal through a series of pulse signals input by the single pin. Accurate control of a multi-bit fuse trimming circuit in a chip is realized by using single-pin resources.

The invention belongs to the technical field of integrated circuits, and particularly relates to a dynamic comparator suitable for a low-voltage high-speed analog-to-digital converter, the dynamic comparator adopts a three-stage latch circuit structure to realize rapid comparison of weak input signals so as to generate corresponding digital signals, and the method specifically comprises the following steps of: in a pre-amplification stage, pre-amplification is carried out; the positive feedback effect of the cross-coupled transistor pair is utilized to efficiently convert a tiny input voltage difference (lt; 10mV) into a recognizable voltage difference, and then through two-stage regeneration of the main latch module and the auxiliary latch module, a logic level is quickly output to complete quantization judgment. The auxiliary latch stage is additionally arranged on the basis of a traditional cross coupling latch circuit, the working speed of the comparator is effectively increased under the condition that only small area overhead is introduced, and the probability that the dynamic comparator has a metastable state is greatly reduced.

The present disclosure discloses a duty cycle signal processing circuit and method, and an audio signal processing device. The duty cycle signal processing circuit includes an amplitude detector and an operation unit, where the amplitude detector is configured to detect a first amplitude of an audio signal, generate a second amplitude, and send the second amplitude to the operation unit; and the operation unit is configured to obtain a power supply voltage, and perform operation processing on the second amplitude and the power supply voltage, to obtain a duty cycle control signal that matches at least one parameter of the second amplitude and the power supply voltage. In the present disclosure, conversion efficiency of a corresponding power amplifier unit can be improved.

The invention relates to a trigger unit. The trigger unit comprises a first comparison feedback circuit, a first clock gating circuit, a master latch and a slave latch assembly, the first comparison feedback circuit is used for detecting a signal hopping state of an external input signal according to a first output signal output by the output end of the main latch, and generating a corresponding first state feedback signal, so that the first clock gating circuit generates a corresponding first gating clock signal according to the first state feedback signal and a reference clock signal, and sends the first gating clock signal to the second clock gating circuit; under the condition that the first gating clock signal is valid, the main latch is controlled to update the first output signal according to the external input signal; the state switching opportunity of the main latch can be accurately controlled, and unnecessary clock flipping in the trigger and transistor switching activity caused by the unnecessary clock flipping are effectively reduced, so that dynamic power consumption related to a clock network and dynamic power consumption generated by flipping of nodes in a data path are effectively reduced.

A current comparator comprising: a P-type metal oxide semiconductor field effect transistor, PMOS FET (614), and an N-type metal oxide semiconductor field effect transistor, NMOS FET (615). The source of the PMOS FET is connected to a first comparator input terminal (610). The source of the NMOS FET is connected to a second comparator input terminal (611). The drain of the PMOS FET is connected to a current-comparator-input-node (602). The drain of the NMOS FET is connected to the current-comparator-input-node. The gate of the PMOS FET is connected to a first bias-voltage-node (VP). The gate of the NMOS FET is connected to a second bias-voltage-node (VN). The current comparator also includes a bias circuit (613) that provides a bias voltage to each of the first and second bias-voltage-nodes, and a current-comparator-circuit (601). A current-comparator-circuit-input-terminal (602) is connected to the current-comparator-input-node in order to receive a difference-current-input signal (IIn), which is representative of the difference between a first current input signal and a second current input signal. The current-comparator-circuit is configured to provide a current comparator output signal (Vout) as a digital voltage signal based on the received difference-current-input signal.

An input / output (I / O) sensor is provided for a multi-IC (Integrated Circuit) module. The I / O sensor includes: a signal input, configured to receive a data signal from an interconnected part of an IC of the multi-IC module; and a time duration measurement circuit, configured to measure a time duration between a first time, at which the data signal is at a first level, and a second time, at which the data signal is at a second level, different from the first level. The sensor may be incorporated into an I / O block, an IC, and / or a multi-IC module. An I / O sensor which includes a controller configured to measure duty cycle distortion of a multi-phase clock is also disclosed.

The invention discloses an output OVP protection circuit and a control method thereof, the output OVP protection circuit comprises a VIN sampling circuit, a VCS sampling circuit, a timer, an output overvoltage protection control module OVP control, an RS trigger G3, an OR gate G2 and a GATE generation circuit, and the output overvoltage protection control module OVP control comprises a voltage division module Divider 2, a filter 2, a compensation module Combination, a comparator CMP4, an RS trigger G5, an AND gate G6 and a phase inverter G7. According to the invention, the overvoltage protection point is high in precision and stable, so that no large margin needs to be reserved on the type selection of the output capacitor, and the cost of a power supply system is reduced.

The invention discloses a vibration suppression circuit applied to a wheel speed sensor and a suppression method of the vibration suppression circuit, the vibration suppression circuit comprises a Hall disc HallR, a Hall disc HallC, a Hall disc HallL, a first signal link, a second signal link, a digital processor DSP and a current signal output module IOUT, differential electric signals output by the Hall disc HallR and the Hall disc HallC are input to the input end of the first signal link, and differential electric signals output by the Hall disc HallL are input to the output end of the second signal link; differential electric signals output by the Hall disc Hall L and the Hall disc Hall C are input to the input end of the second signal link, the output end of the first signal link and the output end of the second signal link are connected with the first input end and the second input end of the digital processor DSP respectively, and the first output end of the digital processor DSP is connected with the current signal output module IOUT. According to the invention, the vibration suppression function of the wheel speed sensor is improved, and the vibration suppression difficulty of the DSP is reduced.