264 results about "Eye pattern" patented technology

The invention relates to a retiming circuit applied to an ultra-high-speed and high-precision DAC (Digital-to-Analog Converter), which comprises an alignment module, a cross point adjusting module, a coding module, a phase detection module and a digital module, the coding module is connected with the alignment module, the phase detection module is connected with the cross point adjusting module and the coding module, and the digital module is connected with the phase detection module and the alignment module. According to the circuit structure provided by the invention, the sampling clock can be accurately aligned to the center of a data eye pattern, so that the delay difference between a clock tree and a data path caused by process deviation and the like is effectively reduced, the high-frequency spurious suppression performance is improved by eliminating nonlinear distortion caused by time sequence errors, the SFDR is greatly improved, and compared with a traditional scheme, the SNR is effectively improved.

The invention discloses a method and system for testing a direct-current offset compensation circuit of an optical transceiving driving chip and a medium, and relates to the technical field of photoelectric integrated circuit testing, and the method comprises the following steps: carrying out the time alignment of a test waveform and an offset track of the optical transceiving driving chip, extracting the phase dislocation amount and the amplitude kick amount between beats, and carrying out the calculation of the phase offset amount and the amplitude kick amount; a continuous change result is mapped into a time sequence conflict observation band which is used for identifying a beat overlapping region; and on the basis of the phase dislocation trend of the time sequence conflict observation band, determining a beat overlapping point of the direct current offset compensation loop, and generating an overlapping beat index according to the duration of amplitude kick and the polarity direction for identifying an interference node. According to the method, millisecond-level beat observation and microsecond-level overlapping identification are realized in a test stage, interference nodes are accurately extracted, a coupling strength graph is constructed, and by combining beat rearrangement and an energy unloading strategy, nonlinear oscillation is inhibited, oscillation and overload risks are reduced, eye pattern quality and error code stability are improved, and chip test precision and robustness are enhanced.

The invention discloses a statistical eye pattern generation method and device and a storage medium. The method comprises the following steps: inputting a step signal at a transmitting end of a channel, and determining a step response function based on the step signal; introducing a dithering signal at the transmitting end, and determining a dithering probability model based on the dithering signal; based on a jitter probability model, determining a jitter value set and a jitter probability set; determining a state transition probability matrix between the first moment and the second moment in the input step signal; based on the state transition probability matrix and the step response function, establishing an equivalent response distribution kernel for the target sampling moment; performing convolution operation on the voltage probability distribution at the previous sampling moment of the target sampling moment and the equivalent response distribution kernel, determining the voltage probability distribution at the target sampling moment, and determining the voltage probability distribution at multiple sampling moments; and generating a statistical eye pattern based on the voltage probability distribution at the plurality of sampling moments. The method has the technical effect of assisting in improving the credibility of simulation evaluation.

The invention relates to a UCIe-based data link test method and device, and a chip. The method comprises the steps that a local core particle obtains an eye pattern inspection result which is returned by a remote core particle and is associated with any data channel in a data link; according to the eye pattern inspection result and a preset eye pattern threshold interval parameter, determining whether the eye pattern inspection result accords with an interval range allowed by the eye pattern threshold interval parameter; determining any data channel as a qualified channel under the condition that the eye pattern inspection result accords with an interval range allowed by the eye pattern threshold interval parameter; and under the condition that the eye pattern inspection result does not accord with the interval range allowed by the eye pattern threshold interval parameter, determining any data channel as an unqualified channel. According to the technical scheme, the available bandwidth of the data link can be improved, the stable communication rate of the data link can be ensured, the flexibility of configuration about link training can be improved, and the method and the device can be compatible with a related UCIe protocol.

The invention discloses an LPO wired receiver adopting adaptive CTLE based on a genetic algorithm, and the receiver comprises an analog front end, a data sampler, an edge sampler, an error sampler, a 1: 32 demultiplexer, a verification module, an eye pattern monitor, a genetic algorithm module, clock recovery logic, and a clock path. The eye pattern monitor is used for calculating the eye pattern closure degree according to the data of the data sampler and the error of the error sampler and outputting the eye pattern closure degree to the genetic algorithm module; and the genetic algorithm module is used for realizing parameter adaptive control of a continuous time linear equalizer CTLE and a variable gain amplifier VGA in the analog front end. The invention aims to apply the genetic algorithm to the adaptive equalization of the adaptive continuous time linear equalizer, so that the adaptive continuous time linear equalizer has stronger global search capability and lower power consumption and is not easy to fall into local optimum, and the complexity and power consumption of the adaptive continuous time linear equalizer are reduced. And the real-time and energy-saving requirements are met.

The invention relates to the technical field of communication signals, in particular to an eye pattern limit offset determination method and system, and the method comprises the steps: carrying out the data bias sampling in an analog circuit according to a current bias data code value, obtaining the current bias data, comparing the current normal data with the current bias data through a serial-parallel conversion module, obtaining the waveform comparison data, and determining the eye pattern limit offset according to the waveform comparison data. And performing ratio calculation on the total bit number and the error bit number according to the waveform comparison data to obtain a current bit error rate, judging whether the current bit error rate is greater than a bit error rate threshold value or not, if not, returning to perform bias data code value regulation and control, and if so, obtaining a previous bias data code value of the current bias data code value. And determining the limit offset of the eye pattern according to the last bias data code value. According to the invention, the recognition efficiency of the eye pattern limit offset can be improved.

The invention relates to a performance monitoring method of a forward transmission network, an optical module, equipment and a storage medium. The method comprises the following steps: acquiring an optical signal which is sent from a far-end radio frequency unit and is transmitted to a receiving unit of a performance monitoring optical module, and converting the optical signal into an electric signal; performing eye pattern analysis on the electric signal to generate an eye pattern distribution histogram; the eye pattern distribution histogram is used for representing distribution conditions of different signal amplitudes in different intervals; determining a multipath interference deformation factor according to the deformation condition of the eye pattern distribution histogram of the electric signal compared with the eye pattern distribution histogram before signal transmission; and determining a signal-to-noise ratio estimation value according to the multipath interference deformation factor, and determining a performance monitoring result of the forward transmission network according to the signal-to-noise ratio estimation value. By adopting the method, the link quality of the forward network can be accurately evaluated.

The invention discloses an eye pattern generation method based on channel simulation, a storage medium and electronic equipment, and the method comprises the steps: carrying out the channel simulation according to a target channel parameter, a signal source parameter and an initial code pattern sequence, and generating jitter-free initial eye pattern data; obtaining a deterministic jitter parameter and a random jitter parameter, and generating a deterministic jitter time sequence based on the obtained deterministic jitter parameter and the initial code pattern sequence; generating a random jitter time sequence based on the obtained random jitter parameter; synthesizing the deterministic jitter time sequence and the random jitter time sequence to generate a total jitter time sequence offset sequence; and modulating time sequence information in the initial eye pattern data by using the total jitter time sequence offset sequence to generate a target eye pattern. Simulation of deterministic jitter and random jitter is added in the channel simulation process, and the consistency of the simulation result and the signal characteristic of a real communication scene is greatly improved.

The invention discloses a high-speed link signal integrity analysis general modeling method and system based on fast time domain simulation and transfer learning. The method comprises the following steps: S1, selecting a high-speed link structure to be modeled; s2, extracting a pure edge signal without intersymbol interference based on a multi-edge response method, and calculating a reconstructed transient waveform and a worst eye pattern; s3, only performing a small amount of high-precision transient simulation and preprocessing in the target domain, and constructing a target domain data set; s4, designing special neural network DNN and TCN models, and constructing a source domain data pre-training model by using source domain fast time domain simulation data; and S5, based on a transfer learning strategy, the model is finely tuned by using limited target domain data. The method is used for constructing the high-speed link signal integrity agent model, so that under the condition that the number of times of high-precision transient simulation is remarkably reduced, the model prediction precision and training efficiency are improved, and the problems that traditional transient simulation consumes too long time, ANN model data dependence is large, and the transfer learning application range is limited are solved.

The invention belongs to the technical field of time sequence calibration, and relates to a core particle parallel interface time sequence calibration method, which comprises the following steps of: introducing a phase interpolator with 180-degree phase deviation in a clock path of a receiving end, and positioning a sampling clock at the center of a data eye diagram; in a data path of a receiving end, a coarse adjustment delay calibration unit is firstly adopted to carry out periodic delay compensation, and the coarse adjustment delay calibration unit adopts a numerical control delay line structure to carry out delay adjustment; and then, a fine adjustment delay calibration unit is adopted to further realize sub-period-level delay adjustment, the fine adjustment delay calibration unit adopts a phase interpolator structure and a dynamic fine adjustment calibration mechanism, and finally, the delayed data signal and the clock signal are aligned at a receiving end. According to the invention, the binary search method is introduced, the positioning speed of the optimal delay configuration is obviously improved, delay drift is fully considered, a dynamic calibration mechanism is added, a sampling window is constructed based on a phase interpolator, and a high-precision and dynamic calibration effect is realized.

The invention relates to the technical field of data storage, and discloses a method for testing the signal quality of an IO interface of a memory module, and the method comprises the steps: verifying the signal integrity of the I / O interface in the memory module based on an eye diagram analysis method; after the signal is verified to be complete, the morphological characteristics of the input eye pattern and the output eye pattern are quantitatively compared, whether morphological characteristic changes occur in the signal transmission process or not is judged, and the morphological characteristic changes at least comprise logic level flipping errors, time sequence recognition errors and signal quality degradation; if the morphological characteristics of the input eye pattern are consistent with the morphological characteristics of the output eye pattern, the test is successful; and if the morphological characteristics of the input eye pattern are inconsistent with the morphological characteristics of the output eye pattern, determining that the test fails. Visual and quantitative verification of signal integrity is realized through eye pattern analysis, multi-dimensional indexes such as voltage, time sequence and noise are covered, and the signal transmission quality is reflected more comprehensively compared with a single parameter test.

The invention relates to an LPDDR4X simulation method and system based on a statistics theory. The method comprises the steps that a single-byte BYTE time domain simulation platform used for simulating LPDDR4X signal transmission characteristics is constructed; routing delay analysis is carried out on packaging and PCB channels corresponding to each signal in the single-byte BYTE, time sequence inconsistency in signal transmission is captured, and then the influence of phase crosstalk noise on eye height is captured; carrying out pulse response analysis on the signal, and quantifying ISI noise basic data caused by packaging and a PCB channel; independently analyzing the influence of crosstalk noise on each signal to obtain direct influence data of noise on eye height; processing ISI noise basic data and direct influence data by utilizing an MATLAB script, and extracting a main cursor voltage value, an ISI noise amplitude and crosstalk noise; according to the main cursor voltage value, the ISI noise amplitude and the crosstalk noise, the final eye pattern eye height is calculated. According to the method, the problem that a traditional simulation method is insufficient in eye pattern height evaluation is solved, and more accurate and efficient simulation support can be provided for high-speed low-power-consumption DDR design.

The invention provides an eye pattern intersection point estimation method and system, relates to the technical field of communication link evaluation, and solves the problems of insufficient estimation precision and low efficiency caused by sparse data of an intersection point region in an existing eye pattern test. The method comprises the following steps: acquiring VNA frequency domain data, converting the VNA frequency domain data into time domain data, and performing convolution calculation by using a random sequence to generate a convolution sequence; according to a preset unit interval length, segmenting the convolution sequence into a plurality of eye pattern data units to form an eye pattern data set; screening out a rising edge data subset and a falling edge data subset based on the position relationship between the starting point and the ending point of each eye pattern data unit in the eye pattern data set and the middle position of the eye pattern; and respectively carrying out average processing to obtain rising edge data and falling edge data, and carrying out linear fitting to obtain an intersection point of the rising edge data and the falling edge data as an eye pattern intersection point. According to the method, calculation can be completed only through a small number of basic data points, the processing burden is greatly relieved, and the testing efficiency is improved.

The invention provides an eye pattern search space optimization method and system and a computer storage medium. The eye pattern search space optimization method comprises the steps of presetting an initial search space of a to-be-optimized circuit parameter; constructing an initial simulation case combination according to the initial search space; generating a plurality of simulation netlists and performing simulation to obtain corresponding eye pattern performance response values; establishing a second-order polynomial meta model according to the eye pattern performance response value and the circuit parameters; calculating an eye diagram performance response maximum value and a circuit parameter value corresponding to the eye diagram performance response maximum value; presetting a scaling coefficient, and updating the search space according to the eye pattern performance response maximum value and the corresponding circuit parameter value; and updating the simulation case combination according to the updated search space to carry out iterative calculation on the search space, and outputting an optimal search space. According to the scheme, the search range can be automatically focused on the potential optimal region, and the global optimal parameter combination for optimizing the eye height and eye width performance is accurately positioned with the minimum simulation times, so that the signal integrity judgment of the high-speed serial link is facilitated.

The invention provides a DDR wafer test anomaly detection method and device based on machine learning, and the method comprises the steps: obtaining a time sequence eye pattern synchronously collected in a DDR wafer test process and time sequence waveform data related to total jitter, deterministic jitter and random jitter, and carrying out the clock edge phase segmentation alignment of differential time sequence sampling points in the time sequence waveform data, phase domain dense sampling data is constructed, adaptive sparse coding is completed in combination with DDR jitter physical priori, noise and normal process fluctuation related components are removed, defect sensitive sparse components are obtained, variational mode decomposition is performed, components related to process drift, normal process fluctuation and abrupt change abnormity are obtained, and the defect sensitive sparse components are subjected to sparse coding; and the abrupt change anomaly correlation component is extracted as target detection data, a preset machine learning model is input, an anomaly mode correlation result is generated, a DDR wafer test anomaly detection result is output based on the result, and a corresponding test setting item adjustment instruction is generated. According to the invention, the overall efficiency and the result reliability of the DDR wafer test can be improved.

The invention relates to the technical field of jitter analysis, in particular to a high-speed oscilloscope eye diagram real-time jitter detection method and system, and the method comprises the following steps: carrying out high-speed collection waveform zero-cross detection to obtain a timestamp, calculating offset grouping to obtain a cross-period edge time sequence, merging a jump cluster according to a sequence hierarchy cluster, calculating offset, obtaining a drift trend vector, and calculating the jitter of the drift trend vector; and based on the trend vector distribution compensation weight, weighting and correcting the time coordinate, calling a corrected coordinate detection period boundary to calculate a difference value exceeding a threshold value, triggering correction to obtain a period correction rear edge coordinate, and extracting a jitter frequency amplitude according to corrected coordinate Fourier analysis to generate an eye pattern jitter detection result. Phase correlation is established based on a cross-period sequence, an analyzable offset mode is formed through a clustering identification distribution structure, accumulated deviation is suppressed through a drift trend and weight correction, an abnormal period is calibrated through period dynamic discrimination, and the relation between a jitter structure and amplitude is separated through frequency analysis, so that the overall stability and integrity are enhanced.

A method for identifying margins in an eye opening includes capturing first data from a data signal based on edges in a data clock signal, capturing second data from the data signal responsive to edges in a phase shifted version of the data clock signal, iteratively increasing phase difference between the phase shifted version of the data clock signal and the data clock signal when the first data initially matches the second data until the first data differs from the second data, iteratively decreasing the phase difference between the phase shifted version of the data clock signal and the data clock signal when the first data initially differs from the second data until the first data matches the second data, and determining the margin of the eye opening when the first data begins to match the second data or when the first data begins to differ from the second data.

The invention relates to an impedance determination method and device, computer equipment, a readable storage medium and a program product. The method comprises the steps that first eye diagrams of an on-chip terminal are acquired, and the first eye diagrams are eye diagrams of an electric signal under target equalizer parameter conditions corresponding to candidate impedance values of the on-chip terminal; each candidate impedance value corresponds to a target equalizer parameter; according to a first preset condition and the eye diagram parameters in the first eye diagrams, obtaining a target eye diagram from the first eye diagrams; wherein the first preset condition represents a screening condition related to the eye pattern parameter; and taking the candidate impedance value corresponding to the target eye diagram as a target impedance value. According to the method, the target impedance value is adopted to design the chip system, so that the performance of the chip is improved.

The present invention relates to the technical field of optical communications and particularly relates to a method for implementing a signal-to-noise ratio reporting function based on a CDR solution, and an optical module. In the present invention, eye diagram data is obtained by means of scanning data in a communication link, and after the eye diagram data is processed, the average value thereof is obtained, so as to obtain a signal-to-noise ratio value to be reported, thereby achieving SNR reporting of the optical module based on the CDR solution, effectively improving the accuracy and stability of the SNR reporting, enabling the optical module based on the CDR solution to also effectively measure the link SNR indicator health status, and providing an effective test method and means for testing the chromatic dispersion of the optical module, investigating the influence of temperature and MPI on the SNR, and the like. In addition, a bit error rate can also be reduced by guiding the configuration of FEC correction and equalization compensation, thereby improving the quality of signal transmission.

This invention provides a method and system for testing the high-temperature transmission characteristics of low-capacitance ESD devices, comprising: connecting a low-capacitance ESD device array under test in parallel to a differential signal line of a test channel; simultaneously applying a PRBS code stream signal and a surge pulse superimposed on the PRBS code stream signal to the test channel under a preset temperature environment; extracting the instantaneous drop depth of the eye diagram opening after the surge impact and the recovery time for the eye diagram opening to return to the pre-impact level based on the aligned eye diagram opening change curve; determining that the low-capacitance ESD device array does not meet the protection requirement of no packet loss during surge impact under high-temperature conditions when the instantaneous drop depth exceeds a preset eye diagram drop threshold or the recovery time exceeds a preset recovery time threshold; and determining that the low-capacitance ESD device array does not meet the protection requirement of no packet loss during surge impact under high-temperature conditions when simulating actual working conditions. This invention can simultaneously evaluate the impact of high-temperature environment on the signal transmission quality and surge protection capability of low-capacitance ESD devices under simulated actual working conditions.

This invention discloses a control method, system, and medium for a DC offset compensation circuit of an optical transceiver driver chip, relating to the field of optoelectronic integrated circuit testing technology. The method includes the following steps: time-aligning the test waveform and bias trajectory of the optical transceiver driver chip; extracting the phase misalignment and amplitude jump between beats; and mapping the continuous changes to a timing conflict observation band for identifying beat overlap regions. Based on the phase misalignment trend of the timing conflict observation band, the beat overlap points of the DC offset compensation loop are determined, and an overlap beat index is generated based on the duration and polarity of the amplitude jump to identify interfering nodes. This invention achieves millisecond-level beat observation and microsecond-level overlap identification during the testing phase, accurately extracting interfering nodes and constructing a coupling strength map. Combined with beat rearrangement and energy unloading strategies, it suppresses nonlinear oscillations, reduces oscillation and overload risks, improves eye diagram quality and bit error rate stability, and enhances the accuracy and robustness of chip testing.

Methods, systems, and devices for signal monitoring by a memory system are described. A memory system may receive signaling (e.g., from a host system) and may sample the signal and generate an eye diagram. During a normal mode of operation, the memory system monitor characteristics of the eye diagram to improve signaling. The memory system may determine a voltage level of the signaling based on one or more input parameters and sampling times associated with the signaling. An indication of the voltage level of the signaling may be stored (e.g., to a register of the memory system) and may be periodically transmitted to the host system.

The invention discloses an SOQPSK demodulation performance monitoring method and system based on upper computer visual feedback. An SOQPSK signal is demodulated by adopting a maximum likelihood sequence detection method based on a Viterbi algorithm; removing the influence of a phase pulse function through matched filtering processing, extracting I / Q data of a fixed sampling point in each symbol period, carrying out time domain superposition, and generating eye pattern data in real time; based on the mapping relation between the grid state variable of the SOQPSK demodulator and the CPM phase state, the maximum survival state in the Viterbi algorithm is used as a phase value, and constellation diagram data is generated in real time in combination with the survival path measurement increment; and packaging the eye diagram data and the constellation diagram data to an upper computer for display, performing performance parameter evaluation and feeding back to a demodulator. The FPGA generates eye diagram and constellation diagram data in real time and sends the eye diagram and constellation diagram data to the upper computer for display and performance evaluation, and visual performance monitoring is provided. And parameters of the demodulator are adjusted in real time, so that a closed loop is integrally formed.

Methods, systems, and apparatus for signal monitoring by a memory system are described. A memory system may receive signaling (e.g., from a host system), and may sample the signal and generate an eye pattern. During a normal mode of operation, the memory system monitors characteristics of the eye pattern to improve signaling. The memory system may determine a voltage level of the signaling based on one or more input parameters and a sampling time associated with the signaling. An indication of the voltage level of the signaling may be stored (e.g., to a register of the memory system), and may be periodically transmitted to the host system.

A method for identifying margins in an eye opening includes capturing first data from a data signal based on edges in a data clock signal, capturing second data from the data signal responsive to edges in a phase shifted version of the data clock signal, iteratively increasing phase difference between the phase shifted version of the data clock signal and the data clock signal when the first data initially matches the second data until the first data differs from the second data, iteratively decreasing the phase difference between the phase shifted version of the data clock signal and the data clock signal when the first data initially differs from the second data until the first data matches the second data, and determining the margin of the eye opening when the first data begins to match the second data or when the first data begins to differ from the second data.

The invention relates to the technical field of waveform display, in particular to an eye pattern generation method and system based on a high-resolution oscilloscope, and the method comprises the following steps: analyzing a channel impact response, extracting effective delay, defining an operation kernel range, constructing sparse inverse filtering compensation distortion, judging an edge generation eye pattern track, and quantifying noise as a weight to carry out sub-pixel diffusion. According to the method, a delay set is established, a non-linear participation range is made to fit real channel behaviors, a high-order cross product is constructed in an original waveform, detail compensation of amplitude and time is enhanced in a sparse inverse filtering mode, and zero point and amplitude characteristics of a second derivative are combined, so that the error rate contour is deduced. A real edge interval is separated, continuous diffusion is formed in a histogram through a discrete probability weight constructed by quantizing noise, so that a statistical form of a low-probability region is completely reserved, and an error code related boundary presents a regular distribution structure in combination with a tail probability gradient.

This invention provides a method, system, and medium for crosstalk suppression and timing optimization in high-frequency circuits. A sensor array is deployed along the critical signal path to simultaneously acquire high-frequency crosstalk spectrum and timing eye diagram parameters, generating a crosstalk intensity matrix (CIM) and a timing margin heatmap (TMM) to achieve multi-dimensional quantitative characterization of signal integrity. Based on the CIM, the main interference source is located, and the impedance of the affected line is dynamically adjusted and a reverse compensation current is injected to cancel high-frequency crosstalk at its source. The margin attenuation is predicted using a pre-trained model, and the clock phase of the affected line is fine-tuned to compensate for timing deviations. The optimized efficiency index per unit energy consumption after compensation is calculated, triggering a dynamic update or re-compensation mechanism for the strategy library. This invention achieves dynamic synergy between crosstalk suppression and timing optimization based on a closed-loop architecture composed of monitoring data, neural network prediction, dual-loop compensation, energy efficiency verification, and strategy learning.

The invention relates to an exception handling circuit and exception handling method for clock data recovery. According to the method and the device, the data sender can be supported to implement data scrambling with direct current balance as a target on the target data to be transmitted, so that the data receiver can receive scrambled data with a direct current balance characteristic through a physical channel. On the basis, periodic samples of sampled data obtained by sampling the scrambled data by a data receiver can be obtained, and when it is judged that a sampling clock phase of the scrambled data is locked at a false eye position in an eye pattern of the scrambled data according to periodic direct-current unbalance deviation of a plurality of continuous periodic samples, the scrambled data is locked at the false eye position in the eye pattern of the scrambled data. According to the method, the phase of the sampling clock can be separated from the false eye position by implementing unlocking phase adjustment on the phase of the sampling clock, so that the dynamic calibration of the phase of the sampling clock can be recovered in time, and the failure risk of clock data recovery can be reduced.

The application discloses a method for determining an eye diagram gear, a display device and an electronic device, and is used for solving the problem that due to the performance deviation of different combinations, the output difference of high-speed signals cannot be compensated optimally, and then the yield loss is caused. The method comprises the following steps: reading the combination information of different modules contained in the display device, wherein the combination information comprises manufacturer information; determining the mapping relationship between the different combination information and the eye diagram gear, wherein the mapping relationship is obtained by debugging the eye diagram gear corresponding to the different combination information based on the image signal quality of the eye diagram; and determining the eye diagram gear matched with the read combination information according to the mapping relationship between the different combination information and the eye diagram gear, wherein the eye diagram gear matched with the combination information is used for determining the optimal compensation value of the image signal, and the optimal compensation value is used for signal compensation of the image signal.