313 results about "Eye pattern" patented technology

Die or chip interconnect clock skew compensation can be performed for a multi -IC (Integrated Circuit) module. A timing margin or eye-width parameter (for example, a setup or hold time) for each of one or more interconnect lanes may be measured at a first die or chip of the multi - IC module that is receiving data and clock signals from a second die or chip of the multi -IC module. Compensation information can be determined based on the measured timing margin or eye-width parameter for each of one or more interconnect lanes. Compensation for clock skew can then be based on the determined compensation information.

The invention relates to a retiming circuit applied to an ultra-high-speed and high-precision DAC (Digital-to-Analog Converter), which comprises an alignment module, a cross point adjusting module, a coding module, a phase detection module and a digital module, the coding module is connected with the alignment module, the phase detection module is connected with the cross point adjusting module and the coding module, and the digital module is connected with the phase detection module and the alignment module. According to the circuit structure provided by the invention, the sampling clock can be accurately aligned to the center of a data eye pattern, so that the delay difference between a clock tree and a data path caused by process deviation and the like is effectively reduced, the high-frequency spurious suppression performance is improved by eliminating nonlinear distortion caused by time sequence errors, the SFDR is greatly improved, and compared with a traditional scheme, the SNR is effectively improved.

The invention discloses a method and system for testing a direct-current offset compensation circuit of an optical transceiving driving chip and a medium, and relates to the technical field of photoelectric integrated circuit testing, and the method comprises the following steps: carrying out the time alignment of a test waveform and an offset track of the optical transceiving driving chip, extracting the phase dislocation amount and the amplitude kick amount between beats, and carrying out the calculation of the phase offset amount and the amplitude kick amount; a continuous change result is mapped into a time sequence conflict observation band which is used for identifying a beat overlapping region; and on the basis of the phase dislocation trend of the time sequence conflict observation band, determining a beat overlapping point of the direct current offset compensation loop, and generating an overlapping beat index according to the duration of amplitude kick and the polarity direction for identifying an interference node. According to the method, millisecond-level beat observation and microsecond-level overlapping identification are realized in a test stage, interference nodes are accurately extracted, a coupling strength graph is constructed, and by combining beat rearrangement and an energy unloading strategy, nonlinear oscillation is inhibited, oscillation and overload risks are reduced, eye pattern quality and error code stability are improved, and chip test precision and robustness are enhanced.

The invention relates to the technical field of cable fault detection, in particular to a fault detection method and system for a DAC high-speed cable, and the method comprises the steps: decomposing test data, obtaining a plurality of component signals, and obtaining the change degree of the component signals according to the fluctuation of each component signal; setting sliding windows, and obtaining the direction anisotropy of adjacent sliding windows according to the change trend of data in the sliding windows; further obtaining the change complexity of each component signal; the attenuation possibility of the time domain data is further obtained; obtaining the variability of the time domain data according to the attenuation possibility of the time domain data and the opening height and the opening width of the eye pattern data; the attenuation degree of the time domain data is obtained; abnormal data are obtained through screening according to the attenuation degree of the time domain data, and the fault of the DAC high-speed cable is detected; according to the method, signal attenuation caused by electromagnetic interference and the like in the data transmission process of the DAC high-speed cable can be accurately analyzed, early warning is performed in time, and signal loss is avoided.

The invention relates to the technical field of optical fiber communication, in particular to a method and a system for realizing optical fiber interconnection transmission by a high-speed serial transceiver based on an FPGA (Field Programmable Gate Array). Constructing a link feature baseline and combining with a multi-dimensional weighted quality index to drive an improved particle swarm algorithm to dynamically adjust a pre-emphasis coefficient and a receiving equalization parameter of the transceiver; signal jitter characteristics are extracted, clock data are dynamically adjusted based on the jitter characteristics and the bit error rate to recover the loop bandwidth, a forward error correction mode is dynamically switched through hysteresis threshold logic, and time delay and error correction capability are balanced; and continuously updating the baseline parameters through a closed-loop feedback mechanism to realize real-time adjustment and optimization of the quality of the optical fiber communication link.

This disclosure relates to a receiver device for pulse amplitude modulation (PAM) signals. The receiver device calculates a transmitter dispersion eye closure quaternary (TDECQ). The receiver device first obtains a signal, wherein the signal is based on a PAM signal sent by a transmitter device over a channel to the receiver device, and filters the obtained signal. Further, the transmitter device equalizes the filtered signal using a FFE with multiple taps, and filters the equalized signal output by the FFE using a 2-tap post filter, wherein high frequency noise caused by the FFE is compressed. The receiver device applies a Max-Log-Map (MLM) algorithm on the filtered signal output by the 2-tap post filter, reconstructs a signal constellation of the PAM signal based on the result of the MLM algorithm, and calculates a TDECQ based on the reconstructed signal constellation.

The invention discloses a statistical eye pattern generation method and device and a storage medium. The method comprises the following steps: inputting a step signal at a transmitting end of a channel, and determining a step response function based on the step signal; introducing a dithering signal at the transmitting end, and determining a dithering probability model based on the dithering signal; based on a jitter probability model, determining a jitter value set and a jitter probability set; determining a state transition probability matrix between the first moment and the second moment in the input step signal; based on the state transition probability matrix and the step response function, establishing an equivalent response distribution kernel for the target sampling moment; performing convolution operation on the voltage probability distribution at the previous sampling moment of the target sampling moment and the equivalent response distribution kernel, determining the voltage probability distribution at the target sampling moment, and determining the voltage probability distribution at multiple sampling moments; and generating a statistical eye pattern based on the voltage probability distribution at the plurality of sampling moments. The method has the technical effect of assisting in improving the credibility of simulation evaluation.

The invention relates to a UCIe-based data link test method and device, and a chip. The method comprises the steps that a local core particle obtains an eye pattern inspection result which is returned by a remote core particle and is associated with any data channel in a data link; according to the eye pattern inspection result and a preset eye pattern threshold interval parameter, determining whether the eye pattern inspection result accords with an interval range allowed by the eye pattern threshold interval parameter; determining any data channel as a qualified channel under the condition that the eye pattern inspection result accords with an interval range allowed by the eye pattern threshold interval parameter; and under the condition that the eye pattern inspection result does not accord with the interval range allowed by the eye pattern threshold interval parameter, determining any data channel as an unqualified channel. According to the technical scheme, the available bandwidth of the data link can be improved, the stable communication rate of the data link can be ensured, the flexibility of configuration about link training can be improved, and the method and the device can be compatible with a related UCIe protocol.

The invention discloses an LPO wired receiver adopting adaptive CTLE based on a genetic algorithm, and the receiver comprises an analog front end, a data sampler, an edge sampler, an error sampler, a 1: 32 demultiplexer, a verification module, an eye pattern monitor, a genetic algorithm module, clock recovery logic, and a clock path. The eye pattern monitor is used for calculating the eye pattern closure degree according to the data of the data sampler and the error of the error sampler and outputting the eye pattern closure degree to the genetic algorithm module; and the genetic algorithm module is used for realizing parameter adaptive control of a continuous time linear equalizer CTLE and a variable gain amplifier VGA in the analog front end. The invention aims to apply the genetic algorithm to the adaptive equalization of the adaptive continuous time linear equalizer, so that the adaptive continuous time linear equalizer has stronger global search capability and lower power consumption and is not easy to fall into local optimum, and the complexity and power consumption of the adaptive continuous time linear equalizer are reduced. And the real-time and energy-saving requirements are met.

The invention relates to the technical field of communication signals, in particular to an eye pattern limit offset determination method and system, and the method comprises the steps: carrying out the data bias sampling in an analog circuit according to a current bias data code value, obtaining the current bias data, comparing the current normal data with the current bias data through a serial-parallel conversion module, obtaining the waveform comparison data, and determining the eye pattern limit offset according to the waveform comparison data. And performing ratio calculation on the total bit number and the error bit number according to the waveform comparison data to obtain a current bit error rate, judging whether the current bit error rate is greater than a bit error rate threshold value or not, if not, returning to perform bias data code value regulation and control, and if so, obtaining a previous bias data code value of the current bias data code value. And determining the limit offset of the eye pattern according to the last bias data code value. According to the invention, the recognition efficiency of the eye pattern limit offset can be improved.

The invention relates to a performance monitoring method of a forward transmission network, an optical module, equipment and a storage medium. The method comprises the following steps: acquiring an optical signal which is sent from a far-end radio frequency unit and is transmitted to a receiving unit of a performance monitoring optical module, and converting the optical signal into an electric signal; performing eye pattern analysis on the electric signal to generate an eye pattern distribution histogram; the eye pattern distribution histogram is used for representing distribution conditions of different signal amplitudes in different intervals; determining a multipath interference deformation factor according to the deformation condition of the eye pattern distribution histogram of the electric signal compared with the eye pattern distribution histogram before signal transmission; and determining a signal-to-noise ratio estimation value according to the multipath interference deformation factor, and determining a performance monitoring result of the forward transmission network according to the signal-to-noise ratio estimation value. By adopting the method, the link quality of the forward network can be accurately evaluated.

The invention discloses a three-dimensional eyeball model reconstruction method and system based on multi-modal fusion, and the method comprises the following steps: S1, feature extraction: respectively extracting features of an original infrared eye diagram and a generated event diagram, carrying out the calculation of channel attention, and fusing the features of two modals in a spatial dimension; s2, time sequence feature fusion: compressing spatial dimensions through global average pooling, taking an ordered sequence of eye features and an ordered sequence of event graph features after spatial multi-modal fusion, and outputting corresponding eye parameters; s3, three-dimensional eyeball model reconstruction: defining an eyeball as a sphere with an eyeball center Oe and an eyeball radius re; generating discrete point clouds from pupils and irises of the 3D eye model; and S4, carrying out weak supervision on few samples. According to the method, the model can better learn a deformable eyeball model, and a robust and high-precision sight line estimation task can be carried out under the condition of a small number of samples.

The invention discloses an eye pattern generation method based on channel simulation, a storage medium and electronic equipment, and the method comprises the steps: carrying out the channel simulation according to a target channel parameter, a signal source parameter and an initial code pattern sequence, and generating jitter-free initial eye pattern data; obtaining a deterministic jitter parameter and a random jitter parameter, and generating a deterministic jitter time sequence based on the obtained deterministic jitter parameter and the initial code pattern sequence; generating a random jitter time sequence based on the obtained random jitter parameter; synthesizing the deterministic jitter time sequence and the random jitter time sequence to generate a total jitter time sequence offset sequence; and modulating time sequence information in the initial eye pattern data by using the total jitter time sequence offset sequence to generate a target eye pattern. Simulation of deterministic jitter and random jitter is added in the channel simulation process, and the consistency of the simulation result and the signal characteristic of a real communication scene is greatly improved.

Systems and methods related for duo-binary transceivers with adaptive channel equalization are described. An example method for adapting a channel between a first duo-binary transceiver and a second duo-binary transceiver, different from the first duo-binary transceiver, where the transmitter includes a feed-forward equalizer (FFE), is described. The method includes, at a receiver associated with the second duo-binary transceiver, selectively processing information at a given time from only an upper eye or a lower eye of a received duo-binary signal to determine updated coefficients for the feed-forward equalizer (FFE) of the transmitter associated with the first duo-binary transceiver. The method further includes using a backchannel between the transmitter and the receiver, sending the updated coefficients to the transmitter. The method further includes transmitting duo-binary signals that are equalized using the updated coefficients for the FFE of the transmitter associated with the first duo-binary transceiver.

The invention provides a serdes chip performance control parameter optimization method and device, and the method comprises the steps: setting the value ranges of all configuration parameters of a preset configuration type in a serdes chip, and generating an initial particle swarm according to each configuration parameter and the corresponding value range; inputting the initial particle swarm as an input particle swarm into a first round of iteration; each round of iteration comprises the steps of inputting each particle in the input particle swarm into a corresponding serdes chip, obtaining an eye diagram corresponding to each particle, and obtaining a target value corresponding to each particle according to the eye diagram corresponding to each particle; obtaining the maximum target value in all particles in the input particle swarm as a local optimal value, and obtaining the local optimal value with the maximum target value in all current iteration rounds as a global optimal value; and after the termination condition is met, the optimal configuration parameter of the serdes chip is obtained, so that the optimization efficiency and the channel compensation performance are improved.

The invention discloses a high-speed link signal integrity analysis general modeling method and system based on fast time domain simulation and transfer learning. The method comprises the following steps: S1, selecting a high-speed link structure to be modeled; s2, extracting a pure edge signal without intersymbol interference based on a multi-edge response method, and calculating a reconstructed transient waveform and a worst eye pattern; s3, only performing a small amount of high-precision transient simulation and preprocessing in the target domain, and constructing a target domain data set; s4, designing special neural network DNN and TCN models, and constructing a source domain data pre-training model by using source domain fast time domain simulation data; and S5, based on a transfer learning strategy, the model is finely tuned by using limited target domain data. The method is used for constructing the high-speed link signal integrity agent model, so that under the condition that the number of times of high-precision transient simulation is remarkably reduced, the model prediction precision and training efficiency are improved, and the problems that traditional transient simulation consumes too long time, ANN model data dependence is large, and the transfer learning application range is limited are solved.

The invention belongs to the technical field of time sequence calibration, and relates to a core particle parallel interface time sequence calibration method, which comprises the following steps of: introducing a phase interpolator with 180-degree phase deviation in a clock path of a receiving end, and positioning a sampling clock at the center of a data eye diagram; in a data path of a receiving end, a coarse adjustment delay calibration unit is firstly adopted to carry out periodic delay compensation, and the coarse adjustment delay calibration unit adopts a numerical control delay line structure to carry out delay adjustment; and then, a fine adjustment delay calibration unit is adopted to further realize sub-period-level delay adjustment, the fine adjustment delay calibration unit adopts a phase interpolator structure and a dynamic fine adjustment calibration mechanism, and finally, the delayed data signal and the clock signal are aligned at a receiving end. According to the invention, the binary search method is introduced, the positioning speed of the optimal delay configuration is obviously improved, delay drift is fully considered, a dynamic calibration mechanism is added, a sampling window is constructed based on a phase interpolator, and a high-precision and dynamic calibration effect is realized.

The utility model relates to the technical field of display, and discloses a display module and a display device. The display module can comprise a display panel, a second chip on film, at least two first chip on films and at least two rigid circuit boards, connecting a first chip on film between each rigid circuit board and the display panel; the second chip on film is connected between at least part of two adjacent rigid circuit boards. According to the display module, signal attenuation of at least part of signals on the connector and the flexible circuit board can be reduced, and the eye pattern quality of a large-size high-resolution display panel can be improved; the cost can be reduced by replacing a connector and a flexible circuit board with the second chip-on-film, and the thickness and the size of the second chip-on-film are small, so that the ultrathin design of the display device is facilitated; the second chip-on-film and the first chip-on-film can be subjected to a binding process at the same time, productivity improvement is facilitated, compared with manual insertion, the binding process is higher in precision, and product yield improvement is facilitated.

The invention relates to a PSRAM controller, in particular to a PSRAM data eye pattern training system and method, and the system comprises a training control module, a write delay unit combination, a read delay unit combination, and PSRAM particles. The training control module is used for clock enabling, data sending, data receiving, data comparing, writing delay unit number control and reading delay unit number control; the write delay unit combination is used for obtaining a write delay clock by adjusting the delay of the main frequency clock so as to find the optimal position of the write data eye diagram; the read delay unit combination is used for obtaining a read delay clock by adjusting the delay of an output data strobe signal DQS of the PSRAM particles so as to find the optimal position of a read data eye diagram; the PSRAM particles are memory storage units; according to the technical scheme provided by the invention, the defect that the position of the sampling clock is difficult to dynamically adjust during the working period of the chip in the prior art can be effectively overcome.

The invention provides an optical module and a forming method of the optical module. The optical module comprises a housing which is internally provided with an accommodating cavity; the circuit board is positioned in the accommodating cavity; the chip assembly is positioned in the accommodating cavity and is coupled with the circuit board; the cooling fin assembly is located between the chip assembly and the circuit board; the heat conduction protruding block is located in the containing cavity and connected between the cooling fin assembly and the shell. Based on the above technical scheme, the heat generated by the chip assembly can be dissipated through the cooling fin assembly, the heat conduction bump and the housing in sequence, thereby effectively reducing the working temperature of the optical module, enabling the optical module to work more stably, and avoiding the problems that the sensitivity of the optical module is reduced and the parameters of an optical eye diagram are degraded at a high temperature.

The invention relates to the technical field of data storage, and discloses a method for testing the signal quality of an IO interface of a memory module, and the method comprises the steps: verifying the signal integrity of the I / O interface in the memory module based on an eye diagram analysis method; after the signal is verified to be complete, the morphological characteristics of the input eye pattern and the output eye pattern are quantitatively compared, whether morphological characteristic changes occur in the signal transmission process or not is judged, and the morphological characteristic changes at least comprise logic level flipping errors, time sequence recognition errors and signal quality degradation; if the morphological characteristics of the input eye pattern are consistent with the morphological characteristics of the output eye pattern, the test is successful; and if the morphological characteristics of the input eye pattern are inconsistent with the morphological characteristics of the output eye pattern, determining that the test fails. Visual and quantitative verification of signal integrity is realized through eye pattern analysis, multi-dimensional indexes such as voltage, time sequence and noise are covered, and the signal transmission quality is reflected more comprehensively compared with a single parameter test.

The invention relates to an LPDDR4X simulation method and system based on a statistics theory. The method comprises the steps that a single-byte BYTE time domain simulation platform used for simulating LPDDR4X signal transmission characteristics is constructed; routing delay analysis is carried out on packaging and PCB channels corresponding to each signal in the single-byte BYTE, time sequence inconsistency in signal transmission is captured, and then the influence of phase crosstalk noise on eye height is captured; carrying out pulse response analysis on the signal, and quantifying ISI noise basic data caused by packaging and a PCB channel; independently analyzing the influence of crosstalk noise on each signal to obtain direct influence data of noise on eye height; processing ISI noise basic data and direct influence data by utilizing an MATLAB script, and extracting a main cursor voltage value, an ISI noise amplitude and crosstalk noise; according to the main cursor voltage value, the ISI noise amplitude and the crosstalk noise, the final eye pattern eye height is calculated. According to the method, the problem that a traditional simulation method is insufficient in eye pattern height evaluation is solved, and more accurate and efficient simulation support can be provided for high-speed low-power-consumption DDR design.

The invention provides an eye pattern intersection point estimation method and system, relates to the technical field of communication link evaluation, and solves the problems of insufficient estimation precision and low efficiency caused by sparse data of an intersection point region in an existing eye pattern test. The method comprises the following steps: acquiring VNA frequency domain data, converting the VNA frequency domain data into time domain data, and performing convolution calculation by using a random sequence to generate a convolution sequence; according to a preset unit interval length, segmenting the convolution sequence into a plurality of eye pattern data units to form an eye pattern data set; screening out a rising edge data subset and a falling edge data subset based on the position relationship between the starting point and the ending point of each eye pattern data unit in the eye pattern data set and the middle position of the eye pattern; and respectively carrying out average processing to obtain rising edge data and falling edge data, and carrying out linear fitting to obtain an intersection point of the rising edge data and the falling edge data as an eye pattern intersection point. According to the method, calculation can be completed only through a small number of basic data points, the processing burden is greatly relieved, and the testing efficiency is improved.

The invention provides a signal quality detection method. A to-be-detected eye pattern is formed based on eye pattern original data under the same temperature and voltage; the target indexes comprise at least one of a center point centering index, an eye diagram boundary index, an eye diagram area index and an eye diagram shape balance index; the eye diagram boundary index comprises an initial center point of a to-be-detected eye diagram and a minimum read-write frame drawn based on the initial center point; the target indexes comprise at least one of a center point centering index, an eye diagram boundary index, an eye diagram area index and an eye diagram shape balance index; and determining a target evaluation value corresponding to the target temperature and the target voltage according to the offset of the initialization center point and the collapse range of the eye diagram under the condition that the at least one target index is determined to accord with the respective corresponding condition threshold value. Through evaluation of the center point centering index, the eye pattern boundary index, the eye pattern area index and the eye pattern shape balance index, deviation introduced by subjective judgment during manual analysis is reduced, in addition, the corresponding relation between the temperature voltage and the evaluation value is calculated, measurement is replaced by calculation, and the detection period of the signal quality is shortened.

The invention provides an eye pattern search space optimization method and system and a computer storage medium. The eye pattern search space optimization method comprises the steps of presetting an initial search space of a to-be-optimized circuit parameter; constructing an initial simulation case combination according to the initial search space; generating a plurality of simulation netlists and performing simulation to obtain corresponding eye pattern performance response values; establishing a second-order polynomial meta model according to the eye pattern performance response value and the circuit parameters; calculating an eye diagram performance response maximum value and a circuit parameter value corresponding to the eye diagram performance response maximum value; presetting a scaling coefficient, and updating the search space according to the eye pattern performance response maximum value and the corresponding circuit parameter value; and updating the simulation case combination according to the updated search space to carry out iterative calculation on the search space, and outputting an optimal search space. According to the scheme, the search range can be automatically focused on the potential optimal region, and the global optimal parameter combination for optimizing the eye height and eye width performance is accurately positioned with the minimum simulation times, so that the signal integrity judgment of the high-speed serial link is facilitated.

The invention provides a DDR wafer test anomaly detection method and device based on machine learning, and the method comprises the steps: obtaining a time sequence eye pattern synchronously collected in a DDR wafer test process and time sequence waveform data related to total jitter, deterministic jitter and random jitter, and carrying out the clock edge phase segmentation alignment of differential time sequence sampling points in the time sequence waveform data, phase domain dense sampling data is constructed, adaptive sparse coding is completed in combination with DDR jitter physical priori, noise and normal process fluctuation related components are removed, defect sensitive sparse components are obtained, variational mode decomposition is performed, components related to process drift, normal process fluctuation and abrupt change abnormity are obtained, and the defect sensitive sparse components are subjected to sparse coding; and the abrupt change anomaly correlation component is extracted as target detection data, a preset machine learning model is input, an anomaly mode correlation result is generated, a DDR wafer test anomaly detection result is output based on the result, and a corresponding test setting item adjustment instruction is generated. According to the invention, the overall efficiency and the result reliability of the DDR wafer test can be improved.

The invention relates to the technical field of jitter analysis, in particular to a high-speed oscilloscope eye diagram real-time jitter detection method and system, and the method comprises the following steps: carrying out high-speed collection waveform zero-cross detection to obtain a timestamp, calculating offset grouping to obtain a cross-period edge time sequence, merging a jump cluster according to a sequence hierarchy cluster, calculating offset, obtaining a drift trend vector, and calculating the jitter of the drift trend vector; and based on the trend vector distribution compensation weight, weighting and correcting the time coordinate, calling a corrected coordinate detection period boundary to calculate a difference value exceeding a threshold value, triggering correction to obtain a period correction rear edge coordinate, and extracting a jitter frequency amplitude according to corrected coordinate Fourier analysis to generate an eye pattern jitter detection result. Phase correlation is established based on a cross-period sequence, an analyzable offset mode is formed through a clustering identification distribution structure, accumulated deviation is suppressed through a drift trend and weight correction, an abnormal period is calibrated through period dynamic discrimination, and the relation between a jitter structure and amplitude is separated through frequency analysis, so that the overall stability and integrity are enhanced.

A method for identifying margins in an eye opening includes capturing first data from a data signal based on edges in a data clock signal, capturing second data from the data signal responsive to edges in a phase shifted version of the data clock signal, iteratively increasing phase difference between the phase shifted version of the data clock signal and the data clock signal when the first data initially matches the second data until the first data differs from the second data, iteratively decreasing the phase difference between the phase shifted version of the data clock signal and the data clock signal when the first data initially differs from the second data until the first data matches the second data, and determining the margin of the eye opening when the first data begins to match the second data or when the first data begins to differ from the second data.

The invention relates to an impedance determination method and device, computer equipment, a readable storage medium and a program product. The method comprises the steps that first eye diagrams of an on-chip terminal are acquired, and the first eye diagrams are eye diagrams of an electric signal under target equalizer parameter conditions corresponding to candidate impedance values of the on-chip terminal; each candidate impedance value corresponds to a target equalizer parameter; according to a first preset condition and the eye diagram parameters in the first eye diagrams, obtaining a target eye diagram from the first eye diagrams; wherein the first preset condition represents a screening condition related to the eye pattern parameter; and taking the candidate impedance value corresponding to the target eye diagram as a target impedance value. According to the method, the target impedance value is adopted to design the chip system, so that the performance of the chip is improved.

The present application relates to the field of integrated circuit technologies and provides a training system and method for a high-speed parallel port IP. The system includes: a high-speed transceiver for transmitting and receiving data and command signals; a delay and reference voltage regulator for performing delay adjustment and reference voltage adjustment; a multi-branch generator for separately generating command combinations, data sequences, and adjustment signals; a microprocessor for controlling the generation of the multi-branch generator based on a first instruction combination; and an instruction memory for storing the first instruction combination. The microprocessor is further configured to generate, based on the first instruction combination, a first scanning strategy including a first scanning object, which is determined based on a first high-speed parallel port IP. The microprocessor controls the generation of the multi-branch generator to utilize the delay and reference voltage regulator to implement the first scanning strategy for the first scanning object in the data and command signals so as to complete eye diagram adaptation. In this way, flexibility and compatibility are achieved.