160 results about "Eye pattern" patented technology

The invention relates to the technical field of communication signals, in particular to an eye pattern limit offset determination method and system, and the method comprises the steps: carrying out the data bias sampling in an analog circuit according to a current bias data code value, obtaining the current bias data, comparing the current normal data with the current bias data through a serial-parallel conversion module, obtaining the waveform comparison data, and determining the eye pattern limit offset according to the waveform comparison data. And performing ratio calculation on the total bit number and the error bit number according to the waveform comparison data to obtain a current bit error rate, judging whether the current bit error rate is greater than a bit error rate threshold value or not, if not, returning to perform bias data code value regulation and control, and if so, obtaining a previous bias data code value of the current bias data code value. And determining the limit offset of the eye pattern according to the last bias data code value. According to the invention, the recognition efficiency of the eye pattern limit offset can be improved.

The invention discloses an eye pattern generation method based on channel simulation, a storage medium and electronic equipment, and the method comprises the steps: carrying out the channel simulation according to a target channel parameter, a signal source parameter and an initial code pattern sequence, and generating jitter-free initial eye pattern data; obtaining a deterministic jitter parameter and a random jitter parameter, and generating a deterministic jitter time sequence based on the obtained deterministic jitter parameter and the initial code pattern sequence; generating a random jitter time sequence based on the obtained random jitter parameter; synthesizing the deterministic jitter time sequence and the random jitter time sequence to generate a total jitter time sequence offset sequence; and modulating time sequence information in the initial eye pattern data by using the total jitter time sequence offset sequence to generate a target eye pattern. Simulation of deterministic jitter and random jitter is added in the channel simulation process, and the consistency of the simulation result and the signal characteristic of a real communication scene is greatly improved.

The invention relates to the technical field of data storage, and discloses a method for testing the signal quality of an IO interface of a memory module, and the method comprises the steps: verifying the signal integrity of the I / O interface in the memory module based on an eye diagram analysis method; after the signal is verified to be complete, the morphological characteristics of the input eye pattern and the output eye pattern are quantitatively compared, whether morphological characteristic changes occur in the signal transmission process or not is judged, and the morphological characteristic changes at least comprise logic level flipping errors, time sequence recognition errors and signal quality degradation; if the morphological characteristics of the input eye pattern are consistent with the morphological characteristics of the output eye pattern, the test is successful; and if the morphological characteristics of the input eye pattern are inconsistent with the morphological characteristics of the output eye pattern, determining that the test fails. Visual and quantitative verification of signal integrity is realized through eye pattern analysis, multi-dimensional indexes such as voltage, time sequence and noise are covered, and the signal transmission quality is reflected more comprehensively compared with a single parameter test.

The invention provides an eye pattern intersection point estimation method and system, relates to the technical field of communication link evaluation, and solves the problems of insufficient estimation precision and low efficiency caused by sparse data of an intersection point region in an existing eye pattern test. The method comprises the following steps: acquiring VNA frequency domain data, converting the VNA frequency domain data into time domain data, and performing convolution calculation by using a random sequence to generate a convolution sequence; according to a preset unit interval length, segmenting the convolution sequence into a plurality of eye pattern data units to form an eye pattern data set; screening out a rising edge data subset and a falling edge data subset based on the position relationship between the starting point and the ending point of each eye pattern data unit in the eye pattern data set and the middle position of the eye pattern; and respectively carrying out average processing to obtain rising edge data and falling edge data, and carrying out linear fitting to obtain an intersection point of the rising edge data and the falling edge data as an eye pattern intersection point. According to the method, calculation can be completed only through a small number of basic data points, the processing burden is greatly relieved, and the testing efficiency is improved.

The invention provides a DDR wafer test anomaly detection method and device based on machine learning, and the method comprises the steps: obtaining a time sequence eye pattern synchronously collected in a DDR wafer test process and time sequence waveform data related to total jitter, deterministic jitter and random jitter, and carrying out the clock edge phase segmentation alignment of differential time sequence sampling points in the time sequence waveform data, phase domain dense sampling data is constructed, adaptive sparse coding is completed in combination with DDR jitter physical priori, noise and normal process fluctuation related components are removed, defect sensitive sparse components are obtained, variational mode decomposition is performed, components related to process drift, normal process fluctuation and abrupt change abnormity are obtained, and the defect sensitive sparse components are subjected to sparse coding; and the abrupt change anomaly correlation component is extracted as target detection data, a preset machine learning model is input, an anomaly mode correlation result is generated, a DDR wafer test anomaly detection result is output based on the result, and a corresponding test setting item adjustment instruction is generated. According to the invention, the overall efficiency and the result reliability of the DDR wafer test can be improved.

The invention relates to the technical field of jitter analysis, in particular to a high-speed oscilloscope eye diagram real-time jitter detection method and system, and the method comprises the following steps: carrying out high-speed collection waveform zero-cross detection to obtain a timestamp, calculating offset grouping to obtain a cross-period edge time sequence, merging a jump cluster according to a sequence hierarchy cluster, calculating offset, obtaining a drift trend vector, and calculating the jitter of the drift trend vector; and based on the trend vector distribution compensation weight, weighting and correcting the time coordinate, calling a corrected coordinate detection period boundary to calculate a difference value exceeding a threshold value, triggering correction to obtain a period correction rear edge coordinate, and extracting a jitter frequency amplitude according to corrected coordinate Fourier analysis to generate an eye pattern jitter detection result. Phase correlation is established based on a cross-period sequence, an analyzable offset mode is formed through a clustering identification distribution structure, accumulated deviation is suppressed through a drift trend and weight correction, an abnormal period is calibrated through period dynamic discrimination, and the relation between a jitter structure and amplitude is separated through frequency analysis, so that the overall stability and integrity are enhanced.

The present invention relates to the technical field of optical communications and particularly relates to a method for implementing a signal-to-noise ratio reporting function based on a CDR solution, and an optical module. In the present invention, eye diagram data is obtained by means of scanning data in a communication link, and after the eye diagram data is processed, the average value thereof is obtained, so as to obtain a signal-to-noise ratio value to be reported, thereby achieving SNR reporting of the optical module based on the CDR solution, effectively improving the accuracy and stability of the SNR reporting, enabling the optical module based on the CDR solution to also effectively measure the link SNR indicator health status, and providing an effective test method and means for testing the chromatic dispersion of the optical module, investigating the influence of temperature and MPI on the SNR, and the like. In addition, a bit error rate can also be reduced by guiding the configuration of FEC correction and equalization compensation, thereby improving the quality of signal transmission.

This invention provides a method and system for testing the high-temperature transmission characteristics of low-capacitance ESD devices, comprising: connecting a low-capacitance ESD device array under test in parallel to a differential signal line of a test channel; simultaneously applying a PRBS code stream signal and a surge pulse superimposed on the PRBS code stream signal to the test channel under a preset temperature environment; extracting the instantaneous drop depth of the eye diagram opening after the surge impact and the recovery time for the eye diagram opening to return to the pre-impact level based on the aligned eye diagram opening change curve; determining that the low-capacitance ESD device array does not meet the protection requirement of no packet loss during surge impact under high-temperature conditions when the instantaneous drop depth exceeds a preset eye diagram drop threshold or the recovery time exceeds a preset recovery time threshold; and determining that the low-capacitance ESD device array does not meet the protection requirement of no packet loss during surge impact under high-temperature conditions when simulating actual working conditions. This invention can simultaneously evaluate the impact of high-temperature environment on the signal transmission quality and surge protection capability of low-capacitance ESD devices under simulated actual working conditions.

This invention discloses a control method, system, and medium for a DC offset compensation circuit of an optical transceiver driver chip, relating to the field of optoelectronic integrated circuit testing technology. The method includes the following steps: time-aligning the test waveform and bias trajectory of the optical transceiver driver chip; extracting the phase misalignment and amplitude jump between beats; and mapping the continuous changes to a timing conflict observation band for identifying beat overlap regions. Based on the phase misalignment trend of the timing conflict observation band, the beat overlap points of the DC offset compensation loop are determined, and an overlap beat index is generated based on the duration and polarity of the amplitude jump to identify interfering nodes. This invention achieves millisecond-level beat observation and microsecond-level overlap identification during the testing phase, accurately extracting interfering nodes and constructing a coupling strength map. Combined with beat rearrangement and energy unloading strategies, it suppresses nonlinear oscillations, reduces oscillation and overload risks, improves eye diagram quality and bit error rate stability, and enhances the accuracy and robustness of chip testing.

Methods, systems, and devices for signal monitoring by a memory system are described. A memory system may receive signaling (e.g., from a host system) and may sample the signal and generate an eye diagram. During a normal mode of operation, the memory system monitor characteristics of the eye diagram to improve signaling. The memory system may determine a voltage level of the signaling based on one or more input parameters and sampling times associated with the signaling. An indication of the voltage level of the signaling may be stored (e.g., to a register of the memory system) and may be periodically transmitted to the host system.

The invention discloses an SOQPSK demodulation performance monitoring method and system based on upper computer visual feedback. An SOQPSK signal is demodulated by adopting a maximum likelihood sequence detection method based on a Viterbi algorithm; removing the influence of a phase pulse function through matched filtering processing, extracting I / Q data of a fixed sampling point in each symbol period, carrying out time domain superposition, and generating eye pattern data in real time; based on the mapping relation between the grid state variable of the SOQPSK demodulator and the CPM phase state, the maximum survival state in the Viterbi algorithm is used as a phase value, and constellation diagram data is generated in real time in combination with the survival path measurement increment; and packaging the eye diagram data and the constellation diagram data to an upper computer for display, performing performance parameter evaluation and feeding back to a demodulator. The FPGA generates eye diagram and constellation diagram data in real time and sends the eye diagram and constellation diagram data to the upper computer for display and performance evaluation, and visual performance monitoring is provided. And parameters of the demodulator are adjusted in real time, so that a closed loop is integrally formed.

A method for identifying margins in an eye opening includes capturing first data from a data signal based on edges in a data clock signal, capturing second data from the data signal responsive to edges in a phase shifted version of the data clock signal, iteratively increasing phase difference between the phase shifted version of the data clock signal and the data clock signal when the first data initially matches the second data until the first data differs from the second data, iteratively decreasing the phase difference between the phase shifted version of the data clock signal and the data clock signal when the first data initially differs from the second data until the first data matches the second data, and determining the margin of the eye opening when the first data begins to match the second data or when the first data begins to differ from the second data.

The invention relates to the technical field of waveform display, in particular to an eye pattern generation method and system based on a high-resolution oscilloscope, and the method comprises the following steps: analyzing a channel impact response, extracting effective delay, defining an operation kernel range, constructing sparse inverse filtering compensation distortion, judging an edge generation eye pattern track, and quantifying noise as a weight to carry out sub-pixel diffusion. According to the method, a delay set is established, a non-linear participation range is made to fit real channel behaviors, a high-order cross product is constructed in an original waveform, detail compensation of amplitude and time is enhanced in a sparse inverse filtering mode, and zero point and amplitude characteristics of a second derivative are combined, so that the error rate contour is deduced. A real edge interval is separated, continuous diffusion is formed in a histogram through a discrete probability weight constructed by quantizing noise, so that a statistical form of a low-probability region is completely reserved, and an error code related boundary presents a regular distribution structure in combination with a tail probability gradient.

This invention provides a method, system, and medium for crosstalk suppression and timing optimization in high-frequency circuits. A sensor array is deployed along the critical signal path to simultaneously acquire high-frequency crosstalk spectrum and timing eye diagram parameters, generating a crosstalk intensity matrix (CIM) and a timing margin heatmap (TMM) to achieve multi-dimensional quantitative characterization of signal integrity. Based on the CIM, the main interference source is located, and the impedance of the affected line is dynamically adjusted and a reverse compensation current is injected to cancel high-frequency crosstalk at its source. The margin attenuation is predicted using a pre-trained model, and the clock phase of the affected line is fine-tuned to compensate for timing deviations. The optimized efficiency index per unit energy consumption after compensation is calculated, triggering a dynamic update or re-compensation mechanism for the strategy library. This invention achieves dynamic synergy between crosstalk suppression and timing optimization based on a closed-loop architecture composed of monitoring data, neural network prediction, dual-loop compensation, energy efficiency verification, and strategy learning.

The invention relates to an exception handling circuit and exception handling method for clock data recovery. According to the method and the device, the data sender can be supported to implement data scrambling with direct current balance as a target on the target data to be transmitted, so that the data receiver can receive scrambled data with a direct current balance characteristic through a physical channel. On the basis, periodic samples of sampled data obtained by sampling the scrambled data by a data receiver can be obtained, and when it is judged that a sampling clock phase of the scrambled data is locked at a false eye position in an eye pattern of the scrambled data according to periodic direct-current unbalance deviation of a plurality of continuous periodic samples, the scrambled data is locked at the false eye position in the eye pattern of the scrambled data. According to the method, the phase of the sampling clock can be separated from the false eye position by implementing unlocking phase adjustment on the phase of the sampling clock, so that the dynamic calibration of the phase of the sampling clock can be recovered in time, and the failure risk of clock data recovery can be reduced.

The application discloses a method for determining an eye diagram gear, a display device and an electronic device, and is used for solving the problem that due to the performance deviation of different combinations, the output difference of high-speed signals cannot be compensated optimally, and then the yield loss is caused. The method comprises the following steps: reading the combination information of different modules contained in the display device, wherein the combination information comprises manufacturer information; determining the mapping relationship between the different combination information and the eye diagram gear, wherein the mapping relationship is obtained by debugging the eye diagram gear corresponding to the different combination information based on the image signal quality of the eye diagram; and determining the eye diagram gear matched with the read combination information according to the mapping relationship between the different combination information and the eye diagram gear, wherein the eye diagram gear matched with the combination information is used for determining the optimal compensation value of the image signal, and the optimal compensation value is used for signal compensation of the image signal.

According to one embodiment, a method, computer system, and computer program product for adjusting output swing voltage of a Peripheral Component Interconnect Express (PCIe) system is provided. The present invention may include training a neural network, recording, in real time, lane input data of PCIe lanes comprising a PCIe link, generating eye diagrams representing the PCIe lanes based on the lane input data, predicting, by the trained neural network, predicted eye heights for the PCIe lanes, and adjusting a current output swing voltage of one or more PCIe lanes based on the predicted eye heights.

The application relates to the technical field of circuit design, and discloses a signal simulation analysis method and system. The method comprises the following steps: building a simulation structure; acquiring scattering parameters of a main control chip substrate, a PCB board and a storage chip particle substrate respectively according to the built simulation structure; optimizing a second wiring design according to the scattering parameters of the PCB board, optimizing a third wiring design according to the scattering parameters of the storage chip particle substrate, and obtaining an optimized simulation structure; inputting the optimized simulation structure into pre-configured simulation software for signal transmission simulation test, and obtaining eye diagram data; analyzing the signal quality index of corresponding pins based on the eye diagram data, and determining whether the optimized simulation structure meets the preset transmission rate requirement according to the signal quality index; and through the above method, the interconnection link outside the main control chip and the internal wiring structure of the storage chip can be optimized simultaneously.

The application discloses a DDR reference voltage parameter adjustment method, system, device and storage medium, the method comprises the following steps: obtaining a digital eye diagram of a read direction of a DDR memory and a corresponding eye height amplitude distribution; excluding invalid sampling points caused by register range limitation from sampling points of the digital eye diagram to obtain a set of valid sampling points; determining a target optimization region according to the eye height amplitude distribution of the set of valid sampling points; optimizing a read direction Vref value of the target optimization region, and synchronously adjusting a write direction Vref value and a terminal resistance parameter; compiling the read direction Vref value, the write direction Vref value and the terminal resistance parameter after adjustment into configuration code to write into a test program of a DDR memory controller; running the test program and obtaining an optimized digital eye diagram until the eye height of the optimized digital eye diagram meets a preset tolerance; and the application can avoid interference of invalid sampling points caused by register range limitation, and realize accurate determination of an optimal Vref parameter combination.

The present application relates to the technical field of jitter analysis, in particular to a high-speed oscilloscope eye diagram real-time jitter detection method and system, comprising the following steps: high-speed acquisition waveform zero-crossing detection obtains timestamp calculation offset, grouping obtains cross-period edge time sequence, according to sequence hierarchical clustering merges jump cluster, calculates deviation, obtains drift trend vector, based on trend vector, assigns compensation weight, weightedly corrects time coordinate, calls corrected coordinate to detect period boundary, calculates difference, triggers correction when difference exceeds threshold, obtains period-corrected edge coordinate, and according to correction coordinate, Fourier analysis is carried out to extract jitter frequency and amplitude to generate eye diagram jitter detection result, in the present application, phase correlation is established based on cross-period sequence, and a resolvable offset mode is formed by identifying the distribution structure through clustering, the cumulative deviation is suppressed through drift trend and weight correction, the abnormal period is calibrated through period dynamic discrimination, and the jitter structure and amplitude relationship are separated through frequency analysis, so that the overall stability and integrity are strengthened.

Systems and methods for delivering effective and accurate vision care diagnostics to remotely situated patients are provided. A diagnostic assessment may be performed by using a depth of field assessment. The chart and the person may move or be moved relative to each other until the focal length of the refractive error of the eye equals the distance to the chart. The refraction systems / methods can also be conducted at a specific fixed work distance instead of moving the chart(s) relative to the person or the person relative to the chart(s) using an algorithm to calculate the refractive state of sphere, axis and cylinder power by size of the subtended angle in relationship to the distance to the chart. The system / method may include a holographic eye testing device that includes a head mounted device and that may be operative in a virtual reality, augmented reality or mixed reality frameworks.

The invention provides a high-precision eye pattern jitter analysis method for a sampling oscilloscope. The high-precision eye pattern jitter analysis method comprises the following steps: collecting a high-speed serial signal to be detected, an orthogonal sine wave signal and a data signal; performing time base correction on the orthogonal sine wave signal, and reconstructing a precise time base; carrying out jitter measurement on the high-speed serial signal to be measured by selecting an oscilloscope mode to obtain first root-mean-square jitter and first peak-to-peak value jitter, and carrying out jitter measurement on the data signal by selecting an eye pattern mode to obtain second root-mean-square jitter and second peak-to-peak value jitter; generating a high-resolution eye pattern based on the data signal and the reconstructed precise time base, and calculating eye pattern parameters based on the form of the high-resolution eye pattern; and outputting an analysis result. According to the high-precision eye pattern jitter analysis method for the sampling oscilloscope, harmonic waves can be suppressed, the purity of time sequence reference signals can be ensured, a precise time base can be reconstructed, jitter characteristics of signals of a high-speed communication system can be comprehensively reflected, quantitative evaluation of analysis results is achieved, the measurement precision is high, and the measurement mode adaptability is high.

A simulation system and a method thereof are disclosed. In the simulation system, a system power transmission model, and analog current time-domain model and digital current time-domain model are connected to obtain power noise generated after a supply current is obtained; jitter time-domain information of each interface connection circuit model under the power noise is obtained based on transmission of a clock signal outputted from a phase lock loop, by a simulation program; next, a voltage step response of a voltage measurement point when a clock terminal of each interface connection circuit model receives an ideal signal, is simulated by the simulation program to generate a first voltage time-domain model; a system waveform is generated based on the jitter time-domain information of each interface connection circuit model under the power noise, the first voltage time-domain model and data transmission, thereby obtaining an eye diagram and time-domain jitter distribution.

A method of training a memory device is provided. In first to third DCA training steps, a score for each of first to third DCA code combinations is calculated based on an eye window size of a data signal, and in response to a tie occurring among scores, a DCA code combination is selected based on the sum of an even-eye window minimum value and an odd-eye window minimum value of the data signal.

The application provides a kind of based on eye diagram radio frequency fingerprint identification method and system, it is related to wireless communication technical field.The method comprises: the demodulation processing of transmitter signal to be identified, the separation of carrier is realized, the Gaussian baseband waveform of transmitter signal is obtained;Calculate eye diagram UI, with eye diagram UI as period to the Gaussian baseband waveform is intercepted section, all eye diagram trajectory frames intercepted are superimposed to obtain eye diagram;Calculate the probability density of eye diagram;The BT value of GMSK signal is obtained by backstepping using the probability density of eye diagram;The difference between the measured signal eye diagram and modeling eye diagram under the condition of same BT value is obtained, the subtle difference between them is obtained, the statistical characteristics of eye diagram difference are further extracted, and the radio frequency fingerprint feature vector is constructed by combining BT value characteristics;Radio frequency fingerprint feature vector is input to support vector machine to do the identity authentication of equipment.The authentication method of the application can utilize the hardware subtle difference between different wireless devices of modulation mode GMSK to accurately identify the identity of the same.

The invention relates to the technical field of circuit design, and discloses a signal simulation analysis method and system. The method comprises the following steps: building a simulation structure; according to the built simulation structure, scattering parameters of the main control chip substrate, the PCB and the storage chip particle substrate are obtained respectively; optimizing the second wiring design according to the scattering parameters of the PCB, and optimizing the third wiring design according to the scattering parameters of the storage chip particle substrate to obtain an optimized simulation structure; inputting the optimized simulation structure into pre-configured simulation software to perform a signal transmission simulation test to obtain eye pattern data; analyzing a signal quality index of the corresponding pin based on the eye pattern data, and determining whether the optimized simulation structure meets a preset transmission rate requirement or not according to the signal quality index; in this way, the external interconnection link of the main control chip and the internal wiring structure of the storage chip can be optimized at the same time.

The invention discloses an eye pattern data processing method and device and a storage medium. The method comprises the following steps: acquiring eye pattern data generated by electronic design automation software; storing the eye pattern data in a first storage space; in response to an operation instruction of a user on the eye diagram data, identifying a business operation type corresponding to the operation instruction, the business operation type including eye diagram display or eye diagram calculation data; according to the business operation type, a corresponding target data loading strategy is adopted to locally read the eye pattern data from the first storage space to a second storage space, and the reading speed of the second storage space is higher than that of the first storage space; the target data loading strategy comprises at least one of the following strategies: a linear prefetching strategy aiming at a sequential traversal operation, a jump loading strategy aiming at a random probing operation, and a matrix block loading strategy aiming at a region calculation operation; and executing the operation instruction based on the eye pattern data in the second storage space. The processing efficiency of the eye pattern data can be improved.

The application discloses a method for calibrating a misadjustment voltage, a comparison device and a decision feedback equalization circuit. The method calibrates the misadjustment voltage by adjusting the voltage of the reference input end of the comparator. The method does not need to short the input end of the comparator, so it does not need to insert a transmission gate in the receiving link, thus not affecting the signal quality of the receiving end. After calibration, the eye diagram of the receiving end of the comparator is obviously larger, and the margin of the whole receiving end is greatly increased. In addition, for two single-ended signal comparators constituting the structure of the decision feedback equalizer, the method for synchronously adjusting the reference voltages of the two comparators is used to calibrate the misadjustment voltage, and the DFE strength is combined, so that the DFE and the misadjustment voltage calibration are simultaneously performed, and the logic complexity of the calibration system is greatly simplified.

The invention belongs to the technical field of micro-ring modulator optimization, and particularly relates to a micro-ring modulator feedback control system for realizing optical modulation amplitude and linearity optimization. A low-speed PAM-4 test signal easy to process is generated through a test code generation module and is pre-distorted through a feedback control module to drive a micro-ring modulator, a signal acquisition module acquires a response signal of the modulator in real time, and an eye pattern calculation module extracts current light modulation amplitude and linearity of quantitative performance from the response signal and calculates the light modulation amplitude and linearity of the micro-ring modulator. And the feedback control module synchronously adjusts the working points of the micro-ring modulator based on the indexes to optimize the light modulation amplitude, and adjusts the pre-distortion coefficient to optimize the linearity, thereby solving the problems of performance compromise and power consumption increase caused by the separation of the light modulation amplitude and the linearity optimization in the prior art. Compared with the prior art, collaborative optimization is achieved, and energy efficiency is improved while performance compromise is avoided.