21 results about "Serializer" patented technology

The quality of service guaranteed function-free computing system comprises an HTTP gateway, a scheduler and a work pool; the HTTP gateway serializes the incoming DAG request through a serializer, and sequentially adds the serialized function-free function in the DAG request to a waiting queue; the scheduler retrieves the function-free function from the waiting queue and the chain running queue to the work pool for processing according to a scheduling strategy. The quality of service guaranteed function-free system and method of the application process the incoming request through the producer-consumer mode by reforming the scheduler in the platform. In addition, a strategy framework containing rich strategies is added. Different kinds of strategies are set for different kinds of application requests, so that the queuing time is reduced to a certain extent, and the running performance is improved.

The application discloses a data alignment circuit based on a time-interleaved ADC topology and relates to the technical field of analog-to-digital converters, and aims to solve the problem of inaccurate timing correspondence in the data conversion process of a traditional data alignment circuit. The data alignment circuit comprises a first-stage flip-flop circuit, a second-stage flip-flop circuit and a third-stage flip-flop circuit; the clock input ends of the flip-flop circuits are connected to the sampling clock of the sub-ADCs of the time-interleaved ADC; the output end of the third-stage flip-flop circuit is connected to the input end of a serializer-deserializer; the first-stage flip-flop circuit comprises a plurality of first flip-flop sub-circuits; the data input ends of the first flip-flop sub-circuits are connected to the sub-ADCs in different rows of the time-interleaved ADC, respectively. The data alignment circuit based on the time-interleaved ADC topology can be used to keep accurate timing correspondence in the process of massive data conversion and transmission between the time-interleaved ADC and the serializer-deserializer.

A computer implementable method, an asset developer computer, and a computer readable medium for managing an asset for machine learning are provided. The method comprises retrieving, from a version control system server over a network, an asset for machine learning, deserializing the asset from a serialized asset data format to a deserialized asset data format using a seriazlier / deserializer to generate a deserialized asset, modifying, via at least one processor of an asset developer workstation, the deserialized asset to generate a new version of the asset, serializing the new version of the asset using the serializer / deserializer to generate a serialized new asset, and sending, from the asset developer workstation, the serialized new asset to the version control system server over the network for storage.

This utility model discloses a large-screen video signal simulator, comprising: at least one MCU module, at least one serializer, and at least one memory. The memory stores a level status table. The serializer is connected to the MCU module. The MCU module reads the level status of the serializer and compares it with the level status table to determine the type of the serializer. It also includes at least one SOC module, which communicates with the MCU module. The serializer communicates with both the SOC module and the MCU module. This utility model has a simple structure. The MCU module reads the pin levels of the serializer and compares them with data in its internal memory to determine the type of the serializer. Based on the different execution codes of different types of serializers, the corresponding serializer is configured via I2C. The CANFD protocol is used to notify the SOC module to switch the video feed on the in-vehicle large screen, such as switching between side and rear video feeds.

The utility model discloses a video acquisition circuit, electronic equipment and a vehicle driving system, and relates to the technical field of video monitoring. In an acquisition circuit between a processor and a camera, in consideration of interface resource limitation of the processor, on the basis of a first-stage deserializer of the acquisition circuit, a serializer is added, so that video data of a multi-path camera module is serialized, and the serialized data occupies one path of interface of the first-stage deserializer in a one-path interface manner; and the access of multiple paths of modules is realized through one path of interface. Through the access of N stages of deserializers, one stage of serializer is connected between every two stages of deserializers, so that the next stage of deserializer can be connected with a plurality of cameras under the condition that each stage of deserializer can be connected with the plurality of cameras, the interface resources of the deserializers are fully utilized to access a plurality of camera modules, and the multi-camera module access efficiency is improved. And when each stage of serializer is finally accessed to the first stage of deserializer, one path of interface is adopted for access, so that the requirement of sufficient interface resources for transmission of a plurality of interfaces is met, and the experience feeling of a user is improved.

A recording device for a recording of a serialized image data stream from a sensor device. The recording device comprises a deserializer for deserializing the image data stream. To configure the first deserializer, the recording device comprises a configuration device, which records a configuration data stream transmitted by a receiving device for the purpose of configuring a serializer arranged in the sensor device and derives a configuration of the deserializer of the recording device by an analysis of the recording of the configuration data. In an example, the derivation takes place by an abstraction of the configuration of the serializer into a functionality of the serializer, a derivation of a functionality of the first deserializer from the functionality of the first serializer, and a concretization of the functionality of the first deserializer into a configuration of the first deserializer.

A serializer and a deserializer are disclosed. The serializer includes a sequence module and a data up-conversion module. The data up-conversion module receives a data packet sequence from a media access control block based on an output operation frequency and outputs the data packet sequence based on a sequence operation frequency. The deserializer includes a de-sequence module and a plurality of data down-conversion modules. The deserializer generates a data operation frequency based on a de-sequence operation frequency and outputs a recovered data packet sequence based on the data operation frequency. Embodiments of the present application can transmit or receive data in coordination with an operation frequency of a media access control block and exchange data at a transmission frequency that meets the transmission specification requirements of a physical layer, thereby achieving the goal of improving the convenience of the serializer and the deserializer in applications.

The invention relates to the technical field of API (Application Program Interface) data processing and machine translation, and discloses a precise translation and asynchronous blocking processing method for API response body content, which comprises the following steps that: a tree path encoder identifies a field to be translated by utilizing a reflection mechanism; and generating task metadata containing a path vector of the to-be-translated field in the JSON nested structure according to a path coding formula. The identifier generator and the serializer generate a global request serial number and task snapshot data and distribute asynchronous tasks. A regular cleaner generates a cleaned text, and a semantic compensation extraction algorithm executes logic truncation and splices a semantic compensation window to generate a to-be-translated input sequence. And the thread pool concurrently schedules a third-party engine to obtain translation blocks, and the structure reconstruction engine executes in-situ backfilling to generate a translated response body after eliminating redundant translation contents. And the exponential backoff retry device processes the exception, and the callback polling module adopts a double-track delivery strategy to deliver the result. The problem of context deficiency is solved, and translation continuity is guaranteed.

A transceiver circuit is disclosed, the transceiver circuit including a first register circuit, configured to receive serial stimulus data and to generate multi-bit parallel stimulus data, a serializer circuit configured to receive the multi-bit parallel stimulus data and to generate serialized data based on the multi-bit parallel stimulus data, where the serializer circuit includes a serializer data storage device, and where the serializer data storage device lacks circuit structures for scanability, a deserializer circuit configured to receive serial receiver data corresponding with the serialized data and to generate multi-bit parallel response data based on the serial receiver data, where the deserializer circuit includes a deserializer data storage device, and where the deserializer data storage device lacks circuit structures for scanability, and a second register circuit, configured to receive the multi-bit parallel response data and to generate serial response data.

A computer implementable method, an asset developer computer, and a computer readable medium for managing an asset for machine learning are provided. The method comprises retrieving, from a version control system server over a network, an asset for machine learning, deserializing the asset from a serialized asset data format to a deserialized asset data format using a seriazlier / deserializer to generate a deserialized asset, modifying, via at least one processor of an asset developer workstation, the deserialized asset to generate a new version of the asset, serializing the new version of the asset using the serializer / deserializer to generate a serialized new asset, and sending, from the asset developer workstation, the serialized new asset to the version control system server over the network for storage.

The application disclose a digital serializer / deserializer circuit and a data eye monitoring method thereof. A received analog signal is converted to first digital samples at a first sample rate. The first digital samples are equalized to generate a first equalized signal. A symbol decision signal is generated from the first equalized signal. The received analog signal is converted to second digital samples at a second sample rate. Difference between the first digital samples and the second digital samples is determined, and the first equalized signal and the determined difference are combined to generate a signal processing output. A data eye error rate is determined according to the symbol decision signal and the signal processing output.

The invention provides a serializer, a 2N: N serializer and electronic equipment, sampling ends of a pull-up network of the serializer are coupled to two ends of a first input geminate transistor and two ends of a second input geminate transistor through different switches, an input end of the first input geminate transistor receives first input data, a second end of the first input geminate transistor is grounded through a switch and a first network in sequence, and a second end of the second input geminate transistor is grounded through a second network. The input end of the second input geminate transistor receives second input data, and the second end of the second input geminate transistor is grounded through the switch and the second network in sequence. The sampling end samples the first input data and the second input data based on the on-off of the switch. According to the invention, the sampling end is only communicated with the first input pair transistor or the second input pair transistor at the same time, so that the influence of unnecessary input data on the voltage of the sampling end is avoided, the intersymbol interference is effectively reduced, and the data transmission quality is improved.

The invention provides a multipurpose D2D transmitter, a configuration method thereof and a transmitter. The multipurpose D2D transmitter comprises a data loading module, a data detection module, a serializer module and an adjustment module, at least two delay units are arranged in the data loading module, the corresponding delay unit is selected according to the received mode control signal to delay the data signal and the indication signal, and the data detection module performs AND operation on the data signal and the indication signal after delay processing to obtain effective data. The serializer module obtains target data according to effective data, and the adjusting module performs logical operation on a target signal and a control signal and selects an SST driver according to a result so as to realize adjustment of impedance and balance. Therefore, according to the scheme, delay adjustability and bit width adjustability can be achieved, transmission requirements for different types of data can be met, adaptability to various application scenes is good, and flexible configuration of bit width, delay, impedance and balance of the transmitter by external signals can be supported.

The invention relates to the technical field of computers, and provides a chip interface debugging method and device, a storage medium and a program product. The chip interface comprises a serializer and a deserializer, the serializer is connected with the deserializer through a plurality of channels, and the method comprises the following steps: determining a plurality of first parameter groups of an equalizer in the serializer and an error rate threshold value of each channel; debugging the chip interface according to the plurality of first parameter groups, and selecting at least one target parameter group for the serializer according to a debugging result and an error rate threshold; wherein when the chip interface is debugged at any time according to any first parameter group, the serializer outputs a test code pattern to the at least one channel, the deserializer determines the error rate of the channel according to the actual code pattern and the test code pattern received from each channel, and the obtained debugging result comprises the error rate of the at least one channel. According to the method, the hardware cost and the labor cost can be reduced, the debugging efficiency is improved, and the adaptability of the chip interface debugging method to different application scenes is improved.

Techniques for universal data transmission to multiple cloud storage platforms are described. A universal data transmission system includes a data integration framework, a set of serializers, a plurality of authenticators, a plurality of transports, and a cloud connection service. The cloud connection service is capable of loading the data from an on-premise device to each of the plurality of cloud storage platforms. The cloud connection service receives a selection of a cloud storage platform for the cloud connection service to load the data and configures a plurality of channels based on the category of the collected data and the selected cloud storage platform to a specific configuration. The cloud connection service selects a specific serializer, a specific authenticator, and a specific transport, which are pluggable to form the transmission route connecting the on-premise device to the selected cloud storage platform.

Various technologies for providing a knowledge-driven data format framework (KDF) are disclosed. The KDF uses a declarative, format-independent description of logical information being stored and / or exchanged by different computing systems to drive reading, writing and translation of information objects to and from different data formats. The KDF uses this description to navigate a logical structure of input information objects, and determines formatting decisions for reading, writing, and / or translating the information objects using one or more format-specific coder / decoder (CODEC). The KDF uses a format-independent, data driven (FIDD) API, FIDD translation elements, and FIDD in-memory data structures for translation of information objects from at least one of a plurality of data formats into another one of the plurality of data formats. As such, there are no mismatches between in-memory data structures, and thus, no coding is required to translate between various ones of the plurality of APIs, parsers, serializers, and data structures.

This invention belongs to the field of electronic technology and provides a built-in self-test circuit and method for high-speed interface IP intellectual property cores. The built-in self-test circuit includes: a pseudo-random binary sequence generator for generating corresponding code pattern data; a serializer for converting the code pattern data into serial data; a signal transceiver unit; a deserializer for deserializing the serial data to obtain deserialized data and an encoded clock signal; a synchronization module for performing delay compensation on the deserialized data according to the encoded clock signal and aligning the delay-compensated data with the pseudo-random binary sequence code pattern data to obtain aligned data pairs; and a comparator for performing logical decisions on the aligned data pairs to determine whether the built-in self-test of the high-speed interface IP is successful or failed. The built-in self-test circuit of this invention has a simple structure, does not occupy additional convex resources, and improves the self-test efficiency and accuracy of high-speed interface IP in BIST mode.

The invention provides a load box for testing an automatic driving domain controller and a testing method, and relates to the technical field of computers, in particular to the technical fields of automatic driving, domain controller testing and the like. The load box specifically comprises a master control and management unit used for setting function positioning of a video link subsystem according to test configuration, and the function positioning comprises a serializer and a deserializer; the video link subsystem is used for establishing a video link with the domain controller according to function positioning; based on the video link, carrying out data communication with the domain controller; and the Ethernet subsystem is used for sending the link statistical information of the receiving end and the sending end of the video link to the upper computer, and the link statistical information is used for carrying out a first test on the domain controller. According to the invention, the complexity of a domain controller test environment can be reduced, and the test reliability is improved.

Examples of the present disclosure provide a network device and a data processing method, which relates to the field of communication technology. The network device includes a FlexE interface board, a backplane and at least one forwarding board; wherein a first VLAN configuration unit is provided on the FlexE interface board, and the first VLAN configuration unit is connected to the backplane through a serializer / deserializer; a mapping relationship between FlexE service ports and FlexE channels is stored in the first VLAN configuration unit; a second VLAN configuration unit is provided on the at least one forwarding board, and the second VLAN configuration unit is connected to the backplane through a serializer / deserializer; the mapping relationship between the FlexE service ports and the FlexE channels is stored in the second VLAN configuration unit; the serializer / deserializer transmits a data frame by using an Ethernet backplane protocol.

The application provides a self-diagnosis and switching system, method and vehicle terminal; the self-diagnosis and switching system is applied to frequency configuration of a serializer and at least comprises a microcontroller, a serializer and a switching circuit; the microcontroller is at least configured with an input and output pin and a diagnosis pin; the serializer comprises at least one configuration pin; the switching circuit is connected between the input and output pin and the configuration pin; the diagnosis pin comprises a first sampling pin and a second sampling pin; the first sampling pin and the second sampling pin are respectively connected to the input and output pin and the configuration pin. The application does not need to replace hardware and complex software configuration, adapts to bandwidth and transmission distance requirements of different scenes of a vehicle system, greatly improves universality, does not need complex communication protocols and register read and write operations, and the configuration takes effect extremely fast, can meet strict timing requirements of the vehicle system on fast start and real-time mode switching, and also realizes real-time online diagnosis and meets requirements of L3+ level automatic driving.

The invention provides a port exception processing method and device, equipment, a medium and a program product, which are applied to the technical field of information security, and the method comprises the following steps: under the condition that a first message sent by second terminal equipment is received, obtaining the number of abnormal SerDes channels of the first terminal equipment; sending a second message to the second terminal device; receiving a third message sent by the second terminal device; and processing the port of the first terminal device based on the target port rate. In the method, under the condition that port SerDes channels of a first terminal device are sensed to be abnormal, the number of the abnormal SerDes channels is obtained, the target port rate can be determined according to the number of the abnormal SerDes channels, and ports of the first terminal device and a second terminal device are made to operate according to the target port rate, so that although the port rate is reduced, the port rate is not reduced, and the port rate of the first terminal device and the port rate of the second terminal device are not reduced. But business message abnormity can be reduced and uninterrupted business can be guaranteed so that probability of network business abnormity can be reduced.