32 results about "Serializer" patented technology

The quality of service guaranteed function-free computing system comprises an HTTP gateway, a scheduler and a work pool; the HTTP gateway serializes the incoming DAG request through a serializer, and sequentially adds the serialized function-free function in the DAG request to a waiting queue; the scheduler retrieves the function-free function from the waiting queue and the chain running queue to the work pool for processing according to a scheduling strategy. The quality of service guaranteed function-free system and method of the application process the incoming request through the producer-consumer mode by reforming the scheduler in the platform. In addition, a strategy framework containing rich strategies is added. Different kinds of strategies are set for different kinds of application requests, so that the queuing time is reduced to a certain extent, and the running performance is improved.

The application discloses a data alignment circuit based on a time-interleaved ADC topology and relates to the technical field of analog-to-digital converters, and aims to solve the problem of inaccurate timing correspondence in the data conversion process of a traditional data alignment circuit. The data alignment circuit comprises a first-stage flip-flop circuit, a second-stage flip-flop circuit and a third-stage flip-flop circuit; the clock input ends of the flip-flop circuits are connected to the sampling clock of the sub-ADCs of the time-interleaved ADC; the output end of the third-stage flip-flop circuit is connected to the input end of a serializer-deserializer; the first-stage flip-flop circuit comprises a plurality of first flip-flop sub-circuits; the data input ends of the first flip-flop sub-circuits are connected to the sub-ADCs in different rows of the time-interleaved ADC, respectively. The data alignment circuit based on the time-interleaved ADC topology can be used to keep accurate timing correspondence in the process of massive data conversion and transmission between the time-interleaved ADC and the serializer-deserializer.

A computer implementable method, an asset developer computer, and a computer readable medium for managing an asset for machine learning are provided. The method comprises retrieving, from a version control system server over a network, an asset for machine learning, deserializing the asset from a serialized asset data format to a deserialized asset data format using a seriazlier / deserializer to generate a deserialized asset, modifying, via at least one processor of an asset developer workstation, the deserialized asset to generate a new version of the asset, serializing the new version of the asset using the serializer / deserializer to generate a serialized new asset, and sending, from the asset developer workstation, the serialized new asset to the version control system server over the network for storage.

This utility model discloses a large-screen video signal simulator, comprising: at least one MCU module, at least one serializer, and at least one memory. The memory stores a level status table. The serializer is connected to the MCU module. The MCU module reads the level status of the serializer and compares it with the level status table to determine the type of the serializer. It also includes at least one SOC module, which communicates with the MCU module. The serializer communicates with both the SOC module and the MCU module. This utility model has a simple structure. The MCU module reads the pin levels of the serializer and compares them with data in its internal memory to determine the type of the serializer. Based on the different execution codes of different types of serializers, the corresponding serializer is configured via I2C. The CANFD protocol is used to notify the SOC module to switch the video feed on the in-vehicle large screen, such as switching between side and rear video feeds.

The utility model discloses a video acquisition circuit, electronic equipment and a vehicle driving system, and relates to the technical field of video monitoring. In an acquisition circuit between a processor and a camera, in consideration of interface resource limitation of the processor, on the basis of a first-stage deserializer of the acquisition circuit, a serializer is added, so that video data of a multi-path camera module is serialized, and the serialized data occupies one path of interface of the first-stage deserializer in a one-path interface manner; and the access of multiple paths of modules is realized through one path of interface. Through the access of N stages of deserializers, one stage of serializer is connected between every two stages of deserializers, so that the next stage of deserializer can be connected with a plurality of cameras under the condition that each stage of deserializer can be connected with the plurality of cameras, the interface resources of the deserializers are fully utilized to access a plurality of camera modules, and the multi-camera module access efficiency is improved. And when each stage of serializer is finally accessed to the first stage of deserializer, one path of interface is adopted for access, so that the requirement of sufficient interface resources for transmission of a plurality of interfaces is met, and the experience feeling of a user is improved.

A recording device for a recording of a serialized image data stream from a sensor device. The recording device comprises a deserializer for deserializing the image data stream. To configure the first deserializer, the recording device comprises a configuration device, which records a configuration data stream transmitted by a receiving device for the purpose of configuring a serializer arranged in the sensor device and derives a configuration of the deserializer of the recording device by an analysis of the recording of the configuration data. In an example, the derivation takes place by an abstraction of the configuration of the serializer into a functionality of the serializer, a derivation of a functionality of the first deserializer from the functionality of the first serializer, and a concretization of the functionality of the first deserializer into a configuration of the first deserializer.

Examples of technology disclosed herein determine, by a serializer and a deserializer, one or more of calibration parameters and adaptive equalization (AEQ) parameters to perform calibration and AEQ for a communication link between the serializer and the deserializer. Such examples store the one or more parameters into a retention memory, and then put at least one of the serializer and deserializer into a sleep / low power mode. Upon receiving a wakeup command at each of the serializer and the deserializer put into the sleep mode, the serializer and the deserializer perform link lock of the communication link using the stored parameters.

A serializer and a deserializer are disclosed. The serializer includes a sequence module and a data up-conversion module. The data up-conversion module receives a data packet sequence from a media access control block based on an output operation frequency and outputs the data packet sequence based on a sequence operation frequency. The deserializer includes a de-sequence module and a plurality of data down-conversion modules. The deserializer generates a data operation frequency based on a de-sequence operation frequency and outputs a recovered data packet sequence based on the data operation frequency. Embodiments of the present application can transmit or receive data in coordination with an operation frequency of a media access control block and exchange data at a transmission frequency that meets the transmission specification requirements of a physical layer, thereby achieving the goal of improving the convenience of the serializer and the deserializer in applications.

The invention relates to the technical field of API (Application Program Interface) data processing and machine translation, and discloses a precise translation and asynchronous blocking processing method for API response body content, which comprises the following steps that: a tree path encoder identifies a field to be translated by utilizing a reflection mechanism; and generating task metadata containing a path vector of the to-be-translated field in the JSON nested structure according to a path coding formula. The identifier generator and the serializer generate a global request serial number and task snapshot data and distribute asynchronous tasks. A regular cleaner generates a cleaned text, and a semantic compensation extraction algorithm executes logic truncation and splices a semantic compensation window to generate a to-be-translated input sequence. And the thread pool concurrently schedules a third-party engine to obtain translation blocks, and the structure reconstruction engine executes in-situ backfilling to generate a translated response body after eliminating redundant translation contents. And the exponential backoff retry device processes the exception, and the callback polling module adopts a double-track delivery strategy to deliver the result. The problem of context deficiency is solved, and translation continuity is guaranteed.

A serial-connection is tested by transmitting a PRBS generated using a kth-order monic-polynomial from transmission-circuitry to reception-circuitry, and determining operation is proper based upon the PRBS received. The PRBS is formed by generating x intermediate-words of the PRBS, x being a result of an integer-divide between a total number of bits in the PRBS and a bit-width of a serializer that transmits the PRBS, generating a leading-word of the PRBS as having first y-bits of the PRBS as its LSBs, y being based upon a modulo-divide between the total number of bits in the PRBS and x, and generating a trailing-word of the PRBS as having last z-bits of the PRBS as its MSBs, z being based upon a difference between a result of the modulo-divide and y. The PRBS is transmitted sequentially as the leading-word of the PRBS, the intermediate-words of the PRBS, and the trailing-word of the PRBS.

A transceiver circuit is disclosed, the transceiver circuit including a first register circuit, configured to receive serial stimulus data and to generate multi-bit parallel stimulus data, a serializer circuit configured to receive the multi-bit parallel stimulus data and to generate serialized data based on the multi-bit parallel stimulus data, where the serializer circuit includes a serializer data storage device, and where the serializer data storage device lacks circuit structures for scanability, a deserializer circuit configured to receive serial receiver data corresponding with the serialized data and to generate multi-bit parallel response data based on the serial receiver data, where the deserializer circuit includes a deserializer data storage device, and where the deserializer data storage device lacks circuit structures for scanability, and a second register circuit, configured to receive the multi-bit parallel response data and to generate serial response data.

A computer implementable method, an asset developer computer, and a computer readable medium for managing an asset for machine learning are provided. The method comprises retrieving, from a version control system server over a network, an asset for machine learning, deserializing the asset from a serialized asset data format to a deserialized asset data format using a seriazlier / deserializer to generate a deserialized asset, modifying, via at least one processor of an asset developer workstation, the deserialized asset to generate a new version of the asset, serializing the new version of the asset using the serializer / deserializer to generate a serialized new asset, and sending, from the asset developer workstation, the serialized new asset to the version control system server over the network for storage.

The invention provides a debugging method and device for a serial deserializer, electronic equipment and a storage medium, and the debugging method comprises the steps: obtaining a configuration file used for debugging the serial deserializer in response to an external instruction which is received by the serial deserializer and represents the start of debugging, and analyzing the configuration file, determining debugging command information in the configuration file; in response to the fact that the debugging command information is determined, performing debugging configuration on the serial deserializer so as to convert the running state of the serial deserializer into a debugging working state; and in response to the condition that the serial deserializer is in the debugging working state, debugging the serial deserializer based on the debugging command information to obtain a debugging result of the serial deserializer. Through the method, the debugging efficiency of the serial deserializer is improved, and the debugging stability of the serial deserializer is further improved.

The application disclose a digital serializer / deserializer circuit and a data eye monitoring method thereof. A received analog signal is converted to first digital samples at a first sample rate. The first digital samples are equalized to generate a first equalized signal. A symbol decision signal is generated from the first equalized signal. The received analog signal is converted to second digital samples at a second sample rate. Difference between the first digital samples and the second digital samples is determined, and the first equalized signal and the determined difference are combined to generate a signal processing output. A data eye error rate is determined according to the symbol decision signal and the signal processing output.

A transceiver circuit is disclosed, the transceiver circuit including a first register circuit, configured to receive serial stimulus data and to generate multi-bit parallel stimulus data, a serializer circuit configured to receive the multi-bit parallel stimulus data and to generate serialized data based on the multi-bit parallel stimulus data, where the serializer circuit includes a serializer data storage device, and where the serializer data storage device lacks circuit structures for scanability, a deserializer circuit configured to receive serial receiver data corresponding with the serialized data and to generate multi-bit parallel response data based on the serial receiver data, where the deserializer circuit includes a deserializer data storage device, and where the deserializer data storage device lacks circuit structures for scanability, and a second register circuit, configured to receive the multi-bit parallel response data and to generate serial response data.

A computer-implemented method for employing a time-series-to-text generation model to generate accurate description texts is provided. The method includes passing time series data through a time series encoder and a multilayer perceptron (MLP) classifier to obtain predicted concept labels, converting the predicted concept labels, by a serializer, to a text token sequence by concatenating an aspect term and an option term of every aspect, inputting the text token sequence into a pretrained language model including a bidirectional encoder and an autoregressive decoder, and using adapter layers to fine-tune the pretrained language model to generate description texts.

The invention provides a serializer, a 2N: N serializer and electronic equipment, sampling ends of a pull-up network of the serializer are coupled to two ends of a first input geminate transistor and two ends of a second input geminate transistor through different switches, an input end of the first input geminate transistor receives first input data, a second end of the first input geminate transistor is grounded through a switch and a first network in sequence, and a second end of the second input geminate transistor is grounded through a second network. The input end of the second input geminate transistor receives second input data, and the second end of the second input geminate transistor is grounded through the switch and the second network in sequence. The sampling end samples the first input data and the second input data based on the on-off of the switch. According to the invention, the sampling end is only communicated with the first input pair transistor or the second input pair transistor at the same time, so that the influence of unnecessary input data on the voltage of the sampling end is avoided, the intersymbol interference is effectively reduced, and the data transmission quality is improved.

The invention provides a multipurpose D2D transmitter, a configuration method thereof and a transmitter. The multipurpose D2D transmitter comprises a data loading module, a data detection module, a serializer module and an adjustment module, at least two delay units are arranged in the data loading module, the corresponding delay unit is selected according to the received mode control signal to delay the data signal and the indication signal, and the data detection module performs AND operation on the data signal and the indication signal after delay processing to obtain effective data. The serializer module obtains target data according to effective data, and the adjusting module performs logical operation on a target signal and a control signal and selects an SST driver according to a result so as to realize adjustment of impedance and balance. Therefore, according to the scheme, delay adjustability and bit width adjustability can be achieved, transmission requirements for different types of data can be met, adaptability to various application scenes is good, and flexible configuration of bit width, delay, impedance and balance of the transmitter by external signals can be supported.

The invention relates to the technical field of computers, and provides a chip interface debugging method and device, a storage medium and a program product. The chip interface comprises a serializer and a deserializer, the serializer is connected with the deserializer through a plurality of channels, and the method comprises the following steps: determining a plurality of first parameter groups of an equalizer in the serializer and an error rate threshold value of each channel; debugging the chip interface according to the plurality of first parameter groups, and selecting at least one target parameter group for the serializer according to a debugging result and an error rate threshold; wherein when the chip interface is debugged at any time according to any first parameter group, the serializer outputs a test code pattern to the at least one channel, the deserializer determines the error rate of the channel according to the actual code pattern and the test code pattern received from each channel, and the obtained debugging result comprises the error rate of the at least one channel. According to the method, the hardware cost and the labor cost can be reduced, the debugging efficiency is improved, and the adaptability of the chip interface debugging method to different application scenes is improved.

The utility model discloses a data conversion device, a data conversion system and debugging equipment. The device comprises a first video connector, a deserializer chip, a serializer chip and a second video connector, the flat panel display link FPD-Link camera is in signal connection with the first video connector, the first video connector is in signal connection with the deserializer chip, the deserializer chip is in signal connection with the serializer chip, and the second video connector is in signal connection with the serializer chip. The serializer chip is in signal connection with a second video connector, and the second video connector is in signal connection with a GMSL (Gigabit Multimedia Serial Link) controller. By applying the scheme provided by the utility model, the time cost and the research and development cost can be greatly reduced.

Techniques for universal data transmission to multiple cloud storage platforms are described. A universal data transmission system includes a data integration framework, a set of serializers, a plurality of authenticators, a plurality of transports, and a cloud connection service. The cloud connection service is capable of loading the data from an on-premise device to each of the plurality of cloud storage platforms. The cloud connection service receives a selection of a cloud storage platform for the cloud connection service to load the data and configures a plurality of channels based on the category of the collected data and the selected cloud storage platform to a specific configuration. The cloud connection service selects a specific serializer, a specific authenticator, and a specific transport, which are pluggable to form the transmission route connecting the on-premise device to the selected cloud storage platform.

The utility model relates to a serialization-deserialization system, which comprises an accessory end, which is used for carrying out serialization processing on first data and second data which are parallel to each other so as to generate serial data and is provided with a first connecting structure; the host end is provided with a second connecting structure; the accessory end and the host end are detachably connected through the first connecting structure and the second connecting structure, when the first connecting structure and the second connecting structure are connected, the serial data are transmitted to the host end through the first connecting structure and the second connecting structure, and the host end receives the serial data and transmits the serial data to the accessory end. And deserializing the serial data to regenerate first data and second data which are parallel to each other. According to the invention, the parallel data is converted into the serial data through the serializer, and then the serial data is transmitted to the deserializer through the connection structure for deserialization, so that the number of signal interfaces is smaller, hot plugging of the accessory end can be realized, meanwhile, the accessory type can be rapidly detected through the accessory type detection unit, and the application program corresponding to the accessory can be loaded, thereby improving the user experience.

Various technologies for providing a knowledge-driven data format framework (KDF) are disclosed. The KDF uses a declarative, format-independent description of logical information being stored and / or exchanged by different computing systems to drive reading, writing and translation of information objects to and from different data formats. The KDF uses this description to navigate a logical structure of input information objects, and determines formatting decisions for reading, writing, and / or translating the information objects using one or more format-specific coder / decoder (CODEC). The KDF uses a format-independent, data driven (FIDD) API, FIDD translation elements, and FIDD in-memory data structures for translation of information objects from at least one of a plurality of data formats into another one of the plurality of data formats. As such, there are no mismatches between in-memory data structures, and thus, no coding is required to translate between various ones of the plurality of APIs, parsers, serializers, and data structures.

This invention belongs to the field of electronic technology and provides a built-in self-test circuit and method for high-speed interface IP intellectual property cores. The built-in self-test circuit includes: a pseudo-random binary sequence generator for generating corresponding code pattern data; a serializer for converting the code pattern data into serial data; a signal transceiver unit; a deserializer for deserializing the serial data to obtain deserialized data and an encoded clock signal; a synchronization module for performing delay compensation on the deserialized data according to the encoded clock signal and aligning the delay-compensated data with the pseudo-random binary sequence code pattern data to obtain aligned data pairs; and a comparator for performing logical decisions on the aligned data pairs to determine whether the built-in self-test of the high-speed interface IP is successful or failed. The built-in self-test circuit of this invention has a simple structure, does not occupy additional convex resources, and improves the self-test efficiency and accuracy of high-speed interface IP in BIST mode.

The invention provides a load box for testing an automatic driving domain controller and a testing method, and relates to the technical field of computers, in particular to the technical fields of automatic driving, domain controller testing and the like. The load box specifically comprises a master control and management unit used for setting function positioning of a video link subsystem according to test configuration, and the function positioning comprises a serializer and a deserializer; the video link subsystem is used for establishing a video link with the domain controller according to function positioning; based on the video link, carrying out data communication with the domain controller; and the Ethernet subsystem is used for sending the link statistical information of the receiving end and the sending end of the video link to the upper computer, and the link statistical information is used for carrying out a first test on the domain controller. According to the invention, the complexity of a domain controller test environment can be reduced, and the test reliability is improved.

The invention relates to the technical field of I2C buses, in particular to a method and system for achieving different transmission functions by adding virtual addresses, and the method comprises the steps: configuring a plurality of virtual device addresses for a serializer connected with a deserializer to indicate a transmission mode and / or a communication protocol corresponding to a read-write instruction; the deserializer receives the read-write instruction, determines a corresponding transmission mode and / or communication protocol according to the marked address and performs operation; in order to solve the problem that in the prior art, the change of I2C bus data message format can cause the incompatibility of part of equipment at the rear stage of a system, a plurality of virtual equipment addresses are distributed for a serializer and rear-end equipment in a deserializer, and are respectively used for marking different transmission modes and communication protocols, so that the support for more transmission modes and communication protocols is realized, and the communication efficiency is improved. And the message format of the I2C bus does not need to be changed, so that the compatibility problem cannot be caused.

The invention discloses a data serialization method and device and electronic equipment. The method comprises the following steps: acquiring an object to be serialized, and determining a fractal dimension and a self-similarity coefficient of the object to be serialized; according to the fractal dimension and the self-similarity coefficient, determining a target object of which the self-similarity structure meets a preset threshold in the to-be-serialized object, and determining a fractal template of the target object, the fractal template being used for storing a field rule and type conversion information of the target object; a byte code serializer is generated according to the fractal template, and the byte code serializer comprises pre-compiling logic corresponding to the fractal template; and performing iterative serialization processing on the to-be-serialized object according to the byte code serializer or preset general logic. The technical problem that the serialization efficiency is low when a JSON serialization method in related technologies processes data objects with high self-similarity and complex nested structures is solved.

Examples of the present disclosure provide a network device and a data processing method, which relates to the field of communication technology. The network device includes a FlexE interface board, a backplane and at least one forwarding board; wherein a first VLAN configuration unit is provided on the FlexE interface board, and the first VLAN configuration unit is connected to the backplane through a serializer / deserializer; a mapping relationship between FlexE service ports and FlexE channels is stored in the first VLAN configuration unit; a second VLAN configuration unit is provided on the at least one forwarding board, and the second VLAN configuration unit is connected to the backplane through a serializer / deserializer; the mapping relationship between the FlexE service ports and the FlexE channels is stored in the second VLAN configuration unit; the serializer / deserializer transmits a data frame by using an Ethernet backplane protocol.

The invention provides a serial deserializer initialization method, a medium and equipment, and relates to the technical field of software design, S100, configuring a deserializer address; s200, detecting whether LINK Defect is in the deserializer or not, resetting the serializer if no LINK Defect is in the far-end deserializer, initializing the serializer to access the deserializer and setting flag as false, and then returning to the step S200; s200, if the LINK Deject reaches the far-end deserializer and the flag is marked as false, re-initializing the serial deserializer, and then returning to the step S200; and if the LINK Detect reaches the far-end deserializer and the flag is marked as true, directly returning to the step S200. According to the invention, in the initialization process of the serial deserializer, the display part of the vehicle-mounted terminal system can be normally displayed or immediately recovered to be normal under an abnormal condition.

The application provides a self-diagnosis and switching system, method and vehicle terminal; the self-diagnosis and switching system is applied to frequency configuration of a serializer and at least comprises a microcontroller, a serializer and a switching circuit; the microcontroller is at least configured with an input and output pin and a diagnosis pin; the serializer comprises at least one configuration pin; the switching circuit is connected between the input and output pin and the configuration pin; the diagnosis pin comprises a first sampling pin and a second sampling pin; the first sampling pin and the second sampling pin are respectively connected to the input and output pin and the configuration pin. The application does not need to replace hardware and complex software configuration, adapts to bandwidth and transmission distance requirements of different scenes of a vehicle system, greatly improves universality, does not need complex communication protocols and register read and write operations, and the configuration takes effect extremely fast, can meet strict timing requirements of the vehicle system on fast start and real-time mode switching, and also realizes real-time online diagnosis and meets requirements of L3+ level automatic driving.