44 results about "Serializer" patented technology

Methods and systems for stacking multiple chips with high speed serializer / deserializer blocks are presented. These methods make use of Through Via (TV) to connect the dice to each other, and to the external pads. The methods enable efficient multilayer stacking that simplifies design and manufacturing, and at the same time, ensure high speed operation of serializer / deserializer blocks, using the TVs.

A method for serializing communications in the computing field includes serializing input data into a serialized stream of symbols, based on one or more encodings, at a serializer, each symbol including a disparity code selected based on a running disparity (RD) of the serialized stream of symbols. The running disparity (RD) is tracked by setting the RD to an initial value, and then adding a disparity of each symbol to the RD to ensure the RD does not exceed a desired maximum, e.g., three. A positive disparity encoding or a negative disparity encoding of each symbol is selected for transmission based on the RD. The serialized data stream of symbols is transmitted along a data conduit, to a deserializer, in which the serialized data stream of symbols is deserialized to determine a corresponding bit value, for outputting decoded information in parallel form.

The quality of service guaranteed function-free computing system comprises an HTTP gateway, a scheduler and a work pool; the HTTP gateway serializes the incoming DAG request through a serializer, and sequentially adds the serialized function-free function in the DAG request to a waiting queue; the scheduler retrieves the function-free function from the waiting queue and the chain running queue to the work pool for processing according to a scheduling strategy. The quality of service guaranteed function-free system and method of the application process the incoming request through the producer-consumer mode by reforming the scheduler in the platform. In addition, a strategy framework containing rich strategies is added. Different kinds of strategies are set for different kinds of application requests, so that the queuing time is reduced to a certain extent, and the running performance is improved.

The invention relates to a data transmission method and device and a vehicle, and relates to the technical field of data transmission. The method comprises the steps that a data collector obtains point cloud data; the data collector encodes the point cloud data to obtain first multimedia serial data, and transmits the first multimedia serial data to a serializer; the serializer converts the first multimedia serial data into a first data packet, and transmits the first data packet to a deserializer by using a multimedia serial link; the deserializer analyzes the first data packet to obtain first multimedia serial data, and transmits the first multimedia serial data to the controller. According to the invention, the multimedia serial link is used for transmission, so that the intelligent perception of the vehicle on the related elements of the road is realized; by utilizing the high bandwidth characteristic of the multimedia serial link, enough communication bandwidth is provided for data transmission between the data collector and the controller, so that the upgrade of the automatic driving technology is not limited by the communication bandwidth.

The application discloses a data alignment circuit based on a time-interleaved ADC topology and relates to the technical field of analog-to-digital converters, and aims to solve the problem of inaccurate timing correspondence in the data conversion process of a traditional data alignment circuit. The data alignment circuit comprises a first-stage flip-flop circuit, a second-stage flip-flop circuit and a third-stage flip-flop circuit; the clock input ends of the flip-flop circuits are connected to the sampling clock of the sub-ADCs of the time-interleaved ADC; the output end of the third-stage flip-flop circuit is connected to the input end of a serializer-deserializer; the first-stage flip-flop circuit comprises a plurality of first flip-flop sub-circuits; the data input ends of the first flip-flop sub-circuits are connected to the sub-ADCs in different rows of the time-interleaved ADC, respectively. The data alignment circuit based on the time-interleaved ADC topology can be used to keep accurate timing correspondence in the process of massive data conversion and transmission between the time-interleaved ADC and the serializer-deserializer.

The present invention discloses an image serializer and an electronic device, relating to the field of artificial intelligence technology. Among them, the image serializer receives read-write control parameters and original feature data through an input end, uses a read-write control module to determine a data writing method and a data reading method based on the read-write control parameters, and writes the original feature data into a data storage module according to the data writing method; under the control of the data reading method, corresponding data is read from the data storage module according to a convolution operation behavior method to generate feature matrix data, and the feature matrix data is output through an output end. The present invention can solve the problem that there are a large number of duplicate data in the im2col operation in the related art, effectively reduce the memory and data transmission overhead, effectively reduce the communication delay, improve the execution efficiency of artificial intelligence tasks, and thus effectively reduce the memory resources and computing resources required for artificial intelligence tasks.

A computer implementable method, an asset developer computer, and a computer readable medium for managing an asset for machine learning are provided. The method comprises retrieving, from a version control system server over a network, an asset for machine learning, deserializing the asset from a serialized asset data format to a deserialized asset data format using a seriazlier / deserializer to generate a deserialized asset, modifying, via at least one processor of an asset developer workstation, the deserialized asset to generate a new version of the asset, serializing the new version of the asset using the serializer / deserializer to generate a serialized new asset, and sending, from the asset developer workstation, the serialized new asset to the version control system server over the network for storage.

This utility model discloses a large-screen video signal simulator, comprising: at least one MCU module, at least one serializer, and at least one memory. The memory stores a level status table. The serializer is connected to the MCU module. The MCU module reads the level status of the serializer and compares it with the level status table to determine the type of the serializer. It also includes at least one SOC module, which communicates with the MCU module. The serializer communicates with both the SOC module and the MCU module. This utility model has a simple structure. The MCU module reads the pin levels of the serializer and compares them with data in its internal memory to determine the type of the serializer. Based on the different execution codes of different types of serializers, the corresponding serializer is configured via I2C. The CANFD protocol is used to notify the SOC module to switch the video feed on the in-vehicle large screen, such as switching between side and rear video feeds.

The utility model discloses a video acquisition circuit, electronic equipment and a vehicle driving system, and relates to the technical field of video monitoring. In an acquisition circuit between a processor and a camera, in consideration of interface resource limitation of the processor, on the basis of a first-stage deserializer of the acquisition circuit, a serializer is added, so that video data of a multi-path camera module is serialized, and the serialized data occupies one path of interface of the first-stage deserializer in a one-path interface manner; and the access of multiple paths of modules is realized through one path of interface. Through the access of N stages of deserializers, one stage of serializer is connected between every two stages of deserializers, so that the next stage of deserializer can be connected with a plurality of cameras under the condition that each stage of deserializer can be connected with the plurality of cameras, the interface resources of the deserializers are fully utilized to access a plurality of camera modules, and the multi-camera module access efficiency is improved. And when each stage of serializer is finally accessed to the first stage of deserializer, one path of interface is adopted for access, so that the requirement of sufficient interface resources for transmission of a plurality of interfaces is met, and the experience feeling of a user is improved.

A recording device for a recording of a serialized image data stream from a sensor device. The recording device comprises a deserializer for deserializing the image data stream. To configure the first deserializer, the recording device comprises a configuration device, which records a configuration data stream transmitted by a receiving device for the purpose of configuring a serializer arranged in the sensor device and derives a configuration of the deserializer of the recording device by an analysis of the recording of the configuration data. In an example, the derivation takes place by an abstraction of the configuration of the serializer into a functionality of the serializer, a derivation of a functionality of the first deserializer from the functionality of the first serializer, and a concretization of the functionality of the first deserializer into a configuration of the first deserializer.

Examples of technology disclosed herein determine, by a serializer and a deserializer, one or more of calibration parameters and adaptive equalization (AEQ) parameters to perform calibration and AEQ for a communication link between the serializer and the deserializer. Such examples store the one or more parameters into a retention memory, and then put at least one of the serializer and deserializer into a sleep / low power mode. Upon receiving a wakeup command at each of the serializer and the deserializer put into the sleep mode, the serializer and the deserializer perform link lock of the communication link using the stored parameters.

A serializer and a deserializer are disclosed. The serializer includes a sequence module and a data up-conversion module. The data up-conversion module receives a data packet sequence from a media access control block based on an output operation frequency and outputs the data packet sequence based on a sequence operation frequency. The deserializer includes a de-sequence module and a plurality of data down-conversion modules. The deserializer generates a data operation frequency based on a de-sequence operation frequency and outputs a recovered data packet sequence based on the data operation frequency. Embodiments of the present application can transmit or receive data in coordination with an operation frequency of a media access control block and exchange data at a transmission frequency that meets the transmission specification requirements of a physical layer, thereby achieving the goal of improving the convenience of the serializer and the deserializer in applications.

The invention relates to the technical field of API (Application Program Interface) data processing and machine translation, and discloses a precise translation and asynchronous blocking processing method for API response body content, which comprises the following steps that: a tree path encoder identifies a field to be translated by utilizing a reflection mechanism; and generating task metadata containing a path vector of the to-be-translated field in the JSON nested structure according to a path coding formula. The identifier generator and the serializer generate a global request serial number and task snapshot data and distribute asynchronous tasks. A regular cleaner generates a cleaned text, and a semantic compensation extraction algorithm executes logic truncation and splices a semantic compensation window to generate a to-be-translated input sequence. And the thread pool concurrently schedules a third-party engine to obtain translation blocks, and the structure reconstruction engine executes in-situ backfilling to generate a translated response body after eliminating redundant translation contents. And the exponential backoff retry device processes the exception, and the callback polling module adopts a double-track delivery strategy to deliver the result. The problem of context deficiency is solved, and translation continuity is guaranteed.

The invention discloses a signal transmission circuit, an internet access conversion method, a board card system and a server, and relates to the technical field of servers. The signal transmission circuit comprises an adaptable network port, a physical layer driver, a physical layer converter and a controller, the adaptable network port is connected with the physical layer driver through a third bus, the physical layer driver is connected with the physical layer converter through a serial / deserial bus, and the physical layer converter is connected with the controller through a first bus; the wire length of the serial / deserial bus is greater than the sum of the wire length of the third bus and the wire length of the first bus. The first signal is converted into the second signal for long-distance transmission and then converted into the quality-dependent interface signal, the signal transmission link from the adaptable network port to the controller is established, and the second signal is introduced into the signal transmission link due to the fact that the second signal is high in anti-interference capacity, so that the overall transmission quality of the signal is improved.

A serial-connection is tested by transmitting a PRBS generated using a kth-order monic-polynomial from transmission-circuitry to reception-circuitry, and determining operation is proper based upon the PRBS received. The PRBS is formed by generating x intermediate-words of the PRBS, x being a result of an integer-divide between a total number of bits in the PRBS and a bit-width of a serializer that transmits the PRBS, generating a leading-word of the PRBS as having first y-bits of the PRBS as its LSBs, y being based upon a modulo-divide between the total number of bits in the PRBS and x, and generating a trailing-word of the PRBS as having last z-bits of the PRBS as its MSBs, z being based upon a difference between a result of the modulo-divide and y. The PRBS is transmitted sequentially as the leading-word of the PRBS, the intermediate-words of the PRBS, and the trailing-word of the PRBS.

A transceiver circuit is disclosed, the transceiver circuit including a first register circuit, configured to receive serial stimulus data and to generate multi-bit parallel stimulus data, a serializer circuit configured to receive the multi-bit parallel stimulus data and to generate serialized data based on the multi-bit parallel stimulus data, where the serializer circuit includes a serializer data storage device, and where the serializer data storage device lacks circuit structures for scanability, a deserializer circuit configured to receive serial receiver data corresponding with the serialized data and to generate multi-bit parallel response data based on the serial receiver data, where the deserializer circuit includes a deserializer data storage device, and where the deserializer data storage device lacks circuit structures for scanability, and a second register circuit, configured to receive the multi-bit parallel response data and to generate serial response data.

A computer implementable method, an asset developer computer, and a computer readable medium for managing an asset for machine learning are provided. The method comprises retrieving, from a version control system server over a network, an asset for machine learning, deserializing the asset from a serialized asset data format to a deserialized asset data format using a seriazlier / deserializer to generate a deserialized asset, modifying, via at least one processor of an asset developer workstation, the deserialized asset to generate a new version of the asset, serializing the new version of the asset using the serializer / deserializer to generate a serialized new asset, and sending, from the asset developer workstation, the serialized new asset to the version control system server over the network for storage.

The invention provides a debugging method and device for a serial deserializer, electronic equipment and a storage medium, and the debugging method comprises the steps: obtaining a configuration file used for debugging the serial deserializer in response to an external instruction which is received by the serial deserializer and represents the start of debugging, and analyzing the configuration file, determining debugging command information in the configuration file; in response to the fact that the debugging command information is determined, performing debugging configuration on the serial deserializer so as to convert the running state of the serial deserializer into a debugging working state; and in response to the condition that the serial deserializer is in the debugging working state, debugging the serial deserializer based on the debugging command information to obtain a debugging result of the serial deserializer. Through the method, the debugging efficiency of the serial deserializer is improved, and the debugging stability of the serial deserializer is further improved.

The application disclose a digital serializer / deserializer circuit and a data eye monitoring method thereof. A received analog signal is converted to first digital samples at a first sample rate. The first digital samples are equalized to generate a first equalized signal. A symbol decision signal is generated from the first equalized signal. The received analog signal is converted to second digital samples at a second sample rate. Difference between the first digital samples and the second digital samples is determined, and the first equalized signal and the determined difference are combined to generate a signal processing output. A data eye error rate is determined according to the symbol decision signal and the signal processing output.

A transceiver circuit is disclosed, the transceiver circuit including a first register circuit, configured to receive serial stimulus data and to generate multi-bit parallel stimulus data, a serializer circuit configured to receive the multi-bit parallel stimulus data and to generate serialized data based on the multi-bit parallel stimulus data, where the serializer circuit includes a serializer data storage device, and where the serializer data storage device lacks circuit structures for scanability, a deserializer circuit configured to receive serial receiver data corresponding with the serialized data and to generate multi-bit parallel response data based on the serial receiver data, where the deserializer circuit includes a deserializer data storage device, and where the deserializer data storage device lacks circuit structures for scanability, and a second register circuit, configured to receive the multi-bit parallel response data and to generate serial response data.

A computer-implemented method for employing a time-series-to-text generation model to generate accurate description texts is provided. The method includes passing time series data through a time series encoder and a multilayer perceptron (MLP) classifier to obtain predicted concept labels, converting the predicted concept labels, by a serializer, to a text token sequence by concatenating an aspect term and an option term of every aspect, inputting the text token sequence into a pretrained language model including a bidirectional encoder and an autoregressive decoder, and using adapter layers to fine-tune the pretrained language model to generate description texts.

The invention provides a serializer, a 2N: N serializer and electronic equipment, sampling ends of a pull-up network of the serializer are coupled to two ends of a first input geminate transistor and two ends of a second input geminate transistor through different switches, an input end of the first input geminate transistor receives first input data, a second end of the first input geminate transistor is grounded through a switch and a first network in sequence, and a second end of the second input geminate transistor is grounded through a second network. The input end of the second input geminate transistor receives second input data, and the second end of the second input geminate transistor is grounded through the switch and the second network in sequence. The sampling end samples the first input data and the second input data based on the on-off of the switch. According to the invention, the sampling end is only communicated with the first input pair transistor or the second input pair transistor at the same time, so that the influence of unnecessary input data on the voltage of the sampling end is avoided, the intersymbol interference is effectively reduced, and the data transmission quality is improved.

The invention provides a multipurpose D2D transmitter, a configuration method thereof and a transmitter. The multipurpose D2D transmitter comprises a data loading module, a data detection module, a serializer module and an adjustment module, at least two delay units are arranged in the data loading module, the corresponding delay unit is selected according to the received mode control signal to delay the data signal and the indication signal, and the data detection module performs AND operation on the data signal and the indication signal after delay processing to obtain effective data. The serializer module obtains target data according to effective data, and the adjusting module performs logical operation on a target signal and a control signal and selects an SST driver according to a result so as to realize adjustment of impedance and balance. Therefore, according to the scheme, delay adjustability and bit width adjustability can be achieved, transmission requirements for different types of data can be met, adaptability to various application scenes is good, and flexible configuration of bit width, delay, impedance and balance of the transmitter by external signals can be supported.

The invention relates to the technical field of communication, and provides a signal quality adjusting and testing system, device and method of an optical module port and computer equipment. The debugging and testing device is connected with to-be-tested equipment and computer equipment; the computer equipment configures an equalization parameter for a serializer of an optical module port of the equipment to be tested; after the computer equipment configures equalization parameters for the serializer of the optical module port every time, the debugging and testing device receives a high-speed serial signal, sent by the equipment to be tested, of the serializer, evaluates the quality of the high-speed serial signal, obtains a signal quality testing result and feeds back the signal quality testing result to the computer equipment; and finally, the computer equipment selects a target equalization parameter of the serializer from each signal quality test result. The system can replace a conventional oscilloscope to adjust and test the signal of the optical module port, the debugging process is simple and convenient, the manual participation workload is small, and accidental errors can be reduced.

The invention relates to the technical field of computers, and provides a chip interface debugging method and device, a storage medium and a program product. The chip interface comprises a serializer and a deserializer, the serializer is connected with the deserializer through a plurality of channels, and the method comprises the following steps: determining a plurality of first parameter groups of an equalizer in the serializer and an error rate threshold value of each channel; debugging the chip interface according to the plurality of first parameter groups, and selecting at least one target parameter group for the serializer according to a debugging result and an error rate threshold; wherein when the chip interface is debugged at any time according to any first parameter group, the serializer outputs a test code pattern to the at least one channel, the deserializer determines the error rate of the channel according to the actual code pattern and the test code pattern received from each channel, and the obtained debugging result comprises the error rate of the at least one channel. According to the method, the hardware cost and the labor cost can be reduced, the debugging efficiency is improved, and the adaptability of the chip interface debugging method to different application scenes is improved.

The present invention relates to an interface circuit of a printhead. The interface circuit of the printhead at least includes the interface circuit of the printhead provided by the embodiments of the present invention. The interface circuit of the printhead at least includes a headboard connection circuit, a first printhead connection circuit, and a second printhead connection circuit. The headboard connection circuit is respectively connected to the headboard and the first printhead connection circuit. The first printhead connection circuit is connected to the printhead through the second printhead connection circuit. In the embodiments of the present invention, a serializer / deserializer circuit is provided between the headboard and the printhead, and a DVI-I interface and a standard cable are used for connection therebetween. At the same time, the headboard can be moved out of the existing printhead to the main control box, so that the size of the printhead is reduced, the printhead and the ink supply system can be efficiently maintained, and even the overall replacement of the printhead becomes a reasonable choice for customers, thereby greatly improving the reliability and production efficiency of the whole machine.

The utility model discloses a data conversion device, a data conversion system and debugging equipment. The device comprises a first video connector, a deserializer chip, a serializer chip and a second video connector, the flat panel display link FPD-Link camera is in signal connection with the first video connector, the first video connector is in signal connection with the deserializer chip, the deserializer chip is in signal connection with the serializer chip, and the second video connector is in signal connection with the serializer chip. The serializer chip is in signal connection with a second video connector, and the second video connector is in signal connection with a GMSL (Gigabit Multimedia Serial Link) controller. By applying the scheme provided by the utility model, the time cost and the research and development cost can be greatly reduced.

A detection system and a terminal device, which relate to the technical field of detection, and are used for reducing the power consumption of the detection system. The detection system comprises at least one first detection apparatus and a second detection apparatus, wherein the at least one first detection apparatus and the second detection apparatus perform communication by means of a serializer / deserializer (SerDes), and the second detection apparatus comprises a centralized processing unit; the at least one first detection apparatus is used for performing detection on least one first field of view so as to obtain at least one first echo signal, and sending the at least one first echo signal to the second detection apparatus by means of the SerDes; and the second detection apparatus is used for performing detection on a second field of view so as to obtain a second echo signal, and identifying a target by means of the centralized processing unit and on the basis of the first echo signal and the second echo signal. By means of using the SerDes to realize the communication between the at least one first detection apparatus and the second detection apparatus, communication loss can be reduced, and the power consumption of the detection system is saved on; and by means of providing the centralized processing unit in the second detection apparatus to process echo signals in a centralized manner, the power consumption can be further saved on, and the cost can also be reduced.

Techniques for universal data transmission to multiple cloud storage platforms are described. A universal data transmission system includes a data integration framework, a set of serializers, a plurality of authenticators, a plurality of transports, and a cloud connection service. The cloud connection service is capable of loading the data from an on-premise device to each of the plurality of cloud storage platforms. The cloud connection service receives a selection of a cloud storage platform for the cloud connection service to load the data and configures a plurality of channels based on the category of the collected data and the selected cloud storage platform to a specific configuration. The cloud connection service selects a specific serializer, a specific authenticator, and a specific transport, which are pluggable to form the transmission route connecting the on-premise device to the selected cloud storage platform.

The present disclosure relates to a configuration method and apparatus. An image processing device obtains an access configuration file from an image obtaining device, obtains a serializer configuration file and a deserializer configuration file based on the access configuration file, sends the serializer configuration file to the image obtaining device, and the serializer configuration file is used to configure a serializer that is in the image obtaining device, so as to enable the image obtaining device to convert an obtained parallel electrical signal into a serial electrical signal for transmission, and configures a deserializer that is in the image processing device by using the deserializer configuration file, to process a serial electrical signal that is from the image obtaining device, so as to obtain a parallel electrical signal that can be displayed on an image signal processing ISP chip.