63 results about "Serializer" patented technology

The invention relates to the technical field of serial deserializer design, and discloses an FPGA-based direct-current balanced digital audio and video signal serial deserializer, which comprises a serializer, a deserializer, a control configuration module, a power management module, a configuration storage module and a time sequence control module, the serializer is used for converting parallel digital audio and video data into high-speed serial data streams; the deserializer is used for detecting and repairing abnormal data in the high-speed serial data stream by using a machine learning technology, and converting the repaired high-speed serial data stream back to parallel digital audio and video data; the control configuration module is used for configuring working parameters of the serializer and the deserializer through an external interface; the time sequence control module is used for managing the time sequence relation in the system and ensuring synchronization of data flow between different modules. According to the method, the defects of a traditional deserializer in the aspects of anomaly detection and repair, signal quality evaluation and parameter optimization are overcome, and the stability and quality of high-resolution digital audio and video data transmission are improved.

A video display interface includes a first component, such as a mattress, having a serializer. A second component, such as a handheld pendant controller for the mattress, includes a deserializer and an electronic component, such as graphical user interface having a touch screen display. The serializer converts a first plurality of signals into a serial data signal that is transmitted through at least one wire to the deserializer. The deserializer converts the serial data signal into the second plurality of signals that are transmitted to the electronic component.

A video display interface includes a first component, such as a mattress, having a serializer. A second component, such as a handheld pendant controller for the mattress, includes a deserializer and an electronic component, such as graphical user interface having a touch screen display. The serializer converts a first plurality of signals into a serial data signal that is transmitted through at least one wire to the deserializer. The deserializer converts the serial data signal into the second plurality of signals that are transmitted to the electronic component.

Techniques for training a simulation of a Serializer / Deserializer (SerDes) receiver are described. For example, one implementation of a method includes: based on a channel impulse response (CIR) input, selecting a first receiver equalization model from a plurality of receiver equalization models using a first optimization process, the first receiver equalization model having a corresponding set of model parameters; converting the CIR to an equalized CIR based on the selected receiver equalization model and corresponding set of model parameters; predicting a first bit error rate (BER) based on the first receiver equalization model and corresponding set of model parameters using a second optimization process; and based on a difference between the first BER and an expected or known BER, selecting a second receiver equalization model from the plurality of receiver equalization models using the first optimization process.

Methods and systems for stacking multiple chips with high speed serializer / deserializer blocks are presented. These methods make use of Through Via (TV) to connect the dice to each other, and to the external pads. The methods enable efficient multilayer stacking that simplifies design and manufacturing, and at the same time, ensure high speed operation of serializer / deserializer blocks, using the TVs.

A method for serializing communications in the computing field includes serializing input data into a serialized stream of symbols, based on one or more encodings, at a serializer, each symbol including a disparity code selected based on a running disparity (RD) of the serialized stream of symbols. The running disparity (RD) is tracked by setting the RD to an initial value, and then adding a disparity of each symbol to the RD to ensure the RD does not exceed a desired maximum, e.g., three. A positive disparity encoding or a negative disparity encoding of each symbol is selected for transmission based on the RD. The serialized data stream of symbols is transmitted along a data conduit, to a deserializer, in which the serialized data stream of symbols is deserialized to determine a corresponding bit value, for outputting decoded information in parallel form.

The quality of service guaranteed function-free computing system comprises an HTTP gateway, a scheduler and a work pool; the HTTP gateway serializes the incoming DAG request through a serializer, and sequentially adds the serialized function-free function in the DAG request to a waiting queue; the scheduler retrieves the function-free function from the waiting queue and the chain running queue to the work pool for processing according to a scheduling strategy. The quality of service guaranteed function-free system and method of the application process the incoming request through the producer-consumer mode by reforming the scheduler in the platform. In addition, a strategy framework containing rich strategies is added. Different kinds of strategies are set for different kinds of application requests, so that the queuing time is reduced to a certain extent, and the running performance is improved.

The invention relates to a data transmission method and device and a vehicle, and relates to the technical field of data transmission. The method comprises the steps that a data collector obtains point cloud data; the data collector encodes the point cloud data to obtain first multimedia serial data, and transmits the first multimedia serial data to a serializer; the serializer converts the first multimedia serial data into a first data packet, and transmits the first data packet to a deserializer by using a multimedia serial link; the deserializer analyzes the first data packet to obtain first multimedia serial data, and transmits the first multimedia serial data to the controller. According to the invention, the multimedia serial link is used for transmission, so that the intelligent perception of the vehicle on the related elements of the road is realized; by utilizing the high bandwidth characteristic of the multimedia serial link, enough communication bandwidth is provided for data transmission between the data collector and the controller, so that the upgrade of the automatic driving technology is not limited by the communication bandwidth.

The application discloses a data alignment circuit based on a time-interleaved ADC topology and relates to the technical field of analog-to-digital converters, and aims to solve the problem of inaccurate timing correspondence in the data conversion process of a traditional data alignment circuit. The data alignment circuit comprises a first-stage flip-flop circuit, a second-stage flip-flop circuit and a third-stage flip-flop circuit; the clock input ends of the flip-flop circuits are connected to the sampling clock of the sub-ADCs of the time-interleaved ADC; the output end of the third-stage flip-flop circuit is connected to the input end of a serializer-deserializer; the first-stage flip-flop circuit comprises a plurality of first flip-flop sub-circuits; the data input ends of the first flip-flop sub-circuits are connected to the sub-ADCs in different rows of the time-interleaved ADC, respectively. The data alignment circuit based on the time-interleaved ADC topology can be used to keep accurate timing correspondence in the process of massive data conversion and transmission between the time-interleaved ADC and the serializer-deserializer.

The present invention discloses an image serializer and an electronic device, relating to the field of artificial intelligence technology. Among them, the image serializer receives read-write control parameters and original feature data through an input end, uses a read-write control module to determine a data writing method and a data reading method based on the read-write control parameters, and writes the original feature data into a data storage module according to the data writing method; under the control of the data reading method, corresponding data is read from the data storage module according to a convolution operation behavior method to generate feature matrix data, and the feature matrix data is output through an output end. The present invention can solve the problem that there are a large number of duplicate data in the im2col operation in the related art, effectively reduce the memory and data transmission overhead, effectively reduce the communication delay, improve the execution efficiency of artificial intelligence tasks, and thus effectively reduce the memory resources and computing resources required for artificial intelligence tasks.

The invention provides a data distribution device, a control system with the data distribution device and a configuration method of the data distribution device. The data distribution device comprises a deserializer and a plurality of serializers connected with the deserializer, the plurality of serializers comprise a first serializer and a second serializer, each of the first serializer and the second serializer comprises a first interface used for being connected with a control device and a second interface used for being connected with the deserializer, and the first interface is used for being connected with the control device. The first serializer is configured to perform initialization according to an initialization command received from a first interface of the first serializer, and the second serializer is configured to perform initialization according to an initialization command received from a first interface of the second serializer, and in response to completion of initialization, the second serializer is configured to perform initialization according to an initialization command received from a second interface of the second serializer. And notifying the deserializer that the second serializer has completed initialization through a second interface of the second serializer.

A computer implementable method, an asset developer computer, and a computer readable medium for managing an asset for machine learning are provided. The method comprises retrieving, from a version control system server over a network, an asset for machine learning, deserializing the asset from a serialized asset data format to a deserialized asset data format using a seriazlier / deserializer to generate a deserialized asset, modifying, via at least one processor of an asset developer workstation, the deserialized asset to generate a new version of the asset, serializing the new version of the asset using the serializer / deserializer to generate a serialized new asset, and sending, from the asset developer workstation, the serialized new asset to the version control system server over the network for storage.

This utility model discloses a large-screen video signal simulator, comprising: at least one MCU module, at least one serializer, and at least one memory. The memory stores a level status table. The serializer is connected to the MCU module. The MCU module reads the level status of the serializer and compares it with the level status table to determine the type of the serializer. It also includes at least one SOC module, which communicates with the MCU module. The serializer communicates with both the SOC module and the MCU module. This utility model has a simple structure. The MCU module reads the pin levels of the serializer and compares them with data in its internal memory to determine the type of the serializer. Based on the different execution codes of different types of serializers, the corresponding serializer is configured via I2C. The CANFD protocol is used to notify the SOC module to switch the video feed on the in-vehicle large screen, such as switching between side and rear video feeds.

The utility model discloses a video acquisition circuit, electronic equipment and a vehicle driving system, and relates to the technical field of video monitoring. In an acquisition circuit between a processor and a camera, in consideration of interface resource limitation of the processor, on the basis of a first-stage deserializer of the acquisition circuit, a serializer is added, so that video data of a multi-path camera module is serialized, and the serialized data occupies one path of interface of the first-stage deserializer in a one-path interface manner; and the access of multiple paths of modules is realized through one path of interface. Through the access of N stages of deserializers, one stage of serializer is connected between every two stages of deserializers, so that the next stage of deserializer can be connected with a plurality of cameras under the condition that each stage of deserializer can be connected with the plurality of cameras, the interface resources of the deserializers are fully utilized to access a plurality of camera modules, and the multi-camera module access efficiency is improved. And when each stage of serializer is finally accessed to the first stage of deserializer, one path of interface is adopted for access, so that the requirement of sufficient interface resources for transmission of a plurality of interfaces is met, and the experience feeling of a user is improved.

A recording device for a recording of a serialized image data stream from a sensor device. The recording device comprises a deserializer for deserializing the image data stream. To configure the first deserializer, the recording device comprises a configuration device, which records a configuration data stream transmitted by a receiving device for the purpose of configuring a serializer arranged in the sensor device and derives a configuration of the deserializer of the recording device by an analysis of the recording of the configuration data. In an example, the derivation takes place by an abstraction of the configuration of the serializer into a functionality of the serializer, a derivation of a functionality of the first deserializer from the functionality of the first serializer, and a concretization of the functionality of the first deserializer into a configuration of the first deserializer.

Examples of technology disclosed herein determine, by a serializer and a deserializer, one or more of calibration parameters and adaptive equalization (AEQ) parameters to perform calibration and AEQ for a communication link between the serializer and the deserializer. Such examples store the one or more parameters into a retention memory, and then put at least one of the serializer and deserializer into a sleep / low power mode. Upon receiving a wakeup command at each of the serializer and the deserializer put into the sleep mode, the serializer and the deserializer perform link lock of the communication link using the stored parameters.

The present disclosure provides a method and apparatus for acquiring a timestamp of a data stream, a storage medium and an electronic apparatus. The method for acquiring the timestamp of the data stream includes: receiving a data stream to be transmitted, and acquiring a first frame header identifier of the data stream to be transmitted in a serializer-deserializer (SERDES) clock mode, the first frame header identifier being used for representing a position of a frame header of the data stream to be transmitted; determining, based on the first frame header identifier, a timestamp of the data stream to be transmitted under a system clock; encapsulating the timestamp to obtain a first target data frame; and outputting the first target data frame.

A serializer and a deserializer are disclosed. The serializer includes a sequence module and a data up-conversion module. The data up-conversion module receives a data packet sequence from a media access control block based on an output operation frequency and outputs the data packet sequence based on a sequence operation frequency. The deserializer includes a de-sequence module and a plurality of data down-conversion modules. The deserializer generates a data operation frequency based on a de-sequence operation frequency and outputs a recovered data packet sequence based on the data operation frequency. Embodiments of the present application can transmit or receive data in coordination with an operation frequency of a media access control block and exchange data at a transmission frequency that meets the transmission specification requirements of a physical layer, thereby achieving the goal of improving the convenience of the serializer and the deserializer in applications.

Techniques for universal data transmission to multiple cloud storage platforms are described. A universal data transmission system includes a data integration framework, a set of serializers, a plurality of authenticators, a plurality of transports, and a cloud connection service. The cloud connection service is capable of loading the data from an on-premise device to each of the plurality of cloud storage platforms. The cloud connection service receives a selection of a cloud storage platform for the cloud connection service to load the data and configures a plurality of channels based on the category of the collected data and the selected cloud storage platform to a specific configuration. The cloud connection service selects a specific serializer, a specific authenticator, and a specific transport, which are pluggable to form the transmission route connecting the on-premise device to the selected cloud storage platform.

The invention relates to the technical field of API (Application Program Interface) data processing and machine translation, and discloses a precise translation and asynchronous blocking processing method for API response body content, which comprises the following steps that: a tree path encoder identifies a field to be translated by utilizing a reflection mechanism; and generating task metadata containing a path vector of the to-be-translated field in the JSON nested structure according to a path coding formula. The identifier generator and the serializer generate a global request serial number and task snapshot data and distribute asynchronous tasks. A regular cleaner generates a cleaned text, and a semantic compensation extraction algorithm executes logic truncation and splices a semantic compensation window to generate a to-be-translated input sequence. And the thread pool concurrently schedules a third-party engine to obtain translation blocks, and the structure reconstruction engine executes in-situ backfilling to generate a translated response body after eliminating redundant translation contents. And the exponential backoff retry device processes the exception, and the callback polling module adopts a double-track delivery strategy to deliver the result. The problem of context deficiency is solved, and translation continuity is guaranteed.

The utility model provides a polling type data transmission device and a polling type data transmission system, and the polling type data transmission device carries out the polling adaption of a deserializer polling module and a serializer in a camera through the arrangement of a transistor control structure, and carries out the polling adaption of the serializer polling module and a data collection device in the camera. Therefore, the defect that the serializer of the camera is not matched with the deserializer of the data acquisition equipment in model is overcome, and the problem that in the prior art, transmission between the camera and the data acquisition equipment can be carried out in a serial port mode under the condition that the deserializer needs to be matched with the serializer in model is solved.

The invention discloses a signal transmission circuit, an internet access conversion method, a board card system and a server, and relates to the technical field of servers. The signal transmission circuit comprises an adaptable network port, a physical layer driver, a physical layer converter and a controller, the adaptable network port is connected with the physical layer driver through a third bus, the physical layer driver is connected with the physical layer converter through a serial / deserial bus, and the physical layer converter is connected with the controller through a first bus; the wire length of the serial / deserial bus is greater than the sum of the wire length of the third bus and the wire length of the first bus. The first signal is converted into the second signal for long-distance transmission and then converted into the quality-dependent interface signal, the signal transmission link from the adaptable network port to the controller is established, and the second signal is introduced into the signal transmission link due to the fact that the second signal is high in anti-interference capacity, so that the overall transmission quality of the signal is improved.

A serial-connection is tested by transmitting a PRBS generated using a kth-order monic-polynomial from transmission-circuitry to reception-circuitry, and determining operation is proper based upon the PRBS received. The PRBS is formed by generating x intermediate-words of the PRBS, x being a result of an integer-divide between a total number of bits in the PRBS and a bit-width of a serializer that transmits the PRBS, generating a leading-word of the PRBS as having first y-bits of the PRBS as its LSBs, y being based upon a modulo-divide between the total number of bits in the PRBS and x, and generating a trailing-word of the PRBS as having last z-bits of the PRBS as its MSBs, z being based upon a difference between a result of the modulo-divide and y. The PRBS is transmitted sequentially as the leading-word of the PRBS, the intermediate-words of the PRBS, and the trailing-word of the PRBS.

A transceiver circuit is disclosed, the transceiver circuit including a first register circuit, configured to receive serial stimulus data and to generate multi-bit parallel stimulus data, a serializer circuit configured to receive the multi-bit parallel stimulus data and to generate serialized data based on the multi-bit parallel stimulus data, where the serializer circuit includes a serializer data storage device, and where the serializer data storage device lacks circuit structures for scanability, a deserializer circuit configured to receive serial receiver data corresponding with the serialized data and to generate multi-bit parallel response data based on the serial receiver data, where the deserializer circuit includes a deserializer data storage device, and where the deserializer data storage device lacks circuit structures for scanability, and a second register circuit, configured to receive the multi-bit parallel response data and to generate serial response data.

A computer implementable method, an asset developer computer, and a computer readable medium for managing an asset for machine learning are provided. The method comprises retrieving, from a version control system server over a network, an asset for machine learning, deserializing the asset from a serialized asset data format to a deserialized asset data format using a seriazlier / deserializer to generate a deserialized asset, modifying, via at least one processor of an asset developer workstation, the deserialized asset to generate a new version of the asset, serializing the new version of the asset using the serializer / deserializer to generate a serialized new asset, and sending, from the asset developer workstation, the serialized new asset to the version control system server over the network for storage.

The invention provides a debugging method and device for a serial deserializer, electronic equipment and a storage medium, and the debugging method comprises the steps: obtaining a configuration file used for debugging the serial deserializer in response to an external instruction which is received by the serial deserializer and represents the start of debugging, and analyzing the configuration file, determining debugging command information in the configuration file; in response to the fact that the debugging command information is determined, performing debugging configuration on the serial deserializer so as to convert the running state of the serial deserializer into a debugging working state; and in response to the condition that the serial deserializer is in the debugging working state, debugging the serial deserializer based on the debugging command information to obtain a debugging result of the serial deserializer. Through the method, the debugging efficiency of the serial deserializer is improved, and the debugging stability of the serial deserializer is further improved.

The application disclose a digital serializer / deserializer circuit and a data eye monitoring method thereof. A received analog signal is converted to first digital samples at a first sample rate. The first digital samples are equalized to generate a first equalized signal. A symbol decision signal is generated from the first equalized signal. The received analog signal is converted to second digital samples at a second sample rate. Difference between the first digital samples and the second digital samples is determined, and the first equalized signal and the determined difference are combined to generate a signal processing output. A data eye error rate is determined according to the symbol decision signal and the signal processing output.

A transceiver circuit is disclosed, the transceiver circuit including a first register circuit, configured to receive serial stimulus data and to generate multi-bit parallel stimulus data, a serializer circuit configured to receive the multi-bit parallel stimulus data and to generate serialized data based on the multi-bit parallel stimulus data, where the serializer circuit includes a serializer data storage device, and where the serializer data storage device lacks circuit structures for scanability, a deserializer circuit configured to receive serial receiver data corresponding with the serialized data and to generate multi-bit parallel response data based on the serial receiver data, where the deserializer circuit includes a deserializer data storage device, and where the deserializer data storage device lacks circuit structures for scanability, and a second register circuit, configured to receive the multi-bit parallel response data and to generate serial response data.

A computer-implemented method for employing a time-series-to-text generation model to generate accurate description texts is provided. The method includes passing time series data through a time series encoder and a multilayer perceptron (MLP) classifier to obtain predicted concept labels, converting the predicted concept labels, by a serializer, to a text token sequence by concatenating an aspect term and an option term of every aspect, inputting the text token sequence into a pretrained language model including a bidirectional encoder and an autoregressive decoder, and using adapter layers to fine-tune the pretrained language model to generate description texts.

The invention provides a serializer, a 2N: N serializer and electronic equipment, sampling ends of a pull-up network of the serializer are coupled to two ends of a first input geminate transistor and two ends of a second input geminate transistor through different switches, an input end of the first input geminate transistor receives first input data, a second end of the first input geminate transistor is grounded through a switch and a first network in sequence, and a second end of the second input geminate transistor is grounded through a second network. The input end of the second input geminate transistor receives second input data, and the second end of the second input geminate transistor is grounded through the switch and the second network in sequence. The sampling end samples the first input data and the second input data based on the on-off of the switch. According to the invention, the sampling end is only communicated with the first input pair transistor or the second input pair transistor at the same time, so that the influence of unnecessary input data on the voltage of the sampling end is avoided, the intersymbol interference is effectively reduced, and the data transmission quality is improved.