21results about "Angle demodulation by phase difference detection" patented technology

Systems and methods for synchronizing networks are described. A phase monitor circuit can determine at least one phase offset among a plurality of reference clock signals. A timing circuit can generate an output clock signal using a primary reference clock. The primary reference clock can be among the plurality of reference clock signals. The timing circuit can determine failure of the primary reference clock. The timing circuit can, in response to the failure of the primary reference clock, generate the output clock signal using a specific phase offset and a secondary reference clock for the PLL. The specific phase offset can be among the at least one phase offset determined by the phase monitor circuit, the specific phase offset is between the primary reference clock and the secondary reference clock, and the secondary reference clock can be among the plurality of reference clock signals.

The disclosure includes a memory, a horizontal synchronization detection circuit, a phase comparator, a lock circuit, a PLL, and a frequency divider. The memory that reads out a written video signal in response to a read clock signal and outputs it as an output video signal. The horizontal synchronization detection circuit detects a horizontal synchronization signal from the video signal. The phase comparator generates a phase difference signal indicating a phase difference between the horizontal synchronization signal and a frequency-divided clock signal. The lock circuit receives a free-running clock signal and generates a reference clock signal in which a phase signal is shifted by an amount of the phase difference indicated by the phase difference signal. The PLL generates the read clock signal that is locked to the phase of the reference clock signal. The frequency divider generates the frequency-divided clock signal by dividing the read clock signal.

A phase detector is provided according to this disclosure. The phase detector of this disclosure comprises a first transistor leg and a second transistor leg. Each of the first and second transistor legs includes a pair of transistors connected to each other at a plurality of common nodes. The phase detector of this disclosure further comprises an input section connected to the first transistor leg. The input section is configured to receive a first input signal and a second input signal. The phase detector of this disclosure further comprises an output section connected to the second transistor leg. The output section is configured to provide an output signal. The output signal includes a component indicating the phase difference between the first input signal and the second input signal.

Certain aspects of the present disclosure are directed towards apparatus and techniques for receiver calibration. An example apparatus generally includes: a first receiver having a first oscillating signal generation circuit, an output of the first oscillating signal generation circuit being coupled to an input of a first splitter, wherein the first splitter has multiple outputs; a second receiver having a second oscillating signal generation circuit coupled to an LO input of each of a first plurality of mixers of the second receiver; and signal paths between the multiple outputs of the first splitter and signal inputs of the first plurality of mixers, respectively.

The invention provides a demodulation circuit and a digital isolator. The demodulation circuit comprises a waveform regulator, a first counter, a second counter and an SR latch. The waveform adjuster generates an adjusted modulation signal from a differential isolation modulation signal generated by modulating an input data signal with a carrier clock signal. The first counter counts a period of the adjusted modulation signal to generate a set signal. The second counter counts cycles of a reference clock signal to generate a reset signal. The SR latch comprises: a setting end, which is used for receiving the setting signal; the reset end is used for receiving the reset signal; and the output end is used for outputting the demodulated output signal. And the SR latch is triggered by the setting signal to pull up the demodulated output signal, and is triggered by the reset signal to pull down the demodulated output signal.

According to an embodiment, a circuit for quadrate error correction is proposed. The circuit includes a set of first resistors receiving a demodulated low-voltage differential signal from gyroscope sense electrodes; an ICMFB circuit with adjustable current sinks maintaining a low-voltage input level by controlling current; an HV driver circuit creating a high-voltage differential output from the low-voltage input, supplied to gyroscope correction electrodes; a set of second resistors where the input-to-output differential gain is defined by their relative resistances; and an output common-mode feedback circuit adapting the high-voltage output to a low-voltage for the HV driver.

The application discloses a kind of full symmetry MEMS resonator phase demodulation error identification and compensation method, system, medium and equipment in the technical field of circuit error, to solve the problem that prior art cannot meet actual demand.The detection modal output signal, demodulation reference signal and modulation signal are obtained;The detection modal output signal and the demodulation reference signal are in-phase demodulated and quadrature demodulated, and high-frequency components are filtered out using a low-pass filter to obtain in-phase demodulated signals and quadrature demodulated signals;The phase of the detection modal output signal is left-shifted by 22.5°, and the phase of the demodulation reference signal is right-shifted by 22.5°;The demodulation reference signal after phase shift is multiplied with the detection modal output signal after phase shift to obtain new in-phase demodulated signals and quadrature demodulated signals;The amplitude of the in-phase demodulated signals and the quadrature demodulated signals is compared with that of the new in-phase demodulated signals and the quadrature demodulated signals, and the phase error is obtained by fitting a curve equation and phase correction is performed.

A lock-detection circuit detects whether a first clock signal is frequency locked to a second clock signal. A lock-detection scheme that continuously evaluates the lock condition between the clock signals and as programmable frequency-offset tolerances for reporting lock acquisition and loss. A quadrature clock generator produces two periodic signals from the first clock signal. The periodic signals are in quadrature, which is to say they are misaligned with one another by ninety degrees. These quadrature signals are sampled on edges of the second clock signal to produce a sequence of states that exhibit a Gray-code progression if first and second clock signals are locked. Errors in the Gray-code progression indicate whether edges of the first clock signal are early or late with respect to the second clock signal. The lock-detection circuit is adjustable to indicate loss of lock under in dependence upon the temporal spacing of errors.

An injection-locked clock multiplier includes an oscillator control unit configured to output an injection clock signal with a frequency of N times a reference clock signal, an error detector configured to detect a frequency error indicating whether a frequency of the injection clock signal corresponds to the N times the frequency of the reference clock signal in a first operation mode and configured to detect an error due to injection path non-ideality from the injection clock signal in a second operation mode, and an error adjuster configured to receive one of information on the frequency error and information on the error due to the injection path non-ideality from the error detection unit and configured to adjust an operation frequency of the oscillator based on the frequency error or configured to adjust an operation cycle of the oscillator based on the error due to the injection path non-ideality.

A method of operating an interface device including a first elastic buffer is provided. The method of operating the interface device includes performing a link equalization operation, checking a transmission mode of the interface device, and determining a transmission parameter of the interface device based on a status of the first elastic buffer or a status of a second elastic buffer included in another interface device communicating with the interface device when the transmission mode is a transmission parameter adjustment mode.

A clock and data recovery device includes an equalizer that compensates for channel loss of input data, a phase detector that compares data output from the equalizer and a fed back clock and outputs an up signal and a down signal, a charge pump that operates according to the up signal and the down signal to output a control signal, a loop filter that removes a high-frequency component included in the control signal output from the charge pump, a voltage-controlled oscillator that changes a frequency of the clock and outputs the clock according to the control signal from which the high-frequency component is removed, and a voltage-controlled oscillator buffer that adjusts a slew rate of the clock output by the voltage-controlled oscillator according to the up signal and the down signal directly received from the phase detector and transmits the clock to the phase detector.

An apparatus is described comprising a plurality of phase modulator pairs arranged in series, each phase modulator pair comprising a first phase modulator and a second phase modulator. The modulators of the first pair of the plurality receive a modulation signal and a carrier signal. Each modulator pair includes a phase shift circuit for phase shifting the carrier signal based on the modulation signal. The modulators of the last pair of the plurality provide outputs of carrier signals modulated based on the modulation signal.

In one embodiment, the disclosure includes a network node synchronization system. The system may include a first node. The first node may include a first host card comprising a first (TOD) time of day counter, a first digital signal processor (DSP) comprising a first DSP counter; and a first optical communication device comprising a first DSP communication channel, wherein the first DSP communication channel transports DSP frames. In various embodiments, the DSP is a coherent DSP.

A circuit includes (i) an input terminal for receiving a single-ended input signal; (ii) an operational amplifier (op-amp) comprising an inverting input, a non-inverting input, and an op-amp output; (iii) a capacitor coupled between the inverting input and the op-amp output; (iv) a first resistor coupled between the inverting input and the input terminal; and (v) a second resistor coupled between the non-inverting input and the input terminal. In an example, a phase locked loop (PLL) includes the circuit, and a voltage controlled oscillator (VCO) is coupled to the output of the operational amplifier.

An apparatus is described comprising a plurality of phase modulator pairs arranged in series, each phase modulator pair comprising a first phase modulator and a second phase modulator. The modulators of the first pair of the plurality receive a modulation signal and a carrier signal. Each modulator pair includes a phase shift circuit for phase shifting the carrier signal based on the modulation signal. The modulators of the last pair of the plurality provide outputs of carrier signals modulated based on the modulation signal.

A multiple-frequency receiver is disclosed and includes a single voltage-controlled oscillator (VCO) configured to generate an output frequency; a first division circuit configured to divide the output frequency by a first value to generate a first local oscillator (LO) frequency for a first frequency chain; and a second division circuit configured to divide the output frequency by a second value to generate a second LO frequency for a second frequency chain, wherein the first value is different than the second value.

The application discloses a lubricating oil metal debris monitoring device and method, which is applied to the technical field of signal detection and comprises a lubricating oil metal debris sensor, an excitation circuit, a routing circuit, an analog-digital conversion circuit, a collection circuit for outputting a received induction signal to the analog-digital conversion circuit after demodulation and amplification, and a processing circuit for applying an excitation signal through the excitation circuit in an adaptation mode, obtaining an induction signal from the lubricating oil metal debris sensor output by a first output end of the routing circuit through the analog-digital conversion circuit, and determining a phase difference between the excitation signal and the induction signal; in a monitoring mode, a reference signal for demodulation is generated based on the phase difference and sent to the collection circuit, and a detection result of the metal debris is obtained by analyzing an output signal of the analog-digital conversion circuit. The scheme of the application can be flexibly adapted to lubricating oil metal debris sensors of different manufacturers.

The invention relates to a method for demodulation comprising the following steps: - exciting a oscillation element (1) which is mounted such that it can oscillate and is designed as a beam, at least in some sections, to oscillate in the range of a resonant frequency of the oscillation element (1), an excitation signal (Aact) which varies over time, particularly periodically, being used for the excitation, and at least the variation of the excitation signal (uact) over time being known or being determined; - detecting a modulated oscillation of the oscillation element (1) by means of at least one sensor (2), the sensor (2) supplying a sensor measured variable (SMG) which varies over time as a function of an amplitude (Ac) and a phase (φc) of the modulated oscillation of the oscillation element (1). According to the invention, the method comprises the following step: - generating a first comparison signal (VS1) by amplitude modulation of a known demodulation signal (DMS) which varies over time, particularly periodically, by means of the sensor measured variable (SMG) which varies over time.

A spectroscopic measurement system, comprising: a laser source (110) configured to generate a pump beam (BP) and a Stokes beam (BS), a modulator (120) configured to modulate one of the beams (BP, BS), a beam overlap system (130) configured to spatially and temporally overlap the beams (BP, BS), a sample holder (140) configured to receive the overlapped beams, at least one detector (150) configured to detect a signal resulting from Stimulated Raman Scattering (SRS), and a lock-in amplifier (160) configured to generate an output signal based on an input signal from the detector (150) and a reference signal (REF), characterized in that the drive signal for the modulator (120) and the reference signal (REF) for the lock-in amplifier (160) are both provided by the internal reference oscillator (INT_TRG) of the lock-in amplifier (160).

Random number generator (GL) comprises three ring oscillators (GP1, GP2, GP3) and seven bistables (UB1, UB2, UB3, UB4, UB5, UB6, UB7). The ring oscillators (GP1, GP2, GP3) comprise delay lines (LO1, LO2, LO3) closed in loops. The delay lines (LO1, LO2, LO3) comprise delays (EO) connected in series between inputs (i-LO1, i-L02, i-L03) and outputs (o-LO1, o-LO2, o-LO3) of the delay lines. Outputs (o-UB1, o-UB2, o-UB3, o-UB4, o-UB5, o-UB6, o-UB7) of the bistables (UB1, UB2, UB3, UB4, UB5, UB6, UB7) are connected to outputs (o1-GL, o2-GL, o3-GL, o4-GL, o-5GL, o6-GL, o7-GL) of the random number generator (GL). Inputs (i1-UB1, 12-UB1, 11-UB2, 12-UB2, 11-UB3, 12-UB3, 11-UB4, i2-UB4, 11-UB5, 12-UB5, 11-UB6, 12-UB6, 11-UB7, 12-UB7) of the bistables (UB1, UB2, UB3, UB4, UB5, UB6, UB7) are connected to the delay lines (LO1, LO2, LO3) of the ring oscillators (GP1, GP2, GP3) to outputs of selected delays (EO).

In one embodiment, an apparatus comprises: a receiver to receive training data from a transmitter; a clock and data recovery (CDR) circuit coupled to the receiver, the CDR circuit to recover a recovered clock signal from the training data; and a media access control (MAC) circuit coupled to the CDR circuit, wherein the MAC circuit is to send a clock switch indicator to the CDR circuit to cause the CDR circuit to halt tracking operation of the CDR circuit. Other embodiments are described and claimed.