3765results about "Angle demodulation by phase difference detection" patented technology

The present invention provides methods and apparatus for implementing spatial multiplexing in conjunction with the one or more multiple access protocols during the broadcast of information in a wireless network. A wireless cellular network for transmitting subscriber datastream(s) to corresponding ones among a plurality of subscriber units located within the cellular network is disclosed. The wireless cellular network includes base stations and a logic. The base stations each include spatially separate transmitters for transmitting, in response to control signals, selected substreams of each subscriber datastream on an assigned channel of a multiple access protocol. The logic communicates with each of the base stations. The logic assigns an available channel on which to transmit each subscriber datastream. The logic routes at least a substream of each datastream to at least a selected one of the base stations. The logic also generates control signals to configure the at least a selected one of the base stations to transmit the selected substreams to a corresponding one among the plurality of subscriber units on the assigned channel. A subscriber unit for use in a cellular system is also disclosed. The subscriber unit includes: spatially separate receivers, a spatial processor, and a combiner. The spatially separate receivers receive the assigned channel composite signals resulting from the spatially separate transmission of the subscriber downlink datastream(s). The spatial processor is configurable in response to a control signal transmitted by the base station to separate the composite signals into estimated substreams based on information obtained during the transmission of known data patterns from at least one of the base stations. The spatial processor signals the base stations when a change of a spatial transmission configuration is required. The combiner combines the estimated substreams into a corresponding subscriber datastream.

A system and method for synchronizing a local clock to a reference clock using a linear model of the error between the local clock and the reference clock is disclosed. In one embodiment, a direct smoothing process is used in conjunction with the linear model to estimate a frequency offset by which the frequency of an oscillator of the local clock is adjusted. Also disclosed herein is a phased-lock loop (PLL) adapted to synchronize a local clock with a reference clock using the direct smoothing process, as well as a system implementing the PLL for timing the playout of data received from a transmitter.

A fully integrated, programmable mixed-signal transceiver comprising a radio frequency integrated circuit (RFIC) which is frequency and protocol agnostic with digital inputs and outputs, the transceiver being programmable and configurable for multiple radio frequency bands and standards and being capable of connecting to many networks and service providers. The RFIC does not use spiral inductors and instead includes transmission line inductors allowing for improved scalability. Components of the transceiver are programmable to allow the transceiver to switch between different frequency bands of operating. Frequency switching can be accomplished though the content of digital registers coupled to the components.

[Problems] To realize a reliable and stable transfer of digital data that does not require a reference clock and a handshake operation.

[Means for Solving the Problem] The present invention provides a digital data transfer method for alternately and periodically transferring first information and second information respectively in a first period and in a second period, wherein: an amount of information of the first information per unit time in the first period is greater than an amount of information of the second information per unit time in the second period; and the second information in the first period is transferred as pulse-width-modulated serial data.

Clock alignment circuits and techniques for reducing power dissipation, increasing power supply noise immunity, decreasing process and temperature variation sensitivity, and providing a wide operating range. A power supply generator generates an isolated supply voltage for a delay line used in a clock alignment circuit. The delay line generates a delayed clock from a reference clock. A comparator detects a correction information (i.e., delay or phase error) between the delayed clock and the reference clock and generates error information representative of the correction information. A charge pump circuit converts the error information into a voltage signal, wherein the voltage signal is a scaled representation of the error information. The power supply generator includes an amplifier having a first input coupled to the voltage signal and an output to provide the supply voltage and a capacitor coupled between the supply voltage and a ground voltage, wherein the amplifier tracks the voltage signal level to regulate the supply voltage.

The present invention is related to a method for multi-user wireless transmission of data signals in a communication system having at least one base station and at least one terminal. It comprises, for a plurality of users, the following steps: adding robustness to frequency-selective fading to the data to be transmitted. performing spreading and scrambling of at least a portion of a block of data, obtainable by grouping data symbols by demultiplexing using a serial-to-parallel operation, combining (summing) spread and scrambled portions of the blocks of at least two users, adding transmit redundancy to the combined spread and scrambled portions, and transmitting the combined spread and scrambled portions with transmit redundancy.

An efficient decoding of vector signaling codes is obtained using a circuit that ranks received signal levels, designates ranked values as representing particular code elements, and translates those particular code elements into a decoded result. An optimized ranking circuit combines analog crossbar switching of signal values with comparators that provide digital results. These elements may be repetitively tiled into processing arrays capable of larger ranking operations, or iteratively applied to selected portions of the data set under control of a sequencer or controller.

Systems, apparatus, and methods for new generations of wireless systems, including multiple standard, interoperable Third-Generation (3G) and Second-Generation (2G), Spread Spectrum CDMA, WCDMA, GSM, Enhanced GSM systems and CSMA, TDMA and OFDM. Bit Rate Agile (BRA), Modulation and Code Selectable processing techniques of Gaussian Minimum Shift Keying (GMSK), Quadrature Phase Shift Keying (QPSK), Quadrature Amplitude Modulation (QAM), and of Mis-Matched demodulator filters in which the demodulator filter set is mismatched to the filter set of the signal modulator.

Circuits and methods are provided for implementing programmable sub-integer N frequency dividers for use in, e.g., frequency synthesizer applications, providing glitch free outputs signals with minimal fractional spurs. Phase-rotating sub-integer N frequency dividers are programmable to provide multi-modulus division with a wide range of arbitrary sub-integer division ratios.

A digital communications transmitter (100) includes a digital linear-and-nonlinear predistortion section (200, 1800, 2800) to compensate for linear and nonlinear distortion introduced by transmitter-analog components (120). A direct-digital-downconversion section (300) generates a complex digital return-data stream (254) from the analog components (120) without introducing quadrature imbalance. A relatively low resolution exhibited by the return-data stream (254) is effectively increased through arithmetic processing. Distortion introduced by an analog-to-digital converter (304) may be compensated using a variety of adaptive techniques. Linear distortion is compensated using adaptive techniques with an equalizer (246) positioned in the forward-data stream (112). Nonlinear distortion is then compensated using adaptive techniques with a plurality of equalizers (226) that filter a plurality of orthogonal, higher-ordered-basis functions (214) generated from the forward-data stream (112). The filtered-basis functions are combined together and subtracted from the forward-data stream (112).

A novel apparatus for and a method of estimating, calibrating and tracking in real-time the gain of a radio frequency (RF) digitally controlled oscillator (DCO) in an all-digital phase locked loop (ADPLL). Precise setting of the inverse DCO gain in the ADPLL modulating path allows direct wideband frequency modulation that is independent of the ADPLL loop bandwidth. The gain calibration technique is based on a steepest descent iterative algorithm wherein the phase ADPLL error is sampled and correlated with the modulating data to generate a gradient. The gradient is then scaled and added to the current value of the DCO gain multiplier.

A delay compensation circuit for a delay locked loop which includes a main delay line having a fine delay line comprising fine delay elements and a coarse delay line comprising coarse delay elements, the main delay line being controlled by a controller, the delay compensation circuit comprising: an adjustable fine delay for modeling a coarse delay element, a counter for controlling the adjustable fine delay to a value which is substantially the same as that of a coarse delay element, a circuit for applying a representation of the system clock to the delay compensation circuit, and a circuit for applying the fine delay count from the counter to the controller for adjusting the fine delay line of the main delay line to a value which is substantially the same as that of a coarse delay element of the main delay line.

A novel interpolating phase detector for use in a multiphase PLL is described comprising an array of individual phase comparators, all operating at essentially the same operating point which permits the circuits to be designed simultaneously for high speed and for low power consumption. Two adjacent phase outputs of a multi-phase VCO may be selected and interpolated in between, by selectively attaching a variable number of phase comparators to each phase output and summing their phase error outputs. By varying the number of phase comparators attached to each phase output, interpolation can be achieved with high linearity.