14 results about "Digital control oscillator" patented technology

The invention relates to the technical field of digital signal processing, and particularly discloses a mixed precision low-resource digital control oscillator implementation method and system based on an FPGA (Field Programmable Gate Array), and the method comprises the steps: dividing a 32-bit phase accumulator into a high-bit 24-bit dominant frequency control section and a low-bit 8-bit dynamic compensation section, and carrying out the phase accumulation in parallel through double carry chains, the high-order section receives high 24 bits of a frequency tuning word FTW to control a dominant frequency, and the low-order section receives low 8 bits of the FTW and overlaps an overflow remainder to dynamically compensate for a phase error. According to the implementation method of the mixed precision low-resource digital control oscillator based on the FPGA disclosed by the embodiment of the invention, through collaborative innovation of mixed precision phase accumulation, hierarchical mixed storage, high-order interpolation reconstruction and dynamic phase compensation, the core problems of a traditional NCO in resource occupation, phase continuity, waveform precision and time sequence performance are systematically solved.

A communication system includes a master communication device and a slave communication device. The master communication device includes a first signal generator, a second signal generator, a signal combiner, and a transmitting HBC (Human Body Communication) electrode. The signal combiner combines a first signal with a second signal, so as to generate a third signal. The transmitting HBC electrode transmits the third signal through a human body. The slave communication device includes a receiving HBC electrode, a signal splitter, a processor, and an injection-locked DCO (Digital Control Oscillator). The receiving HBC electrode receives a mix signal from the human body. The signal splitter divides the mix signal into a data signal and a synchronization signal. The injection-locked DCO performs a time synchronization process according to the synchronization signal.

The application discloses a satellite navigation receiver signal processing method and system, and belongs to the technical field of satellite navigation. The method comprises the following steps: step 1, initializing the satellite navigation receiver, and establishing a communication link between the satellite navigation receiver and an RTK reference station; step 2, processing received satellite signals by the satellite navigation receiver to obtain satellite ephemeris parameters; then combining the received reference station data to form basic data; step 3, constructing a carrier phase double difference prediction model and a code phase prediction model, combining the basic data, respectively calculating local carrier signal control quantities and local code signal control quantities, and writing the control quantities into a digital control oscillator; and step 4, performing position solving, updating a satellite navigation receiver predicted position by using a new position obtained by solving, and feeding back to step 3 to form a closed loop control of position solving assisted signal tracking. The application can realize high-precision and continuous signal tracking in a complex environment.

The invention relates to the technical field of integrated circuits, and discloses a phase-locked loop circuit, which comprises a time-to-digital converter for receiving a reference clock, a feedback clock and a frequency clock, the sampling module is used for counting and sampling a frequency clock according to a reference clock and a feedback clock and calculating frequency deviation information between the reference clock and the frequency clock and phase deviation information between the reference clock and the feedback clock; the digital frequency and phase detection filter is used for carrying out weighted integration on the frequency deviation information and the phase deviation information and generating a control signal; the digital control oscillator is used for generating a frequency clock according to the control signal; and the feedback frequency divider is used for carrying out frequency division on the frequency clock and generating a feedback clock. According to the invention, the frequency deviation information and the phase deviation information are jointly used as the input of the integral path in the digital phase frequency detection filter, so that the phase frequency detection function under the digital phase-locked loop system is realized.

The application discloses a high-sensitivity fast acquisition method and system in a star-ground dynamic environment, and the method comprises the following steps: S1, a transmitting end transmits a communication signal conforming to a target communication frequency, and a receiving end receives the communication signal; S2, a plurality of local signals with different frequency points are generated in a frequency search interval through a local parallel digital control oscillator (NCO) group, and FFT-IFFT acquisition determination is performed on the communication signal; S3, if the acquisition determination fails, the frequency search interval is adjusted, and the step S2 is performed again; if the acquisition determination fails in two adjacent frequency search intervals, sideband interval estimation is performed on the two adjacent frequency search intervals, and FFT-IFFT acquisition determination is performed according to the sideband interval estimation result; the step is repeated until the acquisition determination succeeds. Under the conditions that the detection probability is more than 99%, the minimum carrier-to-noise ratio is 34.66 dB, and the minimum signal-to-noise ratio is 16 dB, the receiver sensitivity of-130 dBm can be realized, the total Doppler frequency offset acquisition range can reach 140 kHz, and the acquisition time can be as low as 0.8 seconds.

The application relates to the field of satellite positioning technology and discloses a satellite signal receiving control method, device and equipment and a storage medium, the method comprising the following steps: receiving a frequency configuration instruction; determining a frequency configuration module to be switched according to a to-be-switched frequency in the frequency configuration instruction; adjusting the frequency of a local oscillator frequency signal of a transceiver through a digital control oscillator according to a target frequency in the frequency configuration instruction; controlling the local oscillator frequency signal to be input into a mixer of the frequency configuration module to be switched, so that the input signal of the frequency configuration module to be switched sequentially passes through the mixer, an analog-to-digital converter and a filtering and decimation module of the frequency configuration module to be switched, and then is matched with the target frequency, frequency configuration operation of the transceiver is completed, and the input signal is mixed with the local oscillator frequency signal in the mixer. The technical scheme of the application can adaptively configure the working frequency of the transceiver, and improve the detection precision and resolution of satellite signals.

The application provides a communication antenna steering control system and method, and relates to the technical field of antenna control, and comprises the following: a parameter configuration module, which is used for acquiring the initial state of a communication antenna and collecting hardware state information in real time; a signal capture and tracking module, which is used for configuring the initial frequency of a digital control oscillator, starting a parallel correlator group to scan the carrier frequency, and calculating frequency domain power spectrum data; and an angle calculation module, which maps the resampling phase difference and baseline parameters to an azimuth angle based on quaternion solution, and superimposes IMU angular velocity data for dynamic compensation. The application realizes high sensitivity capture of signals in a wide frequency band by adopting a multi-stage phase-locked loop architecture, a dynamic threshold adaptive algorithm, a cascaded frequency division coefficient compensation and a FIR comb filter; greatly reduces the phase lag of a steering engine system by fusing extended Kalman filtering and mechanical hysteresis compensation algorithms; and makes the system still maintain high pointing accuracy in a dynamic scene by combining real-time fusion of IMU angular velocity.

The application provides a software-defined wake-up receiver implementation method and system, which comprises the following steps: a transmitter generates a wake-up sequence according to an agreed code rate and a wake-up sequence, and transmits the wake-up sequence at a frequency point at which a wake-up receiver works, so as to form a wake-up signal; a radio frequency front end of the wake-up receiver performs low-power down-conversion on the received wake-up signal, so as to obtain a baseband signal, and then moves the baseband signal from a carrier frequency to a base frequency; a comparator in the wake-up receiver compares the baseband signal after down-conversion with a threshold, so as to generate a bit stream; a correlator and a masker in a digital circuit of the wake-up receiver compare the bit stream under the clock driving of a digital control oscillator, detect a moment at which the wake-up signal ends, and pull up a wake-up flag, so as to enable a high-power circuit part. According to different steps and purposes of software definition, the wake-up receiver technology can be used for implementing network address allocation, changing signal properties of the wake-up sequence, improving security and the like.

This invention provides a fully digital phase-locked loop (PLL) and its locking method, comprising: dividing the output frequency of a numerically controlled oscillator (CNC) into N frequency bands through pre-calibration, and obtaining the input control word range corresponding to each frequency band, where N is a natural number greater than 1; setting the input control word of the CNC oscillator according to the locking frequency; inputting a reference signal and a feedback signal to a time-to-digital converter (TD-SCDC); and switching the loop state of the fully digital PLL from open-loop to closed-loop when the value of the phase digital signal output by the TD-SCDC meets a preset condition. By setting the input control word of the CNC oscillator according to the locking frequency, the phase of the feedback signal output by the CNC oscillator is made close to the phase of the reference signal, thereby making the value of the phase digital signal output by the TD-SCDC close to 0, thus enabling the loop state of the fully digital PLL to be quickly switched to closed-loop, solving the problem of how to shorten the locking time of the fully digital PLL.

The application relates to the technical field of radio frequency signal processing, and discloses an adaptive digital phase calibration method and device, a radio frequency system-on-chip board card, a multi-channel radio frequency receiving system and electronic equipment. The method comprises the following steps: in the case that a synchronous acquisition instruction is received, a signal acquisition unit is used to synchronously acquire radio frequency signals of each antenna channel at the same time; a digital processing unit is used to perform digital domain signal processing on the radio frequency signals to obtain baseband signal data of each antenna channel; phase calculation is performed on the baseband signal data to determine relative phase data of each antenna channel; and a digital control oscillator corresponding to each antenna channel is dynamically configured based on the relative phase data to adaptively calibrate each antenna channel. Without relying on additional hardware devices such as phase shifters or delay lines, the phase difference between channels can be dynamically corrected, the application demand of a large-scale multi-channel radio frequency receiving system can be adapted, and the inter-channel phase synchronization demand can be effectively met.

The application provides a quartz gyro digital circuit phase compensation method and system, the method comprising: generating a co-directional signal and a quadrature signal through a digital control oscillator in a microprocessor; co-directionally demodulating a driving displacement signal output by an ADC in the microprocessor by taking the co-directional signal as a reference signal, and quadrature demodulating the driving displacement signal by taking the quadrature signal as a reference signal; and performing angle rotation on the driving displacement signal after co-directional demodulation and quadrature demodulation according to the time delay of a driving loop in a digital circuit of a quartz gyro, to obtain a new co-directional signal and a new quadrature signal. The application realizes phase compensation, guarantees the phase stability of the driving loop, accurately, reliably and efficiently controls the driving frequency of a digital quartz gyro, improves the performance of the quartz gyro, and is simple in design, saves devices and reduces costs.

The invention provides a programming method and device of a digital phase-locked loop system and a storage medium. The programming method comprises the following steps: acquiring a system design index and a process design package input by a user; generating a first file when the standard subunit is established according to the process design package; analyzing the system design indexes and the standard subunits to obtain types, sizes and connection relations of corresponding devices; configuring a numerical control oscillator, a time-to-digital converter and a digital filter according to the type, size and connection relationship of the corresponding device, and generating a second file based on the related information of the configuration process; performing a digital back-end process based on the second file to generate a third file; and integrating the first file, the second file and the third file into a configuration file. On the basis, key simulation units such as a numerical control oscillator and a time-to-digital converter can be parameterized, so that the key simulation units have the characteristics of configurable specification, migratable process and automatic layout generation while high performance is maintained.

The application discloses a signal loop adjusting method and device, electronic equipment and a storage medium, relates to the chip technical field, and the method is applied to an estimation module of a resolver digital converter and comprises the following steps: acquiring a first initial angle according to sine output signals and cosine output signals of a resolver; acquiring a first initial angular velocity according to at least two first initial angles and a sampling frequency of an analog-to-digital converter; sending the first initial angle to a digital control oscillator and sending the first initial angular velocity to a loop filter, so that the signal loop of the resolver digital converter performs a phase synchronization operation based on the first initial angle and the first initial angular velocity. The technical scheme of the embodiment of the application reduces the construction time of the closed loop of the resolver digital converter, improves the response speed of the feedback control system in the resolver digital converter, and further improves the decoding efficiency of the resolver digital converter.

The application discloses a frequency error correction method, system, device and full-digital phase-locked loop, and the method comprises the following steps: adjusting the actual output frequency of a digital control oscillator according to the value of a frequency coarse adjustment control word, so that the quantization value of the actual frequency difference between the actual output frequency and a target output frequency is less than a preset integer value; detecting the frequency difference between the actual output frequency and the target output frequency to obtain a detection frequency difference, quantizing the detection frequency difference to obtain a quantization value of the detection frequency difference; comparing the quantization value of the detection frequency difference with a set threshold value, and correcting the quantization value of the detection frequency difference according to the comparison result. The application corrects the detection frequency difference exceeding the threshold value by setting the threshold value, improves the accuracy of the frequency difference as feedback in the full-digital phase-locked loop system, and effectively reduces the frequency search times. The application can be widely applied to the full-digital phase-locked loop system.