224 results about "Delay unit" patented technology

The invention provides a PWM signal generation circuit and a control device. The PWM signal generation circuit comprises a control module, a delay chain module and an edge detection module, wherein the delay chain module and the edge detection module are electrically connected with the control module; the edge detection module is used for receiving an original PWM signal output by the PWM system, detecting the edge of the original PWM signal based on an edge detection instruction, generating an edge indication signal and sending the edge indication signal to the delay chain module; the delay chain module comprises a plurality of delay units and is used for delaying the edge of the original PWM signal by target delay time to generate a target PWM signal; according to the invention, the delay operation is carried out on the original PWM signal at the specified edge through the delay chain module, the target PWM signal with the resolution higher than that of the original PWM signal is obtained, and the high-resolution PWM signal is generated by using the low-frequency clock of the PWM system on the premise of not changing the system work clock period of the PWM system.

The invention belongs to the technical field of distributed optical fiber sensing, and relates to a coding difference phase noise and distortion cooperative suppression optical frequency domain reflection method, which comprises the following steps: acquiring upper and lower frequency sweeping and beat frequency signals; separating the upper and lower sweep-frequency beat-frequency signals to obtain an upper sweep-frequency beat-frequency signal and a lower sweep-frequency beat-frequency signal; acquiring an upper sweep frequency beat frequency electric signal and a lower sweep frequency beat frequency electric signal; and the upper frequency-sweeping beat-frequency electric signal is delayed by one spatial resolution and then is mixed with the lower frequency-sweeping beat-frequency electric signal, or the lower frequency-sweeping beat-frequency electric signal is delayed by one spatial resolution and then is mixed with the upper frequency-sweeping beat-frequency electric signal, a frequency-mixing signal after phase frequency noise and frequency domain distortion suppression is obtained, and the Fourier frequency domain spectrum of the frequency-mixing signal is analyzed. The invention also provides a coding difference phase noise and distortion cooperative suppression optical frequency domain reflection system. The system comprises a positive and negative double-sideband sweep frequency light acquisition device, an optical splitter, a spectrum spreading device, an interference device, a beat frequency signal acquisition device and an electric delay unit. According to the invention, phase noise and frequency domain distortion noise can be effectively suppressed.

The application provides an AM-PM distortion calibration method applied to an UWB transmitter and belongs to the field of UWB communication. The method adds a sampling resistor between a linear voltage stabilizing power supply LDO and a digital power amplifier DPA driving stage of the UWB transmitter using a digital power amplifier, so as to simulate the instantaneous change of the power supply voltage of the DPA driving stage when the UWB pulse is transmitted; an adjustable delay unit is added between a carrier input port LO and the DPA driving stage; the continuous sine wave is transmitted, the phase information under each digital baseband amplitude control word is collected to form original data of the AM-PM distortion of the UWB transmitter, the digital baseband output AM-PM control word is used to control the adjustable delay unit to output the phase which is opposite to the original data and has the same size, so that the phase predistortion of the transmitted UWB pulse is realized, and the AM-PM distortion calibration is completed. The application has the advantages of simple implementation and strong compensation capacity.

The application discloses a kind of delay pulse generation device, method and electronic equipment based on FPGA chip, field programmable gate array FPGA chip has M delay units, the device includes: clock generation module, for generating reference clock, output clock and delay clock;Pulse generation module, for generating first output pulse according to reference clock;Delay adjustment module, for first output pulse is delayed adjustment according to delay clock, obtains second output pulse, wherein, delay adjustment module includes N delay units, N is less than or equal to M positive integer;And serial conversion module, for second output pulse is converted into parallel according to reference clock and output clock, and output delay pulse sequence.The device is based on FPGA chip internal logic to realize sub-nanosecond delay adjustment, generates sub-nanosecond delay pulse sequence, and the requirement level of peripheral circuit is low, with the advantages of low cost, simple structure, easy to realize.

A calibration unit for a sampling system, a sampling system and a method for sampling. The calibration unit for a sampling system includes an oscillator having a number of cycles, a digital counter configured to capture a count value that is representative of a time duration to complete the number of cycles, a digital integrator configured to accumulate a difference between a predetermined count value and the captured count value, and a digital to analog converter (DAC) configured to translate an output from the digital integrator to an analog input for delay cells in the sampling system.

The application discloses a ring oscillator and a phase-locked loop. The ring oscillator comprises: the output terminals of nth and mth delay units are connected to the main input terminals of (n+1)th and 1st delay units respectively; m is an odd number, the electrode polarity of the output terminal of the nth delay unit is opposite to the electrode polarity of the main input terminal of the (n+1)th delay unit, or the electrode polarity of the output terminal of the mth delay unit is opposite to the electrode polarity of the main input terminal of the 1st delay unit, m is an even number, the electrode polarity of the output terminal of the nth delay unit is the same as the electrode polarity of the main input terminal of the (n+1)th delay unit, or the electrode polarity of the output terminal of the mth delay unit is the same as the electrode polarity of the main input terminal of the 1st delay unit, n comprises an integer greater than or equal to 1 and less than m; the auxiliary input terminals of the (n+1)th and 1st delay units are connected to the main input terminals of the nth and mth delay units respectively. The technical scheme of the application can realize a ring oscillator with a high oscillation frequency.

The present application relates to the technical field of spectral analysis, and particularly relates to a Fourier spectrometer and a control method thereof. The Fourier spectrometer provided by the present application comprises a control unit, a light receiving unit, a first detection unit, a second detection unit, an interference unit and a delay unit with a rotating structure. The second detection unit is used for sequentially inputting a laser signal to the interference unit and the delay unit to obtain a laser interference signal, and outputting the laser interference signal to the control unit to obtain a sampling clock signal, which is used for controlling the sampling frequency of the interference signal. The present application introduces the second detection unit and the delay unit with the rotating structure, so that the sampling process of the spectrometer can be more flexibly controlled, and the accuracy and efficiency of the sampling are improved. By accurately controlling the change of the optical path difference, the resolution of the spectral data is improved, which is helpful for more accurately analyzing the spectral characteristics of the sampling light.

A digital signal processing device and a control method of the digital signal processing device are provided. It is made possible to generate audio data having a delay time in units of a sampling period. The digital signal processing device has a delay unit (114) that delays the audio data in units of the sampling period, and a control unit (106) that controls to sequentially write the audio data in units of a word in the sampling period to a first buffer memory, burst transfer the audio data of a burst length from the first buffer memory to a DRAM, and controls to burst transfer the audio data of the burst length from the DRAM to a second buffer memory, sequentially output the audio data in units of a word from the second buffer memory (107) to the delay unit in the sampling period, and the delay time of the audio data outputted by the delay unit is determined by a combination of a delay time in units of a plurality of the sampling periods depending on the burst length of the DRAM and a delay time in units of the sampling period of the delay unit.

The invention discloses a signal calibration method and system for semiconductor testing equipment, and relates to the technical field of semiconductor testing, and the method comprises the steps: selecting a calibration port, controlling a relay matrix to enable a source measurement channel, a time measurement channel and an electrical sensor to be connected to a same Kelvin terminal, and carrying out the calibration of a calibration signal; transmitting a calibration pulse train, extracting a sending segment, an arrival segment and a backflow segment, and obtaining a port mirror image routing table and a baseline segment table; controlling the calibration pulse train to execute commutation sending and polarity flipping along a path corresponding to the port mirror image routing table, and comparing an arrival fragment, a backflow fragment and a front and back edge sequence to obtain a commutation difference table and a polarity setting code table; and the calibration pulse train is controlled to enter the measured branch and the reference straight-through branch respectively, and single-stage trimming is carried out on the comparison judgment chain and the delay unit chain. According to the invention, the measured branch and the reference straight-through branch are compared in parallel, and the comparison judgment chain and the delay unit chain are trimmed step by step, so that the measurement resolution of the time parameter is remarkably improved.

The present disclosure relates to an amplifier device for amplifying an input signal Sx at a device input X to an output signal Sy at a device output Y, for driving a loudspeaker or comparable reactive load, comprises a self-oscillating Class D power amplifier stage with transfer function KA(s). The amplifier stage includes a comparator, a power stage, and a second-order low-pass output filter comprising an inductor and a capacitor. A time delay unit provides a delay determined by one or more of the comparator, the power stage, and a first feedback filter. The output signal Sy is fed back to the comparator via the first feedback path to establish oscillation and provide basic low-frequency feedback. A correction stage is provided, comprising a second feedback path that feeds the output signal Sy, via a scaling resistor, to a virtual ground input of a transimpedance amplifier.

This invention proposes a measurement system, method, apparatus, and medium for a delay-locked loop (PLL) within a chip. The system includes: a clock correction unit, with the output of the PLL communicatively connected to it; the clock correction unit includes a period calibration delay unit, a fine adjustment delay unit, a calibration control terminal, and an adjustment control terminal; a clock comparison unit, with the output of the clock correction unit communicatively connected to its input; a counting unit, with its input communicatively connected to both the output of the clock comparison unit and the clock correction unit; and a data processing unit, with its input communicatively connected to the counting unit. The data processing unit outputs the period jitter measurement result and the phase linearity measurement result of the clock signal under test based on the count value. According to the technical solution of this invention, the measurement results can reflect the true clock signal under test, improving the efficiency of chip circuit structure adjustment.

The present application relates to the technical field of suspension furnace, and particularly relates to a chip control panel for a suspension furnace, which comprises a chip unit, a PLC unit, a power supply unit, a start delay unit, a power adjustment unit, a rectification trigger unit, an inverter pulse output unit and a line protection unit, wherein the chip unit, the PLC unit, the line protection unit, the start delay unit, the power adjustment unit, the rectification trigger unit and the inverter pulse output unit are integrated together through a circuit board; the chip unit, the PLC unit, the power supply unit, the start delay unit, the power adjustment unit, the rectification trigger unit, the inverter pulse output unit and the line protection unit are matched, the logic circuit suitable for integration is processed through chip internal logic array assembly, a plurality of electronic components are integrated into the same chip, the chip has the functions of high integration, miniaturization, low power and low cost, and meets the needs of current informatization, digitization and intelligent management control.

This disclosure discloses a watchdog circuit for a controller and a self-test method for the watchdog circuit. A watchdog circuit for a controller may include: a watchdog unit; a gating unit, wherein a reset signal output pin of the watchdog unit is coupled to a reset pin of the controller via the gating unit; and a delay unit, wherein the delay unit is coupled to the gating unit to control the gating unit to prevent the reset signal output pin from being transmitted to the reset pin within a predetermined delay window after the watchdog circuit is powered on. The watchdog circuit according to this disclosure forms a predetermined delay window to prevent the reset signal of the watchdog unit from being transmitted to the reset pin of the controller after power-on, thereby enabling the controller to complete the PBIT self-test of the watchdog unit without interrupting operation, thus improving reliability.

The utility model relates to a mobile phone back clip capable of synchronously arranging an external flash lamp in the field of mobile phone accessories, which comprises a mobile phone connecting frame, the mobile phone connecting frame is used for being clamped on the back of an intelligent mobile phone, and further, a hot shoe interface, a wireless signal transmitter, a programmable delayer, a shutter button and a main control circuit board are arranged in the mobile phone connecting frame. The hot shoe interface, the wireless signal emitter, the shutter button and the programmable delayer are all electrically connected with the main control circuit board, accurate synchronization is achieved through the programmable delayer, the built-in programmable delayer can automatically adjust the time offset of a flash trigger signal, the shutter delay difference of different mobile phone models is accurately compensated, and the real-time performance of the mobile phone is improved. The flash time of the external flash lamp is ensured to be completely synchronous with the actual exposure window of the mobile phone, and the problem of light supplement failure or light dislocation is avoided.

The present disclosure provides a circuit timing processing method and device, electronic equipment and storage medium, and relates to the technical field of integrated circuits. The method comprises: obtaining a timing violation path in a chip circuit and a timing margin of the timing violation path; the timing margin of the timing violation path does not satisfy a timing constraint condition; determining interface attribute information of an interface connection through which the timing violation path passes; based on the interface attribute information and the timing margin, determining a physical position of a delay unit to be inserted in the timing violation path; and generating a control instruction according to the physical position of the delay unit, the control instruction being used to instruct insertion of the delay unit at the physical position. The present scheme can improve the efficiency of circuit timing processing.

The invention discloses a DLL lock detection module, a VCDL circuit of a DLL comprises N stages of delay units, and each stage of delay unit outputs each stage of clock signal. And when the DLL is correctly locked, the phase difference between the Nth-stage clock signal output by the Nth-stage delay unit and the clock input signal is one period. The locking detection module is used for realizing the following detection at the rising edge of the clock input signal: detecting the OR operation result of the first half of each stage of clock signal from the first stage of clock signal to the (N-1) th stage of clock signal, and taking the OR operation result as a first detection result. And detecting an AND operation result of each stage of clock signals of the second half from the first stage of clock signals to the (N-1) th stage of clock signals, and taking the AND operation result as a second detection result. A locking detection signal is output according to the first detection result and the second detection result, and if the first detection result is 0 and the second detection result is 1, the locking detection signal is a first value and indicates that the DLL is correctly locked. According to the invention, whether the DLL locking is correct or not can be detected, so that the incorrect locking is eliminated.

The application discloses an adaptive slope compensation method and circuit of a multiphase control circuit, and is characterized in that the method comprises the following steps: step 1, setting a slope compensation time limit of a slope compensation unit in the multiphase control circuit based on a power supply voltage of the multiphase control circuit, a load limit of an inductance current sampling signal, a turn-on slope of an upper power tube and a turn-on slope of the slope compensation unit; and step 2, realizing feedback control of the multiphase control circuit by using the slope compensation time limit and a pulse width modulation signal together. The circuit of the application comprises a slope compensation delay unit, an AND gate, a NOT gate, a switch tube, a compensation capacitor, a bias current source, a voltage-controlled current source, a resistor and a superposition circuit, and is used for realizing the adaptive slope compensation method. The application can prevent a too large difference of control signals in adjacent phases in the circuit by adjusting the highest compensation time of the slope compensation in each cycle, so that the stability of the whole system is ensured.

This invention provides a transmitter circuit for a CAN bus, relating to the field of CAN bus communication. The circuit includes: a common-mode feedback circuit for generating first and second gate voltages; a slew rate control circuit comprising a CANH terminal circuit for receiving the first gate voltage and a CANL terminal circuit for receiving the second gate voltage, each terminal circuit including multiple sequentially connected delay units and power transistors, the delay units controlling the gate voltage of the power transistors stage by stage to alternately switch the power transistors; and a port positive and negative high-voltage protection circuit, respectively connected between the output terminals of the CANH and CANL terminal circuits and the bus port, for protecting against positive and negative high voltages on the bus and suppressing parasitic effects. The beneficial effects are: by controlling the switching of the power transistors stage by stage through the delay units, the current surge rate is reduced, and electromagnetic radiation is reduced; by stabilizing the gate voltage and balancing the output current through common-mode feedback, signal symmetry is improved and common-mode interference is suppressed.

The invention belongs to the field of large-scale application-specific integrated circuit design, and particularly relates to a phase-locked loop circuit. The phase-locked loop circuit comprises a phase frequency detector, a charge pump, a low-pass filter, a voltage-controlled oscillator and a frequency divider; the voltage-controlled oscillator comprises a common-source amplifier, a multi-stage delay unit and a level conversion unit; the control end of the common source amplifier serves as the input end of the voltage-controlled oscillator, and the output end of the common source amplifier is connected with the voltage end of the multi-stage delay unit. The output end of the multi-stage delay unit is connected with the input end of the level conversion unit; the output end of the level conversion unit is used as the output end of the voltage-controlled oscillator; according to the voltage-controlled oscillator, the common-source amplifier is used for controlling the multi-stage delay unit along with the change of the control voltage output by the charge pump so as to adjust the oscillation frequency, and a multi-phase clock signal is output through the level conversion unit, so that the power consumption of the phase-locked loop is reduced, and the output clock has relatively small clock jitter.

The embodiment of the application relates to the technical field of electronics, in particular to a PWM signal generation system, which comprises a PWM generation circuit and a clock cycle analysis circuit. The embodiment of the application dynamically adjusts the number of buffers of an initial delay line, and adaptively determines a target number according to a delay signal state, thereby greatly shortening the calculation period of the total number of buffers in the PWM generation circuit and avoiding the time-consuming iterative calculation in the traditional scheme. In addition, the logic of deriving the total number of buffers based on the target number can realize accurate matching of the delay time of the buffer and the clock cycle, improve the control accuracy of the PWM duty cycle by combining the fine delay processing of the delay unit on the PWM signal, and make up for the defects of insufficient accuracy of the traditional circuit. The system also integrates a temperature sensor and a voltage sensor, and the microprocessor can correct the deviation of the delay time of the buffer in combination with the environmental parameters, enhance the stability of the system under complex working conditions, and widen the applicable scenarios of the system in the technical field of electronics.

Embodiments of this disclosure provide an apparatus and method for generating a circuit clock signal. The apparatus includes: a clock buffer configured to buffer an original clock signal to obtain a buffered clock signal; a clock delay unit configured to delay the original clock signal to obtain a plurality of delayed clock signals, the plurality of delayed clock signals being delayed by different amounts of time relative to the original clock signal; a broadened clock generator configured to generate a broadened clock signal based on the original clock signal and the plurality of delayed clock signals, the frequency of the broadened clock signal being lower than the frequency of the original clock signal; and a clock selector configured to select one of the buffered clock signal and the broadened clock signal as the circuit clock signal based on the selection signal.

The invention discloses a time delay circuit which comprises a first selector, a plurality of series-connected time delay units, an NAND gate, a second selector and a plurality of phase inverters, a first data input end of the first selector is connected with a first enable signal, and the first enable signal serves as an input signal of the time delay circuit in an input mode; the delay units are connected with the output end of the first selector, the first input end of the NAND gate is connected to the output end of the last-stage delay unit, the second input end of the NAND gate is connected with a second enable signal, the second enable signal is used for controlling the working mode of the delay circuit, and the selection control end of the second selector is connected to the output end of the NAND gate. The first data input end and the second data input end are connected through the first phase inverter, the output end is connected to the second data input end of the first selector through the second phase inverter, and the third phase inverter is connected to the output end of the second selector and used for outputting an output signal of the time delay circuit. The method is used for testing register establishment time and retention time.

This application discloses an LVDS adaptive frame synchronization system, comprising: a transmitting end: a clock generation module providing multi-rate clocks; a data parallel-to-serial conversion module converting parallel data into a high-speed serial bit stream under clock control; a multi-functional auxiliary channel parallel-to-serial conversion module interleaving and encoding auxiliary control information and synchronization information into a composite bit stream; and an LVDS driver group converting signals into differential signals for transmission. The receiving end: an LVDS receiver group converts differential signals into single-ended signals, including multiple data signals, one auxiliary channel signal, and one half-rate clock signal. A serial-to-parallel conversion and synchronization control module uses a half-rate clock to perform DDR sampling of the data and auxiliary channel signals. Synchronization information is extracted by sampling on the falling edge of the auxiliary channel signal, and auxiliary control information is extracted by sampling on the rising edge. A synchronization detection unit obtains the capture sequence from the synchronization information, and a numerically controlled delay unit calculates the delay correction amount based on the mapping relationship between the capture sequence and the correction signal to delay the data, thereby achieving adaptive frame synchronization.

This invention belongs to the field of time measurement technology and discloses a resource-saving short-chain time-to-digital converter and its conversion method. It utilizes a delay unit and conversion circuit to build a local oscillator, which flips the output state at fixed time intervals during a continuous high-level input signal. The time at which the local oscillator causes the level to flip is known. The time of the last flip is obtained using TDL and TDC, and the start and last flip times are obtained by recording the number of flips of the local oscillator. The resource-saving short-chain time-to-digital converter provided by this invention has good linearity, completely avoiding nonlinearity problems caused by inconsistent line lengths introduced across multiple resource blocks. The resource-saving short-chain time-to-digital converter has a simple and flexible structure, low resource consumption, and high utilization rate. It has good robustness and can be directly ported between different channels or even devices, and can correct temperature-induced drift online.

The application relates to the technical field of intelligent control, and discloses an intelligent control system and method for an oil pump, which comprises a BLDC oil pump and a control module. A collection unit in the control module is used to acquire the running speed and running temperature of the BLDC oil pump. A judgment unit is used to judge whether a dormant mode is triggered according to conditions and set an initial dormant duration. A correction unit is used to acquire an ambient temperature and correct the initial dormant duration. A delay unit is used to acquire a task quantity difference value and set a delay dormant time. An adjustment unit is used to acquire the running parameter change rate of the BLDC oil pump within the delay dormant time and adjust the delay dormant time. A wake-up unit is used to detect an emergency signal in real time when the BLDC oil pump is in the dormant mode, start the BLDC oil pump according to the emergency signal, and issue a warning. The application can flexibly control the dormant time, adapt to different working conditions and task quantity changes, improve energy efficiency, timely respond to emergency situations through the wake-up unit, and improve the response speed and reliability of the system.

The application discloses a kind of linear frequency modulation signal generating device and method, including integrated mutual injection laser for generating single periodic state optical signal, optical signal is divided into two beams by optical fiber splitter, one of which sequentially passes through short delay unit, first photoelectric detector and then enters first electric coupler, the other sequentially passes through long delay unit, second photoelectric detector and then enters first electric coupler, the electric signal synthesized by the first electric coupler is amplified by the radio frequency power amplifier and then input into the electric splitter and divided into two ways, one of which outputs linear frequency modulation signal, the other is coupled with driving signal input into the second electric coupler and then directly modulated onto integrated mutual injection laser.The application can generate linear frequency modulation signal with high stability, high purity and large time-bandwidth product, and the structure of the device is exquisite, easy to integrate and low in cost.

The utility model relates to the technical field of power-off logic control, in particular to an anti-oscillation circuit for a power supply output voltage power-off process, which is characterized in that a voltage comparison unit is arranged to sample an output voltage, different reference voltages are arranged to realize different functions, and power supply is controlled by generating a first detection signal. The power-off detection function is not triggered by mistake, the output voltage is detected through the second detection signal to judge whether the output is powered off or not, if the power-off output signal is detected to the delay unit, a set fixed-time square wave is output to turn off the power supply enable, and the power supply enable is reset after the output voltage is detected to be reduced through the third detection signal, so that the power supply enable becomes effective again. The time delay from the output power-off to the turn-off of the power supply is only 1-2 microseconds, and the oscillation in the power-off process of the output voltage can be controlled in time.

The invention belongs to the technical field of integrated circuits, and particularly relates to a broadband low-amplitude error delayer. The delayer comprises an input matching network, an output matching network, a first single-pole double-throw switch, a second single-pole double-throw switch, a delay unit and a delay reference network, the input matching network is connected with one end of the first single-pole double-throw switch, and the other end of the first single-pole double-throw switch is connected with the input end of the delay unit and the input end of the delay reference network. One end of the second single-pole double-throw switch is connected with the output matching network, and the other end is connected with the input end of the delay unit and the output end of the delay reference network; the delayer designed by the invention has a wide-band large-frequency delay function, and has a good application prospect.

The present disclosure relates to a 5G communication system or a 6G communication system for supporting higher data rates beyond a 4G communication system such as long term evolution (LTE). Joint phase time array transmission employs dual polarized holographic beamforming antenna rather than phased array antenna. Every antenna element including an array of holographic beamforming unit cells requires only a single power amplifier between the antenna element and a corresponding delay element. Dual polarization is provided by antenna tiles each with parallel arrays of horizontal slot holographic beamforming unit cells rotated relative to each other, or by antenna elements of 45° slot holographic beamforming unit cells alternated on an antenna panel with 135° slot holographic beamforming unit cells. Improvements in transmit power and efficiency are achieved over joint phase time array transmission with phased array antenna, with fewer phase shifters and other active components per beam steering antenna element.

A pulse generator comprises a circuit configured to generate a coarse pulse width (CPW) signal, a first delay unit configured to generate a first delayed coarse pulse width signal, a delay locked loop circuit configured to generate a first subphase signal and a second subphase signal, a first analog interpolator, a second analog interpolator, and an amplifier having a first input connected to the first analog interpolator and a second input connected to the second analog interpolator and configured to generate a fine pulse width modulation signal.