369 results about "Delay unit" patented technology

The embodiment of the invention discloses a delay-locked loop circuit, a clock generator, a chip and electronic equipment, and belongs to the technical field of integrated circuits. The delay-locked loop circuit includes: a digital control circuit for transmitting a first adjustment code adapted to adjust the number of delay units in a coarse adjustment phase, and determining whether to adjust the first adjustment code based on a first feedback signal; in the fine adjustment stage, a third adjustment code suitable for adjusting the delay attribute parameter of the delay unit is sent, and whether the third adjustment code is adjusted or not is determined based on the second feedback signal; in the locking phase, transmitting a second adjustment code suitable for adjusting the control voltage of the delay unit, and determining whether to adjust the second adjustment code based on the third feedback signal; and the phase detection unit is used for sending the first feedback signal, the second feedback signal and the third feedback signal to the digital control circuit. A hybrid circuit of digital design and analog design is provided, high-precision clock phase adjustment is achieved, and an output clock in a wide frequency range can also be achieved.

The invention provides a calibration system applied to DLL-TDC, and solves the technical problems of low circuit linearity and large time measurement result error of an existing time-to-digital converter. The device comprises a DLL-TDC module and a calibration network module. The DLL-TDC module is used for feeding back a control voltage in real time and carrying out preliminary calibration on the delay time of each delay unit; obtaining the number of the delay units passing by at the stop moment and a count value according to the start and stop of the to-be-measured signal, and calculating the number of the delay units passing by the to-be-measured signal; and the calibration network module is used for detecting the change relationship between the temperature and the delay time, correspondingly predicting the delay time of the to-be-detected signal passing through each delay unit according to the temperature, and adding the delay time to obtain the time interval of the calibrated to-be-detected signal. The circuit can be widely applied to the technical field of integrated circuits.

The invention provides a PWM signal generation circuit and a control device. The PWM signal generation circuit comprises a control module, a delay chain module and an edge detection module, wherein the delay chain module and the edge detection module are electrically connected with the control module; the edge detection module is used for receiving an original PWM signal output by the PWM system, detecting the edge of the original PWM signal based on an edge detection instruction, generating an edge indication signal and sending the edge indication signal to the delay chain module; the delay chain module comprises a plurality of delay units and is used for delaying the edge of the original PWM signal by target delay time to generate a target PWM signal; according to the invention, the delay operation is carried out on the original PWM signal at the specified edge through the delay chain module, the target PWM signal with the resolution higher than that of the original PWM signal is obtained, and the high-resolution PWM signal is generated by using the low-frequency clock of the PWM system on the premise of not changing the system work clock period of the PWM system.

The invention belongs to the technical field of distributed optical fiber sensing, and relates to a coding difference phase noise and distortion cooperative suppression optical frequency domain reflection method, which comprises the following steps: acquiring upper and lower frequency sweeping and beat frequency signals; separating the upper and lower sweep-frequency beat-frequency signals to obtain an upper sweep-frequency beat-frequency signal and a lower sweep-frequency beat-frequency signal; acquiring an upper sweep frequency beat frequency electric signal and a lower sweep frequency beat frequency electric signal; and the upper frequency-sweeping beat-frequency electric signal is delayed by one spatial resolution and then is mixed with the lower frequency-sweeping beat-frequency electric signal, or the lower frequency-sweeping beat-frequency electric signal is delayed by one spatial resolution and then is mixed with the upper frequency-sweeping beat-frequency electric signal, a frequency-mixing signal after phase frequency noise and frequency domain distortion suppression is obtained, and the Fourier frequency domain spectrum of the frequency-mixing signal is analyzed. The invention also provides a coding difference phase noise and distortion cooperative suppression optical frequency domain reflection system. The system comprises a positive and negative double-sideband sweep frequency light acquisition device, an optical splitter, a spectrum spreading device, an interference device, a beat frequency signal acquisition device and an electric delay unit. According to the invention, phase noise and frequency domain distortion noise can be effectively suppressed.

The invention relates to the technical field of analog integrated circuits, and discloses a reference clock frequency multiplier circuit and a chip, and the reference clock frequency multiplier circuit comprises a phase discriminator, a charge pump, a loop filter, a voltage-controlled delay unit, a multiphase injection locked ring oscillator and an edge combiner. And the voltage-controlled delay unit, the phase discriminator, the charge pump and the loop filter form a multi-phase clock generator. The multi-phase injection clock signal is generated by adopting the voltage-controlled delay unit, and the multi-phase injection locking ring oscillator is further adopted as an input clock source of the edge combiner, so that the phase error of the multi-phase injection clock signal generated by the voltage-controlled delay unit is suppressed; therefore, a frequency multiplication clock signal with an accurate duty ratio and low noise is obtained.

The application discloses a kind of photonic tensor convolution calculation method and system for multi-channel data processing.The system includes multi-wavelength light source, high-speed modulator, signal generating unit, weighting unit, delay unit, balanced photodetector and signal processing unit, and the multi-channel tensor reconstruction algorithm of input signal.By improving the vectorization rule of tensor data, the elements of different channels in high-order tensor are rearranged into a one-dimensional vector.Based on the technology of three-dimensional multiplexing of time, space and frequency, only one modulator and a set of signal generating unit are needed to realize the convolution calculation of single optical link with arbitrary multi-channel tensor data simultaneously.The sliding convolution of multi-channel data can be directly completed in one calculation, which can release more physical hardware resources for multi-tensor parallel operation, complete more concise and efficient photonic tensor convolution operation, and greatly increase the integration and scalability of the scheme.

The invention belongs to the technical field of analog-to-digital converters, and particularly relates to a dynamic delay adaptive asynchronous time sequence control circuit for an SAR ADC (Synthetic Aperture Radar Analog to Digital Converter). According to the circuit disclosed by the invention, through an innovative circuit architecture and a control method, remarkable breakthrough is realized in the aspects of conversion precision and speed. According to the circuit, a unique two-stage dynamic delay adjustment mechanism is adopted, intelligent optimization of delay time is achieved based on real-time comparison frequency monitoring, the effective conversion rate under 16-bit precision is improved by 25% or above, and meanwhile it is kept that ENOB is not lower than 15 bits. The innovative current charging capacitance type delay unit is combined with the PVT compensation technology, and the delay time stability is superior to + / -3% within the working temperature range of-40 DEG C to 125 DEG C. Through a dynamic adjustment algorithm of cooperative work of a shift register and a lookup table, the system can automatically adapt to establishment time change of 10 ns to 50 ns, and compared with a fixed delay scheme, invalid waiting time is saved by more than 30%.

The application provides an AM-PM distortion calibration method applied to an UWB transmitter and belongs to the field of UWB communication. The method adds a sampling resistor between a linear voltage stabilizing power supply LDO and a digital power amplifier DPA driving stage of the UWB transmitter using a digital power amplifier, so as to simulate the instantaneous change of the power supply voltage of the DPA driving stage when the UWB pulse is transmitted; an adjustable delay unit is added between a carrier input port LO and the DPA driving stage; the continuous sine wave is transmitted, the phase information under each digital baseband amplitude control word is collected to form original data of the AM-PM distortion of the UWB transmitter, the digital baseband output AM-PM control word is used to control the adjustable delay unit to output the phase which is opposite to the original data and has the same size, so that the phase predistortion of the transmitted UWB pulse is realized, and the AM-PM distortion calibration is completed. The application has the advantages of simple implementation and strong compensation capacity.

The application discloses a kind of delay pulse generation device, method and electronic equipment based on FPGA chip, field programmable gate array FPGA chip has M delay units, the device includes: clock generation module, for generating reference clock, output clock and delay clock;Pulse generation module, for generating first output pulse according to reference clock;Delay adjustment module, for first output pulse is delayed adjustment according to delay clock, obtains second output pulse, wherein, delay adjustment module includes N delay units, N is less than or equal to M positive integer;And serial conversion module, for second output pulse is converted into parallel according to reference clock and output clock, and output delay pulse sequence.The device is based on FPGA chip internal logic to realize sub-nanosecond delay adjustment, generates sub-nanosecond delay pulse sequence, and the requirement level of peripheral circuit is low, with the advantages of low cost, simple structure, easy to realize.

The application discloses a ring oscillator circuit, a PCB and a controller, comprising a voltage bias unit, an input end of the voltage bias unit being connected with an external control signal end, a first bias voltage output end and a second bias voltage output end of the voltage bias unit being respectively connected with an enable end of a delay unit, the second bias voltage output end of the voltage bias unit being further connected with an enable end of a buffer unit, an inverting output end of the delay unit being connected with a same-phase input end thereof and an input end of a first buffer driving unit, an output end of the first buffer driving unit being connected with an inverting input end of the buffer unit, a same-phase output end of the delay unit being connected with an inverting input end thereof and an input end of a second buffer driving unit, and an output end of the second buffer driving unit being connected with a same-phase input end of the buffer unit, so that the first buffer driving unit and the second buffer driving unit are used to pre-drive an original oscillation signal, and the clock signal output by the buffer unit has greater driving current output capacity.

A calibration unit for a sampling system, a sampling system and a method for sampling. The calibration unit for a sampling system includes an oscillator having a number of cycles, a digital counter configured to capture a count value that is representative of a time duration to complete the number of cycles, a digital integrator configured to accumulate a difference between a predetermined count value and the captured count value, and a digital to analog converter (DAC) configured to translate an output from the digital integrator to an analog input for delay cells in the sampling system.

The invention discloses a power cost control active-to-passive control conversion circuit, a converter and a wiring method, and relates to the technical field of power cost control. The control conversion circuit comprises an analog-to-digital conversion unit, an isolation unit, a delay unit, a trigger unit and an output unit, the control conversion circuit is connected in series in a control loop between the intelligent electric energy meter and the circuit breaker, and an alternating current control signal sent by the intelligent electric energy meter is converted into a passive contact to be output through the control conversion circuit. Therefore, switching-on and switching-off control of the circuit breaker is realized, and the problems that a protection device cannot be additionally arranged in an active output mode and cost control of a simple circuit breaker containing high-supply and low-metering users cannot be realized are solved.

The application discloses a ring oscillator and a phase-locked loop. The ring oscillator comprises: the output terminals of nth and mth delay units are connected to the main input terminals of (n+1)th and 1st delay units respectively; m is an odd number, the electrode polarity of the output terminal of the nth delay unit is opposite to the electrode polarity of the main input terminal of the (n+1)th delay unit, or the electrode polarity of the output terminal of the mth delay unit is opposite to the electrode polarity of the main input terminal of the 1st delay unit, m is an even number, the electrode polarity of the output terminal of the nth delay unit is the same as the electrode polarity of the main input terminal of the (n+1)th delay unit, or the electrode polarity of the output terminal of the mth delay unit is the same as the electrode polarity of the main input terminal of the 1st delay unit, n comprises an integer greater than or equal to 1 and less than m; the auxiliary input terminals of the (n+1)th and 1st delay units are connected to the main input terminals of the nth and mth delay units respectively. The technical scheme of the application can realize a ring oscillator with a high oscillation frequency.

Provided are a control circuit, a semiconductor memory device, and a control method thereof that are capable of efficiently estimating the amount of delay between a first signal and a second signal and generating an output signal according to the amount of delay. [Solution] The control circuit 30 comprises a delay line section 31 to which a start signal start_tdc is input, the delay line section including a plurality of delay units U1 to U8 connected in series; a detection section 32 to which an end signal end_tdc is input, the detection section detecting, when an end signal is input after the start signal is input to the delay line section, the number of delay units among the plurality of delay units through which the start signal has passed before the end signal is input; and a control section 33 that controls the transmission path of the start signal in the delay line section so that the number of delay units through which the start signal has passed before the start signal is output from the delay line section is equal to the number of delay units detected by the detection section.

The present application relates to the technical field of spectral analysis, and particularly relates to a Fourier spectrometer and a control method thereof. The Fourier spectrometer provided by the present application comprises a control unit, a light receiving unit, a first detection unit, a second detection unit, an interference unit and a delay unit with a rotating structure. The second detection unit is used for sequentially inputting a laser signal to the interference unit and the delay unit to obtain a laser interference signal, and outputting the laser interference signal to the control unit to obtain a sampling clock signal, which is used for controlling the sampling frequency of the interference signal. The present application introduces the second detection unit and the delay unit with the rotating structure, so that the sampling process of the spectrometer can be more flexibly controlled, and the accuracy and efficiency of the sampling are improved. By accurately controlling the change of the optical path difference, the resolution of the spectral data is improved, which is helpful for more accurately analyzing the spectral characteristics of the sampling light.

The invention provides a method and a device for optimizing retention time of a chip. The retention time optimization method of the chip comprises the following steps: in a layout wiring stage of the chip to be optimized, determining a unit to be optimized in the chip to be optimized according to an initial layout of the chip to be optimized; allocating a reserved space for the unit to be optimized; and after the wiring stage of the to-be-optimized chip is completed, performing time sequence analysis on the to-be-optimized chip by using a time sequence analysis tool, and adding a delay unit in the reserved space of the to-be-optimized unit according to a time sequence analysis result. Through the chip retention time optimization method, a large number of redundant delay units are prevented from being inserted into the to-be-optimized chip.

A digital signal processing device and a control method of the digital signal processing device are provided. It is made possible to generate audio data having a delay time in units of a sampling period. The digital signal processing device has a delay unit (114) that delays the audio data in units of the sampling period, and a control unit (106) that controls to sequentially write the audio data in units of a word in the sampling period to a first buffer memory, burst transfer the audio data of a burst length from the first buffer memory to a DRAM, and controls to burst transfer the audio data of the burst length from the DRAM to a second buffer memory, sequentially output the audio data in units of a word from the second buffer memory (107) to the delay unit in the sampling period, and the delay time of the audio data outputted by the delay unit is determined by a combination of a delay time in units of a plurality of the sampling periods depending on the burst length of the DRAM and a delay time in units of the sampling period of the delay unit.

The invention discloses a signal calibration method and system for semiconductor testing equipment, and relates to the technical field of semiconductor testing, and the method comprises the steps: selecting a calibration port, controlling a relay matrix to enable a source measurement channel, a time measurement channel and an electrical sensor to be connected to a same Kelvin terminal, and carrying out the calibration of a calibration signal; transmitting a calibration pulse train, extracting a sending segment, an arrival segment and a backflow segment, and obtaining a port mirror image routing table and a baseline segment table; controlling the calibration pulse train to execute commutation sending and polarity flipping along a path corresponding to the port mirror image routing table, and comparing an arrival fragment, a backflow fragment and a front and back edge sequence to obtain a commutation difference table and a polarity setting code table; and the calibration pulse train is controlled to enter the measured branch and the reference straight-through branch respectively, and single-stage trimming is carried out on the comparison judgment chain and the delay unit chain. According to the invention, the measured branch and the reference straight-through branch are compared in parallel, and the comparison judgment chain and the delay unit chain are trimmed step by step, so that the measurement resolution of the time parameter is remarkably improved.

The invention discloses a delay unit and a broadband multi-sub-band ring oscillator circuit, the delay unit is characterized in that a PM5, a PM7, a PM13 and a first current limiting tube are connected in parallel between a source electrode and a drain electrode of a PM3, the first current limiting tube comprises a PM9, a PM11 and sub-band control switches CB2 and CB12, a PM6, a PM8, a PM14 and a second current limiting tube are connected in parallel between a source electrode and a drain electrode of a PM4, and the second current limiting tube comprises a PM10, a PM12 and sub-band control switches CB2 and CB12; switched capacitors C1-C4 are arranged between the VOP and the VON; the first group of switched capacitors and the second group of switched capacitors are connected in parallel between the VOP and the VON; the first group of switched capacitors comprises C1 and C2 which are connected in series and CB1 for controlling the switching of the C1 and C2, and the second group of switched capacitors comprises C3 and C4 which are connected in series and CB2 for controlling the switching of the C3 and C4; grid electrodes of the PM5 and the PM6 are connected with the sub-band control switch RB1, grid electrodes of the PM7 and the PM8 are connected with the RB2, grid electrodes of the PM9 and the PM10 are connected with the CB2, grid electrodes of the PM11 and the PM12 are connected with the CB12, and a control signal of the CB12 is generated by control signals of the CB1 and the CB2 through an AND gate.

The present disclosure relates to an amplifier device for amplifying an input signal Sx at a device input X to an output signal Sy at a device output Y, for driving a loudspeaker or comparable reactive load, comprises a self-oscillating Class D power amplifier stage with transfer function KA(s). The amplifier stage includes a comparator, a power stage, and a second-order low-pass output filter comprising an inductor and a capacitor. A time delay unit provides a delay determined by one or more of the comparator, the power stage, and a first feedback filter. The output signal Sy is fed back to the comparator via the first feedback path to establish oscillation and provide basic low-frequency feedback. A correction stage is provided, comprising a second feedback path that feeds the output signal Sy, via a scaling resistor, to a virtual ground input of a transimpedance amplifier.

This invention proposes a measurement system, method, apparatus, and medium for a delay-locked loop (PLL) within a chip. The system includes: a clock correction unit, with the output of the PLL communicatively connected to it; the clock correction unit includes a period calibration delay unit, a fine adjustment delay unit, a calibration control terminal, and an adjustment control terminal; a clock comparison unit, with the output of the clock correction unit communicatively connected to its input; a counting unit, with its input communicatively connected to both the output of the clock comparison unit and the clock correction unit; and a data processing unit, with its input communicatively connected to the counting unit. The data processing unit outputs the period jitter measurement result and the phase linearity measurement result of the clock signal under test based on the count value. According to the technical solution of this invention, the measurement results can reflect the true clock signal under test, improving the efficiency of chip circuit structure adjustment.

The present application relates to the technical field of suspension furnace, and particularly relates to a chip control panel for a suspension furnace, which comprises a chip unit, a PLC unit, a power supply unit, a start delay unit, a power adjustment unit, a rectification trigger unit, an inverter pulse output unit and a line protection unit, wherein the chip unit, the PLC unit, the line protection unit, the start delay unit, the power adjustment unit, the rectification trigger unit and the inverter pulse output unit are integrated together through a circuit board; the chip unit, the PLC unit, the power supply unit, the start delay unit, the power adjustment unit, the rectification trigger unit, the inverter pulse output unit and the line protection unit are matched, the logic circuit suitable for integration is processed through chip internal logic array assembly, a plurality of electronic components are integrated into the same chip, the chip has the functions of high integration, miniaturization, low power and low cost, and meets the needs of current informatization, digitization and intelligent management control.

This disclosure discloses a watchdog circuit for a controller and a self-test method for the watchdog circuit. A watchdog circuit for a controller may include: a watchdog unit; a gating unit, wherein a reset signal output pin of the watchdog unit is coupled to a reset pin of the controller via the gating unit; and a delay unit, wherein the delay unit is coupled to the gating unit to control the gating unit to prevent the reset signal output pin from being transmitted to the reset pin within a predetermined delay window after the watchdog circuit is powered on. The watchdog circuit according to this disclosure forms a predetermined delay window to prevent the reset signal of the watchdog unit from being transmitted to the reset pin of the controller after power-on, thereby enabling the controller to complete the PBIT self-test of the watchdog unit without interrupting operation, thus improving reliability.

The application discloses a ring type voltage-controlled oscillator and a multi-mode receiver, the ring type voltage-controlled oscillator comprising three double-path structure delay units connected in sequence, adopting a new structure of double common-source stages plus NMOS tube source following feedback, so that output noise voltage or current can be offset, and phase noise is reduced; meanwhile, the ring type voltage-controlled oscillator adds a varactor pair and a capacitor switch array at an output end, frequency tuning of the circuit can be realized by introducing the varactor and a tuning voltage, and the tuning range of the ring type voltage-controlled oscillator can be further increased through the capacitor switch array; and the ring type voltage-controlled oscillator further adds a biased I-MOS varactor pair in parallel on the basis of the A-MOS varactor pair, so that the poor capacitance characteristic of the A-MOS varactor can be compensated by the I-MOS varactor, and the tuning linearity of the ring type voltage-controlled oscillator can be optimized.

The utility model relates to a mobile phone back clip capable of synchronously arranging an external flash lamp in the field of mobile phone accessories, which comprises a mobile phone connecting frame, the mobile phone connecting frame is used for being clamped on the back of an intelligent mobile phone, and further, a hot shoe interface, a wireless signal transmitter, a programmable delayer, a shutter button and a main control circuit board are arranged in the mobile phone connecting frame. The hot shoe interface, the wireless signal emitter, the shutter button and the programmable delayer are all electrically connected with the main control circuit board, accurate synchronization is achieved through the programmable delayer, the built-in programmable delayer can automatically adjust the time offset of a flash trigger signal, the shutter delay difference of different mobile phone models is accurately compensated, and the real-time performance of the mobile phone is improved. The flash time of the external flash lamp is ensured to be completely synchronous with the actual exposure window of the mobile phone, and the problem of light supplement failure or light dislocation is avoided.

The present disclosure provides a circuit timing processing method and device, electronic equipment and storage medium, and relates to the technical field of integrated circuits. The method comprises: obtaining a timing violation path in a chip circuit and a timing margin of the timing violation path; the timing margin of the timing violation path does not satisfy a timing constraint condition; determining interface attribute information of an interface connection through which the timing violation path passes; based on the interface attribute information and the timing margin, determining a physical position of a delay unit to be inserted in the timing violation path; and generating a control instruction according to the physical position of the delay unit, the control instruction being used to instruct insertion of the delay unit at the physical position. The present scheme can improve the efficiency of circuit timing processing.

The invention discloses a DLL lock detection module, a VCDL circuit of a DLL comprises N stages of delay units, and each stage of delay unit outputs each stage of clock signal. And when the DLL is correctly locked, the phase difference between the Nth-stage clock signal output by the Nth-stage delay unit and the clock input signal is one period. The locking detection module is used for realizing the following detection at the rising edge of the clock input signal: detecting the OR operation result of the first half of each stage of clock signal from the first stage of clock signal to the (N-1) th stage of clock signal, and taking the OR operation result as a first detection result. And detecting an AND operation result of each stage of clock signals of the second half from the first stage of clock signals to the (N-1) th stage of clock signals, and taking the AND operation result as a second detection result. A locking detection signal is output according to the first detection result and the second detection result, and if the first detection result is 0 and the second detection result is 1, the locking detection signal is a first value and indicates that the DLL is correctly locked. According to the invention, whether the DLL locking is correct or not can be detected, so that the incorrect locking is eliminated.

The application discloses an adaptive slope compensation method and circuit of a multiphase control circuit, and is characterized in that the method comprises the following steps: step 1, setting a slope compensation time limit of a slope compensation unit in the multiphase control circuit based on a power supply voltage of the multiphase control circuit, a load limit of an inductance current sampling signal, a turn-on slope of an upper power tube and a turn-on slope of the slope compensation unit; and step 2, realizing feedback control of the multiphase control circuit by using the slope compensation time limit and a pulse width modulation signal together. The circuit of the application comprises a slope compensation delay unit, an AND gate, a NOT gate, a switch tube, a compensation capacitor, a bias current source, a voltage-controlled current source, a resistor and a superposition circuit, and is used for realizing the adaptive slope compensation method. The application can prevent a too large difference of control signals in adjacent phases in the circuit by adjusting the highest compensation time of the slope compensation in each cycle, so that the stability of the whole system is ensured.

This invention provides a transmitter circuit for a CAN bus, relating to the field of CAN bus communication. The circuit includes: a common-mode feedback circuit for generating first and second gate voltages; a slew rate control circuit comprising a CANH terminal circuit for receiving the first gate voltage and a CANL terminal circuit for receiving the second gate voltage, each terminal circuit including multiple sequentially connected delay units and power transistors, the delay units controlling the gate voltage of the power transistors stage by stage to alternately switch the power transistors; and a port positive and negative high-voltage protection circuit, respectively connected between the output terminals of the CANH and CANL terminal circuits and the bus port, for protecting against positive and negative high voltages on the bus and suppressing parasitic effects. The beneficial effects are: by controlling the switching of the power transistors stage by stage through the delay units, the current surge rate is reduced, and electromagnetic radiation is reduced; by stabilizing the gate voltage and balancing the output current through common-mode feedback, signal symmetry is improved and common-mode interference is suppressed.

The invention belongs to the field of large-scale application-specific integrated circuit design, and particularly relates to a phase-locked loop circuit. The phase-locked loop circuit comprises a phase frequency detector, a charge pump, a low-pass filter, a voltage-controlled oscillator and a frequency divider; the voltage-controlled oscillator comprises a common-source amplifier, a multi-stage delay unit and a level conversion unit; the control end of the common source amplifier serves as the input end of the voltage-controlled oscillator, and the output end of the common source amplifier is connected with the voltage end of the multi-stage delay unit. The output end of the multi-stage delay unit is connected with the input end of the level conversion unit; the output end of the level conversion unit is used as the output end of the voltage-controlled oscillator; according to the voltage-controlled oscillator, the common-source amplifier is used for controlling the multi-stage delay unit along with the change of the control voltage output by the charge pump so as to adjust the oscillation frequency, and a multi-phase clock signal is output through the level conversion unit, so that the power consumption of the phase-locked loop is reduced, and the output clock has relatively small clock jitter.