534 results about "Delay unit" patented technology

The invention discloses an intelligent control system for a current transformer, and particularly relates to the technical field of power system monitoring, which comprises a fluctuation identification unit, a redundancy acquisition unit, an error fitting unit, a protection delay unit and a fault response unit, realizes real-time identification and classification of current fluctuation, and has standby path high-speed sampling and fusion signal construction capabilities. The fluctuation trend is judged through error regression, a protection strategy is dynamically set, response is delayed to avoid misoperation, finally, a high-level protection instruction is triggered and a fault event is output when offset overruns or alignment fails, and the data accuracy and the system response stability in the power supply switching process are guaranteed; according to the method, accurate identification of current fluctuation is realized through multi-dimensional feature extraction, data reliability is enhanced by using redundant sampling and error fitting, and by combining delay control and a hierarchical response mechanism, the risk of misoperation is effectively reduced, the fault judgment accuracy and the system protection stability are improved, and the method is suitable for a complex power supply switching scene.

The invention discloses a dual-mode analog front end with a full-speed clock-free decision feedback equalizer (UC-DFE). The dual-mode analog front end comprises a terminating impedance matching network, a linear processing link, the UC-DFE and a signal output module, the terminating impedance matching network realizes broadband impedance matching and electrostatic protection; the linear processing link comprises a CTLE and a VGA and is used for compensating channel attenuation and expanding signal bandwidth; the UC-DFE comprises a summator, a static comparator, a delay unit and a feedback tap, and realizes high-speed signal processing and feedback equalization; and the signal output module converts the balanced signal into a target coding format and outputs the signal. According to the invention, the overall performance of the circuit is improved, the problems of time sequence tension, bandwidth limitation and the like of the traditional DFE architecture at a high speed are solved, and the circuit is suitable for 128Gbps high-speed PAM4 and NRZ signal transmission and shows better comprehensive performance.

The invention provides a repair circuit, a display panel and display equipment. The repairing circuit comprises a dedelay unit, an input end of which is connected with a grid electrode to-be-repaired signal and an output end of which is electrically connected with a first node; the input end of the shaping unit is electrically connected to the first node, and the output end is electrically connected to the second node; the input end of the inverting unit is electrically connected to the second node, and the output end is electrically connected to the third node. The de-delay unit is used for processing the grid signal to be repaired according to the clock signal and outputting a de-delay signal, so that the falling edge of the de-delay signal is consistent with the falling edge of the clock signal; the shaping unit is used for processing the rising edge waveform of the dedelayed signal and outputting a square wave signal opposite to the dedelayed signal in phase; and the inverting unit is used for performing inverting processing on the square wave signal and outputting a grid electrode repairing signal. The repairing circuit can effectively repair abnormal grid signals in the display panel, and the product yield is improved.

The invention discloses a negative group delay system based on SSPP, and belongs to the technical field of microwave communication. A fundamental mode negative group velocity is innovatively generated based on an artificial surface plasmon SSPP, and an SSPP system with negative group delay is realized. The system comprises two parts, namely an amplifier circuit and an SSPP waveguide with a negative group delay unit. The SSPP waveguide with the negative group delay characteristic comprises two coplanar waveguide parts, two transition parts and an SSPP waveguide part, the SSPP waveguide part comprises a unit for generating negative group velocity and a plurality of basic units, and further comprises a microwave dielectric substrate. The amplifier is composed of an amplifier chip, a peripheral capacitor inductor of the amplifier chip and a direct-current power supply. An input signal passes through the system, and advanced transmission of the signal can be realized. The problems of narrow bandwidth, large loss and non-adjustable structure in the prior art are effectively solved, and the antenna has wide application prospects in the fields of 5G communication, radar signal processing, array antenna systems and the like.

The embodiment of the invention discloses a delay-locked loop circuit, a clock generator, a chip and electronic equipment, and belongs to the technical field of integrated circuits. The delay-locked loop circuit includes: a digital control circuit for transmitting a first adjustment code adapted to adjust the number of delay units in a coarse adjustment phase, and determining whether to adjust the first adjustment code based on a first feedback signal; in the fine adjustment stage, a third adjustment code suitable for adjusting the delay attribute parameter of the delay unit is sent, and whether the third adjustment code is adjusted or not is determined based on the second feedback signal; in the locking phase, transmitting a second adjustment code suitable for adjusting the control voltage of the delay unit, and determining whether to adjust the second adjustment code based on the third feedback signal; and the phase detection unit is used for sending the first feedback signal, the second feedback signal and the third feedback signal to the digital control circuit. A hybrid circuit of digital design and analog design is provided, high-precision clock phase adjustment is achieved, and an output clock in a wide frequency range can also be achieved.

The invention relates to the field of pulse signal generation, and discloses an integer frequency signal generation circuit and method for a microprocessor, and the circuit comprises a flipping register, a frequency division register, a counter, a frequency signal flipping module, an integer frequency calculation unit, and a time delay unit. The integer frequency calculation unit is used for calculating the delay series of the fractional part of the frequency division value when the enable signal 1 is valid, and sending the delay series to the delay unit; and the delay unit is used for carrying out delay less than one clock period on the frequency signal output by the frequency signal overturning module according to the delay series sent by the integer frequency calculation unit, and outputting an integer frequency signal. According to the integer frequency signal output circuit disclosed by the invention, the frequency division value and the delay series of the frequency division register are automatically changed through the integer calculation module and the delay series calculation module, and the delay series controls the one-out-of-256 selector to be used for selecting the frequency signal output of the corresponding delay module in the delay unit, so that the generation of the integer frequency signal is realized.

The present disclosure provides to a stretchable display device and a stretchable panel driving circuit, the display device including a stretchable display panel, a gate driving circuit configured to supply gate signals to pixels through gate lines, a data driving circuit, at least one stretch detection circuit group including at least one delay cell and at least one stretch variable capacitor disposed in a non-display area of the display panel, and configured to detect a delay time caused by stretch, a compensation control signal generator configured to generate a compensation control signal based on the delay time, and a timing controller configured to output a compensated signal based on the compensation control signal.

The invention provides a delay circuit applied to a time-interleaved analog-to-digital converter, the circuit comprises a first delay module, a second delay module and a delay selector, the first delay module is composed of multiple stages of delay units connected in series, each stage comprises a fixed inductor connected in series and a variable capacitor connected in parallel, and is used for providing large-range adjustable delay; the second delay module is connected to the output end of the first delay module and comprises a parallel combination of an adjustable constant current source and a programmable capacitor array, high-precision delay adjustment is achieved, the minimum adjustment step length of the second delay module is smaller than that of the first delay module, and multiple input ends of the delay selector are connected with output nodes of all stages of delay units respectively. The selection module is used for selecting coarse delay signals in different stages; the circuit realizes low-noise coarse delay adjustment through the inductance-capacitance network, completes high-precision fine delay adjustment by using current-capacitance combination, and has the advantages of wide delay range, high adjustment precision, low noise, good stability and the like.

The invention provides a numerical control delayer, a four-digit numerical control delayer and a manufacturing method of a chip of the four-digit numerical control delayer. The delayer comprises a first single-pole double-throw switch, a second single-pole double-throw switch, a delay unit and a reference unit, the first single-pole double-throw switch comprises two stages of triodes S1 and S2 which are connected in parallel; the second single-pole double-throw switch comprises a triode S3 and a triode S4 which are connected in parallel; one end of the delay unit is connected with the drain electrode of S1, and the other end is connected with the drain electrode of S3; one end of the reference unit is connected with the drain of S2, and the other end is connected with the drain of S4; drain electrodes of the S1 and the S2 are connected with a radio frequency signal input port; drain electrodes of the S3 and the S4 are connected with a radio frequency signal output port; source electrodes of the S1, the S2, the S3 and the S4 are all in direct current grounding, grid electrodes of the S1, the S2, the S3 and the S4 are all connected with a voltage control unit, and on and off of each triode are controlled by controlling grid electrode voltage, so that the delayer is switched between a reference state and a delay state. According to the invention, the insertion loss of the delayer in the millimeter wave frequency band can be reduced.

The invention provides a calibration system applied to DLL-TDC, and solves the technical problems of low circuit linearity and large time measurement result error of an existing time-to-digital converter. The device comprises a DLL-TDC module and a calibration network module. The DLL-TDC module is used for feeding back a control voltage in real time and carrying out preliminary calibration on the delay time of each delay unit; obtaining the number of the delay units passing by at the stop moment and a count value according to the start and stop of the to-be-measured signal, and calculating the number of the delay units passing by the to-be-measured signal; and the calibration network module is used for detecting the change relationship between the temperature and the delay time, correspondingly predicting the delay time of the to-be-detected signal passing through each delay unit according to the temperature, and adding the delay time to obtain the time interval of the calibrated to-be-detected signal. The circuit can be widely applied to the technical field of integrated circuits.

The invention provides a PWM signal generation circuit and a control device. The PWM signal generation circuit comprises a control module, a delay chain module and an edge detection module, wherein the delay chain module and the edge detection module are electrically connected with the control module; the edge detection module is used for receiving an original PWM signal output by the PWM system, detecting the edge of the original PWM signal based on an edge detection instruction, generating an edge indication signal and sending the edge indication signal to the delay chain module; the delay chain module comprises a plurality of delay units and is used for delaying the edge of the original PWM signal by target delay time to generate a target PWM signal; according to the invention, the delay operation is carried out on the original PWM signal at the specified edge through the delay chain module, the target PWM signal with the resolution higher than that of the original PWM signal is obtained, and the high-resolution PWM signal is generated by using the low-frequency clock of the PWM system on the premise of not changing the system work clock period of the PWM system.

A multi-phase clock signal generating circuit, configured to generate a plurality of output clock signals with different phases, comprising: a charge pump, configured to generate a control voltage according to a reference clock signal and a target clock signal; a delay circuit, comprising a delay chain with a plurality of delay units, configured to generate a plurality of candidate clock signals and the target clock signal according to the control voltage; and a phase selecting circuit, configured to select at least two of the candidate clock signals as the output signals.

The invention belongs to the technical field of distributed optical fiber sensing, and relates to a coding difference phase noise and distortion cooperative suppression optical frequency domain reflection method, which comprises the following steps: acquiring upper and lower frequency sweeping and beat frequency signals; separating the upper and lower sweep-frequency beat-frequency signals to obtain an upper sweep-frequency beat-frequency signal and a lower sweep-frequency beat-frequency signal; acquiring an upper sweep frequency beat frequency electric signal and a lower sweep frequency beat frequency electric signal; and the upper frequency-sweeping beat-frequency electric signal is delayed by one spatial resolution and then is mixed with the lower frequency-sweeping beat-frequency electric signal, or the lower frequency-sweeping beat-frequency electric signal is delayed by one spatial resolution and then is mixed with the upper frequency-sweeping beat-frequency electric signal, a frequency-mixing signal after phase frequency noise and frequency domain distortion suppression is obtained, and the Fourier frequency domain spectrum of the frequency-mixing signal is analyzed. The invention also provides a coding difference phase noise and distortion cooperative suppression optical frequency domain reflection system. The system comprises a positive and negative double-sideband sweep frequency light acquisition device, an optical splitter, a spectrum spreading device, an interference device, a beat frequency signal acquisition device and an electric delay unit. According to the invention, phase noise and frequency domain distortion noise can be effectively suppressed.

The invention relates to a PSRAM controller, in particular to a PSRAM data eye pattern training system and method, and the system comprises a training control module, a write delay unit combination, a read delay unit combination, and PSRAM particles. The training control module is used for clock enabling, data sending, data receiving, data comparing, writing delay unit number control and reading delay unit number control; the write delay unit combination is used for obtaining a write delay clock by adjusting the delay of the main frequency clock so as to find the optimal position of the write data eye diagram; the read delay unit combination is used for obtaining a read delay clock by adjusting the delay of an output data strobe signal DQS of the PSRAM particles so as to find the optimal position of a read data eye diagram; the PSRAM particles are memory storage units; according to the technical scheme provided by the invention, the defect that the position of the sampling clock is difficult to dynamically adjust during the working period of the chip in the prior art can be effectively overcome.

The invention relates to the technical field of analog integrated circuits, and discloses a reference clock frequency multiplier circuit and a chip, and the reference clock frequency multiplier circuit comprises a phase discriminator, a charge pump, a loop filter, a voltage-controlled delay unit, a multiphase injection locked ring oscillator and an edge combiner. And the voltage-controlled delay unit, the phase discriminator, the charge pump and the loop filter form a multi-phase clock generator. The multi-phase injection clock signal is generated by adopting the voltage-controlled delay unit, and the multi-phase injection locking ring oscillator is further adopted as an input clock source of the edge combiner, so that the phase error of the multi-phase injection clock signal generated by the voltage-controlled delay unit is suppressed; therefore, a frequency multiplication clock signal with an accurate duty ratio and low noise is obtained.

A clock signal delay path unit includes a first delay cell including a first root signal line for delaying and transmitting a clock signal, a first repeater to transmit the clock signal transmitted through the first root signal line without signal attenuation, and a second root signal line for delaying and transmitting the clock signal output from the first repeater, a second delay cell including a first inverting circuit configured to invert the clock signal provided from the first delay cell to generate an inverted clock signal, and a third delay cell including a first branch signal line for delaying and transmitting the inverted clock signal provided from the second delay cell, a second repeater to transmit the inverted clock signal transmitted through the first branch signal line, and a second branch signal line for delaying and transmitting the inverted clock signal output from the second repeater.

The invention discloses a microwave photon beam forming network architecture based on a switch switching type optical adjustable true delay line and a phased array radar system thereof. According to the framework, microwave signals are modulated in an optical domain, and the characteristics of a plurality of adjustable delay paths in a single-channel switch switching type delay line are utilized, so that delay difference adjustment of multiple paths of optical signals is realized, the number of delay lines and delay units is greatly reduced, and meanwhile, high-precision and broadband beam-strabismus-free beam forming is supported; through two-stage or multi-stage delay configuration, the network can flexibly meet the broadband delay compensation requirements of different array antenna units, has low complexity and strong dynamic reconfigurable capability, is suitable for realization of a large-scale photonic integrated chip, reduces the number of delay lines by about 50%, does not generate frequency dispersion, and is suitable for large-scale photonic integrated chips. The system complexity, the cost and the power consumption can be remarkably reduced, and the method is particularly suitable for broadband phased array systems of millimeter waves, satellite communication, radar detection and the like.

The invention discloses an implementation method of a high-precision time-to-digital converter, and relates to the technical field of time mode signal processing. The delay chain comprises a Start signal channel and a plurality of Stop signal channels, each delay chain corresponds to one channel, each delay chain is formed by cascading a circuit with a delay function as a delay unit, the chain structure is divided into an integral chain and a differential chain, the integral chain is that one channel corresponds to one independent delay chain, and the differential chain is that one channel corresponds to one independent delay chain. The difference chain regards two delay chains corresponding to two adjacent channels as a group, and the time difference of signals reaching the input ends of the two delay chains is maintained for 1 / 2 of the delay duration of a single-stage delay unit through a back-end constraint physical layout wiring rule, so that difference is formed. According to the invention, the maximum time resolution of TDC can reach about 12ps, and the test precision is lt; and the dynamic range is about 67 ms, so that high-precision time interval measurement capable of being dynamically calibrated is realized.

The invention relates to the field of electronic oscillation circuits, and discloses a low-noise ring oscillator. The ring oscillator comprises an oscillation loop formed by connecting 2N + 1 stages of delay unit modules end to end, each stage of delay unit module comprises a complementary MOS tube and a source electrode degeneration resistor, one end of the source electrode degeneration resistor is connected with a source electrode of the complementary MOS tube, the other end of the source electrode degeneration resistor is connected with a common potential, and the source electrode degeneration resistor is made of a low-noise polycrystalline silicon resistor. By introducing the source electrode degeneration resistor into the delay unit module and utilizing the characteristic that a resistor element has lower noise compared with an MOS (Metal Oxide Semiconductor) device, the proportion of an MOS tube in the integral noise contribution is effectively reduced, so that the phase noise performance of the ring oscillator is improved, and the ring oscillator is particularly suitable for an electronic circuit system needing a high-quality clock signal.

The invention provides a repair circuit, a display panel and a display device. The repairing circuit comprises an input module, a first input end of which is connected with a to-be-repaired signal, a first output end of which is electrically connected with a first node, and which is used for carrying out voltage reduction processing on the to-be-repaired signal and then outputting a first input signal; and the processing module comprises a dedelay unit, a shaping unit and a level conversion unit. The control end of the de-delay unit is electrically connected to the first node, the input end is coupled with the corresponding clock signal, the output end is electrically connected to the second node, the de-delay unit is used for performing de-delay processing on the first input signal according to the corresponding clock signal and then outputting a de-delay signal, and the falling edge of the de-delay signal is consistent with the falling edge of the corresponding clock signal; the shaping unit is electrically connected to the second node and is used for shaping the waveform of the dedelayed signal and then outputting a square wave signal; and the level conversion unit is electrically connected to the output end of the shaping unit and is used for performing level adjustment on the square wave signal and then outputting a scanning repair signal.

The invention provides a signal data synchronization method for a multi-microphone array, and the method comprises the steps: generating a digital synchronization signal through a main control processing unit, generating an analog synchronization signal through a digital-to-analog converter, and transmitting the analog synchronization signal to each microphone array unit; each microphone array unit obtains a respective synchronizing signal and transmits the synchronizing signal to the main control processing unit; the re-sampler adjusts the sampling interval of the synchronizing signal, and the phase discriminator detects the phase difference between the re-sampled synchronizing signal and the local high-frequency synchronizing signal and feeds back the phase difference to the re-sampler until the re-sampled synchronizing signal and the local high-frequency synchronizing signal have the same frequency and keep a stable phase difference; and performing mobile cross-correlation on the resampled synchronizing signal and a local high-frequency synchronizing signal in the delay estimator, and compensating delay deviation through a delayer. And the main control processing unit performs synchronization processing by using the local synchronization signal and the received return synchronization signal, and further adjusts the microphone signal of the array unit to achieve strict sample synchronization.

The invention provides a piezoelectric transducer and method for directionally exciting and receiving non-dispersion torsional guided waves, and relates to the technical field of ultrasonic nondestructive testing, the piezoelectric transducer comprises a first circumferential array, and the first circumferential array is composed of a plurality of first piezoelectric units and a plurality of first time delay units; and the second circumferential array is composed of a plurality of second piezoelectric units and a plurality of second time delay units. The piezoelectric transducer capable of directionally exciting and receiving the non-dispersion torsional guided wave is constructed through the thickness shearing type piezoelectric unit and the height difference time delay unit, no matter unidirectional excitation or unidirectional receiving is needed, an additional circuit or equipment is not needed to provide time delay, and the complexity and cost of the whole structure are reduced. In addition, the time delay unit is adopted to replace a piezoelectric unit to be in curved surface combination with the pipeline, the problem that the piezoelectric unit is not matched with the detected pipeline due to too small flexibility can be avoided, then the fitting degree is improved, signal transmission is guaranteed, and detection is more efficient and accurate.

The application discloses a kind of photonic tensor convolution calculation method and system for multi-channel data processing.The system includes multi-wavelength light source, high-speed modulator, signal generating unit, weighting unit, delay unit, balanced photodetector and signal processing unit, and the multi-channel tensor reconstruction algorithm of input signal.By improving the vectorization rule of tensor data, the elements of different channels in high-order tensor are rearranged into a one-dimensional vector.Based on the technology of three-dimensional multiplexing of time, space and frequency, only one modulator and a set of signal generating unit are needed to realize the convolution calculation of single optical link with arbitrary multi-channel tensor data simultaneously.The sliding convolution of multi-channel data can be directly completed in one calculation, which can release more physical hardware resources for multi-tensor parallel operation, complete more concise and efficient photonic tensor convolution operation, and greatly increase the integration and scalability of the scheme.

The invention discloses a circuit for improving the reliability of a power tube in a temperature control circuit. The circuit comprises a two-phase non-overlapping clock generation module and an output-stage power tube module, the input end of the two-phase non-overlapping clock generation module is connected with a PWM control signal, one path of non-intersecting clock generated by the output end of the two-phase non-overlapping clock generation module is connected with a grid electrode of a PMOS power tube in the output-stage power tube module, and the other path of non-intersecting clock generated by the output end of the two-phase non-overlapping clock generation module is connected with a grid electrode of an NMOS power tube in the output-stage power tube module. Under the condition that only capacitance is increased, time of a dead zone is effectively prolonged, so that the condition that output power tubes are conducted at the same time is avoided, and reliability of the power tubes of the temperature control circuit is improved; in addition, in the structure, the dead time can be changed by only adjusting the capacitance value of the capacitor in the delay unit. Compared with the prior art, the invention has the advantages of less area resource consumption and simple structure.

The invention discloses an automatic conversion time successive approximation type analog-to-digital converter based on pulse width detection. The pulse waveform generation circuit generates a first reference signal and a second reference signal. The pulse width detector compares a comparison clock signal of the comparator with a first reference signal, and the calibration logic unit outputs a first calibration code to the adjustable delay unit, so that the comparison clock signal approaches the reference signal. The pulse width detector also compares the sampling conversion stage signal with a second reference signal, and the calibration logic unit outputs a second calibration code to the adjustable delay unit, so that the sampling conversion stage signal approaches the second reference signal. And the adjustable delay unit adjusts the delay of the control loop according to the calibration code. According to the method, the asynchronous time sequence type SAR ADC can adaptively adjust the comparison period and the conversion time, the resistance to fluctuation factors such as process deviation, process mismatch, temperature and power supply voltage change is improved, and the performance stability of the SAR ADC is ensured.

The utility model discloses an auxiliary power supply protection circuit, a power module and a power conversion system, and the method comprises the steps: receiving an undervoltage signal of a first signal output end through an undervoltage protection unit, and generating a first control signal based on the undervoltage signal; the feedback unit generates a second control signal based on the sleep signal; the control unit receives the first control signal and / or the second control signal, and controls the switching device to stop based on the first control signal and / or the second control signal; the time delay unit generates a time delay signal based on the dormancy signal, and controls the auxiliary power supply control chip to turn off the auxiliary power supply in a delayed manner based on the time delay signal, so that the problem that the auxiliary power supply is damaged due to the fact that a switching device cannot send waves when the auxiliary power supply breaks down can be solved; therefore, signal detection resources are saved, the auxiliary power supply control chip is controlled by the delay unit to turn off the auxiliary power supply in a delayed manner, and a switching device can be protected from being damaged.

The invention belongs to the technical field of analog-to-digital converters, and particularly relates to a dynamic delay adaptive asynchronous time sequence control circuit for an SAR ADC (Synthetic Aperture Radar Analog to Digital Converter). According to the circuit disclosed by the invention, through an innovative circuit architecture and a control method, remarkable breakthrough is realized in the aspects of conversion precision and speed. According to the circuit, a unique two-stage dynamic delay adjustment mechanism is adopted, intelligent optimization of delay time is achieved based on real-time comparison frequency monitoring, the effective conversion rate under 16-bit precision is improved by 25% or above, and meanwhile it is kept that ENOB is not lower than 15 bits. The innovative current charging capacitance type delay unit is combined with the PVT compensation technology, and the delay time stability is superior to + / -3% within the working temperature range of-40 DEG C to 125 DEG C. Through a dynamic adjustment algorithm of cooperative work of a shift register and a lookup table, the system can automatically adapt to establishment time change of 10 ns to 50 ns, and compared with a fixed delay scheme, invalid waiting time is saved by more than 30%.

The utility model provides an asymmetric delay control circuit and device, which can be applied to the technical field of electronic circuits. The asymmetric delay control circuit comprises a delay unit and an asynchronous trigger, the asynchronous trigger comprises a reset input end, a delay input end and an output end, the delay unit is connected with the delay input end, and the delay unit is used for delaying a clock signal input to the delay input end; wherein under the condition that the clock signal input by the reset input end is an invalid level, the output end outputs the invalid level, and under the condition that the clock signal input by the reset input end is an effective level and the clock signal input by the delay input end is detected to be switched from the invalid level to the effective level, the output end outputs the effective level.

The application provides an AM-PM distortion calibration method applied to an UWB transmitter and belongs to the field of UWB communication. The method adds a sampling resistor between a linear voltage stabilizing power supply LDO and a digital power amplifier DPA driving stage of the UWB transmitter using a digital power amplifier, so as to simulate the instantaneous change of the power supply voltage of the DPA driving stage when the UWB pulse is transmitted; an adjustable delay unit is added between a carrier input port LO and the DPA driving stage; the continuous sine wave is transmitted, the phase information under each digital baseband amplitude control word is collected to form original data of the AM-PM distortion of the UWB transmitter, the digital baseband output AM-PM control word is used to control the adjustable delay unit to output the phase which is opposite to the original data and has the same size, so that the phase predistortion of the transmitted UWB pulse is realized, and the AM-PM distortion calibration is completed. The application has the advantages of simple implementation and strong compensation capacity.

The application discloses a kind of delay pulse generation device, method and electronic equipment based on FPGA chip, field programmable gate array FPGA chip has M delay units, the device includes: clock generation module, for generating reference clock, output clock and delay clock;Pulse generation module, for generating first output pulse according to reference clock;Delay adjustment module, for first output pulse is delayed adjustment according to delay clock, obtains second output pulse, wherein, delay adjustment module includes N delay units, N is less than or equal to M positive integer;And serial conversion module, for second output pulse is converted into parallel according to reference clock and output clock, and output delay pulse sequence.The device is based on FPGA chip internal logic to realize sub-nanosecond delay adjustment, generates sub-nanosecond delay pulse sequence, and the requirement level of peripheral circuit is low, with the advantages of low cost, simple structure, easy to realize.