669 results about "Delay unit" patented technology

The invention discloses an intelligent control system for a current transformer, and particularly relates to the technical field of power system monitoring, which comprises a fluctuation identification unit, a redundancy acquisition unit, an error fitting unit, a protection delay unit and a fault response unit, realizes real-time identification and classification of current fluctuation, and has standby path high-speed sampling and fusion signal construction capabilities. The fluctuation trend is judged through error regression, a protection strategy is dynamically set, response is delayed to avoid misoperation, finally, a high-level protection instruction is triggered and a fault event is output when offset overruns or alignment fails, and the data accuracy and the system response stability in the power supply switching process are guaranteed; according to the method, accurate identification of current fluctuation is realized through multi-dimensional feature extraction, data reliability is enhanced by using redundant sampling and error fitting, and by combining delay control and a hierarchical response mechanism, the risk of misoperation is effectively reduced, the fault judgment accuracy and the system protection stability are improved, and the method is suitable for a complex power supply switching scene.

The invention discloses a dual-mode analog front end with a full-speed clock-free decision feedback equalizer (UC-DFE). The dual-mode analog front end comprises a terminating impedance matching network, a linear processing link, the UC-DFE and a signal output module, the terminating impedance matching network realizes broadband impedance matching and electrostatic protection; the linear processing link comprises a CTLE and a VGA and is used for compensating channel attenuation and expanding signal bandwidth; the UC-DFE comprises a summator, a static comparator, a delay unit and a feedback tap, and realizes high-speed signal processing and feedback equalization; and the signal output module converts the balanced signal into a target coding format and outputs the signal. According to the invention, the overall performance of the circuit is improved, the problems of time sequence tension, bandwidth limitation and the like of the traditional DFE architecture at a high speed are solved, and the circuit is suitable for 128Gbps high-speed PAM4 and NRZ signal transmission and shows better comprehensive performance.

The invention discloses a human body existence sensing method based on millimeter wave radar and infrared pyroelectric sensor double-source collaborative fusion, and the method comprises the steps: processing original data collected by a millimeter wave radar sensor receiving end, and obtaining a high-quality distance-speed dimension data matrix; carrying out SVD decomposition, and reconstructing two new data matrixes which are respectively corresponding to a strong target signal and a weak target signal; a human body existence sensing output result of the millimeter wave radar sensor is obtained through the track features and the breathing features; processing a signal of the infrared pyroelectric sensor to obtain a human body existence sensing output result of the infrared pyroelectric sensor; and constructing a heterogenous data matrix according to output results of the two sensors, and performing fusion algorithm processing on the heterogenous data matrix to obtain a fusion result. And finally, the fusion result is stored in a delay memory matrix, and the aging degree is calculated according to the aging factors corresponding to different delay units, so that a final human body existence sensing result is obtained.

The embodiment of the invention discloses a cascade structure delay circuit, a signal delay method applied to a multi-stage delay unit, semiconductor test equipment and a time sequence generation chip, the circuit comprises a clock source, a signal input source and the multi-stage delay unit, and the multi-stage delay unit comprises at least two delay units connected in a cascade mode; the signal input end of the first-stage delay unit in the multiple stages of delay units is connected with a signal input source; and each delay unit in the multiple stages of delay units is used for delaying an input signal according to the delay configuration value received by the respective delay time configuration end, outputting a delayed output signal, and updating the delay configuration value according to the update interval time set by each delay unit. According to the embodiment of the invention, the overall delay precision and delay time range of the multi-stage delay unit is expanded, and the time precision of the synthetic waveform of the time sequence generation device of the semiconductor test equipment is improved.

The invention provides a repair circuit, a display panel and display equipment. The repairing circuit comprises a dedelay unit, an input end of which is connected with a grid electrode to-be-repaired signal and an output end of which is electrically connected with a first node; the input end of the shaping unit is electrically connected to the first node, and the output end is electrically connected to the second node; the input end of the inverting unit is electrically connected to the second node, and the output end is electrically connected to the third node. The de-delay unit is used for processing the grid signal to be repaired according to the clock signal and outputting a de-delay signal, so that the falling edge of the de-delay signal is consistent with the falling edge of the clock signal; the shaping unit is used for processing the rising edge waveform of the dedelayed signal and outputting a square wave signal opposite to the dedelayed signal in phase; and the inverting unit is used for performing inverting processing on the square wave signal and outputting a grid electrode repairing signal. The repairing circuit can effectively repair abnormal grid signals in the display panel, and the product yield is improved.

A PUF circuit based on the threshold loss of MOSFETs comprises N stages of delay units and an arbiter. Each stage of delay unit comprises six inverters and four MOS transistors, wherein the four MOS transistors are all PMOS transistors or NMOS transistors. Each path in each stage of delay unit uses only one PMOS or NMOS transistor and does not use a transmission gate formed by a PMOS transistor and an NMOS transistor. Therefore, it reduces hardware cost. Each MOS transistor on the transmission path has a threshold loss, PMOS and NMOS transistors in a third inverter and a sixth inverter are in an on-state, and output terminals of the third inverter and the sixth inverter will be charged to a high level or discharged to a low level, thus greatly increasing a delay difference between two square signals and enhancing randomness.

The invention discloses a negative group delay system based on SSPP, and belongs to the technical field of microwave communication. A fundamental mode negative group velocity is innovatively generated based on an artificial surface plasmon SSPP, and an SSPP system with negative group delay is realized. The system comprises two parts, namely an amplifier circuit and an SSPP waveguide with a negative group delay unit. The SSPP waveguide with the negative group delay characteristic comprises two coplanar waveguide parts, two transition parts and an SSPP waveguide part, the SSPP waveguide part comprises a unit for generating negative group velocity and a plurality of basic units, and further comprises a microwave dielectric substrate. The amplifier is composed of an amplifier chip, a peripheral capacitor inductor of the amplifier chip and a direct-current power supply. An input signal passes through the system, and advanced transmission of the signal can be realized. The problems of narrow bandwidth, large loss and non-adjustable structure in the prior art are effectively solved, and the antenna has wide application prospects in the fields of 5G communication, radar signal processing, array antenna systems and the like.

The embodiment of the invention discloses a delay-locked loop circuit, a clock generator, a chip and electronic equipment, and belongs to the technical field of integrated circuits. The delay-locked loop circuit includes: a digital control circuit for transmitting a first adjustment code adapted to adjust the number of delay units in a coarse adjustment phase, and determining whether to adjust the first adjustment code based on a first feedback signal; in the fine adjustment stage, a third adjustment code suitable for adjusting the delay attribute parameter of the delay unit is sent, and whether the third adjustment code is adjusted or not is determined based on the second feedback signal; in the locking phase, transmitting a second adjustment code suitable for adjusting the control voltage of the delay unit, and determining whether to adjust the second adjustment code based on the third feedback signal; and the phase detection unit is used for sending the first feedback signal, the second feedback signal and the third feedback signal to the digital control circuit. A hybrid circuit of digital design and analog design is provided, high-precision clock phase adjustment is achieved, and an output clock in a wide frequency range can also be achieved.

The invention provides a delay chain circuit, a voltage drop detection circuit, a chip and electronic equipment, and belongs to the field of electronic circuits. The delay chain circuit comprises m stages of delay units, each stage of delay unit comprises an output end and n input ends, m is an integer greater than or equal to 2, and n is an integer greater than or equal to 2; at least one input end of the ith-level delay unit is connected with the output end of the (i-1) th-level delay unit, and i is an integer greater than or equal to 2; the sensitivity of each stage of delay unit is adjustable, and each stage of delay unit comprises n delay branches which are connected in parallel; the n delay branches comprise at least one controllable delay branch, and the state of each controllable delay branch comprises an on state or an off state. By adjusting the sensitivity of the delay chain circuit, different load changes can be adapted, and the maximum voltage gain of a chip can be supported when a dynamic frequency reduction technology is used.

The invention relates to the field of pulse signal generation, and discloses an integer frequency signal generation circuit and method for a microprocessor, and the circuit comprises a flipping register, a frequency division register, a counter, a frequency signal flipping module, an integer frequency calculation unit, and a time delay unit. The integer frequency calculation unit is used for calculating the delay series of the fractional part of the frequency division value when the enable signal 1 is valid, and sending the delay series to the delay unit; and the delay unit is used for carrying out delay less than one clock period on the frequency signal output by the frequency signal overturning module according to the delay series sent by the integer frequency calculation unit, and outputting an integer frequency signal. According to the integer frequency signal output circuit disclosed by the invention, the frequency division value and the delay series of the frequency division register are automatically changed through the integer calculation module and the delay series calculation module, and the delay series controls the one-out-of-256 selector to be used for selecting the frequency signal output of the corresponding delay module in the delay unit, so that the generation of the integer frequency signal is realized.

The present invention proposes a circuit and working method for realizing power supply monitoring with high efficiency and low power consumption, including a voltage divider circuit, a reference voltage source, a comparator, a high-speed power-on detection circuit, a NOR gate, a clock generation and shutdown circuit, a delay module and an output drive module. The voltage divider circuit is used to generate a reset threshold voltage that is proportional to the input voltage; the reference voltage source is used to generate a reference voltage that is independent of the power supply voltage and temperature; the comparator is used to compare the voltage after voltage division with the reference voltage; the high-speed power-on detection circuit is used to generate an on-chip reset signal of a power supply monitoring circuit with anti-interference capability; the clock generation and shutdown circuit is used to generate a clock signal of a delay unit and shut down a clock generation circuit; and the delay module is used for timing. It introduces a high-speed power-on detection circuit to avoid the reset failure problem caused by the comparator failing to flip in time or the power supply glitch interference, and at the same time introduces a clock shutdown circuit to effectively reduce power consumption.

The invention discloses a chip design hold time violation automatic correction method and system, a medium and a product, and the method comprises the steps: calculating a ratio between a setting time margin and an absolute value of a hold time violation value according to an end point pin of a time sequence path of the hold time violation of the chip design; selecting different insertion points to insert the delay unit or the buffer unit according to whether the ratio is greater than a preset value K; and then finishing one-time retention time violation correction, detecting and reporting whether a time sequence path of retention time violation exists or not, and if yes, repeating the process until all retention time violation paths in the design are repaired. The invention aims to realize the automatic correction of the retention time violation of chip design, make up for the defect that the existing engineering renovation tool can only automatically repair the retention time violation with sufficient time margin at the end point of the time sequence path, and can automatically and efficiently repair various retention time violations with sufficient and insufficient time margin. And the chip design achieves the purpose of time sequence convergence as soon as possible.

The embodiment of the invention discloses a clock signal quadrature phase error calibration device, a clock signal quadrature phase error calibration method and a chip, relates to the technical field of clock circuits, and facilitates calibration of clock signal quadrature phase errors. The apparatus comprises: a DLL loop configured to generate a plurality of sets of quadrature phase clock signals; the phase error detection module is used for comparing phase differences of two adjacent groups of orthogonal phase clock signals and outputting phase error information; the phase calibration module comprises a delay link and a digital state machine, the delay link is located in the DLL loop and comprises a plurality of cascaded delay units, a first pin of the digital state machine is connected with the phase error detection module, and a second pin of the digital state machine is connected with the DLL loop. And a second pin of the digital state machine is connected with each delay unit of the delay link and is configured to control at least one delay unit in the delay link according to the phase error information so as to calibrate the phase error of the quadrature phase clock signal. The method is suitable for application scenes such as clock signal transmission and control.

The present disclosure provides to a stretchable display device and a stretchable panel driving circuit, the display device including a stretchable display panel, a gate driving circuit configured to supply gate signals to pixels through gate lines, a data driving circuit, at least one stretch detection circuit group including at least one delay cell and at least one stretch variable capacitor disposed in a non-display area of the display panel, and configured to detect a delay time caused by stretch, a compensation control signal generator configured to generate a compensation control signal based on the delay time, and a timing controller configured to output a compensated signal based on the compensation control signal.

The invention provides a delay circuit applied to a time-interleaved analog-to-digital converter, the circuit comprises a first delay module, a second delay module and a delay selector, the first delay module is composed of multiple stages of delay units connected in series, each stage comprises a fixed inductor connected in series and a variable capacitor connected in parallel, and is used for providing large-range adjustable delay; the second delay module is connected to the output end of the first delay module and comprises a parallel combination of an adjustable constant current source and a programmable capacitor array, high-precision delay adjustment is achieved, the minimum adjustment step length of the second delay module is smaller than that of the first delay module, and multiple input ends of the delay selector are connected with output nodes of all stages of delay units respectively. The selection module is used for selecting coarse delay signals in different stages; the circuit realizes low-noise coarse delay adjustment through the inductance-capacitance network, completes high-precision fine delay adjustment by using current-capacitance combination, and has the advantages of wide delay range, high adjustment precision, low noise, good stability and the like.

The invention provides a numerical control delayer, a four-digit numerical control delayer and a manufacturing method of a chip of the four-digit numerical control delayer. The delayer comprises a first single-pole double-throw switch, a second single-pole double-throw switch, a delay unit and a reference unit, the first single-pole double-throw switch comprises two stages of triodes S1 and S2 which are connected in parallel; the second single-pole double-throw switch comprises a triode S3 and a triode S4 which are connected in parallel; one end of the delay unit is connected with the drain electrode of S1, and the other end is connected with the drain electrode of S3; one end of the reference unit is connected with the drain of S2, and the other end is connected with the drain of S4; drain electrodes of the S1 and the S2 are connected with a radio frequency signal input port; drain electrodes of the S3 and the S4 are connected with a radio frequency signal output port; source electrodes of the S1, the S2, the S3 and the S4 are all in direct current grounding, grid electrodes of the S1, the S2, the S3 and the S4 are all connected with a voltage control unit, and on and off of each triode are controlled by controlling grid electrode voltage, so that the delayer is switched between a reference state and a delay state. According to the invention, the insertion loss of the delayer in the millimeter wave frequency band can be reduced.

The invention provides a calibration system applied to DLL-TDC, and solves the technical problems of low circuit linearity and large time measurement result error of an existing time-to-digital converter. The device comprises a DLL-TDC module and a calibration network module. The DLL-TDC module is used for feeding back a control voltage in real time and carrying out preliminary calibration on the delay time of each delay unit; obtaining the number of the delay units passing by at the stop moment and a count value according to the start and stop of the to-be-measured signal, and calculating the number of the delay units passing by the to-be-measured signal; and the calibration network module is used for detecting the change relationship between the temperature and the delay time, correspondingly predicting the delay time of the to-be-detected signal passing through each delay unit according to the temperature, and adding the delay time to obtain the time interval of the calibrated to-be-detected signal. The circuit can be widely applied to the technical field of integrated circuits.

The invention provides a PWM signal generation circuit and a control device. The PWM signal generation circuit comprises a control module, a delay chain module and an edge detection module, wherein the delay chain module and the edge detection module are electrically connected with the control module; the edge detection module is used for receiving an original PWM signal output by the PWM system, detecting the edge of the original PWM signal based on an edge detection instruction, generating an edge indication signal and sending the edge indication signal to the delay chain module; the delay chain module comprises a plurality of delay units and is used for delaying the edge of the original PWM signal by target delay time to generate a target PWM signal; according to the invention, the delay operation is carried out on the original PWM signal at the specified edge through the delay chain module, the target PWM signal with the resolution higher than that of the original PWM signal is obtained, and the high-resolution PWM signal is generated by using the low-frequency clock of the PWM system on the premise of not changing the system work clock period of the PWM system.

A multi-phase clock signal generating circuit, configured to generate a plurality of output clock signals with different phases, comprising: a charge pump, configured to generate a control voltage according to a reference clock signal and a target clock signal; a delay circuit, comprising a delay chain with a plurality of delay units, configured to generate a plurality of candidate clock signals and the target clock signal according to the control voltage; and a phase selecting circuit, configured to select at least two of the candidate clock signals as the output signals.

The invention discloses a control system and a robot, and the system comprises a shutdown unit which is used for outputting a shutdown signal; the first power supply unit is connected with the shutdown unit and the control unit and is used for providing first power supply voltage for the control unit, and the provided first power supply voltage is gradually reduced to zero after the shutdown signal is received; the control unit is used for outputting a control signal to the driving chip, so that the driving chip controls the working state of the load; a first delay unit and a second power supply unit, the first delay unit is connected with the shutdown unit and the second power supply unit, and the first delay unit is used for receiving the shutdown signal and transmitting the shutdown signal to the second power supply unit after delaying the shutdown signal; and the second power supply unit is connected with the driving chip and is used for providing a second power supply voltage for the driving chip, and after the second power supply unit receives the delayed shutdown signal, the provided second power supply voltage is gradually reduced to zero. According to the invention, the risk of burnout of the driving circuit caused by unstable driving signals can be avoided.

The invention belongs to the technical field of distributed optical fiber sensing, and relates to a coding difference phase noise and distortion cooperative suppression optical frequency domain reflection method, which comprises the following steps: acquiring upper and lower frequency sweeping and beat frequency signals; separating the upper and lower sweep-frequency beat-frequency signals to obtain an upper sweep-frequency beat-frequency signal and a lower sweep-frequency beat-frequency signal; acquiring an upper sweep frequency beat frequency electric signal and a lower sweep frequency beat frequency electric signal; and the upper frequency-sweeping beat-frequency electric signal is delayed by one spatial resolution and then is mixed with the lower frequency-sweeping beat-frequency electric signal, or the lower frequency-sweeping beat-frequency electric signal is delayed by one spatial resolution and then is mixed with the upper frequency-sweeping beat-frequency electric signal, a frequency-mixing signal after phase frequency noise and frequency domain distortion suppression is obtained, and the Fourier frequency domain spectrum of the frequency-mixing signal is analyzed. The invention also provides a coding difference phase noise and distortion cooperative suppression optical frequency domain reflection system. The system comprises a positive and negative double-sideband sweep frequency light acquisition device, an optical splitter, a spectrum spreading device, an interference device, a beat frequency signal acquisition device and an electric delay unit. According to the invention, phase noise and frequency domain distortion noise can be effectively suppressed.

A method of a signal transmission device includes: providing at least one delay line circuit having a plurality of first delay units connected in series; providing a control voltage as a supply voltage provided for a first delay unit of the at least one delay line circuit; and adjusting the control voltage to maintain a delay amount of the first delay unit at a specific delay amount when a variation of the delay amount of the first delay unit occurs.

The invention relates to a PSRAM controller, in particular to a PSRAM data eye pattern training system and method, and the system comprises a training control module, a write delay unit combination, a read delay unit combination, and PSRAM particles. The training control module is used for clock enabling, data sending, data receiving, data comparing, writing delay unit number control and reading delay unit number control; the write delay unit combination is used for obtaining a write delay clock by adjusting the delay of the main frequency clock so as to find the optimal position of the write data eye diagram; the read delay unit combination is used for obtaining a read delay clock by adjusting the delay of an output data strobe signal DQS of the PSRAM particles so as to find the optimal position of a read data eye diagram; the PSRAM particles are memory storage units; according to the technical scheme provided by the invention, the defect that the position of the sampling clock is difficult to dynamically adjust during the working period of the chip in the prior art can be effectively overcome.

The invention discloses a digital filter structure for sigma-delta ADC downsampling, which adopts an all-digital method to construct a third-order single-ring feed-forward system, and integrates an integral-comb cascade filter, a compensation filter and a half-band filter in series. Wherein the integral-comb cascade filter is of a recursive structure formed by connecting multiple stages of integrators in series, downsampling multiple programming is supported, and the parallelism degree and the hardware utilization rate are improved by advancing the position of a delay unit. The compensation filter adopts odd-order integrator multi-branch parallel, so that the resource occupation is reduced, and the processing speed is remarkably improved; the half-band filter adjusts the coefficient position by using a retiming technology, reduces the delay of a critical path, improves the highest frequency of the system, reduces the calculation amount through a symmetric structure and a multiplexing extraction path, and reduces the operation rate demand and data loss through preposed extraction. According to the invention, low power consumption, low hardware consumption and high design flexibility of the downsampling filter in the sigma-delta ADC digital module are realized.

A device including delay cells connected in series and in a feedback loop to provide a ring oscillator. At least one of the delay cells in the ring oscillator is a stacked gate delay cell that includes two or more PMOS transistors having first drain / source paths connected in series to each other and having first gates connected to each other and two or more NMOS transistors having second drain / source paths connected in series to each other and to the first drain / source paths and having second gates connected to each other and to the first gates.

The invention relates to the technical field of analog integrated circuits, and discloses a reference clock frequency multiplier circuit and a chip, and the reference clock frequency multiplier circuit comprises a phase discriminator, a charge pump, a loop filter, a voltage-controlled delay unit, a multiphase injection locked ring oscillator and an edge combiner. And the voltage-controlled delay unit, the phase discriminator, the charge pump and the loop filter form a multi-phase clock generator. The multi-phase injection clock signal is generated by adopting the voltage-controlled delay unit, and the multi-phase injection locking ring oscillator is further adopted as an input clock source of the edge combiner, so that the phase error of the multi-phase injection clock signal generated by the voltage-controlled delay unit is suppressed; therefore, a frequency multiplication clock signal with an accurate duty ratio and low noise is obtained.

The invention discloses a novel clock tree adaptive optimization method using useful deviation based on an RISC-V architecture. The method comprises the following steps: S1, layout; s2, layout is carried out; s3, after the clock tree is synthesized, S10, optimizing a time sequence path between registers; and S20, optimizing a time sequence path from the register to the memory after wiring in the step S4. According to the invention, through adaptive iteration, a tedious algorithm is not needed, the defect of auto use skew of an EDA tool is overcome, the time sequence problem is repaired to the maximum extent, and meanwhile, a delay unit merging method is adopted, so that the win-win effect of high performance and low power consumption of chip design is realized.

A delay control circuit includes: a delay cell including a plurality of bias inverters, first RC circuits, and second RC circuits, the delay cell activates a number of first RC circuits in response to a step code, delays a signal by a delay time based on the number of the activated first RC circuits, and outputs the delayed signal; a ZQ calibrator including pull-up and pull-down circuits, the ZQ calibrator adjusts a number of activated pull-up and pull-down circuits, and inputs a pull-up and pull-down voltage, based on a calibration code to the bias inverters; and a step adjuster including a first ring oscillator including test delay cells, the step adjuster determining characteristics of the first and second RC circuits and activates a number of second RC circuits based on the characteristics and an operating frequency of the delay control circuit.

A clock signal delay path unit includes a first delay cell including a first root signal line for delaying and transmitting a clock signal, a first repeater to transmit the clock signal transmitted through the first root signal line without signal attenuation, and a second root signal line for delaying and transmitting the clock signal output from the first repeater, a second delay cell including a first inverting circuit configured to invert the clock signal provided from the first delay cell to generate an inverted clock signal, and a third delay cell including a first branch signal line for delaying and transmitting the inverted clock signal provided from the second delay cell, a second repeater to transmit the inverted clock signal transmitted through the first branch signal line, and a second branch signal line for delaying and transmitting the inverted clock signal output from the second repeater.

The invention discloses a microwave photon beam forming network architecture based on a switch switching type optical adjustable true delay line and a phased array radar system thereof. According to the framework, microwave signals are modulated in an optical domain, and the characteristics of a plurality of adjustable delay paths in a single-channel switch switching type delay line are utilized, so that delay difference adjustment of multiple paths of optical signals is realized, the number of delay lines and delay units is greatly reduced, and meanwhile, high-precision and broadband beam-strabismus-free beam forming is supported; through two-stage or multi-stage delay configuration, the network can flexibly meet the broadband delay compensation requirements of different array antenna units, has low complexity and strong dynamic reconfigurable capability, is suitable for realization of a large-scale photonic integrated chip, reduces the number of delay lines by about 50%, does not generate frequency dispersion, and is suitable for large-scale photonic integrated chips. The system complexity, the cost and the power consumption can be remarkably reduced, and the method is particularly suitable for broadband phased array systems of millimeter waves, satellite communication, radar detection and the like.