According to the embodiments of the present application, a common mode level conversion circuit and a
clock buffer are disclosed. The common mode level conversion circuit comprises a first level conversion circuit, a first variable
current source configured to receive a first input
signal to generate a first output
signal; a second level conversion circuit, a second variable
current source configured to receive a second input
signal to generate a second output signal; and a feedback circuit configured to receive the first output signal and the second output signal to output a first feedback signal; wherein the first input signal and the second input signal comprise a first
common mode signal, the first output signal and the second output signal comprise a second
common mode signal, and the current of the first variable
current source and the second variable current source is controlled according to the first feedback signal to make the second
common mode signal close to a preset value. The common mode level conversion circuit in the present application has a better signal-to-
noise ratio.