4645results about "Amplifier with semiconductor-devices/discharge-tubes" patented technology

A dual-band antenna matching system and a method for dual-band impedance matching are provided. The method comprises: accepting a frequency-dependent impedance from an antenna; and, selectively supplying a conjugate impedance match for the antenna at either a first and a second communication band, or a third and a fourth communication band. More specifically, the method comprises: tuning a first tuning circuit to a first frequency; and, simultaneously tuning a second tuning circuit to a second frequency. In response, a conjugate match is supplied to the antenna in the first communication band in response to the first frequency. Simultaneously, the antenna is matched in the second communication band in response to the second frequency. When the first tuning circuit is tuned to a third frequency, and the second tuning circuit is tuned to a fourth frequency, then conjugate matches are supplied for the third and fourth communication bands, responsive to the third and fourth frequencies, respectively.

A switched resonant power amplifier system for ultrasonic transducers is disclosed. The system includes an amplifier that receives and processes a driver output signal for generating a drive signal that is provided to an ultrasonic device for controlling output of the ultrasonic device. An output control circuit receives and processes a signal related to a feedback signal generated by the ultrasonic device and a divider reference signal, and generates a compensated clock signal that is adjusted for at least one of phase and frequency differences between the received feedback signal and the divider reference signal. A compensated drive circuit receives and processes the compensated clock signal for generating the divider reference signal, and for generating the driver output signal.

A variable feedback impedance is presented capable of providing high linearity (e.g. as represented by 1P2 and 1P3) and high linear range (e.g. as represented by P1dB) when used in a feedback path of an RF amplifier in the presence of high voltage amplitudes.

A fully integrated, programmable mixed-signal transceiver comprising a radio frequency integrated circuit (RFIC) which is frequency and protocol agnostic with digital inputs and outputs, the transceiver being programmable and configurable for multiple radio frequency bands and standards and being capable of connecting to many networks and service providers. The RFIC does not use spiral inductors and instead includes transmission line inductors allowing for improved scalability. Components of the transceiver are programmable to allow the transceiver to switch between different frequency bands of operating. Frequency switching can be accomplished though the content of digital registers coupled to the components.

An audio path is constructed to include a multi-bit sigma-delta converter for converting an N-bit digital input to an n-bit output representing an over-sampled, lower resolution n-bit version of the N-bit digital input; a formatter for converting the n-bit output to an m signal output (e.g., as a thermometer code, a SDM format or a PWM format); an m-by-m switching matric for receiving the m output signals and for reordering the m output signals, m class-D drivers individual ones of which are driven by one of the reordered m output signals for driving one of m speakers; and a dynamic element matching (DEM) block coupled to the switching matric for controlling the reordering of the m output signals driving the m class-D drivers for spreading the distortion due at least to driver-speaker pair mismatch to wide band noise. The DEM may operate to generate white noise, or it may generate shaped (colored) noise.

A system and method is provided for full-duplex antenna impedance matching. The method comprises: effectively resonating a first antenna at a frequency selectable first channel in a first frequency band; generating a first antenna impedance at the first channel frequency; effectively resonating a second antenna at a frequency selectable second channel in the first frequency band; generating a second antenna impedance at the second channel frequency; supplying a first conjugate impedance match at the first channel frequency; and, supplying a second conjugate impedance match at the second channel frequency. For example, the first antenna may be used for transmission, while the second antenna is used for received communications. The antennas effectively resonant in response to: supplying frequency selectable conjugate impedance matches to the antennas; generating frequency selectable antenna impedances; and/or selecting the frequency of antenna resonance.

A vision system is disclosed. The system includes a pixel array, at least one multi-resolution window operation circuit, and a pixel averaging circuit. The pixel array has an array of pixels configured to receive light signals from an image having at least one tracking target. The multi-resolution window operation circuits are configured to process the image. Each of the multi-resolution window operation circuits processes each tracking target within a particular multi-resolution window. The pixel averaging circuit is configured to sample and average pixels within the particular multi-resolution window.

A circuit for matching the impedance of an output load to an active device includes a transformer including a first winding having a terminal for coupling to the output of the active device and a second winding electromagnetically coupled to the first winding, and a plurality of taps, each of the plurality of taps having a first end coupled to a position on the second winding corresponding to a ratio of the second winding to first winding differing from other ones of the plurality of taps, and a second end. The matching circuit further includes a plurality of MEMS switches each having a control input for receiving a corresponding control signal, a first terminal coupled to the second end of a corresponding one of the plurality of taps, and a switched output selectively coupled to a matching junction in response to the corresponding control signal.

An inductive power transfer system comprises a transmitter coil TX and a receiver coil RX spaced from the transmitter coil. A transmitter circuit comprises the transmitter coil and is in the form of a Class E amplifier with a first inductor U_choke and a transistor in series between the terminals of a power supply, a first transmitter capacitor C_par in parallel with the transistor between the first inductor and a power supply terminal, a primary tank circuit in parallel with the first transmitter capacitor, the primary tank circuit comprising the transmitter coil and a second transmitter capacitor C_res arranged in parallel with the transmitter coil, and a third transmitter capacitor C_ser in series with the first inductor between the first transmitter capacitor and the primary tank circuit. The transistor is arranged to switch at a first frequency ω_d and the capacitance of the second transmitter capacitor is selected such that the resonant frequency ω_OTX of the primary tank circuit is greater than the first frequency. The receiver circuit comprises a Class E rectifier having a first receiver capacitor C_L arranged in parallel with a load R_L and a secondary tank circuit in parallel with the first receiver capacitor. The secondary tank circuit comprises the receiver coil and a second receiver capacitor C_res arranged in parallel or series with the receiver coil. A first diode D_r2 is provided between the secondary tank circuit and the first receiver capacitor. The capacitance of the second receiver capacitor is selected such that the resonant frequency ω_oRX of the secondary tank circuit differs from the first frequency, so that the secondary tank circuit operates in semi-resonance and maintains some reactive impedance. The transmitter circuit is configured to vary the first frequency, in order to achieve a desired impedance of the primary tank circuit.

An imager pixel including a photodetector, a first MOS transistor functioning as the driver of a source follower amplifier during signal readout, a second MOS transistor serving as a pixel readout transistor, a third MOS transistor serving as a photodetector reset transistor, and a reset noise cancellation circuit including a fourth MOS transistor, first and second capacitances, and an amplifier having a gain which is the inverse of the ratio of the first to the second capacitance.

A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another.

A chopper-stabilized amplifier has switching networks arranged to support a high frequency clocking signal and to provide a high common mode rejection and a high rejection of an offset component of an input signal. A magnetic field sensor includes a Hall effect element coupled to a modulation circuit. The modulation circuit provides a signal to the chopper-stabilized amplifier. The chopper-stabilized amplifier provides an output signal to a low pass filter, which provides an output signal from the magnetic field sensor.

A wireless electric field power transmission system comprises: a transmitter comprising a transmitter antenna, the transmitter antenna comprising at least two conductors defining a volume therebetween; and at least one receiver, wherein the transmitter antenna transfers power wirelessly via electric field coupling when the at least one receiver is within the volume.

An apparatus and a method for a bias modulator using a Zero Current Switching (ZCS) are provided. The bias modulator includes a Pulse Width Modulation (PWM) signal generator for converting an input envelope signal to a PWM signal; a PWM/ZCS converter for calculating the number of ZCS control signals to be provided within an on-time duration of the PWM signal and generating at least one ZCS control signal according to the number of the ZCS control signals; and a ZCS switching regulator for generating a bias current according to the ZCS control signal.

The present disclosure relates to a first active tunable low-noise RF bandpass filter that includes at least a first transistor element and a tunable frequency selective degeneration circuit coupled to a first non-inverting output of the first transistor element. The first active tunable low-noise RF bandpass filter combines low noise amplifier (LNA) and tunable bandpass filter functionalities into a single active RF bandpass filter. The tunable frequency selective degeneration circuit uses degeneration at frequencies outside of a passband of the active RF bandpass filter to increase feedback, thereby decreasing gain of the active RF bandpass filter. By decreasing the gain, linearity of the active RF bandpass filter may be improved in the presence of strong interfering RF signals, thereby enabling elimination of passive bandpass filter elements, such as surface acoustic wave (SAW) and bulk acoustic wave (BAW) filters, without degrading reception of in-band RF signals.

A power supply system comprises a parallel arrangement of a linear amplifier (LA) and a DC-DC converter (CO). The linear amplifier (LA) has an amplifier output to supply a first current (II) to the load (LO). The DC-DC converter (CO) comprises: a converter output for supplying a second current (12) to the load (LO), a first inductor (L1), and a switch (SC) coupled to the first inductor (L1) for generating a current in the first inductor (L1), and a low-pass filter (FI) arranged between the first inductor (L1) and the load (LO). The low pass filter (FI) comprises a first capacitor (C1; CA) which has a first terminal coupled to the switch (SC) an a second terminal coupled to a reference voltage level (GND), and a second inductor (L2; LC) which has a first terminal coupled to the first inductor (L1) and a second terminal coupled to the load (LO). The low-pass filter further comprises, either: (i) a series arrangement of a second capacitor (C2) and a damping resistor (R2), which series arrangement is arranged in parallel with the first capacitor (C1), or (ii) a parallel arrangement of a third capacitor (CB) and a damping resistor (RB) arranged in series with the first capacitor (CA), or (iii) a series arrangement of a third inductor (L3) and a damping resistor (R3), which series arrangement is arranged in parallel with the second inductor (L2), or (iv) a parallel arrangement of a fourth inductor (LD) and a damping resistor (RD), which parallel arrangement is arranged in series with the second inductor (LC).

Electronic devices may be provided that include mechanical and electronic components. Connectors may be used to interconnect printed circuits and devices mounted to printed circuits. Printed circuits may include rigid printed circuit boards and flexible printed circuit boards. Heat sinks and other thermally conductive structures may be used to remove excess component heat. Structures may also be provided in an electronic device to detect moisture. Integrated circuits and other circuitry may be mounted on a printed circuit board under a radio-frequency shielding can.

A highly efficient class-G amplifier includes an amplifier circuit coupled between a positive power rail and a negative power rail to amplify an audio input signal of the class-G amplifier, and a boost inverting power converter to convert a supply voltage to a positive rail voltage and a negative rail voltage on the positive and negative power rails. The boost inverting power converter includes a boost inverting power stage coupled to the positive and negative power rails, and a controller to switch the boost inverting power stage between a boost mode and an inverting mode. An audio level detector detects the audio input signal for the controller to adjust the positive and negative rail voltages. The class-G amplifier has higher efficiency and requires lower cost because it does not need a charge pump.

A high-definition multimedia interface (HDMI) receiver recovers high speed encoded data which are transmitted differentially over data channels of a lossy cable, along with a clock. Inter symbol interference, high-frequency loss, skew between the clock and data channels, and differential skew within a differential signal are compensated by analog circuits which are automatically tuned for best performance by observing the quality of the recovered analog signal. Oversampling is used to provide a 24-bit digital representation of the analog signal for determining the quality of the signal. A corresponding method of deskewing a differential signal and a system and circuit therefor are also provided.

A Switch Node Assisted Linear architecture, including a linear amplifier in parallel with a switched converter, is configurable in two tracking modes: (a) a SMAL regulator in which the amplifier sets toad voltage with an envelope tracking bandwidth, and the switched converter is configured for current assist, and (b) a Switched Mode Power Supply configuration in which the amplifier is switch-decoupled, and the switcher circuit is switched configured with an output capacitor, operable as an SMPS providing load voltage with an adaptive tracking bandwidth that is less than the envelope tracking bandwidth. Staged switching effects substantially seamless transitions between tracking modes, with the amplifier holding the load voltage at a substantially constant envelope tracking voltage (CVET): (a) for ET-AT transitions, the CVET mode enables pre-charging the output capacitor to a target AT voltage, prior to switch-decoupling the amplifier; and (b) for AT-ET transitions, CVET mode enables discharging the output capacitor.

A pulse-width modulation (PWM) amplifier is adapted to a class-D amplifier in which an analog input signal is subjected to integration, pulse-width modulation, and switched amplification, wherein a glitch elimination circuit eliminates noise from a pulse-width modulated signal, from which a high pulse signal and a low pulse signal are isolated such that each pulse is delayed by a dead time at the leading-edge timing thereof. When both of them are simultaneously set to a high level, one of them is reduced in level. In response to the occurrence of clipping, an integration constant applied to an operational amplifier is automatically changed from a primary integration constant to a secondary integration constant. When the clipped state is sustained for a prescribed time, an inversion pulse is compulsorily introduced into the pulse-width modulated signal.