1027 results about "Linear regulator" patented technology

A light-emitting diode (LED) driver is adapted to control either the magnitude of the current conducted through a LED light source or the magnitude of a voltage generated across the LED light source. The LED driver comprises a power converter circuit for generating a DC bus voltage, and an LED drive circuit for receiving the bus voltage and adjusting the magnitude of the current conducted through the LED light source. The LED driver is operable to dim the LED light source using either a pulse-width modulation technique or a constant current reduction technique. The LED drive circuit may comprise a controllable-impedance circuit, such as a linear regulator. The LED driver may be operable to control the magnitude of the bus voltage to optimize the efficiency and reduce the power dissipation in the LED drive circuit, as well ensuring that the load voltage and current do not have any ripple.

A light-emitting diode (LED) driver according to the present invention consists of a voltage pre-regulator and multiple linear current regulators with an adaptively-controlled drive voltage. In this LED driver, the efficiency maximization is achieved by eliminating the sensing of the voltage drops across the linear regulators, i.e., by removing the external voltage feedback for the adjustment of the output voltage of the pre-regulator. In the LED driver of the present invention, the self-adjustment of drive voltage is achieved by relying on a relatively strong dependence between the gate-to-source and drain-to-source voltages of a current-regulating transistor, e.g., a MOSFET, operating in the linear region. The driver powers all LEDs in a string with a constant current and provides consistent illumination and optimum operating efficiency at low cost over a wide range of input / output voltage and temperature.

High-efficiency envelope tracking (ET) methods and apparatus for dynamically controlling power supplied to radio frequency power amplifiers (RFPAs). An exemplary ET circuit includes a switch-mode converter coupled in parallel with a split-path linear regulator. The switch-mode converter is configured to generally track an input envelope signal Venv and supply the current needs of a load (e.g., an RFPA). The split-path linear regulator compensates for inaccurate envelope tracking by sourcing or sinking current to the load via a main current path. A current sense path connected in parallel with the main current path includes a current sense resistor used by a hysteresis comparator to control the switching of the switch-mode converter. The split-path linear regulator is configured so that current flowing in the current sense path is a lower, scaled version of the current flowing in the main current path.

A Switch Node Assisted Linear architecture, including a linear amplifier in parallel with a switched converter, is configurable in two tracking modes: (a) a SMAL regulator in which the amplifier sets toad voltage with an envelope tracking bandwidth, and the switched converter is configured for current assist, and (b) a Switched Mode Power Supply configuration in which the amplifier is switch-decoupled, and the switcher circuit is switched configured with an output capacitor, operable as an SMPS providing load voltage with an adaptive tracking bandwidth that is less than the envelope tracking bandwidth. Staged switching effects substantially seamless transitions between tracking modes, with the amplifier holding the load voltage at a substantially constant envelope tracking voltage (CVET): (a) for ET-AT transitions, the CVET mode enables pre-charging the output capacitor to a target AT voltage, prior to switch-decoupling the amplifier; and (b) for AT-ET transitions, CVET mode enables discharging the output capacitor.

A charging system that concurrently charges a main system and a battery for powering the main system when the charging system is connected to an adapter. The charging system includes a current sensing resistor, a first current control circuit for regulating the current in a linear battery charger and a second current control circuit for controlling the maximum adapter current. The charging system further includes a first temperature control circuit for regulating the current in the battery charger and a second temperature control circuit for controlling the maximum power dissipation of the charging system. The charging system further includes a linear regulator for providing power to the main system from the adapter and a main system voltage control circuit and a battery voltage control circuit. The charging system apportions the adapter current between the main system and the battery charger giving priority to the main system.

A linear regulator and a current sensing circuit are provided. The linear regulator comprises a pass transistor, a compensation capacitor, a variable resistor, an error amplifier and a current sensing circuit comprising a sense transistor controlled by the error amplifier and a voltage follower coupled with the second terminal of the pass transistor and the second terminal of the sense transistor. The sense transistor receives an input voltage, and generates a sense current proportional to a pass current. The voltage follower controls the voltage at the second terminal of the sense transistor to be the same as that at the second terminal of the pass transistor, and adjusts the resistance of the variable resistor according to the voltages at the second terminal of the pass transistor, the voltage at the second terminal of the sense transistor, and the sense current flowing through the sense transistor.

The present invention discloses an LDO (Low DropOut) linear voltage regulator, which is based on an NMC (Nested Miller Compensation) architecture and can be capacitor-free, wherein an active resistor is added to the feedback path of the Miller compensation capacitor to increase the controllability of the damping factor, solve the problem of extensively using the output capacitor with a parasitic resistance, and solve the problem that a compromise must be made between the damping factor control and the system loop gain. Further, the present invention utilizes a capacitor-sharing technique to reduce the Miller capacitance required by the entire system and accelerate the stabilization of output voltage without influencing stability.

The invention discloses a low-dropout (LDO) linear regulator of an integrated slew rate enhancing circuit. The LDO linear regulator comprises a power regulating tube, a first amplifier, a second amplifier, a buffering drive circuit and a compensation capacitor, and is characterized by further comprising a slew rate enhancing circuit, wherein the input end of the slew rate enhancing circuit is connected with the output of the linear regulator; and the output end of the slew rate enhancing circuit is connected with the grid of the power regulating tube. Due to the adoption of a slew rate enhancing technology in the linear regulator, transient regulation of grid driving of the power regulating tube is realized according to the situation of output end VOUT under the condition of ensuring low quiescent current, and the voltage slew rate of the grid of the power regulating tube and the bandwidth of the LDO are increased remarkably; and meanwhile, an adaptive biasing technology is adopted, so that the common-mode input voltage range of the amplifier is enlarged, transient response of an LDO circuit is enhanced greatly, and the output accuracy of the LDO is increased simultaneously.

A current limiting circuit for a linear regulator includes an output stage transistor and a replica transistor, which have gates coupled to receive an output voltage from a linear amplifier and sources coupled to load circuitry. A drain of the output stage transistor is coupled to a VDD supply terminal, while a drain of the replica transistor is coupled to the VDD supply terminal through a first resistor. The output stage transistor and replica transistor are operated in saturation, such that proportional currents flow through these transistors. The voltage drop across the first resistor provides a first voltage, which is applied to a second amplifier. A reference voltage is also applied to the second amplifier. When the first voltage becomes less than the reference voltage, a feedback transistor is enabled to pull down the output voltage of the linear amplifier, thereby limiting the output current supplied to the load circuitry.

The disclosed switched mode assisted linear (SMAL) amplifier / regulator architecture may be configured as a SMAL regulator to supply power to a dynamic load, such as an RF power amplifier. Embodiments of a SMAL regulator include configurations in which a linear amplifier and a switched mode converter (switcher) parallel coupled at a supply node, and configured such that the amplifier sets load voltage, while the amplifier and the switched mode converter are cooperatively controlled to supply load current. In one embodiment, the linear amplifier is AC coupled to the supply node, and the switched converter is configured with a capacitive charge control loop that controls the switched converter to effectively control the amplifier to provide capacitive charge control. In another embodiment, the amplifier includes separate feedback loops: an external relatively lower speed feedback loop may be configured for controlling signal path bandwidth, and an internal relatively higher speed feedback loop may be configured for controlling output impedance bandwidth of the linear amplifier.

A spread spectrum system having a self-oscillating delay-line digital pulse width modulator and a method for mitigating electromagnetic interference. The spread spectrum system has a pseudo-random pattern generator connected to a digital-to-analog converter, which in turn is connected to a linear regulator. The linear regulator receives a reference voltage from the digital-to-analog converter and creates a frequency varying voltage that serves as an input voltage for delay elements of a delay-line based digital pulse width modulator. In response to frequency varying input signal, the delay-line based digital pulse width modulator generates a frequency varying voltage that is input to a switching network to vary its switching frequency.

The invention discloses a circuit for controlling light sources, method and display system. The circuit for controlling light sources comprises a converter, a feedback circuit and a current distribution controller. The converter is operable for converting an input voltage to an output current and for providing the output current to the light sources. The feedback circuit is coupled to the light sources for generating feedback signals indicative of currents flowing through the light sources respectively. The current distribution controller is coupled to the feedback circuit for generating control signals based on the feedback signals respectively so as to regulate the currents of the light sources respectively, and for controlling the converter to regulate the output current based on the feedback signals. The circuit for controlling light sources without a plurality of linear regulators or switch controllers and switch regulators reduces the circuit cost, increases the circuit efficiency and reduces the circuit complexity.

Embodiments of a power-regulator circuit having two operating modes are described. This power-regulator circuit includes control logic that is configured to select a given operating mode based on a load condition of the power-regulator circuit. During a first operating mode, the control logic provides a first signal that operates the power-regulator circuit as a linear regulator. Moreover, during a second operating mode, the control logic provides a second signal and a third signal that operate the power-regulator circuit as a switch-mode regulator.

The invention discloses a dynamic compensation circuit with ultra-low power consumption and a linear regulator with the same. The dynamic compensation circuit comprises a dynamic compensation module, a current output detection module and a control module. In the linear regulator applied with the dynamic compensation circuit with ultra-low power consumption, the dynamic compensation circuit with ultra-low power consumption is connected between the output end of an error amplifier and the output end of the linear regulator. The dynamic compensation circuit with ultra-low power consumption and a linear regulator with the same of the invention have very simple structures and practicality, can effectively ensure the stable work under the application condition of a variety of output load. The dynamic compensation circuit only has ultra-low power consumption less than 1mu A, and reduces the cost of production and application of chips due to the small occupied chip area. The dynamic compensation circuit with ultra-low power consumption and the linear regulator with the same of the invention are widely applicable to power management application process.

The present invention discloses a linear regulator and a voltage regulation method. The method comprises: providing a power transistor for converting a supply voltage to an output voltage to a load according to the conduction condition of the power transistor; controlling the conduction condition of the power transistor according to a comparison between a feedback signal relating to the output voltage and a reference voltage; obtaining a signal relating to a load condition; and controlling the conduction capability of the power transistor according to the signal relating to the load condition.

The invention discloses a low dropout linear regulator. Aiming at the problem of complicated structure of the existing low-dropout linear regulator, the LDO of the present invention includes an error amplifier, a feedback sampling network, a bias circuit and a slew rate enhancement circuit, and is characterized in that a part of the slew rate enhancement circuit is included in the error amplifier Among them, the error amplifier includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; wherein the first NMOS transistor and the second NMOS transistor serve as slew rate enhancement As a component of the circuit, the slew rate enhancing circuit further includes a first capacitor and a second capacitor. The voltage stabilizer of the present invention constitutes a slew rate enhancement circuit through two NMOS transistors and two capacitors, does not require too many additional auxiliary circuits, has a simple structure and low power consumption, and can be applied without reducing performance. Under low voltage, it has extremely fast transient response.

Disclosed are a low dropout linear regulator and a pole adjustment method thereof. A source electrode of a p-channel metal oxide semiconductor (PMOS) adjustment transistor of the low dropout linear regulator is connected with a first voltage end, a drain electrode of the PMOS adjustment transistor is connected with a first end of a first resistor, a grid electrode of the PMOS adjustment transistor is connected with an output end of an error amplifier, a first electric current supply unit is suitable for generating reference current, a second electric current supply unit is suitable for generating regulating current, the regulating current is relevant to the electric current of an output end of the low dropout linear regulator, a first input end of the error amplifier inputs reference voltage, a second input end of the error amplifier is connected with a second end of the first resistor and a first end of a second resistor, a bias current input end inputs bias current generated by superposition of the reference current and the regulating current, the first end of the first resistor serves as the output end of the low dropout linear regulator, a second end of the second resistor is connected with a second voltage end, and the voltage value of the first voltage end is larger than that of the second voltage end.

This invention relates to a circuit for speeding up the stabilized low voltage difference linear regulator output voltage based on a circuit composed of an output tube, an error amplifier, a primary standard voltage source, a resistor bleeder network and a load including reference voltage output by said primary voltage source and a feed back voltage output by the network characterizing that said resistor bleeder network is composed of four serial bleeder resistors used in providing three feed back voltages, namely, a first feed back voltage, a second voltage and a third feed back voltage, which utilizes the instant controlled current to speed up the discharge to the grating capacitance of the MPX and the discharge of the output capacitor so as to improve the instant response of LDO greatly.

An LDO regulator system has first and second current mirror circuits connected to its output terminal. A load attached to the output terminal is supplied with a constant voltage. Variations in the load that cause variations in the magnitude of the output voltage trigger one of the first or second current mirror circuits to generate a current that varies the magnitude of a gate voltage of a pass-transistor. The variation in the gate voltage in turns varies the drain current of the pass-transistor, which varies the output voltage to counter the change in the magnitude of the output voltage. Using the first and second current mirror circuits avoids the need for a large load capacitor and very high bandwidth of a conventional LDO regulator.

The invention discloses a filling in / pulling out current rapid response linear voltage regulator and a regulating method. The regulator comprises a reference voltage source, two error amplifiers, an N-channel MOS (Metal Oxide Semiconductor) tube I, an N-channel MOS tube II and a static current control unit. The static current control unit consists of a current summing unit, a pulling out current subtracting unit and a filling-in current subtracting unit. In the voltage regulating method, two error amplifiers dynamically monitor the voltage variation of a source electrode of the N-channel MOS tube I and a drain electrode of the N-channel MOS tube II when the pulling-out and filling-in current occur and dynamically control the gate-to-source voltage of two N-channel MOS tubes so that the source voltage of the N-channel MOS tube I and the drain voltage of the N-channel MOS tube II vary toward the same direction. The invention has novel and reasonable design, convenient circuit connection, small area of circular bard and good use effect, ensures the large-load stability and greatly improves the transient response of an LDO (Low Dropout Regulator).

A multimode voltage regulator circuit includes a linear regulator sub-circuit configured to supply current to a load in a low-current mode, responsive to a first control signal from a first control path, as well as a switching regulator sub-circuit configured to supply current to the load in a high-current mode, responsive to a second control signal from a second control path. The circuit further comprises a shared error amplifier configured to generate an error signal based on the difference between a reference voltage and a feedback signal coupled from the load, and a switch configured to selectively route the error signal to the first control path in the low-current mode and to the second control path in the high-current mode.

The invention relates to a low dropout linear voltage regulator (LDO) without an off-chip capacitor for improving transient response and increasing power supply rejection ratio (PSRR). The LDO without the off-chip capacitor comprises an error amplifier, a reference voltage source module, a power adjusting tube, an NMC Miller's compensating circuit, a PSRR enhanced network and a transient response intensifier circuit. According to the LDO without the off-chip capacitor, the NMC compensation technique is used for meeting the system stability requirement; a second-stage gm improved circuit of the amplifier is used for increasing the charging and discharging currents to the grid of the power tube; a slew rate intensifier circuit is introduced, needed currents can be provided for a load when the load of the LDO is subjected to step hopping from small to large, and thus the transient response capacity of the LDO is improved under the double actions. In addition, the PSRR enhanced network is additionally arranged to be used for controlling the PSRR feedback factors beta of the system, an original zero point is pushed to the position with higher frequency, and therefore the PSRR characteristic of the system is improved. The LDO without the off-chip capacitor is improved on the aspect of transient response and the aspect of PSRR.