36results about "Amplifiers with impedence circuits" patented technology

An apparatus, including: a first amplifier including: a flipped voltage follower, and a source follower coupled in parallel with the flipped voltage follower; and a load coupled to an output of the first amplifier.

This invention provides a voltage generation circuit that can rapidly stabilize the output voltage while reducing noise, even when generating the output voltage using a capacitor. [Solution] The voltage generation circuit comprises a voltage input terminal to which an input voltage is input, a voltage output terminal to which an output voltage is output, a first resistor having a first terminal and a second terminal, the first terminal being electrically connected to the voltage input terminal and the second electrical terminal being electrically connected to the voltage output terminal, a second resistor having a third terminal and a fourth terminal, the third terminal being electrically connected to the second terminal, a first capacitor electrically connected to one of the first terminal and the second terminal, and a first circuit including a charging circuit electrically connected to one of the first terminal and the second terminal for charging the first capacitor.

A method of envelope detection operates by receiving a RF (radio frequency) signal having a first voltage at a first node and a second voltage at a second node; using a common-mode source-follower (CMSF) having a first source follower and a second source follower connected in parallel and configured to receive the first voltage and the second voltage, respectively, and jointly output a first current to a third node in accordance with a sum of a second current and a third current received via a fourth node; establishing a first negative feedback control loop by converting the first current into the third current using a current-controlled current source (CCCS); and establishing a second negative feedback control loop by converting a drain voltage at the third node into the second current using a voltage-controlled current source (VCCS).

A source follower circuit (100) includes a first MOS transistor (M1), a second MOS transistor (M2), a third MOS transistor (M3), and a feedback loop circuit (104). Regarding the first MOS transistor (M1), a gate terminal receives an input signal (VIN), and a source terminal outputs an output signal (VOUT). Regarding the second MOS transistor (M2), a gate terminal is coupled to a bias voltage (VB), a source terminal is coupled to a first reference voltage (VDD), and a drain terminal is coupled to the source terminal of the first MOS transistor (M1). Regarding the third MOS transistor (M3), it is a self-biased diode-connected MOS transistor. The drain terminal of the third MOS transistor (M3) is coupled to a drain terminal of the first MOS transistor (M1), and a source terminal of the third MOS transistor (M3) is coupled to a second reference voltage (GND).

An amplifier circuit 101 includes: a first current source circuit 113 configured to output a predetermined current amount to a first interconnect L1; a voltage amplifier circuit 110 configured to amplify a voltage of an input signal; a first level shift circuit 111 connected between the first interconnect L1 and an output of the voltage amplifier circuit 110 and configured to shift a voltage of a signal output from the voltage amplifier circuit 110; a first voltage follower 117 connected to the first interconnect L1 and configured to amplify a signal in the first interconnect L1; and a first capacitor 210 connected between the first interconnect L1 and the output of the voltage amplifier circuit 110.

A transimpedance amplifier system (TIA) for stabilizing high gain and high frequency signals while minimizing parasitic capacitance effects on the transimpedance amplifier system. The TIA includes an operational amplifier having a first input terminal, a second input terminal, and an output terminal. The TIA also includes a signal generating device operatively connected with the first input terminal of the operational amplifier. The TIA also includes a T-network feedback architecture operatively connected with the operational amplifier at the first input terminal of the operational amplifier and the output terminal of the operational amplifier. The T-network feedback architecture has a first impedance network and a second impedance network. The T-network feedback architecture is configured to suppress parasitic capacitance from the transimpedance amplifier system.

An apparatus, including: a flipped voltage follower (FVF) including a first pchannel field effect transistor (PFET), a second PFET, and a first current source coupled in series between an upper voltage rail and a lower voltage rail; and a bias voltage control circuit coupled to a node between the second PFET and the first current source.

A bias circuit includes a first transistor and a second transistor configured as a first current mirror. A first current source is arranged between a supply node and the first transistor first terminal. A bias circuit output is coupled to the second transistor second terminal. A second current mirror is coupled to the first current mirror and the bias circuit output. A second current source is arranged between the supply node and the second current mirror. A third transistor in a diode-connected configuration is coupled between the first transistor second terminal and a ground. Alternatively or in addition, the bias circuit includes a first variable capacitor coupled between the second transistor first terminal and the second transistor second terminal. A fourth transistor has a control terminal coupled to the supply node, a first terminal coupled to the supply node and a second terminal coupled to the second transistor first terminal.

In an example, a circuit includes a first field-effect transistor (FET) having a gate and first and second terminals. The circuit includes a second FET having a gate and first and second terminals, the second terminals of the first and second FETs coupled together. The circuit includes a first boosted follower coupled to the gate of the first FET and includes a second boosted follower coupled to the gate of the second FET. A third FET is coupled to the first boosted follower and the second voltage terminal and configured to turn off the first boosted follower responsive to a first level of an output voltage. A fourth FET is coupled to the second boosted follower and the first voltage terminal and configured to turn off the second boosted follower responsive to a second level of the output voltage.

A voltage generating circuit comprises a voltage input terminal to which an input voltage is applied, a voltage output terminal from which an output voltage is output, a first resistor having a first terminal electrically connected to the voltage input terminal and a second terminal electrically connected to the voltage output terminal, a second resistor having a third terminal electrically connected to the second terminal and a fourth terminal, a first capacitor electrically connected to the first terminal or the second terminal, and a first circuit electrically connected to the first terminal or the second terminal comprising a charging circuit configured to charge the first capacitor.

A microphone includes a MEMS device having an output node for generating an analog voltage in response to an input sound wave or vibration; a source follower having a control node coupled to the output node of the MEMS device, a current path coupled between a first controlled node and a second controlled node, and a bulk node, wherein the first controlled node is configured for providing a microphone output voltage, and wherein the second controlled node is coupled to a reference voltage; a current source coupled to the first controlled node; and a voltage differential between the first controlled node and the bulk node, wherein a nonzero value of the voltage differential is configured such that a first 1% total harmonic distortion (THD) cross-point of the microphone output voltage is greater than a second 1% THD cross-point of the microphone output voltage using a zero value voltage differential.

Stacked amplifier architectures that have bias circuits that are tolerant of supply voltage variations, which provide good reliability, are fast to follow Vcc changes, and exhibit small variations in gain as Vcc varies. One embodiment encompasses a bias circuit (500) for an amplifier stack (102), including a source follower circuit configured to output a bias voltage to a transistor within the amplifier stack (102) and configured to be coupled to a variable voltage (Vcc), and a controller coupled to the source follower circuit, configured to be coupled to a constant voltage, and configured to apply a constant voltage to the source follower circuit. The source follower circuit generates a reference voltage and outputs a constant bias voltage when the variable voltage (Vcc) is above the reference voltage, and outputs a bias voltage proportional to the variable voltage (Vcc) when the variable voltage (Vcc) is below the reference voltage.

A method and a device for generating charged particle waves, used to solve problems in existing methods and devices for generating charged particle waves such as being unable to control time phase, intensity, low spatial distribution density or low spatial coverage of charged particle waves. The method comprises the following steps: on the basis of waveform information pre-stored in a waveform storage module, generating a corresponding digital waveform signal; the waveform information comprises amplitude and time phase; on the basis of a digital-to-analog conversion module connected to the waveform storage module, converting the digital waveform signal with a pre-set time phase into an analog waveform signal; on the basis of a power amplification connected to the digital-to-analog conversion module, performing power amplification on the analog waveform signal; on the basis of a high-voltage generator connected to the power amplification module, performing high-voltage amplification on the power signal of the analog waveform signal; and by means of a quasi-continuous emission electrode connected to the high-voltage generator, emitting a particle wave on the basis of the analog waveform voltage signal.

A push-pull source follower circuit (100) includes a main source follower (102), a first biasing circuit (104), and a second biasing circuit (106). The main source follower (102) includes a first transistor and a second transistor between a first power rail and a second power rail, where the first transistor and the second transistor include an N-type transistor and a P-type transistor. The first biasing circuit (104) programs a bias current of the main source follower (102) through generating a first bias voltage of the first transistor. The second biasing circuit (106) programs an output mean voltage of the push-pull source follower circuit (100) through generating a second bias voltage of the second transistor. The bias current and the output mean voltage are programmed independently.

In the amplifier circuit, the rising settling time and the falling settling time are kept short. The amplifier circuit includes a first transistor of a first conductivity type having a first control terminal; a second transistor of a second conductivity type different from the first conductivity type, the second transistor having a second control terminal connected to an input terminal and a fourth current terminal connected to the first control terminal; a third transistor; and a fourth transistor of a fourth conductivity type different from the first conductivity type, the fourth transistor having a fourth control terminal connected to the first control terminal at an equal potential, and a seventh current terminal connected to a third fixed potential.

A high-frequency amplifier has a first transistor and a second transistor, a first drain pad connected to the first transistor and a second drain pad connected to the second transistor, a matching circuit pattern having a first transmission line connected to the first drain pad and a second transmission line connected to the second drain pad, a first lead and a second lead, and a wiring pattern connected to the first drain pad via the first transmission line and the first lead and connected to the second drain pad via the second transmission line and the second lead. An effective impedance of the second lead is larger than an effective impedance of the first lead. The matching circuit pattern has an asymmetric outer shape. An electrical length of the second transmission line is shorter than an electrical length of the first transmission line.

In this disclosure, new structures for high-performance voltage buffers (source followers and emitter followers) are described. The structures achieve high performance (linearity) and reduce power consumption. In addition, they are reconfigurable (sw_cap_gnd, sw_cap_ff, sw_act, sw_noact) to optimize the performance and power consumption depending on the input frequency range.

The present invention relates to an electronic system (1) comprising: • a plurality of sub blocks, each one being required to be supplied with a different power supply output voltage (VDD1, VDD2,..), • a differential amplifier (3) having a plurality of outputs, an input reference voltage (VRF) being applied to a first input of the amplifier, • a voltage regulation loop with transistor feedback connected to a first output of the amplifier and to a second input of the amplifier, said loop comprising a first transistor (40) and a variable resistor (5), • a plurality of additional transistors (41, 42,...), each output of the amplifier being connected to a gate or base of one of said additional transistors and the drain, source, emitter or collector of each additional transistor being connected to one of said sub-blocks, wherein: • the input reference voltage (VRF) and the variable resistor are configured such that a first sub block is supplied with its required power supply output voltage (VDD1) by the transistor it is connected to, • and said amplifier is configured to output on each of its outputs a power supply reference voltage (VG1, VG2...) such that each sub block other than the first sub block is supplied with its required power supply output voltage (VDD2...) by the transistor it is connected to.

A multi-stage device (200-1) includes multiple stages such as a first stage (221-1) and a second stage (222-1). During operation, the first stage (221-1) receives an input signal and outputs an intermediate signal based on the input signal. The second stage (222-1) is coupled to the first stage to receive the intermediate signal and produce an output signal. According to one configuration, the second stage (222-1) includes a transistor (228) and a circuit path between the first stage (221-1) and the transistor (228). The transistor component (228) is controlled to derive the output signal from the intermediate signal inputted to the circuit path.

An apparatus includes a transimpedance amplifier (102) having at least one input and an output. An output voltage level shift circuit (204) is connected to the output of the transimpedance amplifier (104). The output voltage level shift circuit (204) is configured to generate a level-shifted output voltage, where the level-shifted output voltage is adaptive responsive to a reference output voltage.

The invention relates to an amplifier circuit (1) for broadband and low-noise amplification of a capacitive current source, preferably of a pyroelectric sensor, comprising a signal input (3), which can be connected to the capacitive current source in a node K1; an input stage (A1), wherein the input stage (A1) is connected to the node K1 at an input (7) of the input stage (A1) and has a node K2 at the output (9) of the input stage (A1), wherein the input stage (A1) is configured to amplify an input voltage at least 3-fold, wherein the input stage (A1) is configured to provide a high-ohm input resistance at the input of the input stage (A1), wherein the input stage (A1) is configured to provide a stable and load-independent voltage at the output of the input stage (A1); an amplifier cascade, wherein the amplifier cascade (11) has at least one first and one second amplifier (A2, A3), each with an input (13, 17) and an output (15, 19), wherein the output (19) of the first amplifier (A2) is connected to the input (17) of the second amplifier (A3) in a node K3, wherein the input (13) of the first amplifier (A2) is connected to the node K2, wherein the output (19) of the second amplifier (A3) is connected to a node K4, wherein the amplifier cascade (11) is configured to generate a high signal amplification with a low phase rotation over a wide frequency range; a feedback network (F1), wherein the feedback network (F1) is connected to the input (7) of the input stage (A1) in the node K1 and the output (19) of the second amplifier (A3) in the node K4, wherein the feedback network (F1) is configured to provide a high-ohm feedback resistor with a parasitic capacitance of less than 0.5 pF, wherein the feedback network (F1) is configured to provide a negative feedback to an assembly comprising the input stage (A1) and the amplifier cascade (11); and a signal output (21), which is connected to a node K5, wherein the node K5 is connected to the node K4 or corresponds to the node K4. The invention also relates to a sensor system.

An amplifier circuit including a first stage, second stage and output stage. The first stage includes a cathode biased triode. The amplifier circuit includes a second stage having two long tailed pair triodes, each of the second stage tubes output signals inverted from each other wherein the long-tailed pair triodes are direct current coupled to the output tube's grids, Each cathode biased triode section is direct current coupled to one of the two long tailed pair triodes. The output stage includes two output tubes are in a Circlotron configuration with each output tube's cathode connected to the loudspeaker terminals. Each Bluetooth receiver's ground is connected to the ground of the first stage and the output of each Bluetooth is connected to the grid of the first stage.

An envelope tracking (ET) integrated circuit (ETIC) operable across wide modulation bandwidth is disclosed. The ETIC includes at least two auxiliary voltage outputs coupled to a high-bandwidth power amplifier circuit that has a lower equivalent capacitance, and thus a higher impedance resonance frequency. The ETIC also includes a pair of ET voltage circuits configured to generate a pair of ET voltages, respectively. To help mitigate potential distortion in the ET voltages, a control circuit is configured to couple the ET voltage circuits exclusively to the auxiliary voltage outputs when the ETIC needs to operate with a high modulation bandwidth (e.g., ≥200 MHz). Given the higher impedance resonance frequency of the high-bandwidth power amplifier circuit, it is possible to increase separation between an energy spectrum of a voltage disturbance and an energy spectrum of the high modulation bandwidth, thus helping to reduce the potential distortion in the ET voltages.

A bias circuit for a RF amplifier is described. The bias circuit includes a first transistor and a second transistor configured as a first current mirror. A first current source is arranged between a supply node and the first transistor first terminal. An output of the bias circuit is coupled to the second transistor second terminal. A second current mirror coupled to the first current mirror and the bias circuit output. The bias circuit includes a first resistor coupled between a first transistor control terminal and a second transistor control terminal and a variable capacitor coupled between the second transistor control terminal and a ground.