76results about "Amplifiers with impedence circuits" patented technology

The invention relates to an amplifier circuit (1) for broadband and low-noise amplification of a capacitive current source, preferably a thermoelectric sensor, comprising: a signal input (3) which can be connected to the capacitive current source in a node K1; the invention relates to an amplifier (1) for amplifying an input voltage, comprising an input stage (A1), which is connected to a node K1 at an input (7) of the input stage (A1) and has a node K2 at an output (9) of the input stage (A1), the input stage (A1) being designed to amplify the input voltage by at least three times, the input stage (A1) being designed to provide a high-ohm input resistance at the input of the input stage (A1), the input stage (A1) is designed to provide a stable and load-independent voltage at the output of the input stage (A1); the invention relates to a power amplifier comprising a first amplifier (A1) and a second amplifier (A3), an amplifier cascade (11) having at least a first amplifier and a second amplifier (A2, A3), each having an input (13, 17) and an output (15, 19), the output (15) of the first amplifier (A2) being connected in a node K3 to the input (17) of the second amplifier (A3), the input (13) of the first amplifier (A2) being connected to a node K2, the output (15, 19) being connected in a node K3 to the input (17) of the second amplifier (A3). An output (19) of the second amplifier (A3) is connected to a node K4, the amplifier cascade (11) being arranged to produce a high signal gain with a low phase shift over a wide frequency range; a feedback network (F1), which is connected to the input (7) of the input stage (A1) in a node K1 and to the output (19) of the second amplifier (A3) in a node K4, said feedback network (F1) being designed to provide a high-ohm feedback resistance with a parasitic capacitance of less than 0.5 pF, the feedback network (F1) is arranged to provide a negative feedback to a structure comprising the input stage (A1) and the amplifier cascade (11), and a signal output (21) connected to a node K5, which is connected to or corresponds to a node K4. The invention also relates to a sensor system.

Device with a microelectromechanical system (MEMS) comprising the following: a first record (101), a second plate (105) which is arranged above the first plate (101), a first movable plate (102) arranged between the first plate (101) and the second plate (105), and a second movable plate (103) arranged between the first movable plate (102) and the second plate (105), the MEMS device comprising a first input / output node coupled to the first plate (101), a second input / output node coupled to the second plate (105), a third input / output node coupled to the first movable plate (102), and a fourth input / output node coupled to the second movable plate (103), wherein the first input / output node is different from the second input / output node, and wherein the third input / output node is different from the fourth input / output node, wherein the first movable plate (102) is rigidly coupled to the second movable plate (103), wherein the first movable plate (102) is designedto be shielded from capacitive coupling with the second movable plate (103).

An RF transistor amplifier circuit comprises a Group III nitride based RF transistor amplifier having a gate terminal, a Group III nitride based self-bias circuit that includes a first Group III nitride based depletion mode high electron mobility transistor, the Group III nitride based self-bias circuit configured to generate a bias voltage, and a Group III nitride based depletion mode differential amplifier that is configured to generate an inverted bias voltage from the bias voltage and to apply the inverted bias voltage to the gate terminal of the Group III nitride based RF transistor amplifier. The Group III nitride based RF transistor amplifier, the Group III nitride based self-bias circuit and the Group III nitride based depletion mode differential amplifier are all implemented in a single die.

An apparatus, including: a first amplifier including: a flipped voltage follower, and a source follower coupled in parallel with the flipped voltage follower; and a load coupled to an output of the first amplifier.

This invention provides a voltage generation circuit that can rapidly stabilize the output voltage while reducing noise, even when generating the output voltage using a capacitor. [Solution] The voltage generation circuit comprises a voltage input terminal to which an input voltage is input, a voltage output terminal to which an output voltage is output, a first resistor having a first terminal and a second terminal, the first terminal being electrically connected to the voltage input terminal and the second electrical terminal being electrically connected to the voltage output terminal, a second resistor having a third terminal and a fourth terminal, the third terminal being electrically connected to the second terminal, a first capacitor electrically connected to one of the first terminal and the second terminal, and a first circuit including a charging circuit electrically connected to one of the first terminal and the second terminal for charging the first capacitor.

Examples relate to a buffered flipped voltage follower circuit arrangement, low dropout voltage regulators, a capacitive digital-to-analog converter, a transceiver for wireless communication, a mobile communication device, a base station transceiver, and to a method for forming a buffered flipped voltage follower circuit arrangement. The buffered flipped voltage follower circuit arrangement comprises a first transistor (MP) comprising a first terminal, a second terminal, and a gate terminal. The buffered flipped voltage follower circuit arrangement comprises a second transistor (MC) comprising a first terminal, a second terminal and a gate terminal. The buffered flipped voltage follower circuit arrangement comprises a buffer circuit comprising an input terminal and an output terminal. The buffered flipped voltage follower circuit arrangement a feed-forward compensation circuit (−gmf) comprising an input terminal and an output terminal. The first terminal of the first transistor (MP) is coupled to a supply voltage of the flipped voltage follower circuit. The second terminal of the first transistor (MP) is coupled with the first terminal of the second transistor (MC) and with an output voltage terminal of the buffered flipped voltage follower circuit arrangement. The second terminal of the second transistor (MC) is coupled with the input terminal of the buffer circuit and with the output terminal of the feed-forward compensation circuit (−gmf). The gate terminal of the first transistor (MP) is coupled with the output terminal of the buffer circuit and with the input terminal of the feed-forward compensation circuit (−gmf).

Polyphase filter circuitry, comprising: an input node configured to receive an input signal VIN having a dominant frequency fPPF; and a common-source amplifier circuit, wherein: the common-source amplifier circuit comprises a field-effect transistor M1 with its gate terminal connected to the input node and with a capacitor CPFF connected to its source terminal; and for the common-source amplifier circuit, the output resistance RM1 seen at the source terminal of the field-effect transistor M1 and the capacitance of the capacitor CPFF are configured to define the frequency response of the common-source amplifier circuit so that, based on the input signal VIN, a signal VLEAD is generated at the drain terminal of the transistor M1 which leads the input signal VIN in phase by a given phase shift ΔφLEAD and a signal VLAG is generated at the source terminal of the transistor M1 which lags the input signal VIN in phase by a given phase shift ΔφLAG.

Amplifier circuit (1) for broadband and low-noise amplification of a capacitive current source, comprising a signal input (3) which can be connected to the capacitive current source in a node K1, an input stage (A1), wherein the input stage (A1) is connected to the node K1 at an input (7) of the input stage (A1) and has a node K2 at the output (9) of the input stage (A1), wherein the input stage (A1) is arranged to amplify an input voltage at least 3 times, wherein the input stage (A1) is arranged to provide a high-impedance input resistor at the input of the input stage (A1), wherein the input stage (A1) is arranged to provide a stable and load-independent voltage at the output of the input stage (A1), an amplifier cascade, wherein the amplifier cascade (11) has at least a first and a second amplifier (A2, A3), each with an input (13, 17) and an output (15, 19), wherein the output (15) of the first amplifier (A2) is connected in a node K3 to the input (17) of the second amplifier (A3), wherein the input (13) of the first amplifier (A2) is connected to the node K2, wherein the output (19) of the second amplifier (A3) is connected to a node K4, wherein the amplifier cascade (11) is arranged to generate a high signal amplification with low phase shift over a wide frequency range, a feedback network (F1), wherein the feedback network (F1) is connected to the input (7) of the input stage (A1) in node K1 and the output (19) of the second amplifier (A3) in node K4, wherein the feedback network (F1) is arranged to provide a high-ohmic feedback resistor with a parasitic capacitance of less than 0.5 pF, wherein the feedback network (F1) is arranged to provide a negative feedback to a structure comprising the input stage (A1) and the amplifier cascade (11), and a signal output (21) connected to a node K5, wherein the node K5 is connected to the node K4 or corresponds to the node K4, wherein the input stage (A1) comprises a junction field effect transistor (Q1) and a bipolar transistor (Q2), wherein a drain terminal of the junction field effect transistor (Q1) is connected to a base terminal of the bipolar transistor, wherein the junction field effect transistor (Q1) is connected as a source circuit, wherein the bipolar transistor (Q2) is connected as an emitter follower, wherein the first and second amplifiers (A2, A3) of the amplifier cascade (11) are operational amplifiers (Q3, Q4), wherein the first operational amplifier (Q3) has a voltage gain of more than 10 4 has, wherein the second operational amplifier (Q4) has a voltage gain of maximum 10 3 has, wherein the feedback network (F1) has a high-ohm feedback resistor with a parallel capacitance, wherein the feedback network (F1) comprises a series-connected low-pass filter.

A method of envelope detection operates by receiving a RF (radio frequency) signal having a first voltage at a first node and a second voltage at a second node; using a common-mode source-follower (CMSF) having a first source follower and a second source follower connected in parallel and configured to receive the first voltage and the second voltage, respectively, and jointly output a first current to a third node in accordance with a sum of a second current and a third current received via a fourth node; establishing a first negative feedback control loop by converting the first current into the third current using a current-controlled current source (CCCS); and establishing a second negative feedback control loop by converting a drain voltage at the third node into the second current using a voltage-controlled current source (VCCS).

In certain aspects, a composite amplifier core, an amplifier structure, and a circuit structure formed thereof are provided. The composite amplifier core includes one or more first basic amplifiers of a first type and one or more second basic amplifiers of a second type. The amplifier structure includes the composite amplifier core. The amplifier structure further includes one or more coupling networks including at least one of an input coupling network, an output coupling network, or an inter-stage coupling network within the composite amplifier structure. The one or more coupling networks are couple to each other. A sizing ratio between the one or more first basic amplifiers and the one or more second basic amplifiers in the composite amplifier core is adjustable.

A source follower circuit (100) includes a first MOS transistor (M1), a second MOS transistor (M2), a third MOS transistor (M3), and a feedback loop circuit (104). Regarding the first MOS transistor (M1), a gate terminal receives an input signal (VIN), and a source terminal outputs an output signal (VOUT). Regarding the second MOS transistor (M2), a gate terminal is coupled to a bias voltage (VB), a source terminal is coupled to a first reference voltage (VDD), and a drain terminal is coupled to the source terminal of the first MOS transistor (M1). Regarding the third MOS transistor (M3), it is a self-biased diode-connected MOS transistor. The drain terminal of the third MOS transistor (M3) is coupled to a drain terminal of the first MOS transistor (M1), and a source terminal of the third MOS transistor (M3) is coupled to a second reference voltage (GND).

An amplifier circuit 101 includes: a first current source circuit 113 configured to output a predetermined current amount to a first interconnect L1; a voltage amplifier circuit 110 configured to amplify a voltage of an input signal; a first level shift circuit 111 connected between the first interconnect L1 and an output of the voltage amplifier circuit 110 and configured to shift a voltage of a signal output from the voltage amplifier circuit 110; a first voltage follower 117 connected to the first interconnect L1 and configured to amplify a signal in the first interconnect L1; and a first capacitor 210 connected between the first interconnect L1 and the output of the voltage amplifier circuit 110.

A transimpedance amplifier system (TIA) for stabilizing high gain and high frequency signals while minimizing parasitic capacitance effects on the transimpedance amplifier system. The TIA includes an operational amplifier having a first input terminal, a second input terminal, and an output terminal. The TIA also includes a signal generating device operatively connected with the first input terminal of the operational amplifier. The TIA also includes a T-network feedback architecture operatively connected with the operational amplifier at the first input terminal of the operational amplifier and the output terminal of the operational amplifier. The T-network feedback architecture has a first impedance network and a second impedance network. The T-network feedback architecture is configured to suppress parasitic capacitance from the transimpedance amplifier system.

An apparatus, including: a flipped voltage follower (FVF) including a first pchannel field effect transistor (PFET), a second PFET, and a first current source coupled in series between an upper voltage rail and a lower voltage rail; and a bias voltage control circuit coupled to a node between the second PFET and the first current source.

A bias circuit includes a first transistor and a second transistor configured as a first current mirror. A first current source is arranged between a supply node and the first transistor first terminal. A bias circuit output is coupled to the second transistor second terminal. A second current mirror is coupled to the first current mirror and the bias circuit output. A second current source is arranged between the supply node and the second current mirror. A third transistor in a diode-connected configuration is coupled between the first transistor second terminal and a ground. Alternatively or in addition, the bias circuit includes a first variable capacitor coupled between the second transistor first terminal and the second transistor second terminal. A fourth transistor has a control terminal coupled to the supply node, a first terminal coupled to the supply node and a second terminal coupled to the second transistor first terminal.

In described examples, a circuit includes a first current source, a second current source, a first bipolar junction transistor (BJT), a second BJT, a third BJT, a fourth BJT, and a fifth BJT. A base of the second BJT is coupled to a first terminal of the first current source. A base of the third BJT is coupled to a first terminal of the second current source, and an emitter of the third BJT is coupled to an emitter of the second BJT and a collector of the first BJT. A base of the fifth BJT is coupled to a base and an emitter of the fourth BJT and to a collector of the third BJT, and a collector of the fifth BJT is coupled to an emitter of the first BJT.

A reset signal is generated by a TIA circuit alone. In an embodiment, a transimpedance amplifier configured to convert a current signal into a voltage signal includes a transimpedance stage including an amplification stage constituted of a transistor with a grounded emitter, and a comparator configured to compare a collector voltage of the transistor with a reference voltage and output a reset signal.

In an example, a circuit includes a first field-effect transistor (FET) having a gate and first and second terminals. The circuit includes a second FET having a gate and first and second terminals, the second terminals of the first and second FETs coupled together. The circuit includes a first boosted follower coupled to the gate of the first FET and includes a second boosted follower coupled to the gate of the second FET. A third FET is coupled to the first boosted follower and the second voltage terminal and configured to turn off the first boosted follower responsive to a first level of an output voltage. A fourth FET is coupled to the second boosted follower and the first voltage terminal and configured to turn off the second boosted follower responsive to a second level of the output voltage.

The present invention relates to various DC and AC current shunts in an optical receiver. A circuit may include an amplifier circuit configured to: receive a current signal at an amplifier input node; convert the current signal into a voltage signal; and output the voltage signal at an amplifier output node. The circuit may also include an overload circuit configured to receive a replicated DC input voltage and a replicated DC output voltage. The overload circuit may also be configured to detect that the current signal exceeds a threshold level based on the replicated DC input voltage and the replicated DC output voltage. In addition, the overload circuit may be configured to direct the DC current of the current signal through a DC shunt path and direct the AC current of the current signal through an AC shunt path in response to and based on detecting that the current signal exceeds a threshold level. The AC shunt path may be different from the DC shunt path.

A voltage generating circuit comprises a voltage input terminal to which an input voltage is applied, a voltage output terminal from which an output voltage is output, a first resistor having a first terminal electrically connected to the voltage input terminal and a second terminal electrically connected to the voltage output terminal, a second resistor having a third terminal electrically connected to the second terminal and a fourth terminal, a first capacitor electrically connected to the first terminal or the second terminal, and a first circuit electrically connected to the first terminal or the second terminal comprising a charging circuit configured to charge the first capacitor.

A variable transimpedance amplifier may include first and second amplifiers. Each of the first and second amplifiers may include a transistor amplifier with a feedback resistor and a capacitor. The output node of the first amplifier may be an output node of the variable transimpedance amplifier. The output node of the second amplifier is not part of the output node of the variable transimpedance amplifier. The open loop gains of the transistor amplifiers may be variable, but the feedback resistor values can be fixed. The transimpedance may be determined by the feedback resistors and a scaling factor proportional to ratio of open loop gains. The transistor amplifiers may share an input transistor. The configuration can provide a high dynamic range of variable transimpedance that is stable over process and operating condition variations, minimize input capacitance loading and noise contribution to small input signals.

A microphone includes a MEMS device having an output node for generating an analog voltage in response to an input sound wave or vibration; a source follower having a control node coupled to the output node of the MEMS device, a current path coupled between a first controlled node and a second controlled node, and a bulk node, wherein the first controlled node is configured for providing a microphone output voltage, and wherein the second controlled node is coupled to a reference voltage; a current source coupled to the first controlled node; and a voltage differential between the first controlled node and the bulk node, wherein a nonzero value of the voltage differential is configured such that a first 1% total harmonic distortion (THD) cross-point of the microphone output voltage is greater than a second 1% THD cross-point of the microphone output voltage using a zero value voltage differential.

A transimpedance amplifier system (TIA) for stabilizing high gain and high frequency signals while minimizing parasitic capacitance effects on the transimpedance amplifier system. The TIA includes an operational amplifier having a first input terminal, a second input terminal, and an output terminal. The TIA also includes a signal generating device operatively connected with the first input terminal of the operational amplifier. The TIA also includes a T-network feedback architecture operatively connected with the operational amplifier at the first input terminal of the operational amplifier and the output terminal of the operational amplifier. The T-network feedback architecture has a first impedance network and a second impedance network. The T-network feedback architecture is configured to suppress parasitic capacitance from the transimpedance amplifier system.

The present disclosure relates to a circuit (1) comprising a first terminal (T1) for a first output of a differential amplifier, a second terminal (T2) for a second output of the differential amplifier, a third terminal (T3) for an input of a single-ended amplifier, and three transistors each comprising a first terminal, a second terminal and a third terminal. The third terminal of a first transistor is connected to the first terminal of the circuit. The third terminal of a second transistor is connected to the second terminal of the circuit. The third terminal of a third transistor is electrically connected to the second terminal of the first transistor. The second terminal of the second transistor, the first terminal of the third transistor and the third terminal of the circuit are connected to a node. A transconductance of the second transistor equals a transconductance of the third transistor.