476results about "Arbitary function generators" patented technology

A self DC-bias high frequency logic gate is disclosed. The logic gate comprises at least one input terminal and one output terminal for performing Boolean operation on the high frequency input signals. The logic gate is characterized in that each transistor is coupled to an impedance matching network. The impedance matching network comprises a first terminal and a second terminal. Wherein, the first terminal is coupled to a gate of the transistor, and the second terminal is coupled to a drain of the transistor for providing an operation voltage to the transistor. When a gate of an N-type transistor and a gate of a P-type transistor are coupled with each other, and a drain of the N-type transistor and a drain of the P-type transistor are also coupled with each other, a common impedance matching network is shared with both the N-type transistor and the P-type transistor.

A system is provided for substantially reducing variation in AM to PM distortion of a power amplifier caused by variations in RF drive power and temperature. The system includes power control circuitry and power amplifier circuitry. The power amplifier circuitry includes an input amplifier stage and at least one additional amplifier stage coupled in series with the input amplifier stage. The power control circuitry provides a first supply voltage to the input amplifier stage based on a control signal such that the first supply voltage has a predetermined DC offset with respect to the control signal. The first supply voltage is provided such that the predetermined DC offset substantially reduces variations in the AM to PM distortion of the power amplifier due to variations in radio frequency (RF) drive power.

A trailing edge of a control signal of a transistor controller for controlling an output transistor is detected by an edge detector of a clamp controlling circuit. A surge voltage from a back electromotive voltage induced in an inductance L1 is absorbed from the output transistor, only for a given period immediately after the solenoid is turned off, by turning a switching transistor into an on-state by a timer to force a clamping circuit into conduction. At a normal operation, since the clamping circuit is cut off from an output terminal, the clamping voltage can be set in a manner to reduce to a normal voltage in an IGN-line. Therefore, a peak power value of a power loss caused by the surge voltage at the output transistor can be reduced, whereby generation of heat at the output transistor can be reduced. Therefore, the chip size of the power IC can be reduced.

A differential circuit and an amplifier circuit for reducing an amplitude difference deviation, performing a full-range drive, and consuming less power are disclosed. The circuit includes a first pair of p-type transistors and a second pair of n-type transistors. A first current source and a first switch are connected in parallel between the sources of the first pair of transistors, which are tied together, and a power supply VDD. A second current source and a second switch are connected in parallel between the sources of the second pair of transistors, which are tied together, and a power supply VSS. The circuit further includes connection changeover means that performs the changeover of first and second pairs between a differential pair that receives differential input voltages and a current mirror pair that is the load of the differential pair. When one of the two pairs is the differential pair, the other is the current mirror pair. In a differential amplifier circuit, there is provided an added transistor connected in parallel to a transistor, which is one transistor of a differential pair transistors, whose control terminal is a non-inverting input terminal. The added transistor has a control terminal for receiving a control voltage which is set so that, when an input voltage applied to the non-inverting input terminal is in a range in which the transistor whose control terminal is the non-inverting input terminal is turned off, the added transistor is turned on.

A method to establish an adjustable on-chip impedance within a predetermined range that involves establishing a reference current for the adjustable on-chip impedance and applying this reference current to the adjustable on-chip impedance. A voltage produced by applying the reference current to the adjustable on-chip impedance is sensed and compared with the comparator or other similar processor to a reference voltage. This comparison allows the adjustable on-chip impedance to be tuned when the comparison of the sense voltage and the reference voltage is unfavorable. Tuning the impedance results in an impedance value within a predetermined range that accounts for variances of both the reference current and reference voltage.

According to one example embodiment, a buffer, e.g., in a clock/signal distribution apparatus is provided that substantially reduces jitter due to power supply noise. Decoupler and input stage isolates load from the top rail power supply (V_DD). In a more particular embodiment, jitter contributions from the bottom rail power supply (V_SS) can be minimized by cross-coupled load devices within load. Substantial independence from process and temperature is facilitated through the use of current bias, such as Proportional to Absolute Temperature (PTAT) current bias.

A method of processing a signal is disclosed. The present invention includes receiving (a) a downmix signal being generated from plural-channel signal and (b) spatial information indicating attribute of the plural-channel signal, in order to upmix the downmix signal; obtaining inter-channel phase difference(IPD) coding flag indicating whether IPD value is used to the spatial information from a header of the spatial information; obtaining IPD mode flag indicating whether the IPD is used to frame of the spatial information from the frame based on the IPD coding flag; obtaining the IPD value from a parameter band in the frame based on the IPD mode flag; generating plural-channel signal by applying the IPD value to the downmix signal, wherein the spatial information is divided by header and a plurality of the frame and wherein the IPD value indicates phase difference between two channels of the plural-channel signal and wherein the parameter band is at least one sub-band of frequency domain including the IPD value.

A drive circuit for an integrated circuit tester operates in either a drive mode of a termination mode. In the drive mode, the drive circuit supplies a differential test signal to an integrated circuit device under test (DUT) via a pair of transmission lines. In its termination mode, the drive circuit terminates the transmission lines with their characteristic impedances and provides an adjustable load to a DUT output signal appearing on the transmission lines.

A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, which has more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region thereof, and also has more junction area than a normal diode. The SOI diodes of the present invention improve the protection level offered for electrical overstress (EOS)/electrostatic discharge (ESD) due to the low power density and heating for providing more junction area than normal ones. The I/O ESD protection circuits, which comprise primary diodes, a first plurality of diodes, and a second plurality of diodes, all of which are formed of the present SOI diodes, could effectively discharge the current when there is an ESD event. And the ESD protection circuits, which comprise more primary diodes, could effectively reduce the parasitic input capacitance, so that they can be used in the RF circuits or HF circuits. The proposed gated diode and non-gated diode can be fully process-compatiable to general partially-depleted or fully-depleted silicon-on-insulator CMOS processes.

In a parameter correction circuit in an LSI, a reference resistor element with high precision having a resistance value set to a target value is connected to an external terminal of the LSI. A constant current from a mirror circuit connected to a current supply flows through the reference resistor element. A voltage value generated in the reference resistor element is measured by a voltage measuring circuit. The constant current also flows through a variable resistor element. The resistance value of the variable resistor element is adjusted so that a voltage generated in the variable resistor element corresponds to the voltage generated by the reference resistor element.

An input processing circuit includes a first and second input transistors for receiving a differential pair of first and second input signals, respectively. At least one resistor is coupled between first terminals of the first and second input transistors. The input processing circuit includes a variable gain amplifier (VGA) circuit. At least one first transistor has a gate terminal, and is coupled between the first terminals of the first and second input transistors. At least one second transistor has a gate terminal, and is coupled between the first terminals of the first and second input transistors. A gate switch is coupled to the gate terminal of the at least one second transistor. The at least one first transistor and the at least one second transistor adjust a gain of the input processing circuit in response to a control voltage. The control voltage is applied to the gate terminal of the at least one first transistor, and the control voltage is applied to the gate terminal of the at least one second transistor through the gate switch.

An integrated circuit comparator includes a differential amplifier, a source follower circuit coupled to a gate terminal of a first transistor in the differential amplifier, and an output circuit. One or more source follower circuits may be utilized in connection with the differential amplifier, and one or more source follower circuits may be utilized in connection with the output circuit.

A common voltage source IC device includes an operational amplifier, a push-pull circuit receiving an output signal from the operational amplifier and outputting a common voltage to a common voltage terminal; an inverting resistor connected to an inverting input of the operational amplifier; a feedback resistor connected to the common voltage terminal and the inverting input; a capacitor connected to the common voltage terminal and the inverting input; a first switching resistor connected to the inverting input and a first switching transistor, the first switching transistor connected to the common voltage terminal; a driving resistor receiving a drive voltage and connected to a non-inverting input of the operational amplifier; a variable resistor connected to the non-inverting input and a ground source; and a second switching resistor connected to the non-inverting input and a second switching transistor, the second switching transistor connected to the ground source.