21 results about "Input amplifier" patented technology

An example apparatus includes: combination circuitry having a first input, a second input, and an output; analog-to-digital converter (ADC) circuitry having an input and an output, the input of the ADC circuitry coupled to the output of the combination circuitry; digital-to-analog converter (DAC) circuitry having an input and an output, the input of the DAC coupled to the output of the ADC circuitry; a resistor having a first terminal and a second terminal, the first terminal of the resistor coupled to the first input of the combination circuitry; amplifier circuitry having an input coupled to the output of the DAC circuitry and the second terminal of the resistor.

The class AB amplifier device includes an input chopper switch circuit that performs a chopping operation in synchronization with a first and second chopper clock signal, and outputs first and second modulated signals obtained by modulating the first and second differential input signals to a first and second node; an input amplifier circuit that receives the first and second modulated signals via the first and second nodes, and outputs a differential amplified signal obtained by amplifying the first and second modulated signals; an output chopper switch circuit that receives the differential amplified signal, performs a chopping operation in synchronization with the first and second chopper clock signals, and modulates the differential amplified signal to output a demodulated signal demodulated to the frequency band of the first and second differential input signals; and an output amplifier circuit that outputs a first output signal obtained by amplifying the demodulated signal.

Logarithm (100) comprehensive an input amplifier (101), a logarithmic component (102), and a feedback capacitor (103) which is designed to stabilize the logarithm (100), characterized by the fact that the logarithm (100) comprises a switching device (110), and the feedback capacitance (103) is divided into a plurality of n partial feedback capacitances (103a, 103b, 103c) connected in parallel, wherein a first partial feedback capacitor (103a) is a permanently stabilizing component of the logarithm converter (100), and wherein a number of n-1 of the n partial feedback capacitors (103a, 103b, 103c) are switchable partial feedback capacitors (103b, 103c), wherein the n-1 partial feedback capacitors (103b, 103c) can be switched on separately as stabilizing components in addition to the first partial feedback capacitor (103a), and where the switching device (110) is configured to individually switch the n-1 switchable partial feedback capacitors (103b, 103c) depending on an input current (I Ph ) of the logarithm (100) to be automatically switched on or off and thus depending on the input current (I Ph ) of the logarithm (100) automatically increases or decreases an effective feedback capacity (103) with which the logarithm (100) is stabilized, wherein the effective feedback capacitance (103) corresponds to a sum of the first partial feedback capacitance (103a) and all switched-on switchable partial feedback capacitances (103b, 103c), and wherein the switching device (110) comprises • at least one reference current source (111, 111a, 111b), • at least one reference transistor (112, 112a, 112b), • at least one switching amplifier (113a, 113b), and • at least one switch (114a, 114b).

The utility model discloses a voltage displacement driving circuit, which completes real-time driving from input to output under the condition of different input and output voltage polarities, satisfies driving conversion from signals generated from a positive voltage domain to output to a negative voltage domain in some applications, and comprises an input amplification circuit, a phase inverter and an output conversion circuit, the input amplification circuit is connected with the phase inverter and the output conversion circuit, and the phase inverter is connected with the output conversion circuit; the output conversion circuit comprises a signal amplification circuit, a positive feedback circuit and an output driving circuit, the signal amplification circuit is respectively connected with the input amplification circuit, the phase inverter, the positive feedback circuit and the output driving circuit, and the positive feedback circuit is connected with the output driving circuit.

A semiconductor device of a novel structure is provided. The semiconductor device includes a sensor, an amplifier circuit to which a sensor signal of the sensor is input, a sample-and-hold circuit to which an output signal of the amplifier is input and which holds a voltage corresponding to the output signal, an analog-digital conversion circuit to which an output signal of the sample-and-hold circuit corresponding to the voltage is input, and an interface circuit. The interface circuit has a function of controlling switching during a first control period in which the sensor signal is input to the amplifier circuit and an output signal of the amplifier circuit is held in the sample-and-hold circuit, and a second control period in which a digital signal obtained by outputting the voltage held in the sample-and-hold circuit to the analog-digital conversion circuit is output to the interface circuit. The analog-digital conversion circuit is switched to stop the output of the digital signal during the first control period. The first control period is longer than the second control period.

The invention discloses a sampling hold circuit of a pipelined analog-to-digital converter, which relates to the technical field of integrated circuits of analog-to-digital converters and comprises an input amplifier, an output amplifier, an output common-mode feedback module and a sampling hold signal common-mode feedback module. Wherein the input end of the input amplifier is connected with a sampling input signal, the output end of the input amplifier is connected with the input end of the output amplifier, and the output end of the output amplifier is respectively connected with the input end of the assembly line analog-to-digital converter and the input end of the output common-mode feedback module; the output end of the output common-mode feedback module is connected to the input end of the sampling and holding signal common-mode feedback module, and the output end of the sampling and holding signal common-mode feedback module is connected to the input end of the output amplifier. The technical problem that high index requirements are difficult to pursue on the premise of low area and power consumption in the prior art is solved.

The utility model discloses a voltage displacement driving circuit, which completes real-time driving from input to output under the condition of different input and output voltage polarities, meets the requirement of driving conversion from signals generated from a positive voltage domain to output to a negative voltage domain in some applications, and comprises an input amplification circuit, a phase inverter and an output conversion circuit, the input amplification circuit is connected with the phase inverter and the output conversion circuit, and the phase inverter is connected with the output conversion circuit; the output conversion circuit comprises a signal amplification circuit, a clamping circuit, a positive feedback circuit and an output driving circuit, the signal amplification circuit is respectively connected with the input amplification circuit, the phase inverter, the clamping circuit and the output driving circuit, and the clamping circuit is respectively connected with the positive feedback circuit and the output driving circuit. And the positive feedback circuit is connected with the output driving circuit.

The invention relates to a method and apparatus for reducing accumulation in an analog-to-digital converter. An example apparatus includes combining circuitry (220) having a first input, a second input, and an output; analog-to-digital converter (ADC) circuitry (225) having an input and an output, the input of the ADC circuitry coupled to the output of the combinatorial circuitry; a digital-to-analog converter (DAC) circuitry (230) having an input and an output, the input of the DAC circuitry being coupled to the output of the ADC circuitry; a resistor (210) having a first terminal and a second terminal, the first terminal of the resistor being coupled to the first input of the combinatorial circuitry; amplifier circuitry (235) having an input coupled to the output of the DAC circuitry and the second terminal of the resistor.

The application discloses a dual-frequency reconfigurable input amplification stage circuit, an amplifier, a chip and a system, wherein the dual-frequency reconfigurable input amplification stage circuit comprises a first matching network, a second matching network, a first transistor, a second transistor, a first transmission line and a second transmission line. One end of the first matching network is a signal 1 input end, the other end of the first matching network is connected with the gate of the first transistor, the drain of the first transistor is connected with one end of the first transmission line, the other end of the first transmission line is connected with one end of the second transmission line, the other end of the second transmission line is connected with the drain of the second transistor, the gate of the second transistor is connected with one end of the second matching network, and the other end of the second matching network is a signal 2 input end. The dual-frequency reconfigurable low-noise amplifier adopts the architecture of the dual-frequency reconfigurable input amplification stage, a reconfigurable matching network and a wideband amplification stage, frequency switching functions are realized by changing the signal input port and the control voltage of the reconfigurable matching network electronic switch, and the dual-frequency reconfigurable low-noise amplifier has good noise performance.

The present subject matter relates to methods, systems, devices, circuitry and equipment providing for communication service to be transported between first and second networks, and which monitors the communication service and / or injects test signals, and which can provide redundancy. At least one demarcation point or line is established between the first network and the second network, and / or between the first network, the second network and / or a third network. The Circuitry comprises a plurality of input amplifiers, output amplifiers, and multiplexer switches between a plurality of Port connectors. An SFP module or a WSFP module is inserted in the Ports.

The invention relates to a high-input-impedance and low-noise rail-to-rail amplifier which is composed of a high-input-impedance and low-noise rail-to-rail input amplifying circuit, a gain boosting circuit, a rail-to-rail output amplifying circuit and a frequency compensating circuit. The rail-to-rail input amplifying circuit is characterized in that resistors for reducing input noise voltage and current source noise are arranged between a PMOS (P-channel Metal Oxide Semiconductor) load current source in the rail-to-rail input amplifying circuit and the positive electrode of a power supply VDD (Voltage Drain Drain) and between an NMOS (N-channel Metal Oxide Semiconductor) load current source and a power supply ground; and a dynamic bias circuit is additionally arranged to provide dynamic bias voltage for the rail-to-rail input amplifying circuit. Due to the adoption of the technical scheme, the low-frequency amplifier has the advantages that the input amplifier stage and the output amplifier stage have relatively high low-frequency voltage gains, the precision is improved, and the input noise and the gain error are reduced.

The invention provides a multi-transmitting and multi-receiving-end underwater visible light communication device and system, relates to the technical field of visible light communication, is used for relieving the technical problem of low alignment degree of transmitting ends and receiving ends of a visible light communication system in an underwater complex environment, and can realize underwater efficient information transmission. The device comprises an information input end, a visible light emitting end, a visible light receiving end and an information output end, the visible light emitting end comprises a driving power supply, an LD light emitter, an LDMOS series driving module and an arbitrary waveform generator, and the driving power supply and the LDMOS series driving module are connected with the LD light emitter; the LDMOS series drive module is used for controlling the on-off of the LD light emitter to realize the conversion from an electric signal to a light signal; the arbitrary waveform generator is connected with the LDMOS series drive module, and the arbitrary waveform generator is used for generating waveforms; the visible light receiving end comprises a photoelectric detector, a trans-impedance amplifier, a voltage input type amplification device and a micro-control unit. The transimpedance amplifier is connected with the photoelectric detector, and the voltage input type amplification device is connected with the transimpedance amplifier; the micro-control unit is connected with the voltage input type amplification equipment; the photoelectric detector is used for receiving the visible light emitted by the LD light emitter and converting a modulated light signal into an electric signal; and the micro-control unit is used for decoding and restoring.

The application relates to a digital control gain high-fidelity input amplification circuit which comprises an MCU, an analog switch U17, an operational amplifier, an electronic volume controller U16, the 7th and 8th pins of the analog switch U17 are connected to the IO output high-low level signals of the MCU, the analog switch U17 is connected to the operational amplifier, the operational amplifier is connected to the electronic volume controller U16, and the MCU is also connected to the electronic volume controller U16. The circuit of the application is composed of an SGM4519 analog switch, an NJM2122M operational amplifier (the highest gain is 28.95dB) and an NJW1195A electronic volume controller (the highest gain is 31.5dB), a high-fidelity adjustable gain amplifier with a total gain of 60.45dB is realized, and the control mode can be diversified, for example, a potentiometer control, an encoder control, a button control or an upper computer control.

The present disclosure relates to a split input amplifier for protection from DC bias. Embodiments presented herein provide apparatuses and techniques to reduce direct current (DC) voltage bias between a transmitter and a receiver. Embodiments include a shared reference voltage signal generated by a reference voltage source. The receiver can include a first cell gain buffer that receives a reference voltage signal from the reference voltage source. The transmitter can be communicatively coupled to the receiver via one or more connections and can include a second cell gain buffer communicatively coupled to the first cell gain buffer via one of the connections. An amplifier (e.g., an operational amplifier) of the transmitter can include a plurality of positive inputs coupled to the second cell gain buffer and a bias tracker. The bias tracker can compensate for DC bias caused by at least power supply and / or ground bounce.

An amplifier device for receiving currents, comprising a first current path for measuring smaller currents of less than 100 pA, an input amplifier device included in the first current path, having at least one first amplifier, an output, an inverting input, a first feedback path connecting the output to the inverting input, and a feedback element included in the first feedback path, wherein the first amplifier has at least one protective element, a second current path for measuring larger currents with a maximum current of at least 10 times the current to be received in the first current path, characterized in that at least one of the protective elements of the amplifier is part of the second current path.

An example sensing system includes a non-contact sensing electrode configured to sense an electric potential and provide a sensor signal at an output of the sensing electrode based on the sensed electric potential. The output of the sensing electrode is coupled to a first input of an amplifier. The amplifier is configured to provide an amplified output signal representative of at least one measured biosignal based on the sensor signal and a feedback signal provided to the second input of the amplifier. A compensation signal generator is coupled between the output of the amplifier and the second input. The compensation signal generator is configured to estimate corresponding noise and provide the feedback signal to include a filtered signal representative of the estimated noise to the second input to the corresponding noise at the first input of the amplifier and mitigate saturation of the amplifier.

This invention belongs to the field of microwave radio frequency and provides a small-sample high-power input amplifier modeling method based on physical gene anchoring. It addresses the problems in existing technologies, such as difficulty in obtaining existing physical models of high-power input amplifier devices, difficulty in realizing nonlinear characteristics and breakdown properties in the deep saturation region using self-built lookup table-based behavioral models, the extremely large amount of measured data required for self-built behavioral models, high cost of high-power experiments, and limited sample data. This invention proposes a small-sample intelligent modeling method for high-power input amplifiers based on physical gene anchoring. This method uses the core constraints of physical skeleton equations, neural network training parameters coupled with residual correction, and only requires readily available datasheet indicators and single-frequency measured data to automatically generate a high-fidelity P2D file for the entire operating frequency band. Then, a frequency-dependent breakdown threshold prediction algorithm is used to establish the behavioral model of the high-power input amplifier.

The present invention provides a class AB amplification device capable of reducing the influence of the on-resistance of a chopper switch on circuit characteristics. A class AB amplification device is provided with: an input chopper switching circuit that performs chopping operation in synchronization with first and second chopper clock signals and outputs first and second modulated signals obtained by modulating first and second differential input signals to first and second nodes; an input amplifier circuit to which the first and second modulated signals are input via the first and second nodes, and which outputs a differential amplified signal obtained by amplifying the first and second modulated signals; an output chopper switching circuit to which the differential amplified signal is input, which performs chopping operation in synchronization with the first and second chopper clock signals, modulates the differential amplified signal, and outputs a demodulated signal demodulated to the frequency band of the first and second differential input signals; and an output amplifier circuit that outputs, via a first output terminal, a first output signal obtained by amplifying the demodulated signal.

This invention provides a Class AB amplifier that reduces the influence of the chopper switch's on-resistance on the circuit characteristics. [Solution] The Class AB amplifier 100 includes an input chopper switch circuit CSW1 that performs chopping operations in synchronization with the first and second chopper clock signals PHI and PHIB to modulate the first and second differential input signals VINN and VINP, and outputs the first and second modulated signals VA1 and VA2 to the first and second nodes Q1 and Q2; an input amplifier circuit AM1 that receives the first and second modulated signals via the first and second nodes and outputs a differential amplifier signal amplified from the first and second modulated signals; an output chopper switch circuit CSW2 that receives the differential amplifier signal, performs chopping operations in synchronization with the first and second chopper clock signals to modulate the differential amplifier signal, and outputs demodulated signals D1 to D4 demodulated to the frequency band of the first and second differential input signals; and an output amplifier circuit AM2 that outputs a first output signal VOP, which is an amplified demodulated signal, via the first output terminal TOP.

The application discloses a voltage-to-frequency conversion hybrid integrated circuit in the technical field of voltage frequency conversion, which comprises an amplifier circuit, a sawtooth wave generating circuit, a comparator circuit and a discharge circuit; a voltage signal is input from an input end of the amplifier circuit, an output end of the amplifier circuit is connected with an input end of the sawtooth wave generating circuit, the sawtooth wave generating circuit outputs the amplified voltage signal as a sawtooth wave signal, the sawtooth wave signal is processed by the comparator circuit and the discharge circuit to output a pulse signal, and the conversion from voltage to frequency is realized. The circuit has extremely low power consumption, simple structure and easy realization, and can work reliably for a long time only by using a single 1.5V button cell.

This invention relates to the field of analog integrated circuit technology, specifically to a high-speed, low-power comparator circuit for a continuous-time analog-to-digital converter (ADC). The circuit employs a three-stage cascaded optimized architecture, comprising a rail-to-rail input pre-amplifier stage, a gain booster stage, and a differential-to-single-ended output stage. The pre-amplifier stage uses a complementary differential input structure composed of NMOS and PMOS transistors, achieving a wide input swing from power ground to power supply voltage. The gain booster stage employs a unique fully differential inverter input amplifier structure and integrates a self-biased current mirror, achieving high transconductance efficiency and gain by simultaneously utilizing the transconductance of NMOS and PMOS transistors without requiring external bias circuitry. The output stage converts the differential signal into a single-ended signal and drives the load. Through the aforementioned specific circuit structure, this invention significantly reduces power consumption and achieves high-precision comparison without sacrificing response speed.