56 results about "Input amplifier" patented technology

A readout circuit for a MEMS sensor unit. The readout circuit includes at least one circuit component which includes a cascade circuit including at least one input amplifier and at least one output amplifier. A predefined external supply voltage is available for operating the readout circuit. In the process, the input amplifier is operated with a first supply voltage which is, by comparison, less than or equal to the external supply voltage, and the output amplifier is operated with a second supply voltage which is, by comparison, greater than the external supply voltage. At least one circuit means, which makes the second supply voltage is also provided, which is, by comparison, greater than the external supply voltage, available to the output amplifier.

The present subject matter relates to methods, systems, devices, circuitry and equipment providing for communication service to be transported between first and second networks and which monitors the communication service and / or injects test signals over two fiber cables. A first single fiber cable is used to interface the communication services between the first and second network. A second single fiber cable is used to monitor the communication services and / or inject signals. The circuitry comprises a plurality of input amplifiers, output amplifiers, and multiplexer switches between a plurality of port connectors. An SFP module is inserted in all ports, and the SFP modules connect to one or more fiber optic cables.

A semiconductor integrated circuit device capable of inputting a signal of a MEMS transducer 2 includes: a power supply circuit 11 for the MEMS transducer 2; an input amplifier 12 for inputting and amplifying a signal of the MEMS transducer 2; a line driver 13 for amplifying an output from the input amplifier 12 and allowing for driving of a load connected to an output terminal T3, the line driver 13 having an input terminal; and the output terminal T3 for outputting an output of the line driver 13, wherein the power supply circuit 11, the input amplifier 12, and the line driver 13 are integrally formed on a semiconductor substrate, and wherein a gain setting circuit 14 for determining gain of the line driver 13 and a DC potential of the output terminal T3 is connected to the input terminal of the line driver 13.

The wearable wireless transmission multi-channel gastric electric signal acquisition system comprises an electrode signal input module, an analog front-end circuit, an analog-to-digital conversion module, a single chip microcomputer control and feedback module, a wireless transmission module, terminal equipment and a power supply module, the analog front-end circuit comprises a front input amplifier, a second-order active band-pass filter and a voltage-stabilizing buffer amplifier; the characteristics of extremely low amplitude and low frequency of a stomach electric signal are considered, a fully differential input and differential three operational amplifier circuit is used as an input stage, and the signal is amplified by thousand times, so that the magnitude that a subsequent circuit can well process is achieved, and the precision and the stability of the system are improved. And the signal sequence is further filtered and denoised through a second-order active low-pass direct-current anti-aliasing filter and a second-order active high-pass filter, so that the integrity of the signal is ensured. And secondly, the signal becomes stable through a low-power voltage-stabilizing amplifying circuit, so that the ADC sampling circuit can effectively sample the gastric electric signal at a relatively high sampling frequency.

An example apparatus includes: combination circuitry having a first input, a second input, and an output; analog-to-digital converter (ADC) circuitry having an input and an output, the input of the ADC circuitry coupled to the output of the combination circuitry; digital-to-analog converter (DAC) circuitry having an input and an output, the input of the DAC coupled to the output of the ADC circuitry; a resistor having a first terminal and a second terminal, the first terminal of the resistor coupled to the first input of the combination circuitry; amplifier circuitry having an input coupled to the output of the DAC circuitry and the second terminal of the resistor.

The class AB amplifier device includes an input chopper switch circuit that performs a chopping operation in synchronization with a first and second chopper clock signal, and outputs first and second modulated signals obtained by modulating the first and second differential input signals to a first and second node; an input amplifier circuit that receives the first and second modulated signals via the first and second nodes, and outputs a differential amplified signal obtained by amplifying the first and second modulated signals; an output chopper switch circuit that receives the differential amplified signal, performs a chopping operation in synchronization with the first and second chopper clock signals, and modulates the differential amplified signal to output a demodulated signal demodulated to the frequency band of the first and second differential input signals; and an output amplifier circuit that outputs a first output signal obtained by amplifying the demodulated signal.

An amplifier device for receiving currents, comprising a first current path for measuring smaller currents of less than 100 pA, an input amplifier device included in the first current path, having at least one first amplifier, an output, an inverting input, a first feedback path connecting the output to the inverting input, and a feedback element included in the first feedback path, wherein the first amplifier has at least one protective element, a second current path for measuring larger currents with a maximum current of at least 10 times the current to be received in the first current path, characterized in that at least one of the protective elements of the amplifier is part of the second current path.

In accordance with an embodiment, a noise shaping successive approximation analog-to-digital converter (ADC) includes: a digital-to-analog converter (DAC); a multi-input comparator with a first input coupled to the DAC; a multi-input amplifier having a first input coupled to the DAC, and a second input coupled to a second input of the multi-input comparator; and a first delay element having an input coupled to an output of the multi-input amplifier and an output coupled to the second input of the multi-input amplifier and to the second input of the multi-input comparator.

Logarithm (100) comprehensive an input amplifier (101), a logarithmic component (102), and a feedback capacitor (103) which is designed to stabilize the logarithm (100), characterized by the fact that the logarithm (100) comprises a switching device (110), and the feedback capacitance (103) is divided into a plurality of n partial feedback capacitances (103a, 103b, 103c) connected in parallel, wherein a first partial feedback capacitor (103a) is a permanently stabilizing component of the logarithm converter (100), and wherein a number of n-1 of the n partial feedback capacitors (103a, 103b, 103c) are switchable partial feedback capacitors (103b, 103c), wherein the n-1 partial feedback capacitors (103b, 103c) can be switched on separately as stabilizing components in addition to the first partial feedback capacitor (103a), and where the switching device (110) is configured to individually switch the n-1 switchable partial feedback capacitors (103b, 103c) depending on an input current (I Ph ) of the logarithm (100) to be automatically switched on or off and thus depending on the input current (I Ph ) of the logarithm (100) automatically increases or decreases an effective feedback capacity (103) with which the logarithm (100) is stabilized, wherein the effective feedback capacitance (103) corresponds to a sum of the first partial feedback capacitance (103a) and all switched-on switchable partial feedback capacitances (103b, 103c), and wherein the switching device (110) comprises • at least one reference current source (111, 111a, 111b), • at least one reference transistor (112, 112a, 112b), • at least one switching amplifier (113a, 113b), and • at least one switch (114a, 114b).

A bandgap reference circuit includes first through fourth bipolar junction transistors (BJTs). The base and collector of the first BJT are shorted together. The second BJT is coupled to the first BJT via a first resistor. The base of the third BJT is coupled to the base of the first BJT. The base and collector of the fourth BJT are coupled together and also are coupled to the base of the second BJT. A second resistor is coupled to the fourth emitter of the fourth BJT. A third resistor is coupled to the second resistor and to the emitter of the second BJT. An operational amplifier has a first input coupled to the first resistor and the collector of the second BJT, a second input coupled to the emitter of the third BJT and the collector of the fourth BJT, and an output coupled to the collectors of the first and third BJTs.

The utility model relates to a cable fault detection device, which belongs to the technical field of cable fault detection, and solves the problems of poor reliability and easy error detection of cable detection in the prior art. The cable fault detection device includes: an output interface connected to the input end of an output amplifier circuit, the output end of the output amplifier circuit connected to the input end of an output inverter, and the output end of the output inverter connected to an external interface; an input interface connected to the output end of an input amplifier circuit, the input end of the input amplifier circuit connected to the output end of an input inverter, and the input end of the input inverter connected to an external interface; the external interfaces of a first input-output combination and a second input-output combination are connected to a power supply through a voltage-dividing resistor, and the input interface and the output interface are connected to an MCU; the external interface of the first input-output combination is connected to one end of a cable to be tested, and the external interface of the second input-output combination is connected to the other end of the cable to be tested. Accurate fault detection of the cable is achieved.

The utility model discloses a voltage displacement driving circuit, which completes real-time driving from input to output under the condition of different input and output voltage polarities, satisfies driving conversion from signals generated from a positive voltage domain to output to a negative voltage domain in some applications, and comprises an input amplification circuit, a phase inverter and an output conversion circuit, the input amplification circuit is connected with the phase inverter and the output conversion circuit, and the phase inverter is connected with the output conversion circuit; the output conversion circuit comprises a signal amplification circuit, a positive feedback circuit and an output driving circuit, the signal amplification circuit is respectively connected with the input amplification circuit, the phase inverter, the positive feedback circuit and the output driving circuit, and the positive feedback circuit is connected with the output driving circuit.

The invention discloses a variable gain amplifier, including an attenuator, an amplifier, a reference voltage generator, a temperature compensation signal generator and two off-chip inductors; the attenuator is used to attenuate the input signal, and input the attenuated signal from the amplifier input end to the amplifier for amplification, and the amplified signal is output from the amplifier output end, the amplifier output end is respectively connected to one end of the two off-chip inductors, and the other end of the two off-chip inductors is grounded; the reference voltage generator is used to provide a reference voltage for the attenuator, and the temperature compensation signal generator provides a first control signal for the first-stage current source of the amplifier and a second control signal for the second-stage current source, thereby adjusting the current of the first-stage current source and the second-stage current source according to the on-chip temperature, and providing compensation for the temperature gain characteristics of the variable gain amplifier. The invention can achieve a wider bandwidth, a lower noise coefficient, a larger output 1dB compression point and a relatively stable gain at different temperatures.

Embodiments presented herein provide apparatus and techniques to reduce a direct current (DC) voltage offset between a transmitter and receiver. Embodiments include a shared reference voltage signal generated by a reference voltage source. The receiver may include a first unit gain buffer to receive a reference voltage signal from the reference voltage source. The transmitter may be communicatively coupled to the receiver via one or more connections and may include a second unit gain buffer communicatively coupled to the first unit gain buffer via one of the connections. An amplifier (e.g., an operation amplifier) of the transmitter may include multiple positive inputs coupled to the second unit gain buffer and an offset tracker. The offset tracker may compensate for a DC offset caused by at least a power supply and / or a ground bounce.

A semiconductor device of a novel structure is provided. The semiconductor device includes a sensor, an amplifier circuit to which a sensor signal of the sensor is input, a sample-and-hold circuit to which an output signal of the amplifier is input and which holds a voltage corresponding to the output signal, an analog-digital conversion circuit to which an output signal of the sample-and-hold circuit corresponding to the voltage is input, and an interface circuit. The interface circuit has a function of controlling switching during a first control period in which the sensor signal is input to the amplifier circuit and an output signal of the amplifier circuit is held in the sample-and-hold circuit, and a second control period in which a digital signal obtained by outputting the voltage held in the sample-and-hold circuit to the analog-digital conversion circuit is output to the interface circuit. The analog-digital conversion circuit is switched to stop the output of the digital signal during the first control period. The first control period is longer than the second control period.

A power supply system includes a regulator, outputting a system voltage; a load, receiving the system voltage to operate; a battery, charged by the system voltage; a charging transistor, receiving the system voltage and controlling a charging current to the battery; and a three-input amplifier, in which three factors including a charging current detection value, a reference charging current, and a reference limit current determined according to a difference between the system voltage and a minimum system voltage are input, and which obtains an output corresponding to a difference between the reference charging current and the charging current detection value when the reference charging current is equal to or less than the reference limit current, and obtains an output corresponding to a difference between the reference limit current and the charging current detection value when the reference charging current exceeds the reference limit current.

The invention discloses a sampling hold circuit of a pipelined analog-to-digital converter, which relates to the technical field of integrated circuits of analog-to-digital converters and comprises an input amplifier, an output amplifier, an output common-mode feedback module and a sampling hold signal common-mode feedback module. Wherein the input end of the input amplifier is connected with a sampling input signal, the output end of the input amplifier is connected with the input end of the output amplifier, and the output end of the output amplifier is respectively connected with the input end of the assembly line analog-to-digital converter and the input end of the output common-mode feedback module; the output end of the output common-mode feedback module is connected to the input end of the sampling and holding signal common-mode feedback module, and the output end of the sampling and holding signal common-mode feedback module is connected to the input end of the output amplifier. The technical problem that high index requirements are difficult to pursue on the premise of low area and power consumption in the prior art is solved.

The present invention is applicable to the technical field of radio frequency front ends, and particularly to a radio frequency front-end module having input power protection, comprising a signal input end, a bias circuit, an amplifier, and a signal output end that are sequentially electrically connected, wherein the bias circuit comprises a coupling circuit, a rectifier circuit, a switching circuit, and a mirror current source circuit; the coupling circuit is used for isolating a direct-current signal inputted by the signal input end, and allowing a radio frequency signal to pass; the rectifier circuit is used for rectifying the radio frequency signal and outputting an envelope signal; the mirror current source circuit is controlled by the envelope signal and outputs a bias current to the amplifier. The bias circuit in a radio frequency power module of the present invention can measure power inputted to the amplifier, and on the basis of the measured average power of an input signal, actively reduce the bias current inputted to a power amplifier, thereby achieving the purpose of protecting the power amplifier.

The invention discloses an optical time domain reflection detection method and system for avoiding an event blind area and OTDR equipment, and relates to the technical field of OTDR.According to the optical time domain reflection detection method, a second detector is additionally arranged at the grounding end of a first detector, the second detector is used for detecting an optical signal emitted by a second light source, and then when OTDR curve measurement is carried out on a to-be-detected optical fiber, the second detector is used for detecting the optical signal emitted by the second light source; a second driver can be controlled to drive a second light source to emit a compensation light signal within a predetermined saturation time interval, so that light current detected by a second detector is utilized to perform offset compensation on light current detected by a first detector, and current input into an amplification circuit is lower than a saturation threshold; therefore, an event blind area caused by saturation can be eliminated, a blind area event can be detected, no selection switch is added, introduction of extra noise is avoided, the optical fiber OTDR test accuracy is improved, and better noise performance is achieved.

The present invention discloses an improved cascade low-noise and low-power dynamic comparator, belonging to the field of integrated circuit design. The comparator comprises: a reset unit connected to the output end of a differential input amplifier unit to reset the output end of the differential input amplifier unit; the differential input amplifier unit comprises a cascade input structure, the control end of the cascade input structure is connected to a tail current source control unit, the output end of the cascade input structure is connected to a latch unit for receiving a differential input signal, amplifying the differential input signal multiple times through the cascade input structure to obtain a differential amplified signal, and outputting the differential amplified signal to the latch unit; the tail current source control unit provides a stable current to the differential input amplifier unit; the latch unit receives the differential amplified signal and establishes a latch to output a differential output signal. The present invention can improve comparison speed while reducing power consumption while achieving low noise.

The utility model discloses a voltage displacement driving circuit, which completes real-time driving from input to output under the condition of different input and output voltage polarities, meets the requirement of driving conversion from signals generated from a positive voltage domain to output to a negative voltage domain in some applications, and comprises an input amplification circuit, a phase inverter and an output conversion circuit, the input amplification circuit is connected with the phase inverter and the output conversion circuit, and the phase inverter is connected with the output conversion circuit; the output conversion circuit comprises a signal amplification circuit, a clamping circuit, a positive feedback circuit and an output driving circuit, the signal amplification circuit is respectively connected with the input amplification circuit, the phase inverter, the clamping circuit and the output driving circuit, and the clamping circuit is respectively connected with the positive feedback circuit and the output driving circuit. And the positive feedback circuit is connected with the output driving circuit.

The invention relates to a method and apparatus for reducing accumulation in an analog-to-digital converter. An example apparatus includes combining circuitry (220) having a first input, a second input, and an output; analog-to-digital converter (ADC) circuitry (225) having an input and an output, the input of the ADC circuitry coupled to the output of the combinatorial circuitry; a digital-to-analog converter (DAC) circuitry (230) having an input and an output, the input of the DAC circuitry being coupled to the output of the ADC circuitry; a resistor (210) having a first terminal and a second terminal, the first terminal of the resistor being coupled to the first input of the combinatorial circuitry; amplifier circuitry (235) having an input coupled to the output of the DAC circuitry and the second terminal of the resistor.

The variable gain amplifier (4) is configured to include a divider (11) that divides a signal to be amplified into two and outputs one divided signal and the other divided signal, a first variable gain amplifier (12) that has a first variable gain characteristic in which a gain corresponding to a control signal indicating the magnitude of the envelope of the signal to be amplified is expressed by a first sigmoid function, amplifies one signal according to the first variable gain characteristic, and outputs the amplified one signal to a first amplifying element (21), and a second variable gain amplifier (13) that has a second variable gain characteristic in which a gain corresponding to the control signal is expressed by a second sigmoid function, amplifies the other signal according to the second variable gain characteristic, and outputs the amplified other signal to a second amplifying element (22). The variable gain amplifier (4) also includes a characteristic adjusting unit (14) that adjusts one or more gains of the gain of the first sigmoid function and the gain of the second sigmoid function according to the frequency of the signal to be amplified.

The bandgap reference circuit (100) includes first to fourth bipolar junction transistors (BJTs) (M1 to M4). The base and collector of the first BJT (M1) are shorted together. The second BJT (M2) is coupled to the first BJT (M1) via a first resistor (R1). The base of the third BJT (M3) is coupled to the base of the first BJT (M1). The base and collector of the fourth BJT (M4) are coupled together and also to the base of the second BJT (M2). The second resistor (R2) is coupled to a fourth emitter of the fourth BJT (M4). The third resistor (R3) is coupled to the second resistor (R2) and the emitter of the second BJT (M2). An operational amplifier (OP1) has a first input coupled to the first resistor (R1) and the collector of the second BJT (M2), a second input coupled to the emitter of the third BJT (M3) and the collector of the fourth BJT (M4), and an output coupled to the collectors of the first and third BJTs (M1 and M3).

The application discloses a dual-frequency reconfigurable input amplification stage circuit, an amplifier, a chip and a system, wherein the dual-frequency reconfigurable input amplification stage circuit comprises a first matching network, a second matching network, a first transistor, a second transistor, a first transmission line and a second transmission line. One end of the first matching network is a signal 1 input end, the other end of the first matching network is connected with the gate of the first transistor, the drain of the first transistor is connected with one end of the first transmission line, the other end of the first transmission line is connected with one end of the second transmission line, the other end of the second transmission line is connected with the drain of the second transistor, the gate of the second transistor is connected with one end of the second matching network, and the other end of the second matching network is a signal 2 input end. The dual-frequency reconfigurable low-noise amplifier adopts the architecture of the dual-frequency reconfigurable input amplification stage, a reconfigurable matching network and a wideband amplification stage, frequency switching functions are realized by changing the signal input port and the control voltage of the reconfigurable matching network electronic switch, and the dual-frequency reconfigurable low-noise amplifier has good noise performance.

Embodiments presented herein provide apparatus and techniques to reduce a direct current (DC) voltage offset between a transmitter and receiver. Embodiments include a shared reference voltage signal generated by a reference voltage source. The receiver may include a first unit gain buffer to receive a reference voltage signal from the reference voltage source. The transmitter may be communicatively coupled to the receiver via one or more connections and may include a second unit gain buffer communicatively coupled to the first unit gain buffer via one of the connections. An amplifier (e.g., an operation amplifier) of the transmitter may include multiple positive inputs coupled to the second unit gain buffer and an offset tracker. The offset tracker may compensate for a DC offset caused by at least a power supply and / or a ground bounce.

The present invention discloses a large power supply series linear filter circuit, which includes a passive filter circuit, a diode clamp circuit, a follower circuit module and an auxiliary power supply module. The passive filter circuit is composed of a resistor and a capacitor; the diode clamp circuit is composed of two general diodes; the follower circuit module is composed of an input amplifier part, a current mirror, a MOSFET drive part and a MOSFET power tube, and multiple follower modules can be used in parallel. The input positive pole of the linear filter circuit is connected to the output positive pole of the power supply to be filtered, and the negative pole of the linear filter circuit is connected to the output negative pole of the power supply to be filtered. The output positive pole and the negative pole of the linear filter circuit constitute a load output port. The output voltage of the filter circuit of the present invention follows the input voltage, maintains a constant voltage difference, and is easy to modify and control; the filter circuit of the present invention uses a low-voltage, high-current MOSFET as the main power device, and has the ability to connect modules in parallel, which is suitable for output filtering of large-current switching power supplies.

Methods, systems, and devices for sense amplifier with digit line multiplexing are described. A method includes precharging an input and an output of an amplifier stage of a sense component to a first voltage based on a read operation associated with a memory cell. The method includes precharging a first side and a second side of a latch stage of the sense component to the first voltage based on precharging the output of the amplifier stage to the first voltage, the latch stage coupled with the amplifier stage. The method may also include coupling a second voltage from a digit line associated with the memory cell to the input of the amplifier stage, the amplifier stage generating a third voltage on the output based on coupling the second voltage to the input, and the latch stage latching a logic value associated with the memory cell based on the third voltage.

Reconfigurable optical add / drop multiplexer (ROADM) (100) comprising: several interconnected ROADM blocks (110), each ROADM block (110) comprising an input amplifier (245) with switchable gain, an output power detector (365, 465) coupled to an output of the input amplifier (245) with switchable gain, and a wavelength-selective switch (225) coupled to the output of the input amplifier (245) with switchable gain; several add / drop blocks (120) coupled to the wavelength-selective switches (225) of the several ROADM blocks (110); and a control unit (140) configured to receive a specification of an output signal power of the output power detector (365, 465) and to adjust gain and equalization parameters of the input amplifier (245) with switchable gain based on the received specification of the output signal power, wherein The input amplifier (245) with switchable gain includes a low-gain fiber amplifier and a high-gain fiber amplifier; and This includes adjusting the gain and equalization parameters and selectively directing an optical signal through the low-gain fiber amplifier or the high-gain fiber amplifier.

The present subject matter relates to methods, systems, devices, circuitry and equipment providing for communication service to be transported between first and second networks, and which monitors the communication service and / or injects test signals, and which can provide redundancy. At least one demarcation point or line is established between the first network and the second network, and / or between the first network, the second network and / or a third network. The Circuitry comprises a plurality of input amplifiers, output amplifiers, and multiplexer switches between a plurality of Port connectors. An SFP module or a WSFP module is inserted in the Ports.