320 results about "Input amplifier" patented technology

A system is provided for substantially reducing variation in AM to PM distortion of a power amplifier caused by variations in RF drive power and temperature. The system includes power control circuitry and power amplifier circuitry. The power amplifier circuitry includes an input amplifier stage and at least one additional amplifier stage coupled in series with the input amplifier stage. The power control circuitry provides a first supply voltage to the input amplifier stage based on a control signal such that the first supply voltage has a predetermined DC offset with respect to the control signal. The first supply voltage is provided such that the predetermined DC offset substantially reduces variations in the AM to PM distortion of the power amplifier due to variations in radio frequency (RF) drive power.

A power amplifier configuration including power amplifier circuitry and power control circuitry and having improved Power Added Efficiency (PAE) is provided. The power amplifier circuitry includes one or more input amplifier stages in series with a final amplifier stage. The power control circuitry provides a variable supply voltage to the input amplifier stages based on an adjustable power control signal. The final amplifier stage is powered by a fixed supply voltage. In operation, as output power of the power amplifier is reduced from its highest power level, the variable supply voltage is reduced. Accordingly, RF power of an amplified signal provided to the final amplifier stage from the input amplifier stages decreases, and the final amplifier stage transitions from saturation to linear operation, thereby increasing the gain of the final amplifier stage. Thus, a desired output level can be maintained while operating at lower current levels.

A differential amplifier (1D) includes circuitry (5,R1,R2,52) coupling a common mode component of an input voltage (Vin⁺−Vin⁻) to a maximum voltage selector circuit (53) that produces an internal voltage (V_RAIL-TOP) equal to the larger of a first supply voltage (V_REG) and the common mode component. An input amplifier circuit (46) of the differential amplifier is powered by the internal voltage. The input voltage (Vin⁺−Vin⁻) is coupled to inputs (41A,B) of the input amplifier circuit (46). Outputs (64A,B) of the input amplifier circuit (46) are amplified by an output amplifier (50).

An ECG front end and a method for acquiring ECG signals are disclosed. The front end comprises a plurality of parallel measurement branches, each measurement branch comprising a protection resistor having a first terminal and a second terminal, wherein the first terminal is connectable to a respective ECG electrode. Each measurement branch comprises a first input amplifier operatively connected to the second terminal of the protection resistor and a capacitor having a first and a second terminal, wherein the first terminal of the capacitor is operatively connected to a point between the first input amplifier and the second terminal of the protection resistor and the second terminal of the capacitor is connected to a virtual ground of a second input amplifier. Each first input amplifier serves as a source of an ECG channel signal and each second input amplifier as a source of high frequency signal components.

A method and apparatus are shown for automatically adjusting a response bandwidth and input sensitivity of a communications receiver responsive to a frequency of a received data signal. The response bandwidth is adjusted by switching a low pass filter into a receive path of the receiver when the received data signal is a low speed data signal and switching the low pass filter out of the receive path when the received data signal is a high speed data signal. The input sensitivity is adjusted by either changing a detection threshold of a comparator in the receive path or varying a gain of an input amplifier in the receive path. The high speed data signal is discerned when the low pass filter limits the response bandwidth of the receiver by a mode selection circuit which examines the duration of multiple pulses in a pulse train in the received data signal.

Disclosed is a circuit comprising a differential input amplifier stage, a capacitor stage, an inverter chain stage, and a biasing circuit. The inverter chain stage may be formed with or without feedback depending on whether a clock signal or data signal is to be translated using the disclosed circuit. The biasing circuit can be formed using either inverters or transmission gates. Moreover, the biasing circuit, the inverter chain stage, and the amplifier stage can be connected to a power down circuit which, when the translator is not being used, will ensure various circuitry of the translator will not consume extensive power. The inverter chain stage, biasing circuit, and capacitor stage are formed on both an upper and lower section to produce true and complementary outputs that have a consistent and equal delay from the transitions of the incoming differential input signal so as to minimize jitter and associated duty cycle of the translated output.

A modulated carrier signal is produced from a phase modulation signal in a phase locked loop in a polar modulator. This carrier signal is converted via a limiting amplifier to a square-wave signal, which is supplied to an amplifier. At the same time, an amplitude modulation signal at one input is connected to a control input of a controllable current source. The controllable current source is designed to emit a supply current at a current output as a function of the amplitude modulation signal at the control input. The current output of the controllable current source is connected to a supply input of the amplifier. The supply current for the amplifier is thus modulated on the basis of the amplitude information to be transmitted. The processing of the amplitude information within the current domain makes it possible to produce the polar modulator according to the invention as an integrated circuit, using CMOS technology.

The invention provides a mixed compensating type high-stability LDO (low-dropout regulator) chip circuit. The mixed compensating type high-stability LDO chip circuit comprises a differential input amplifier A1, a push-pull buffer amplifier A2, an integrated PMOS (p-channel metal oxide semiconductor) device P0, a resistor Rc, a resistor RF1, a resistor RF2, a capacitor Cc, a capacitor CFF, a chip output capacitor Cout, an equivalent series resistor Resr of the Cout and a chip output load Rload, and is characterized in that the A1 is in output connection with the A2, the Rc and the Cc are serially connected to be bridged at two ends of the A2, the A2 is in output connection with a grid electrode of the P0, a drain electrode of the P0 is an output end Vout and connected with one ends of the RF1, the Cout and the Rload, the RF1 and the RF2 are grounded in a series connection mode, the CFF is bridged at two ends of the RF1, an intersection of the RF1 and the RF2 is connected to an input negative terminal of the A1, the Cout and the Resr are grounded in a series connection mode, and the other end of the Rload is grounded. The mixed compensating type high-stability LDO chip circuit adopts ESR (equivalent series resistance) compensation, miller compensation and front feed-forward capacitance compensation, and stability of the LDO system is improved.

A data driving apparatus for a liquid crystal display device includes an output buffer for buffering and outputting a data voltage input from a digital-analog converter, wherein the output buffer includes an input amplifier for amplifying and outputting current proportional to the data voltage, an outputter for supplying a data voltage corresponding to the input data voltage to an output channel using charging and discharging current proportional to output current from the input amplifier, a control switch unit connected between the input amplifier and the outputter, for driving the outputter in a switching mode to precharge the output channel in a precharge period prior to a data supplying period in which the outputter outputs the data voltage, and a mode controller for controlling the control switch unit in response to an input control signal.

The invention relates to a method for transmitting memory data from a memory to a memory control module, in which method a read command is transmitted from the memory control module to the memory, and the memory data which correspond to the read command are transmitted from the memory to the memory control module, a sampling control signal which controls the acceptance of the memory data into the memory control module being transmitted from the memory to the memory control module in parallel with the memory data. In order to avoid defective data transmission between the memory and the memory control module as reliably as possible, the sampling control signal is transmitted with a preamble which indicates the imminent beginning of data transmission, for the sampling control signal to be monitored for the presence of the preamble, and for a data input amplifier of the memory control module to be switched on only when the presence of the preamble is detected.

Certain embodiments of the invention may be found in a method and system for minimizing power consumption in a communication system. Exemplary aspects of the invention may comprise configuring a supply voltage of an amplifier to enable communication of data using a first communication protocol during a first timeslot in a TDM frame, reconfiguring the supply voltage of the amplifier to enable communication of data using a different communication protocol, and adjusting the supply voltage of the amplifier in proportion to the envelope of a baseband signal conforming to one of the communication protocols. The first and second communication protocols may conform to various communication protocols, such as WCDMA, HSDPA, HSUDPA, GSM, GPRS, EDGE, WiMAX, OFDM, UWB, ZigBee, and Bluetooth. The baseband signal may be delayed by a number of samples before being input into the amplifier.

A signal acquisition system has a signal acquisition probe having probe tip circuitry coupled to a resistive center conductor signal cable. The resistive center conductor signal cable of the signal acquisition probe is coupled to a compensation system in a signal processing instrument via an input node and input circuitry in the signal processing instrument. The signal acquisition probe and the signal processing instrument have mismatched time constants at the input node with the compensation system having an input amplifier with feedback loop circuitry and a shunt pole-zero pair coupled to the input circuitry providing pole-zero pairs for maintaining flatness over the signal acquisition system frequency bandwidth.

One embodiment of the present invention provides a capacitively-coupled receiver amplifier that has an input with no DC coupling. A DC voltage is programmed on the input. During programming, a transmitter is held at a voltage at a midpoint between a voltage that represents a logical “1” and a voltage that represents a logical “0” and the input voltage of the receiver amplifier is programmed to be substantially the switching-threshold voltage for the receiver amplifier. Then, during normal data communication, the transmitter drives high and low electrical signals that are coupled to the receiver amplifier. Since the input of the receiver amplifier has been substantially set to the DC voltage, the receiver amplifier need not control the DC voltage of the input for each transition in the electrical signals.

A near field RF communicator has an antenna circuit (120) to receive a modulated radio frequency signal by inductive coupling and demodulation circuitry (130 or 131) to extract the modulation from a received modulated radio frequency signal inductively coupled to the antenna circuit. The demodulation circuitry has a virtual earth input comprising a current mirror. The demodulation circuitry may be formed by an amplifier (115 or 116) and a demodulator (114) coupled to an output of the amplifier. The amplifier may be a single input amplifier (116) coupled to an output of the antenna circuit or may be a differential amplifier (115) having first and second inputs to receive the modulated radio frequency signal from first and second outputs of the antenna circuit, with each amplifier input providing a virtual earth input.