1927results about "Dc-amplifiers with dc-coupled stages" patented technology

A logarithmic amplifier includes programmable gain amplifiers each having a different gain, wherein an input of each of the programmable gain amplifiers is coupled to an input of the logarithmic amplifier; and a summing circuit having inputs coupled to a corresponding output of each of the programmable gain amplifiers and an output coupled to an output of the logarithmic amplifier, wherein the summing circuit generates a logarithmic transfer function having piecewise linear segments.

The invention discloses a high-voltage power amplifier with an over-temperature and over-current protection circuit, and relates to the technical field of integrated circuits. The high-voltage operational amplifier comprises a high-voltage operational amplifier core unit and a self-adaptive protection circuit unit, the high-voltage operational amplifier core unit comprises a rail-to-rail input stage, a gain amplification stage and an AB type push-pull output stage which are sequentially cascaded, and the AB type push-pull output stage comprises a PMOS upper power tube and an NMOS lower power tube; the self-adaptive protection circuit unit comprises a PMOS (P-channel Metal Oxide Semiconductor) current-limiting protection circuit, an NMOS (N-channel Metal Oxide Semiconductor) current-limiting protection circuit and an over-temperature protection circuit; the PMOS current-limiting protection circuit is used for generating a high-voltage domain over-current control signal when the power tube on the PMOS is over-current; the NMOS current-limiting protection circuit is used for generating a low-voltage domain overcurrent control signal when the NMOS lower power tube is in overcurrent; the over-temperature protection circuit is used for generating high-voltage domain over-temperature turn-off signals and low-voltage domain over-temperature turn-off signals when the amplifier is over-temperature; and finally, carrying out logic synthesis on the corresponding over-current control signal and the over-temperature turn-off signal to generate a gate clamping signal.

The various implementations described herein include techniques and apparatuses for multi-channel biopotential signal acquisition, biopotential signal pre-processing, and adaptive signal conditioning. In one aspect, an analog frontend circuit includes an instrumentation amplifier (INA) and an analog-to-digital circuit (ADC) in a forward signal path. A digital circuit receives input from the ADC. An adaptive baseline tracking and compensation circuit tracks and compensates moving motion artifact driven changes. A power line interference (PLI) detection and compensation circuit tracks a desired number of PLI harmonics, and magnitude, phase and frequency for the PLI harmonics in real time. A digital-to-analog converter (DAC) circuit combines output of the adaptive baseline tracking and compensation circuit and the PLI detection and compensation circuit to output an analog output. A passive filter receives the analog output and drives an analog compensation signal at an input of the INA.

The invention discloses a noise elimination circuit structure, a low noise amplifier, a chip and electronic equipment. The noise elimination circuit structure comprises an input matching network; a common source stage amplification path connected with the first differential output end of the input matching network, comprising a first common source stage differential amplifier, and outputting an amplified first signal inverted from the radio frequency input signal to the ground; the common-gate amplification path is connected with the second differential output end of the input matching network, comprises a first common-gate differential amplifier and outputs an amplified second signal which is opposite to the radio frequency input signal to the ground; and the output end of the common-source amplification path and the output end of the common-gate amplification path are connected in parallel to form the output end of the noise elimination circuit structure. The common-source amplification path and the common-gate amplification path required by the noise elimination structure are realized by using one amplifier path, the utilization rate of the layout area is improved, the compactness of the layout is realized, and the amplifier can be widely applied to the field of communication or radar.

A calibration circuit includes a replica transconductance stage that is a replica of a transconductance amplifier in a serializer / deserializer (SerDes) interface and a replica transimpedance stage that is a replica of a transimpedance amplifier in the SerDes interface. The replica transimpedance stage has an input coupled to its output. A comparison circuit is configured to generate a difference signal representative of a difference between voltage levels of an input signal received at an input of the replica transconductance stage and an output signal representative of voltage level at the output of the replica transimpedance stage. Replica feedback resistors are configured to couple an output of the replica transimpedance stage to the input of the replica transconductance stage. The difference signal can be used to select resistance values provided by the replica feedback resistors and by corresponding gain control resistors in the transimpedance amplifier in the SerDes interface.

A system and method are used to maintain a variance in feedback factors of an amplifier between the first and second phases either below a threshold value or within a specified range. The system includes the amplifier and first through third capacitances. The amplifier is coupled between an input node and an output node that operates during first and second phases of operation. The first capacitance is coupled across the amplifier and between the input node and the output node during the first and second phases of operation. The second capacitance is coupled to the input node during the first phase of operation. The third capacitance is coupled to one of the input and output nodes during one or both of the first and second phases of operation.

The invention provides a fully differential operational amplifier circuit and an operational amplifier. The fully differential operational amplifier circuit comprises an input stage circuit, a gain stage circuit and a common-mode feedback circuit, the input stage circuit is used for processing a differential input voltage signal, converting the differential input voltage signal into a differential current signal and transmitting the differential current signal to the gain stage circuit; the gain stage circuit is used for performing gain processing on the differential current signal and outputting a target differential voltage signal; the common-mode feedback circuit is used for detecting the common-mode voltage of the target differential voltage signal, generating a common-mode feedback signal and transmitting the common-mode feedback signal to the gain-stage circuit to stabilize the common-mode voltage; wherein the gain stage circuit comprises a gain enhancement circuit, and the gain enhancement circuit is used for increasing the output impedance of the gain stage circuit. According to the chopping operational amplifier, the input stage circuit, the gain stage circuit, the common mode feedback circuit and the gain enhancement circuit are combined, so that the precision and the sensitivity of the chopping operational amplifier are improved.

The invention provides a dynamic residual amplification circuit based on charge sampling, and relates to the technical field of integrated circuits, the dynamic residual amplification circuit comprises an integrating circuit, a logic circuit, a charge pump and a zero-cross detection circuit, the integrating circuit is connected with the logic circuit and the zero-cross detection circuit, the integrating circuit converts a sampled input differential signal into a constant current, and the constant current is connected with the charge pump. The output node is continuously charged or discharged, so that the input differential signal is converted into a current integral quantity; the zero-cross detection circuit monitors the output voltage of the integrating circuit in real time, and when the output voltage is greater than or equal to the common mode voltage VCM, the moment when the output voltage is equal to the common mode voltage VCM is converted into a digital clock edge; the logic circuit is connected with the charge pump and outputs digital pulses to the charge pump according to the digital clock edge so as to control the reset time sequence of the whole dynamic residual amplification circuit; the charge pump is configured to output a residual voltage modulated by the digital pulse in response to the digital pulse. The application helps to improve the linearity of the residual signal.

An even harmonic multiplier employing complementary current reuse is disclosed. The even harmonic multiplier employs supply voltage and current density scaling to reduce power consumption. Further, by using complimentary NMOS and PMOS transistors, the even harmonic multiplier achieves high areal efficiency. Current reuse causes a reduction in noise at the first harmonic, as the corresponding first harmonic currents from the NMOS and PMOS transistors are in opposite, i.e., canceling, directions. Complementary current reuse is now feasible, as the performance of PMOS transistors at current process nodes is similar to those of NMOS transistors, with appropriate sizing leading to approximately equivalent transconductances. Multiple even harmonic multiplier configurations are possible, with many using transformer circuits at the input and / or the output. The resultant even harmonic multipliers find ready application in millimeter wave radio frequency receivers. The most common even harmonic multiplier is a frequency doubler, which produces a strong second harmonic signal.

The invention provides a correlated double-sampling program-controlled gain amplifier for a high-energy particle detection pixel sensor and an implementation method, and solves the technical problem that a large dynamic range and high readout precision cannot be considered at the same time during existing high-energy particle detection. The circuit comprises a correlated double-sampling circuit, a signal polarity conversion circuit, an amplification feedback circuit and a configuration automatic judgment circuit. The correlated double sampling circuit is used for performing double sampling on the output voltage of the pixel signal to obtain twice sampling voltage; the configuration automatic judgment circuit is used for selecting configurations for switching according to the voltage difference between the two sampling voltages to obtain an output signal; and the amplification feedback circuit is used for performing fixed gain voltage amplification on the output signal to obtain an amplified voltage signal. The circuit can be widely applied to the technical field of integrated circuits.

The invention discloses a multi-channel common-mode feedback high-gain amplification circuit. The circuit comprises a differential amplification module, an output end of which is connected with a load; the input end of the common-mode detection module is connected with the output end of the differential amplification module; the first input end of the error amplification module is connected with the output end of the common-mode detection module, and the second input end of the error amplification module receives reference voltage; and the multi-path feedback control module comprises at least two feedback branches which are connected in parallel, the input ends of the feedback branches are jointly connected with the output end of the error amplification module, the output ends of the feedback branches are respectively connected with different bias nodes in the differential amplification module, and the feedback branches have path impedance with gradient change. Through a dynamic division mechanism of a feedback branch, and in combination with a gain boosting unit and a hybrid compensation network, high-precision rapid establishment under a high-speed load is realized.

A class D amplifier circuit receives an analog audio signal with a first reference voltage as its center level, and outputs an output pulse signal having a duty cycle that corresponds to the analog audio signal. A bias circuit generates a second reference voltage having a voltage level obtained as a division of the first reference voltage and the power supply voltage. A periodic voltage generating circuit of the class D amplifier circuit generates a periodic voltage having a triangle waveform or otherwise a sawtooth waveform having an amplitude that corresponds to the second reference voltage.

The invention relates to the technical field of signal processing, in particular to a microseismic sensor front-end signal conditioning circuit based on lag correction frequency expansion. The microseismic sensor front-end signal conditioning circuit based on lag correction frequency broadening comprises a differential amplification circuit used for converting a differential signal input by a microseismic sensor into a single-ended vibration signal and carrying out pre-amplification processing on the vibration signal according to a preset gain to obtain an amplified vibration signal; and the filtering and lag correction circuit is used for widening the frequency range of the amplified vibration signal in a filtering and lag correction mode to obtain a conditioned vibration signal. According to the invention, frequency expansion can be carried out on the magnetoelectric sensor through a low-frequency compensation technology, and the response capability of the magnetoelectric sensor to a low-frequency signal is improved.

An electronic device may include wireless circuitry. The wireless circuitry can include a first input transistor, a first capacitance neutralization having a source terminal coupled to a tail node, and a second order intermodulation generation circuit configured to produce second order intermodulation signals at the tail node. The wireless circuitry can further include a second input transistor and a second capacitance neutralization transistor having a source terminal coupled to the tail node. The first and second capacitance neutralization transistors can be cross-coupled with the input transistors. A fixed or adjustable current source can be coupled to the tail node. The second order intermodulation generation circuit can include a transistor biased in a weak inversion mode.

A semiconductor device has an amplifier and common mode suppression (CMS) circuit formed on a common substrate. The CMS circuit has a first input and second input coupled for receiving an input signal and further has a first output coupled to a first input of the amplifier and a second output coupled to a second input of the amplifier to reduce common mode. The CMS circuit further has a ground plane, a first conductive trace disposed over the ground plane and coupled between the first input and first output, second conductive trace disposed over the ground plane and coupled between the second input and second output, and third conductive trace disposed over the ground plane with a first end of the third conductive trace coupled to the ground plane and a second end of the third conductive trace open circuit to form a resonator.

An error amplifier includes a first transistor having a first error amplifier input and having first and second current terminals, a second transistor having a second error amplifier input and having third and fourth current terminals, a first resistor coupled between a supply voltage terminal and the first current terminal, and a second resistor coupled between the supply voltage terminal and the third current terminal. The error amplifier has a second stage circuit coupled to the first and second resistors. The second stage circuit has an error amplifier output. The second stage circuit is configured to cause less current to flow through the second stage circuit than a current that flows through either of the first or second resistors or the first or second transistors.

The invention describes a Josephson parametric amplifier and a manufacturing method thereof. The broadband Josephson parametric amplifier comprises: a substrate; a coplanar waveguide disposed on the substrate, the coplanar waveguide having an impedance that varies in a length direction thereof, in which the coplanar waveguide includes a conductor separated from a first ground plane by a first gap and separated from a second ground plane by a second gap; and a non-linear resonator disposed on the substrate and coupled to the coplanar waveguide.

The ultralow frequency sensor comprises a vibration detection unit, a power supply voltage stabilization unit and a signal conditioning unit, the power supply voltage stabilization unit is provided with a low dropout linear voltage regulator U20, a voltage converter U19 and a negative voltage regulator U21, and the low dropout linear voltage regulator U20 stabilizes an external power supply as a positive power supply VCC; the voltage converter U19 is used for converting positive voltage of an external power supply into negative voltage and outputting stable negative power supply VEE through the negative voltage stabilizer; the positive power supply VCC and the negative power supply VEE supply power to the signal conditioning unit; the signal conditioning unit comprises a high common mode rejection differential amplifier, a differential-to-single-ended amplifier, a band-pass filter and a differential output driver, a differential signal output by the vibration detection unit sequentially passes through the high common mode rejection differential amplifier, the differential-to-single-ended amplifier, the band-pass filter and the differential output driver, and then a differential voltage signal is output; the method has the advantages of high stability and reliability and the like.

A virtual radio frequency (VRF) equalizer for an envelope tracking integrated circuit (ETIC) is disclosed. In one aspect, an ETIC provides envelope tracking (ET) for a barely Doherty (BD) power amplifier stage. The VRF equalizer includes circuitry that provides ripple cancelation that is caused by load modulation of the BD power amplifier stage. Additional circuitry is included to compensate for an amplifier within the ETIC. By canceling the ripple within the ETIC, the overall performance and efficiency of the BD power amplifier stage is improved, resulting in better performance of a transmitter in a wireless communication device.

A cascade amplification circuit module based on complementary parameter amplifiers belongs to the technical field of integrated circuit amplifiers and comprises a first-stage complementary parameter amplifier (CPA) and a second-stage amplifier (floating inverting type or transconductance resistance type). The first-stage CPA adopts an NMOS and PMOS complementary structure, passive amplification is achieved through grid multiplexing, a grid capacitor is used for storing signals in the sampling stage, a depletion layer capacitor is switched to improve gain in the amplification stage, common-mode voltage is stabilized through complementary design, and an extra feedback circuit is not needed. And the second-stage amplifier provides driving capability and is combined with passive gain to suppress noise. The cascade structure does not need frequency compensation, the design is simplified, the problem of balancing gain, noise and power consumption of a traditional amplifier is solved, and the cascade amplifier has the advantages of being high in energy efficiency and low in complexity.

The invention relates to the technical field of amplifiers, and discloses an analog-to-digital converter combination instrument amplifier which comprises a first-stage amplifier, the first-stage amplifier is in signal connection with a second-stage amplifier, the second-stage amplifier is in signal connection with a front-end low-pass filter (LPF), the front-end low-pass filter (LPF) is in signal connection with an analog-to-digital converter (ADC), and the analog-to-digital converter (ADC) is in signal connection with the analog-to-digital converter. And an unbalanced input-to-balanced differential circuit output module is arranged between the second-stage amplifier signal and a front-end low-pass filter (LPF). From the perspective of signal processing and conversion, a precise signal transition bridge is constructed by adding an unbalanced input-to-balanced differential circuit output module, unbalanced signals output by a second-stage amplifier are converted into double-end balanced differential signals, common-mode noise interference is effectively resisted through a differential transmission mode, the signal purity is guaranteed, and the signal quality is improved. The front-end low-pass filter and the analog-to-digital converter are adaptive to differential signals, so that the signal transmission is stable and anti-interference, and the analog-to-digital conversion is more accurate.

A current sense amplifier measures a voltage drop in a drive transistor LS to measure the current flowing through the drive transistor LS. The current sense amplifier includes a preamplifier pre-amp, to which a voltage across the drive transistor LS is inputted, and which obtains a positive output and a negative output corresponding to a voltage difference of the inputted voltage across the drive transistor; and a switch sw, which connects the input end of a common mode voltage vcm and the negative output, the common mode voltage vcm serving as the operation reference of the preamplifier pre-amp. A change of the positive output caused by turning on / off the switch sw can be detected.

Provided is a potentiostat-based electrochemical sensor detection device. The device comprises: a digital-to-analog converter (DAC) configured to receive a digital signal from a waveform generator and digital logic and output an analog signal corresponding to a reference voltage; a control amplifier (CA) configured to receive the analog signal corresponding to the reference voltage and apply the reference voltage to a reference electrode (RE); a gain-boosting current mirror configured to copy a sensor current of an electrochemical sensor and output a copied sensor current; a transimpedance amplifier configured to convert the copied sensor current into a voltage signal; a low-pass filter configured to block a high-frequency band signal component of the voltage signal; and an analog-to-digital converter (ADC) configured to perform digital signal processing on a signal having passed through the low-pass filter, wherein at least one of the gain-boosting current mirror and the transimpedance amplifier employs a dynamic element matching (DEM) technique using a plurality of choppers and a plurality of DEM clock signals.

The invention belongs to the technical field of integrated circuits, and particularly relates to a radio frequency amplifier bandwidth expansion circuit based on resistor-capacitor series feedback. The bandwidth expansion circuit comprises a first-stage common-gate amplifier, a second-stage common-source amplifier, a transformer-based inter-stage matching network between the two stages of amplifiers, and two resistor-capacitor series feedback paths, and a resistor-capacitor series feedback path is bridged at two sides of the interstage matching network, and feedback is introduced from the output end of the common source amplifier to the output end of the common gate amplifier, so that the quality factors of two resonant cavities of the interstage matching transformer are adjusted, and the targets of adjusting the gain of the amplifier and expanding the bandwidth of the radio frequency amplifier are further realized.

A method is provided for use in a sensor, comprising: generating a sensing signal by using one or more sensing elements; amplifying the sensing signal by using a first gain to produce, at least in part, a first amplified signal, the first amplified signal having a first offset; amplifying the sensing signal by using a second gain to produce, at least in part, a second amplified signal, the second amplified signal having a second offset; generating an adjusted signal based on the first amplified signal, the second amplified signal, the first gain, and the second gain, the adjusted signal approximating a difference between the second amplified signal and an offset of the second amplified signal; and using the adjusted signal to generate an output of the sensor.

According to an embodiment, An integrated circuit comprising a first cascode radio frequency (RF) power amplifier that includes a first common source transistor having a gate configured to receive a first RF signal, and a source connected to a neutral point; a first common gate transistor having a gate and a drain connected to a power source node, and a source connected to a drain of the first common source transistor; and a first resistor coupled between a bulk of the first common gate transistor and a first bulk bias node configured to provide a voltage that is greater than or equal to a voltage at the source of the first common gate transistor, wherein the first resistor is configured to obtain a floating point.

A fully differential switched capacitor amplifier receives a differential analog signal from a differential input terminal, amplifies the differential analog signal, and outputs an amplified signal from a differential output terminal. The fully differential switched capacitor amplifier includes: a sampling capacitor that respectively samples the differential analog signal input from the differential input terminal; a differential input switch connected to a path for inputting the differential analog signal between the differential input terminal and the sampling capacitor; a fully differential amplifier that amplifies the differential analog signal input to the sampling capacitor; and a differential input resistor connected between the differential input switch and the sampling capacitor.