64 results about "Common mode feedback" patented technology

This disclosure describes an apparatus that enables rapid transitions during microwave-assisted magnetic recording (MAMR) of storage media. In various aspects, the apparatus incorporates a driver circuit configured to provide a controlled bias current through separate source and sink output terminals, which respond to feedback signals. An MAMR sensor connects between the source and sink output terminals and generates microwave fields when receiving the controlled bias current from the driver circuit. A common-mode feedback (CMFB) loop connects to the source and sink output terminals, detects common-mode voltage (CMV), and delivers feedback signals to the driver circuit to maintain CMV regulation of the MAMR sensor. A differential voltage regulation loop connects to the source and sink output terminals, providing feedback signals that maintain the MAMR sensor voltage differential at a reference value. The apparatus controls the magnetic recording process of the MAMR sensor with rapid transition times.

The invention relates to a low-power-consumption high-performance D-type power amplifier modulation method and circuit and a D-type audio power amplifier, and the method comprises the steps: separating a pair of BD mode modulated signals outputted by a PWM modulation module in the D-type audio power amplifier circuit into a common mode component and a differential mode component, and outputting the common mode component and the differential mode component; feeding back the common-mode component and the differential-mode component to a differential input end through a common-mode feedback link and a differential-mode feedback link respectively; wherein the common-mode component and the common-mode feedback link are completely arranged in the chip; the differential mode component and the differential mode feedback link are realized by a power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) integrated inside the chip or an external power MOSFET; and outputting the differential mode component to a to-be-driven object through the power output stage. According to the method, after two feedback links are separated, in a zero-input mute state, no common-mode signal is sent to an output stage for amplification, and power consumption is not caused at the output stage, so that the overall efficiency is greatly improved; and meanwhile, static bottom noise is almost eliminated.

The application provides a common-source common-gate amplifier, comprising a signal input module, which is used for generating an input signal according to a power supply voltage; a cross-coupling module, which is electrically connected with the signal input module and is used for forming internal positive feedback according to an output signal; a first biasing module, which is electrically connected with the cross-coupling module; a first branch module, which is electrically connected with the first biasing module; a second biasing module, which is electrically connected with the cross-coupling module; a second branch module, which is electrically connected with the second biasing module; wherein the first biasing module and the second biasing module are used for providing biasing after an input common-mode feedback voltage, the first branch module and the second branch module are used for providing large-swing output biasing, and the first branch module and the second branch module are respectively electrically connected with the signal input module, and the signal input module is further used for outputting branch signals to the first branch module and the second branch module. The application improves the voltage swing, the gain and the bandwidth of the circuit under the single-stage amplifier structure.

This application provides an operational amplifier that increases the stability and settling speed of a common-mode feedback circuit. The operational amplifier includes N stages of amplifiers connected in series and M common-mode feedback circuits, where N and M are integers, N≥3, and N≥M>1. An ith common-mode feedback circuit in the M common-mode feedback circuits is configured to: detect a common-mode output voltage of a (j+b)th stage of amplifier, and regulate an electrical parameter of at least one of the jth stage of amplifier to the (j+b)th stage of amplifier, to stabilize the common-mode output voltage of the (j+b)th stage of amplifier. An Mth common-mode feedback circuit is configured to detect and stabilize a common-mode output voltage of an Nth stage of amplifier. Herein i, j, and b are integers, M≥i≥1, N≥j≥1, i≥j, j+b≤N, and b≥0.

This application provides a buffer and chip. The buffer includes a first conversion circuit, a second conversion circuit, and a common-mode feedback circuit. The first conversion circuit outputs a first output signal based on a first input signal, a first bias voltage, and a first substrate bias voltage of a first main input transistor. The first substrate bias voltage includes an initial and an adjusted first substrate bias voltage. The second conversion circuit outputs a second output signal based on a second input signal, the first bias voltage, and a second substrate bias voltage of a second main input transistor. The second substrate bias voltage includes an initial and an adjusted second substrate bias voltage. The common-mode feedback circuit generates a common-mode signal based on the first and second output signals. Based on the common-mode signal and a target voltage value, it generates and adjusts the first and second substrate bias voltages based on the feedback signal. Because the common-mode feedback circuit adjusts the substrate voltage of the main input transistor, it maintains the stability of the common-mode signal, thereby improving the linearity and stability of the buffer.

This invention relates to the field of high-resolution time measurement systems and integrated circuit technology, providing a time measurement circuit with a two-dimensional address-modulated TOT pulse, comprising: a common-gate transimpedance amplifier, a high-speed high-gain comparator, a current-mode logic output stage, a common-mode feedback threshold setting circuit, and a two-dimensional address-modulated TOT pulse circuit; the address modulation pulse circuit includes an address modulation pulse width circuit and an address modulation pulse amplitude circuit, wherein the address modulation pulse width circuit includes: multiple sets of first modulation units, multiple sets of second modulation units, multiple inverters, and multiple bits of first digital code; the address modulation pulse amplitude circuit includes: multiple sets of third modulation units and multiple bits of second digital code. This invention allows a single TOT signal to simultaneously carry time information, energy information, and address information, reducing wiring, improving reliability, and increasing integration density.

The invention provides an operational amplifier and a layout structure thereof. The layout structure comprises a first layout area, a second layout area and a third layout area which are sequentially arranged along a first direction, a first compensation capacitor array area and a second compensation capacitor array area are respectively arranged in the first layout area and the third layout area; a differential pair transistor region, a first common-mode feedback region, a first load region, a second load region, a second common-mode feedback region and an amplifying circuit output region which are sequentially arranged along a second direction are arranged in the second layout region, and the first chopping region and the second chopping region are arranged on two sides of the first load region or the second load region along the first direction; the first chopping region is close to the first layout region, and the second chopping region is close to the third layout region. According to the method, the layout design work of the differential pair in the simulation layout design can be effectively and quickly realized, the process dependence is reduced, the structure of the differential pair can be strictly controlled, and the high symmetry is ensured.

This invention provides a transmitter circuit for a CAN bus, relating to the field of CAN bus communication. The circuit includes: a common-mode feedback circuit for generating first and second gate voltages; a slew rate control circuit comprising a CANH terminal circuit for receiving the first gate voltage and a CANL terminal circuit for receiving the second gate voltage, each terminal circuit including multiple sequentially connected delay units and power transistors, the delay units controlling the gate voltage of the power transistors stage by stage to alternately switch the power transistors; and a port positive and negative high-voltage protection circuit, respectively connected between the output terminals of the CANH and CANL terminal circuits and the bus port, for protecting against positive and negative high voltages on the bus and suppressing parasitic effects. The beneficial effects are: by controlling the switching of the power transistors stage by stage through the delay units, the current surge rate is reduced, and electromagnetic radiation is reduced; by stabilizing the gate voltage and balancing the output current through common-mode feedback, signal symmetry is improved and common-mode interference is suppressed.

The invention discloses a fully differential amplifier circuit with rail-to-rail output. The fully differential amplifier circuit comprises a main amplifier circuit, a first-stage common-mode feedback circuit, a second-stage common-mode feedback circuit and a voltage regulation circuit. The main amplifier circuit comprises a first-stage main amplifier and a second-stage main amplifier which are cascaded; the first-stage common-mode feedback circuit comprises an amplifier Af1, a first input end of the amplifier Af1 is connected to the first-stage differential output end, a second input end of the amplifier Af1 is connected with a first reference voltage end, and the amplifier Af1 compares common-mode voltage output by the first-stage main amplifier with first reference voltage VREF1 and feeds back error quantity to the first-stage main amplifier; the second-stage common-mode feedback circuit comprises an amplifier Af2; the input end of the voltage adjusting circuit is connected with the output end of the amplifier Af2, and the output end of the voltage adjusting circuit provides adjustable first reference voltage for the first reference voltage end. According to the circuit, it can be guaranteed that the output common-mode level is fast and stable, and rail-to-rail output is achieved.

The invention discloses a bipolar voltage-time converter based on phase inverter threshold detection. The bipolar voltage-time converter is characterized in that a differential sampling circuit is connected with a sign bit comparator and a bipolar voltage-time conversion circuit; the sign bit comparator is used for receiving the differential sampling voltage output by the differential sampling circuit and judging the polarity of an input differential analog signal, and is connected with the bipolar voltage-time conversion circuit to output a sign bit signal and a polarity control signal; the bipolar voltage-time conversion circuit is used for charging or discharging the differential sampling voltage under the control of the polarity control signal to generate two paths of voltage ramp signals with opposite polarities, and is connected with the common-mode feedback circuit and the inverter threshold detection circuit; the common-mode feedback circuit is used for detecting a common-mode level of the differential sampling voltage or two paths of voltage ramp signals; the threshold voltage of the inverter threshold detection circuit is configured to be a predetermined common-mode level, and is used for detecting a crossover event of the two voltage ramp signals at the predetermined common-mode level and outputting a threshold detection signal.

The present disclosure describes aspects of a differential current-mode (iMode) driver for microwave-assisted magnetic recording (MAMR) application in hard-disk drives. In some aspects, an iMode driver circuitry employs a driver circuit coupled to power supply connections. The driver circuit is configured to provide a controlled differential bias current and includes separate source and sink output terminals. A MAMR sensor couples between the source and sink output terminals, through which the MAMR sensor receives the controlled differential bias current provided by the driver circuit. The MAMR sensor, which has a field-entry terminal and a field-exit terminal, generates microwave fields for the recording process. A common-mode feedback (CMFB) loop couples to the field-entry and field-exit terminals of the MAMR sensor, forming a feedback pathway with the driver circuit. This CMFB loop detects common-mode voltage (CMV) and adjusts the controlled differential bias current to maintain CMV regulation of the MAMR sensor.

In some aspects, the disclosure is directed to methods and systems for an amplifier having common mode feedback inputs. The inputs are coupled to various points within an amplifier wherein a first set of directly coupled common mode feedback inputs join the amplifier one or more nodes, and a second set of capacitively coupled common mode feedback inputs are joined to the amplifier at one or more different nodes.

A common-mode feedback circuit for a fully differential amplifier comprises first (MB), second (MTP), and third (MTN) transistors, each having a respective drain, source, gate, and back-gate terminals. The drain terminal of the first transistor (MB) and the gate terminals of the first, second, and third transistors (MB, MTP, MTN) are connected together at a bias current terminal. The drain terminals of the second and third transistors are connected together at a tail current terminal. The source terminals of the first, second, and third transistors are connected together. The back-gate terminal of the first transistor (MB) is arranged to receive a common-mode reference voltage input (VCM), the back-gate terminal of the second transistor (MTP) is arranged to receive a positive output voltage (VP) from the fully differential amplifier, and the back-gate terminal of the third transistor (MTN) is arranged to receive a negative output voltage (VN) from the fully differential amplifier.

An operational amplifier includes a first stage of the current-reuse type; and a second stage of the rail-to-rail type, cascaded with respect to the first stage. The first stage comprises a first feedback assembly configured to define a first common mode feedback loop. The second stage comprises a second feedback assembly configured to define a second common mode feedback loop. The first and second common mode feedback loops, of the first and second stages, respectively, are independent of each other.

A signal amplifying circuit includes an amplifier and a common mode feedback circuit. The amplifier generates first and second outputs. The common mode feedback circuit receives the first and second outputs, and controls an output common mode voltage of the first and second outputs to a first reference voltage. The common mode feedback circuit includes an output common mode voltage detection circuit, a pull-up circuit and a pull-down circuit. The output common mode voltage detection circuit generates first and second control signals according to the output common mode voltage. The pull-up circuit with a first conduction degree controlled by the first control signal controls the output common mode voltage to be positively correlated with the first conduction degree. The pull-down circuit with a second conduction degree controlled by the second control signal controls the output common mode voltage to be negatively correlated with the second conduction degree.

The application provides a common-mode feedback circuit with a level conversion function, comprising an amplifier output stage, a resistive common-mode feedback circuit and an amplifier common-mode feedback circuit, the amplifier output stage comprising a first current source I1, a second current source I2, a tail current source I3, input pair tubes M1 and M2 and a common-mode adjusting tube M3, the resistive common-mode feedback circuit comprising a first resistor R1 and a second resistor R2, and the amplifier common-mode feedback circuit comprising a third resistor R3, a fourth resistor R4 and a first operational amplifier AMP1, V OP and V ON The input ports of the resistive common-mode feedback circuit and the amplifier common-mode feedback circuit are commonly connected, for detecting the common-mode voltage and adjusting the common-mode adjusting tube at the same time. The scheme introduces the fast response advantage of the amplifier feedback on the basis of the resistive feedback, realizes the accurate control and dynamic adjustment of the common-mode level, and makes the output common-mode voltage be flexibly set by integrating the level conversion function in the feedback loop, so that the transient response speed of the system is significantly improved.

A system may include a pulse-width modulation mode path configured to drive a load at an output of the system in a first mode of operation, a linear mode path configured to drive the load in a second mode of operation, a common mode control feedback loop configured to set a value of a common mode output signal at the output in the second mode of operation, and an auxiliary circuit coupled to the common mode feedback control loop and configured to maintain a state of the common mode feedback control loop during the first mode of operation as the state was or will be during the second mode of operation.

The present application relates to a kind of earphone type brain electricity collection front-end anti-interference system, including electrode acquisition unit, static electricity protection unit, front-end pollution suppression unit, input anti-interference filter unit, analog front-end acquisition unit, common mode feedback / bias drive unit, power supply and reference stable unit, common ground layout unit, interference monitoring unit and anti-interference control unit.The earphone type brain electricity collection front-end anti-interference system, method, device, processor and its computer readable storage medium of the present application are used, the interference of two different sources of transient impact and chronic leakage can be more accurately governed, the common mode rejection ratio can be improved, baseline drift caused by wearing state change, high impedance contact and human coupling can be reduced, overall noise can be reduced, and data stability and availability can be improved in brain electricity collection and wireless communication concurrent scene.

A low-power programmable gain amplifier (PGA) with 3dB out-of-band amplification is based on a second-generation current conveyor structure of foldable source follower, which comprises a common-mode feedback loop, a DC offset self-calibration loop, a fast start circuit and a dynamic bias circuit. The programmable gain amplifier amplifies narrow-band signals with 3dB out-of-band, changes the bandwidth by adjusting the tail current with digital signals, and then changes the gain size, thereby building a bridge between power consumption and gain. The gain and power consumption are positively correlated, and the effect of dynamic low power consumption is achieved. The common-mode feedback loop controls the PGA output DC point at V DD / 2, so that the PGA output has the maximum swing. The DC offset self-calibration loop suppresses the output DC offset of the PGA through voltage-current negative feedback. The fast start circuit is used to ensure smooth and fast start of the PGA. The dynamic bias circuit is used to provide current bias to control the gain of the PGA.

The application discloses a common-mode feedback device, comprising: a full-differential single-stage amplification unit, a low-frequency high-gain unit, a high-frequency feedforward path unit and a common-mode extraction network unit; the full-differential single-stage amplification unit is connected with the low-frequency high-gain unit through the common-mode extraction network unit; the high-frequency feedforward path unit is connected with the full-differential single-stage amplification unit and the low-frequency high-gain unit; the full-differential single-stage amplification unit, the low-frequency high-gain unit and the high-frequency feedforward path unit are connected with a power supply. The application applies the feedforward compensation idea of a low-frequency high-gain channel and a high-speed channel of a source high-frequency channel to the common-mode feedback device, and realizes the effect of considering high gain and high phase margin of a common-mode feedback loop under a wide frequency band.

Disclosed in the present invention is a two-stage cascaded high-gain amplifier based on adaptive biasing and cascode compensation. Said amplifier uses the basic structure of a two-stage cascaded amplifier, where a first stage uses an adaptively biased cascode floating inverting amplifier structure, which significantly improves the gain by means of cross-coupled biasing while obtaining a larger current to increase the bandwidth and slew rate, and eliminates the need for an external biasing circuit and an additional common-mode feedback circuit, and a second stage uses a current-source-biased inverting amplifier structure, which achieves a higher current efficiency by means of current reuse, and obtains a larger output swing. In addition, the present invention uses a cascode compensation circuit to eliminate the need for a nulling resistor required for Miller compensation, and offers overall advantages of high gain and high speed.

A preamplifier includes an operational transconductance amplifier, a first-type metal-oxide-semiconductor (MOS) transistor have a gate electrically coupled to the OTA output; a first second-type MOS transistor; a second second-type MOS transistor electrically connected in parallel with the first second-type MOS transistor; a first load resistor electrically connected in series with a drain of the first second-type MOS transistor that has a first output voltage; a second load resistor electrically connected in series with a drain of the second second-type MOS transistor that has a second output voltage; a tail node electrically connected to a source of the first second-type MOS transistor, a source of the second second-type MOS transistor, and a drain of a third second-type MOS transistor; a common-mode feedback circuit electrically coupled to the first and second output voltages and to a first OTA input; and a reference voltage electrically coupled to a second OTA input.

The invention discloses a device for improving bus common-mode voltage offset of a CAN (Controller Area Network) transceiver and the CAN transceiver. The device comprises a main driving module, a common-mode clamping module and a slope control module, the common mode clamping module and the slope control module are connected between the CAN high side CANH and the CAN low side CANL; the output end of the common-mode clamping module is connected with common-mode feedback nodes of the CANH and the CANL; the main driving module is used for generating a slope control signal according to a set time sequence control logic; the common-mode clamping module is used for generating common-mode clamping voltage at common-mode feedback nodes of the CANH and the CANL; and the slope control module is used for generating bias current based on the common-mode clamping voltage after the slope control enable signal is enabled, and generating a discharge current path which flows from the CANH and the CANL to the circuit operational amplifier node and is controllable in size based on the bias current and the slope control signal. By using the scheme of the invention, the EMC characteristic of the CAN transceiver can be optimized, and the common mode stability and the system robustness can be ensured.

This invention relates to the field of electroencephalogram (EEG) data acquisition technology, and discloses a 16-channel EEG acquisition circuit system and a human-computer interaction panel. The system includes a signal input module, a signal preprocessing module, an analog-to-digital converter (ADC) module, a human body protection circuit, a control platform, and a power management module. The signal input module protects the input port with an electrostatic discharge (ESD) protection device. The signal preprocessing module uses a low-pass filter circuit to filter out high-frequency noise. The ADC module includes at least two multi-channel ADCs connected in a collaborative manner to achieve serial output of 16 channels of data from a single port, and synchronous sampling is ensured by a shared clock signal. The human body protection circuit limits the amount of current flowing into the human body in the common-mode feedback output line. The human-computer interaction panel obtains the system's absolute time through a time synchronization mechanism and generates relative time information based on the local timing unit. The absolute time and relative time are used together to characterize the actual acquisition time of the EEG data. This invention achieves high-security, high-stability, and high-precision synchronous acquisition of EEG data, and features strong anti-interference capability, flexible power supply, convenient interactive configuration, and good time consistency.

The invention discloses a sampling hold circuit of a pipelined analog-to-digital converter, which relates to the technical field of integrated circuits of analog-to-digital converters and comprises an input amplifier, an output amplifier, an output common-mode feedback module and a sampling hold signal common-mode feedback module. Wherein the input end of the input amplifier is connected with a sampling input signal, the output end of the input amplifier is connected with the input end of the output amplifier, and the output end of the output amplifier is respectively connected with the input end of the assembly line analog-to-digital converter and the input end of the output common-mode feedback module; the output end of the output common-mode feedback module is connected to the input end of the sampling and holding signal common-mode feedback module, and the output end of the sampling and holding signal common-mode feedback module is connected to the input end of the output amplifier. The technical problem that high index requirements are difficult to pursue on the premise of low area and power consumption in the prior art is solved.

The application belongs to the technical field of integrated circuit design, and relates to a variable output range full differential high voltage driver applied to an accelerometer. The application introduces a programmable control high voltage output charge pump to generate a variable high voltage output for the full differential high voltage driver on the basis of a conventional fixed range output full differential high voltage driver; and utilizes a variable resistor to sample the output voltage of the full differential high voltage driver and a stable common mode voltage in a normal voltage circuit part of the accelerometer to compare and realize the purpose of stabilizing the common mode output voltage of the high voltage driver. Because the output of the charge pump often has a large ripple and is greatly affected by power supply fluctuation, directly sampling half of the output voltage of the charge pump as the common mode reference voltage of the high voltage driver is easy to make the common mode feedback inaccurate; by adopting the architecture of the full differential operational amplifier combining the floating current source and the AB class output to increase the power supply rejection ratio, improve the power utilization rate and reduce the static power consumption of the high voltage driver.

According to the duty ratio calibration circuit and the differential clock signal generation device provided by the invention, the duty ratio of an external clock signal can be calibrated to 50% through a collaborative architecture of the common-mode feedback circuit module and the driving circuit module and by adopting a full-analog circuit. A common-mode feedback circuit module collects common-mode levels of differential signals output by a driving circuit in real time, the common-mode levels are directly compared with reference voltage vref to generate a pair of differential control voltages, and then the driving circuit module dynamically corrects input external differential clock signals according to the two signals. The whole process does not need time-consuming links such as ADC analog-to-digital conversion and digital logic operation, the delay problem of a traditional scheme is thoroughly avoided, microsecond-level and even nanosecond-level real-time calibration is finally achieved, the core requirements for rapid initialization when a high-speed system is started and coping with sudden duty ratio deviation in operation can be accurately matched, and the real-time calibration accuracy of the high-speed system is improved. And the overall response efficiency of the system is greatly improved.

The present invention achieves a technology that makes it possible to independently adjust loop gains of a low-frequency path and a high-frequency path of a CMFB circuit, and that improves ease of design.　This technology provides an amplifier circuit comprising: a fully differential amplifier that amplifies a differential signal; and a common mode feedback (CMFB) circuit that stabilizes an output common mode voltage of the fully differential amplifier. The CMFB circuit has a low-frequency path that generates a first feedback signal, and a high-frequency path that generates a second feedback signal. The fully differential amplifier has a differential input transistor pair, and a tail current source that is connected to a common source of the differential input transistor pair. The tail current source is divided into a first current source and a second current source. The low-frequency path supplies the first feedback signal to the first current source and the second current source. The high-frequency path supplies the second feedback signal to the second current source.

The present invention relates to a differential envelope detector, which comprises: input terminals for separating cathode and anode components from a signal and receiving same; a first voltage output unit for outputting a first common mode voltage between the input terminals; a first amplification unit, which receives an input signal as a differential pair and amplifies same so as to output a first output signal; a second amplification unit, which receives the first common mode voltage so as to output a second output signal; and a second voltage output unit for outputting a second common mode voltage between a constant current source unit and an output terminal, wherein the output size of the detector is hardly affected by temperature changes, and an output DC voltage is also fixed so as to be effective with respect to input bias of the next stage amplifier.

Technologies for providing passive equalization with front-end level shifter (FELS) are described. One receiver device includes an input terminal, an analog signal processing circuit; and a front-end equalizer circuit coupled between the input terminal and the analog signal processing circuit. The front-end equalizer circuit includes a programmable common mode feedback (CMFB) circuit and a passive resistor-inductor-capacitor (RLC) network. The programmable CMFB circuit can receive, from the input terminal, an incoming agnostic common-mode (CM) signal having a first voltage level and a differential peak-to-peak voltage in at least one of an alternating current coupled mode (AC-coupled mode) or a direct current-coupled mode (DC-coupled mode). The programmable CMFB circuit can level shift the incoming agnostic CM signal to a CM signal having a second voltage level using an adjustable current source, the second voltage level corresponding to the analog signal processing circuit.