39 results about "Phase margin" patented technology

The invention discloses a single-loop droop control method and system for a wind generating set, and the method comprises the following steps: constructing a doubly-fed fan-power converter-power grid three-module coupling model, and completing the dynamic adaptation of the characteristics of a doubly-fed fan of a single-loop droop control architecture without inner-loop current control; based on the input signal-model collaborative integration body and the adaptive architecture, MIMO-GBC is adopted to analyze a phase margin and a resonance peak value of an open-loop transfer function matrix eigenvalue of a dynamic small signal model, and double risks are identified in a full slip rate interval; aiming at the resonance risk, a current induction type virtual impedance strategy is adopted; aiming at insufficient phase margin, adopting a transient phase calibration strategy; and according to the real-time slip ratio of the DFIG and the stator power change, inter-partition linkage optimization is carried out on the virtual resistance and the phase calibration angle so as to minimize a dual-power step response fluctuation square mean value, a parameter setting period and a rotor side converter control period are synchronously matched, and all-working-condition stable control is realized.

The invention belongs to the technical field of stability compensation circuits, and particularly relates to a stability compensation circuit structure of a high-speed operational amplifier, which is characterized by comprising a function module, a first control module, a second control module, a third control module, a fourth control module and a fourth control module, and the function module comprises an input stage, a differential common-base gain stage, a common-base level converter module and an output stage, and the stability compensation assembly comprises a dual-frequency load unit which is matched with the functional module and comprises a low-frequency load branch and a high-frequency load branch which are connected in parallel. Through the synergistic effect of the double-frequency load unit and the pole regulation and control capacitor, gain segmentation regulation and control of low-frequency high gain and high-frequency fast attenuation are achieved, the open-loop gain of the operational amplifier breaks through the limitation of 30dB of an existing HBT single-stage operational amplifier, and meanwhile the problem that high-frequency phase shift changes too fast is effectively restrained; through simulation verification, the phase margin can reach 67 degrees, the stability requirement of 45-60 degrees and above of an analog circuit is met, and the core contradiction that the high-gain bandwidth and the phase margin of an HBT device are difficult to balance is thoroughly overcome.

This invention relates to a method for measuring the stability margin of a constant-temperature hot-wire anemometer based on in-situ open-loop frequency characteristics, belonging to the field of fluid measurement and automatic control technology. The method disclosed in this invention includes the following steps: S1. Connecting an ultra-low frequency low-pass filter to the closed-loop circuit to form an in-situ open-loop system with a DC closed loop and an AC open loop; S2. Injecting a sweep frequency excitation signal E at the bias circuit. stimu And measure the output response E of the amplifier circuit. a By comparing the amplitude ratio and phase difference of the two, the open-loop frequency response G of the system under actual operating conditions of the hot wire is obtained. open (jω); S3. According to G open (jω) Obtain the phase margin of the system and determine its stability. This invention proposes a new method for measuring the stability margin of a constant-temperature hot-wire anemometer, transforming the complex system stability problem into a measurable and analyzable open-loop frequency characteristic stability margin problem, providing a direct and reliable engineering basis for the circuit design of constant-temperature hot-wire anemometers.

The invention provides a robust design method and system for a fractional order PI controller of an inertia and delay fractional order object. The method comprises the following steps: describing a controlled object by adopting an inertia and delay fractional order transfer function; the feedback controller adopts a fractional order PI controller; a crossing frequency and a phase margin are given, and a proportional gain, an integral gain and a controller order of the fractional order PI controller are solely solved based on three constraint equations of the given crossing frequency, the given phase margin and zero slope of an open-loop phase of a closed-loop system at the crossing frequency; if a null set is solved, the values of the crossing frequency and the phase margin need to be given again, and solving is carried out; and traversing the range of the traversing frequency and the phase margin to obtain a feasible region of the fractional order PI controller. According to the method, the parameters and the feasible region of the fractional order PI controller can be directly calculated, it is guaranteed that the fractional order PI controller has high robustness, and the method has practical application value.

The application discloses a stability evaluation method suitable for a multiple-input multiple-output system and belongs to the technical field of stability control, which obtains the amplitude margin and the phase margin of the multiple-input multiple-output system by calculating the gain solution of the system at different frequencies when the system is critically stable. The application comprises the following steps: calculating the maximum range of the amplitude margin corresponding frequency according to the spectral radius of the transfer function of the multiple-input multiple-output system; calculating whether the amplitude gain solution exists at different frequencies within the frequency range, and if the amplitude gain solution exists, calculating the corresponding amplitude margin; drawing all the amplitude gains and solving the intersection points with the gain curve to obtain the amplitude margin; calculating the maximum range of the phase margin corresponding frequency according to the spectral radius of the transfer function of the multiple-input multiple-output system; calculating whether the phase gain solution exists at different frequencies within the frequency range, and if the phase gain solution exists, calculating the corresponding phase margin; and drawing all the phase gains and solving the intersection points with the phase gain curve to obtain the phase margin.

The application provides a parameter optimization method for improving the near power frequency stability of a new energy flexible direct transmission system, and the method comprises the following steps: dividing the new energy flexible direct transmission system into a source side subsystem and a load side subsystem, and respectively establishing positive and negative sequence impedance models of the source side subsystem and the load side subsystem; evaluating the stability margin of the system in the near power frequency band based on the above models; if the stability margin of the system in the near power frequency band is low, extracting dominant parameters affecting the near power frequency stability of the new energy flexible direct transmission system based on the phase margin sensitivity; determining the optimization interval of the dominant parameters based on the equivalent impedance criterion and the upper and lower limits of the parameter values; establishing the input and disturbance response transfer functions of the source side subsystem and the load side subsystem, evaluating the influence of the change of the dominant parameters on the power frequency control performance, and finally determining the optimal parameter values. The parameter optimization method can improve the near power frequency stability of the new energy flexible direct transmission system while minimizing the influence on the power frequency control performance of the system.

The application discloses an inverter stability optimization control method based on PLL link parameter adjustment. Firstly, the inverter, grid impedance network and the like are introduced into a phase-locked loop in the form of coupled interference of port characteristics, and a synchronous dynamic mathematical expression of the phase-locked loop and the coupled interference is established; secondly, according to the coupling relationship of the PLL in the system, a dynamic control equation of the inverter is determined. Then, based on the PLL dominant loop, the system stability is determined through the phase margin of the equation at the crossing frequency; finally, by adding a transfer function H(s) in series in the PLL to change the loop characteristics of the PLL, parameter design is carried out for the control optimization method of the PLL in different control modes; the application can clearly reveal the dynamic coupling between different frequencies in the phase sequence, can more intuitively study the admittance characteristics of the grid-connected inverter based on the PLL structure, and further proposes an optimization control method of the phase-locked loop to improve the stability of the PLL synchronization control under the condition of a weak grid.

The disclosed second-order residual gradient and frequency division confidence magnetic suspension bearing time delay dynamic compensation method realizes agile online identification of time-varying time delay through a nonlinear variable forgetting factor least square method driven by a residual second-order gradient, constructs a confidence function based on evaluation of high-frequency energy of frequency division of an identified residual, dynamically schedules weights of model-driven compensation and disturbance-driven compensation according to the confidence function, and realizes adaptive adjustment of compensation strength; in a reliable identification stage, the Pade approximation explicit hedge phase lag caused by time delay is used to significantly restore system phase margin; in an uncertain or time delay mutation stage, a residual feedforward mechanism of active disturbance rejection is introduced to instantaneously inhibit total disturbance of the system, effectively preventing unstable risks caused by over-compensation. The collaborative mechanism fully gives play to the complementary advantages of model-driven compensation and disturbance-driven compensation, so that the magnetic suspension bearing has higher dynamic performance and system safety under a variable time delay environment.

This invention discloses an operational amplifier based on a cyclic folded cascode architecture, relating to the field of analog circuit technology, to address the problems of low energy efficiency in existing folded cascode amplifiers and limited energy efficiency improvement in cyclic folded cascode structures. It includes a differential input transistor, a current mirror, an adaptive bias circuit, and an output stage. The adaptive bias circuit is connected to the differential input transistor, and the current mirror is connected to both the differential input transistor and the output stage. The adaptive bias circuit includes a flip-flop voltage follower. The current mirror is used for current recycling and zero-point compensation, and the output stage is used to output amplified signals. The adaptive bias circuit includes a flip-flop voltage follower to improve the dynamic performance of the amplifier. Zero-point compensation can improve the phase margin of the circuit, further improving the gain-bandwidth product. Compared to traditional operational amplifiers, the operational amplifier of this invention can achieve higher bandwidth and higher energy efficiency with lower power consumption.

The invention discloses a virtual synchronous generator power compensation control method, system and device and a medium, and relates to the technical field of flexible interconnection systems.The method comprises the steps that the initial open-loop cut-off frequency of a traditional VSG control system is obtained, and a damping correction ring is arranged in an active frequency ring; obtaining an updated open-loop cut-off frequency based on the expected phase margin, determining a lag coefficient of a damping correction loop, and calculating a time constant of the damping correction loop; based on the lag coefficient and the time constant, calculating equivalent virtual damping and equivalent virtual inertia provided by the damping correction ring for the system and judging whether the equivalent virtual damping and the equivalent virtual inertia both meet corresponding preset index requirements or not, and if not, adjusting the lag coefficient until the corresponding preset index requirements are met; and operating the system containing the damping correction ring to control the network construction converter. The method solves the problems that a traditional VSG control strategy is limited in effect and not large in adjustment range under the high resistance-inductance ratio working condition, and the provided virtual damping and virtual inertia are not high in suppression capacity for frequency and active power oscillation of the system.

The invention discloses a ring amplifier based on double-zero compensation, and the ring amplifier comprises a main amplifier which is used for receiving an input differential voltage signal, amplifying the differential voltage signal, and outputting an amplified signal; and the first zero inverter module and the second zero inverter module are connected with the main amplifier and are used for generating a first zero point and a second zero point and carrying out zero point compensation on the main amplifier based on the first zero point and the second zero point. According to the embodiment of the invention, zero compensation can be carried out on the main amplifier through the first zero inverter module and the second zero inverter module, so that the phase margin of the amplifier can be improved, the stability of the amplifier is improved, and the amplifier can be widely applied to the technical field of circuits.

The invention provides a PID (Proportion Integration Differentiation) controller robust design method and system of an inertia and delay fractional order object. The method comprises the following steps: describing a controlled object by adopting an inertia and delay fractional order transfer function; a proportional-integral-differential controller is adopted to describe the controller; a crossing frequency and a phase margin are given, and a proportional gain, an integral gain and a differential gain of a proportional-integral-differential controller are uniquely solved based on three constraint equations of the given crossing frequency, the given phase margin and the condition that the slope of an open-loop phase of a closed-loop system at the crossing frequency is zero (also known as phase flatness); if a null set is solved, the values of the crossing frequency and the phase margin need to be given again, and solving is carried out; according to the method, the proportional-integral-differential controller parameters can be directly solved on the basis of three given constraint equations such as the crossing frequency, the phase margin and the phase flatness, it is guaranteed that the proportional-integral-differential controller has high robustness, and the method has practical application value.

The application discloses a kind of island microgrid-oriented multi-source collaborative harmonic adaptive suppression method, it is related to island microgrid harmonic suppression technical field, comprising the following steps: extracting the fundamental component of island microgrid local inverter output voltage signal, obtain the real-time fundamental angular frequency perceived;Based on real-time fundamental angular frequency, separate harmonic component is realized by dynamic reconstruction signal delay chain, and the physical phase alignment of compensation vector and grid distortion source is carried out through feedforward correction logic, to prevent system shock induced by insufficient phase margin;Through the consistency protocol of information layer, and coupling aperiodic event trigger mechanism, after dynamic on-demand allocation of channel resources, closed-loop regulation is carried out to local harmonic compensation current.The application significantly reduces the throughput pressure of distributed channel and the invalid task load of processor, greatly improves the engineering reliability and system expansibility of distributed governance architecture in resource-poor environment.

The invention belongs to the technical field of analog integrated circuits, and particularly relates to a high-speed interstage gain amplifier based on source driving. The circuit comprises an input stage driven by a push-pull source electrode, a variable impedance module and a push-pull output stage. According to the push-pull type source electrode driving input stage, the four independent buffers are used for driving the source electrodes of the input transistors respectively, the transconductance of the input stage is improved to be four times that of a traditional scheme, and higher bandwidth and speed are achieved. Meanwhile, the input stage avoids the problem that the slew rate is limited by the current of the input stage in the traditional scheme, so that a higher slew rate can be realized. The impedance of the variable impedance module is relatively low in a static state, so that a relatively far secondary pole is realized, and the phase margin of the amplifier is ensured. When the input swing is large, the module realizes high impedance, and the grid voltage swing of the output stage is improved, so that the output current is expanded, and the overall speed of the amplifier is effectively improved.

The invention relates to a buffer stability compensation circuit, the buffer adopts a two-stage operational amplifier structure, the buffer stability compensation circuit comprises a Miller compensation network connected between a first-stage output node and a second-stage output node of the two-stage operational amplifier structure; one end of the isolation resistor is connected to the second-stage output node, and the other end of the isolation resistor serves as the output end of the buffer and is used for being connected with an external capacitive load; wherein the isolation resistor and the external capacitive load jointly form an RC compensation network, and the RC compensation network is used for adjusting the zero pole position of the buffer so as to improve the phase margin. According to the invention, a large capacitive load at an output end in an actual CP test is utilized, an isolation resistor is added to form a new RC compensation network with the large capacitive load, and a left half plane zero point is effectively generated, so that the phase margin of a system is remarkably improved, and the stability of driving the large capacitive load is enhanced.

The invention discloses a boost circuit system bandwidth optimization method, which comprises the following steps: acquiring an input signal, and outputting an output signal after system signal processing; in the system signal processing process, the duty ratios of the system are detected, and the gain of a compensation loop is modulated under different duty ratios, so that the bandwidth of the system is adjusted; the step of modulating the compensation loop gain comprises the substeps that when it is detected that the duty ratio is gradually increased, the compensation loop gain is increased, so that the system ride-through frequency is improved, the system phase margin is reduced, and the system response speed is increased; and when it is detected that the duty ratio is gradually reduced, the compensation loop gain is reduced, so that the system ride-through frequency is reduced, the system phase margin is increased, and the system stability is improved. The invention further discloses the boost circuit system, and the bandwidth optimization method of the boost circuit system is adopted. The dynamic performance can be optimized while the stability of the system is ensured, and the bandwidth of the system is improved.

The present application relates to the technical field of LDO circuit, especially to a dynamic pole compensation LDO circuit, which eliminates the channel length modulation effect by dynamically mirroring the current of PM0 through PM1 and combining the current mirror structure composed of PM2, PM3, NM0 and NM1, adopts the super source follower composed of NM5, NM6 and NM7 to push the secondary pole of the LDO to the outside of the bandwidth, greatly improves the phase margin, mirrors the dynamic load current to PM9 (diode connection) through NM9, combines the capacitor C1 to form a dynamic zero point, compensates the secondary pole in real time following the load change, avoids the problem that the primary and secondary poles are too close in the traditional Muller compensation, introduces NM2 to break the degenerate point of the current mirror, ensures the normal starting and stable work of the circuit, adjusts the gm value of the super source follower through the dynamic current mirroring of PM5 and PM7, automatically adjusts the secondary pole frequency with the change of the load current, realizes the adaptive optimization of the pole in the full load range, and improves the stability consistency under light load and heavy load.

The invention discloses a method for correcting design errors of a CMOS (complementary metal oxide semiconductor) operational amplifier, which comprises the following steps: firstly, according to preset performance indexes, the performance indexes mainly comprise unity gain bandwidth, phase margin and slew rate; the method comprises the following steps: performing initial design on a CMOS operational amplifier by adopting a conventional design process to obtain initial circuit parameters; performing circuit simulation on the initial circuit, and obtaining an actual unit gain frequency, an actual phase margin and an actual slew rate obtained by simulation; calculating an error factor according to the performance index and the simulation result; and correcting the design parameters by using the error factors, and finally recalculating the size of each MOS tube according to the corrected design parameters to complete design error correction. According to the method, performance errors caused by process deviation, model inaccuracy or manual design simplification are identified and corrected in a mode of combining simulation and theoretical calculation, so that the final circuit performance meets or is superior to a preset index.

The application discloses a method for determining a small signal stability working condition interval and a stability margin of a new energy grid-connected system, and the method comprises the following steps: S1, obtaining a multivariable equivalent binary open-loop transfer function of the new energy grid-connected system with respect to different operating condition variables; S2, calculating phase characteristics and amplitude characteristics of the multivariable open-loop transfer function; S3, setting the phase characteristics as φ k and the amplitude characteristics as 0 dB; drawing a multi-phase contour map containing a plurality of phase contours and amplitude contours; wherein, φ k is a phase value related to critical stability of the new energy grid-connected system; S4, calculating a phase margin of the new energy grid-connected system at the intersection of the phase contours and the amplitude contours, and determining a stable working condition interval of the new energy grid-connected system according to operating condition variables corresponding to the intersection of the phase contours and the amplitude contours. The method can not only obtain a stable running interval of the grid-connected system in the whole operating condition range, but also evaluate the distribution law of the stability margin under different working condition conditions.

This invention discloses a self-testing method and circuit for chip stability. The method is automatically executed before the chip begins operation and includes: sampling the output of the LDO circuit inside the chip, and obtaining the pulse response of the LDO circuit based on the sampled LDO circuit output; calculating the damping ratio of the LDO circuit based on the pulse response, and calculating the phase margin of the LDO circuit based on the damping ratio; determining that the LDO circuit is in a stable state when the phase margin is greater than a preset angle; and determining that the LDO circuit is in an unstable state when the phase margin is less than or equal to the preset angle. This invention addresses the technical problems of low chip power supply reliability, high chip testing cost, and low chip testing efficiency and accuracy in the prior art.

This invention relates to the field of aircraft control technology, and particularly to an aircraft overload control method based on angular velocity command generation and dual-hysteresis correction. The method includes: generating an angular velocity command based on an overload command, and feeding back the actual angular velocity to adjust the damping ratio to a preset ideal range; executing a dual-hysteresis series correction strategy to cancel the zeros of the target transfer function, and adjusting the gain to meet the preset high control gain requirements in the low-frequency band, achieving the preset desired open-loop cutoff frequency and phase margin by configuring zeros and poles; and generating a control surface deflection angle command by combining the dual-hysteresis series correction strategy and the damping adjustment loop to control the deflection of the aircraft control surfaces. This solves the problems caused by the fact that related technologies typically use integral control in the overload control loop to reduce steady-state error, which easily introduces phase hysteresis and reduces the system phase margin, leading to slower overload response, increased dynamic overshoot, and even system oscillation.

The invention discloses a design method of an amplitude-phase corrector for suppressing flexible direct-current broadband oscillation. The design method comprises the following steps: acquiring a power grid frequency characteristic curve; constructing impedance transfer functions of an alternating-current power grid side and a current converter side; determining a frequency point which is unstable or low in stability margin; according to the type of the required amplitude-phase corrector, determining a total impedance function of one side containing the amplitude-phase corrector; setting a plurality of frequency points to be corrected; presetting a target phase frequency characteristic curve after actual correction; calculating a phase value of the total impedance function at a frequency point needing to be corrected, and obtaining a target phase frequency characteristic curve after quasi-correction; and constructing a frequency difference objective function according to the target phase frequency characteristic curve subjected to the quasi-correction and the target amplitude phase frequency characteristic curve subjected to the actual correction, and solving to obtain an element parameter value. According to the amplitude-phase corrector designed by the method, the broadband domain range of a system containing the flexible direct current can be stable under the condition that the phase margin is given, so that the problem of broadband oscillation of the flexible direct current is fundamentally solved.

The invention discloses an inverter repetitive control method, system and equipment based on phase compensation. The method is applied to an inverter control system, the inverter control system comprises a repetitive controller and a lead correction link used for phase compensation, the lead correction link is arranged at the output end of the repetitive controller, and the method comprises the following steps: obtaining an error signal between an inverter output signal and a given reference signal; inputting the error signal into a repetitive controller to generate a preliminary control signal; performing phase lead compensation on the preliminary control signal through a lead correction link to generate a target control signal; and acting the target control signal on a controlled object of an inverter control system to realize phase compensation-based inverter repetitive control. According to the method, the problems of insufficient phase margin and poor stability caused by inherent phase lag of a repetitive control algorithm can be solved.

The invention relates to the technical field of aircraft control, in particular to an aircraft overload control method based on angular velocity instruction generation and double-lag correction, and the method comprises the steps: generating an angular velocity instruction according to an overload instruction, and feeding back an actual angular velocity adjustment damping ratio to a preset ideal range; executing a double-lag series correction strategy, counteracting a zero point of the target transfer function, adjusting the gain to meet a high control gain requirement of a preset low-frequency band, and configuring the zero point and a pole to achieve a preset expected open-loop cut-off frequency and a phase margin; generating a rudder deflection angle instruction of the aircraft control surface by combining the double-lag series correction strategy and the damping adjusting loop, and controlling the aircraft control surface to deflect. Therefore, the problems that in the prior art, integral control is usually adopted in an overload control loop to reduce steady-state errors, phase lag is easily further introduced, and the system phase margin is easily reduced, so that the overload response speed is slowed down, dynamic overshoot is increased, and even system oscillation is caused are solved.

This application provides a method for broadband oscillation stability analysis of power-electronic power systems, including: obtaining broadband impedance models of each subsystem in the power-electronic power system; establishing a full-system impedance frequency domain model of the power-electronic power system based on the broadband impedance models; plotting the amplitude-frequency response curves, phase difference-frequency response curves, and phase-frequency response curves of the main diagonal elements of the full-system impedance matrix based on the full-system impedance frequency domain model; identifying the dominant oscillation mode and determining the potential oscillation frequency and dominant element based on the amplitude-frequency response curves; evaluating the stability margin of the dominant oscillation mode based on the phase difference-frequency response curves; and revealing the direction of influence of each component on the dominant oscillation mode based on the phase-frequency response curves, thereby performing broadband oscillation stability analysis of the power-electronic power system. This application can directly extract stability information such as (potential) oscillation frequency, phase margin, and oscillation risk nodes from the frequency response characteristics of the impedance, providing guidance for system stability analysis.

VSG Frequency Control Method, Device and Storage Medium based on Power Correction, belonging to the field of power electronics technology, which addresses the problem of suppressing VSG output power oscillations. The technical solution of the present application corrects the output power Pe(s) and feeds the corrected value back to the control loop to suppress power oscillations. The transfer function of the power correction stage G(s) is flexible and can be configured with appropriate parameters according to the system's inherent phase margin. Additionally, principles for selecting the parameters of the correction coefficients τ1 and τ2 are also provided. The adjustment coefficients of the power correction stage, the values of τ1 and τ2 do not affect the effect of the steady-state gain during the transient process. The present application can not only suppress VSG output power oscillations, but also provide a larger inertial support, thereby improving the stability of the VSG system.

The application claims an operational amplifier with programmable compensation capacitor array, comprising a chopper module, a sleeve type gain enhancement operational amplifier and a programmable compensation capacitor array. The chopper module is used for periodic modulation of the input signal to suppress low frequency 1 / f noise and bias drift, thereby improving the input accuracy and linearity of the operational amplifier; the gain enhancement preamplifier provides high open loop gain through the sleeve type structure, while maintaining the trade-off between bandwidth and stability, and improving the small signal amplification capability; the programmable compensation capacitor array is composed of multiple switched capacitor units, which are selectively connected or disconnected by control signals, used to adjust the frequency response and phase margin of the operational amplifier, and realize the optimization of closed loop stability under different process, temperature and voltage conditions. The operational amplifier of the application not only maintains good stability at high gain, but also reduces input noise and drift, realizes high precision, low noise analog signal amplification.

The invention provides a second-order feedback voltage detection current compensation type active EMI filter topology, and aims to solve the problem of system instability caused by limited high-frequency gain bandwidth and phase lag of a traditional first-order filter. The structure is composed of a sampling module, an amplification module and a compensation injection module. The sampling module extracts bus common-mode noise through a coupling capacitor. The amplification module uses in-phase operational amplifiers to construct a second-order feedback loop, the first-stage operational amplifier is responsible for high-gain amplification, the second-stage operational amplifier is combined with an injection resistance-capacitance network to achieve buffering and active phase correction, and voltage signals are converted into reverse-phase current to be injected into a bus to offset noise. While the advantage of small size is maintained, the problem of high-frequency oscillation is effectively solved through active phase correction, the effective bandwidth is widened to 30MHz on the premise of ensuring the phase margin, and high-stability suppression of 15-20dB conducted interference is realized.

The application discloses a new energy unit impedance characteristic sensitivity simulation test method, which comprises the following steps: setting a unit control parameter as an operation parameter; obtaining the admittance parameter of the unit at each frequency through a hardware-in-the-loop test method; calculating an AC power grid side impedance; calculating a total impedance open loop transfer function of a grid-connected system from the admittance parameter and the grid-connected system impedance; calculating a grid-connected oscillation frequency and a phase margin according to the total impedance open loop transfer function of the system; and changing the unit control parameter and recalculating the grid-connected oscillation frequency and the phase margin. The method can calculate the impedance characteristic parameter sensitivity without obtaining the structure and parameters of a new energy unit controller, has the advantages of high efficiency and simple realization, and is especially suitable for the case where the structure and parameters of the new energy unit controller are unknown.