267 results about "Ring circuit" patented technology

The invention involves a method of digital phase-locked loop for timestamp clock synchronization and equipment. Firstly, the server sends a value, which includes the message S (t) to timestamp, as the input synchronized signal. Take the time on which timestamp the server sent arriving at phase-locked loop as the recording time R (t) of local time. Then take the local timestamp according to the local clock frequency as reference input signal. The numerically controlled adjusts the output frequency according to ring circuit signal by filter. Lastly, the timestamp creater/ recorder output the signal as the local clock frequency according to the output signal created by DOC. Under the condition that the invention use larger drift mobility and the lower stability oscillator, the system can provide high accuracy time synchronism.

It is a high frequency loop oscillation type phase locked loop circuit with self-accommodation frequency compensation. It consists of a multichannel loop type voltage-control oscillator with self-accommodate central frequency correction function,a difference electric charge pump, a linear double / single conversion circuit, a frequency divider, etc. The voltage-control oscillator possesses two gain channels, fast and slow. Its load transistor connects in serial into the voltage control channel to form a positive feedback. A selectable load array and a switch designed for technology and temperature compensation work in parallel with the original PMOS load. According to the conditions of technology and temperature, an auto-switch control module monitors the loop's lockup status and decides the number of parallel loads. Via self-accommodation feedback monitoring and compensation, it greatly reduces the dependency of the phase lock loop against the technology and temperature.

The invention relates to a double-layer cascaded dual-polarized broadband absorbing type frequency selective surface. A conventional wave absorbing frequency selective structure is designed to be a bandpass type frequency selective structure which has limited pass band width and has difficulty in covering low frequency. According to the invention, a double-ring reflective plane is adopted, a waveabsorbing ring is designed on the other surface of the reflective plane, and the double-layer cascaded dual-polarized broadband absorbing type frequency selective surface is constructed by the combination of a single-ring circuit analog absorber. Therefore, insertion loss in a low frequency passband is low, and an extremely wide absorbing band can be generated near a high frequency place.

This invention relates to a method for constructing new non-standard replacement matrix LDPC codes characterizing that under the principle of optimizing the smallest ring circuit, it takes each sub-block as the smallest unit and utilizes a binary chart with weight to determine the position of the sub-block and the deviation of circulation shift: simplifying the binary chart with bit as the unit of the LDPC code to that with a sub-block as the unit based on the property of the matrix of a replacement unit, then applying the traditional PEG algorithm with the bit as the unit to the new chart with the sub-block as the unit to determine the position of every replacement unit matrix of the H matrix and finally utilizing the ring circuit property of the LDPC code to decide the deviation of circular shift of each replacement unit matrix.

The invention provides a method and a device for processing the internet group management protocol (IGMP) messages, and enables a port in a blocked state to treat IGMP messages in advance, wherein, the method comprises the following steps: when receiving or sending an IGMP message through the port in a blocked state, a switch determinates whether a list item including the IGMP message information exists in an IGMP message list arranged corresponding to the port or not; if no, the list item including the IGMP message information is established in the IGMP message list arranged corresponding to the port, the IGMP message is forwarded; and when the IGMP message is an IGMP adding message, the IGMP message is utilized to establish and forward the list item; if yes, the IGMP message is discarded. The invention can shorten the time of interrupting multicast stream after switching a link circuit, and avoid the broadcast caused by the ring circuit of the IGMP messages.

A safety protection system for hybrid vehicles is characterized in that the invention consists of a signal control loop formed by connecting a collision sensor 2, open circuit protection sensors 3, 4 and control relays 7,6 in series, and a high-voltage ring circuit interlocked loop formed by connecting contact points of the control relays 7,6 and an open circuit relay 9 of a power battery in series; an entire controller HCU provides 12v power for the loop and connects with a control switch at an input end and provides a control signal Enable; the open circuit relay 9 also connects with a control switch and shares the control signal Enable; when in danger, the high-voltage loop can cut off automatically and can release the residual charge on the driving side of a motor; when vehicles are collided, the ring circuit interlocking can cut off the high-voltage loop automatically to prevent the battery from shot cutting, and to prevent people from being attacked by the electricity of the high-voltage loop.

The invention discloses a method for compensating the frequency of a broadband common mode feedback ring circuit for a two-stage operational amplifier, belonging to the field of analog integrated circuit design. A broadband feedback amplifier in the two-stage operational amplifier with the Miller compensation is used as the common mode feedback ring circuit so as to reduce the area and the power consumption of the common mode feedback circuit; the two-stage operational amplifier has only one main pole in the range of the unit gain bandwidth, a fully differential input and output structure is adopted, the sampling of the common mode output level is performed by the differential output end; and a control signal fed back by the common mode simultaneously controls the output level of a first-stage common mode and the output level of a second-stage common mode of the operational amplifier through a controllable bias circuit. The frequency of the main pole of the broadband feedback amplifier is far higher than the unit gain bandwidth of the operational amplifier, therefore the margin of phase position of the common mode ring circuit is basically equal to that of the operational amplifier, thereby forming the stable feedback ring circuit. The method has the advantages of few elements for a common mode feedback circuit, lower power consumption of the common mode feedback circuit and simpler and more convenient circuit design.

The invention discloses an FPGA-based true random number generator. The FPGA-based true random number generator comprises an oscillating ring circuit, a multi-tap signal delay chain, a trigger array, a logic XOR circuit and a postprocessing circuit. A clock signal generated by the oscillating ring circuit is fed into the signal delay chain, the trigger array samples the level states of all taps of the delay chain under the control of a system clock, acquisition results of all triggers are subjected to logic XOR processing and sent into the postprocessing circuit, and output of the postprocessing circuit is a generated binary true random number sequence. The FPGA-based true random number generator not only can generate random numbers at a rate as high as possible, but also can guarantee the quality of the random numbers.

The invention discloses an insulated gate bipolar translator (IGBT) series connection type high-voltage pulse generator. The voltage is provided for the high-voltage pulse generator by a high-voltage power supply, and after the energy storage of an energy storage capacitor, high-voltage pulses are generated through a multistage IGBT series connection circuit. A programmable logic controller (PLC) generates pulse-width modulation (PWM) control pulses, the PWM control pulses are input into an optical fiber isolation circuit after passing through a PWM amplification circuit, further, the IGBT series connection circuit is driven, and the power supply required by the work of the IGBT series connection circuit is provided by a secondary circuit of the isolation power supply connected with the IGBT series connection circuit. Commercial electricity is changed into direct current through a rectifying circuit and a filter circuit, the direct current is changed into high-frequency square waves through a high-frequency power metal-oxide-semiconductor field-effect transistor (MOSFET) full-bridge inverter circuit driven by a power MOSFET driving circuit, and the high-frequency square waves are input into the secondary circuit of the isolation power supply after being isolated by a series connection magnetic ring circuit. When the IGBT series connection circuit generates faults, fault signals are input into the PLC through a fault output circuit and an optical fiber feedback circuit, the PLC interrupts control signals so that the IGBT series connection circuit is in a switch-off state, and the whole system is further protected.

A variable-frequency digital ring oscillator provides small and consistent frequency adjustments throughout a locked range. The ring oscillator of the invention is standard cell placeable and operates at the technology limits to provide small and precise delay changes that is inexpensive to implement. The digital variable-frequency ring oscillator includes multiple macro delay elements forming an inverter ring circuit, each element having an individual macro delay unit that in turn is comprised of multiple adjustable delay units. All of these adjustable delay units are controlled by a single delay control signal.

The invention relates to a whole-course adjustable digital pulse width modulator based on an oscillation ring circuit, which comprises an oscillation ring-counting comparator circuit and an output logic circuit, wherein the oscillation ring circuit is formed by connecting K stages of D triggers end to end and used for generating a reset signal required by the D trigger and output by the output logic circuit together with a multi-channel gating device and the counting comparator circuit according to an digital duty cycle control signal externally input, thereby resetting an output signal of the output D trigger to a low level; and the clock end of the output D trigger is used for controlling a high level at the input end to be transferred to the output end, and the reset signal and a clock signal act jointly for finally generating a duty cycle signal at the output end. The whole-course adjustable digital pulse width modulator can not only keep the advantages of a conventional oscillation ring structure digital pulse width modulator, but also enlarge the adjustable range of output duty cycle, thereby being very applicable to being integrated in high-frequency DC(direct current)-DC switching mode power supplies (SMPS) in power supply management systems of miniature handheld devices.

The invention discloses a full digital time delay locking ring circuit, which comprises a main time delay wire, a controller, a phase detection unit and a duplicate time delay wire, wherein a clock interface of the main time delay wire is connected with a clock interface of the controller and a clock interface of the phase detection unit respectively; a feedback clock interface of the main time delay wire is connected with another clock interface of the phase detection unit; an output end of the phase detection unit is connected with an input end of the controller; and an output end of the controller is connected with an input end of the main time delay wire and an input end of the duplicate time delay wire respectively. The full digital time delay locking ring circuit widens the operating frequency range and improves the compatibility with a DDR controller.

A ring-shaped light-emitting heat-dissipating fan comprises a base having a ring-shaped frame and a pivot portion; a fan pivotally disposed at the pivot portion; a ring-shaped light guide having an upper top surface, a lower top surface, an inner lateral surface, and an outer lateral surface; a lid disposed on the ring-shaped frame, with the ring-shaped light guide disposed between the base and the lid, and a receiving space formed between the lid and the ring-shaped light guide; and a ring-shaped circuit board disposed on an upper top surface of the ring-shaped light guide in the receiving space and having thereon a plurality of light-emitting elements arranged annularly. Therefore, the ring-shaped flat region dispenses with any receiving recesses for receiving the light-emitting elements. The ring-shaped circuit board controls color of light emitted from the light-emitting elements and their light emission cycles.

The present invention relates to a cooking gas flame regulating system. The system includes sensor, processing circuit and gas regulator. The described sensor portion includes the flame state sensor for detecting heat transfer medium and cooked material, etc. related to flame and flame mainly-regulating ring circuit of cooking machine which is formed from flame state sensor, processing circuit and gas regulator, and the described sensor portion also includes operation state sensor for detecting regulation displacement, valve opening, gas component and state parameter of gas regulator and its flame fine-regulating ring circuit formed from the operation state sensor, etc.

The invention provides a rapid ring protection protocol (RRPP) ring link switching method and a system thereof. Transmission node ports which directly link a RRPP ring and a transmission equipment link are enabled with a fault detection feature, one port of the ports enabled with the fault detection feature, which firstly receives a ring circuit detection message sent from a master node, is used as a detection port, and the other port is used as an assistant port. The method comprises that the transmission node where the assistant port locates forwards a ring circuit detection message after receiving the ring circuit detection message via the assistant port, and copies N ring circuit detection messages and redirects to the detection port via the assistant port, wherein, N is an integer larger than 1; and the transmission node where detection port locates notifies the link fault to the master node if not receiving the ring circuit detection message via the detection port within a set time period after sending the ring circuit detection message via the detection port. The method and the system can reduce traffic interrupting time in the RRPP ring when a fault occurs in the transmission equipment link.

The invention discloses a servo system for a linear motor. The servo system comprises a linear motor and a linear motor driver, wherein the linear motor driver comprises a DSP, a switch power supply, a drive circuit, a motor feedback position acquisition unit, a motor feedback rotary speed computing unit, a motor feedback current acquisition unit, a position ring computing unit, a speed ring computing unit, and a vector control unit, wherein the DSP controls a position ring circuit, a speed ring circuit and a current ring circuit of a linear motor; the motor feedback position acquisition unit obtains the actual position of a motor rotor; the motor feedback rotary speed computing unit works out the actual rotary speed of the motor according to the actual position of the motor rotor and the measuring time; and the motor feedback current acquisition unit samples by a resistor, sends the sample to an AD converter through linear opto coupling insulation, and sends the sampling signal to the DSP through a serial port after converting to the analogue signal to the digital signal. The servo system adopts a structure integrating power supply, drive and control, and mixes strong current signals and weak current signals, so that the servo system can avoid the interference among various signals of strong current, weak current, switch power supply and the like.

The present invention relates to a clock frequency division technology for an integrated circuit, in particular to a clock frequency division method based on a trigger ring and a clock frequency division circuit thereof. The method is to orderly connect data input ends and data output ends of a plurality of triggers to form a trigger ring circuit. The number of the triggers with set ends and reset ends in the trigger ring is selected according to the requirement of the frequency division circuit for a duty ratio. The positions of the triggers with set ends and reset ends are determined according to the requirement of a clock waveform. The trigger ring circuit accesses a system frequency division circuit, and a spare data output end of the last trigger is used as an output end of the trigger ring circuit so as to realize clock frequency division. The number of the frequency division of the method and the circuit structure thereof do not influence the highest frequency of the working circuit. The normal work of the frequency division circuit can be at a comparatively high clock frequency, and the clock frequency division can be realized in the manner of cascade connection of the frequency division circuit so that the scale of the circuit realization can be properly reduced.

The invention provides a method for protecting an Ethernet. The method is used for the Ethernet comprising trunk equipment and comprises the following steps: nodes which are close to the trunk equipment and support the high speed link detection are chosen on two sides of the trunk equipment; the relay transmission link state between the two chosen nodes are detected; when the failure of the relay transmission link is detected, one interface which is positioned on one chosen node and connected with the failure link is blocked and a link failure message is reported to a main node; after the main node receives the link failure message, an auxiliary interface is opened. In addition, the invention also provides an Ethernet protection system and a node. The technical proposal provided by the invention can realize quick protection switching and avoid the generation of a ring circuit in the Ethernet comprising the trunk equipment.

The invention discloses a ring shape oscillating circuit that consists of a regulator that is connected between the band gap voltage and the power source access end of the inverter and is used for providing stable band gap voltage for the inverter; a power source absolute current circuit that is connected to the power source access end of the inverter and is used for converting the accessed band gap voltage so as to provide power source absolute current for the inverter; an earth absolute current circuit that is connected with the earth end of the inverter and is used for converting the accessed band gap voltage so as to provide earth absolute current for the inverter. The invention also provides an integrated circuit chip that has ring shape circuit.

The invention provides a method for detecting and processing a link failure in a RRPP (Rapid Ring Protect Protocol) ring network. The method comprises the following steps: if a slave port of a main node does not receive a ring-circuit state detection message within timing time of an invalidation timer, the main node transmits a single-pass ring circuit detection message through the slave port and starts the invalidation timer of a main port; if the main port of the main node receives the single-pass ring circuit detection message within the timing time of the invalidation timer of the main port, the main node maintains the block state of the slave port and reports single-pass ring circuit warning information; and if the main port of the main node does not receive the single-pass ring circuit detection message, the main node removes the block state of the slave port and transmits a data message through the slave port. The embodiment of the invention also provides the main node in the RRPP ring network. According to the method provided by the invention, the slave port is continuously blocked when the link failure is discovered to be a unidirectional failure, so that the storm of the data message, generated in a reverse ring circuit, is avoided, the warning information is timely reported and the stability of a ring circuit service is increased.