Adaptive process and temperature compensated high frequency ring-oscillating phase-locking ring circuit

Abstract

It is a high frequency loop oscillation type phase locked loop circuit with self-accommodation frequency compensation. It consists of a multichannel loop type voltage-control oscillator with self-accommodate central frequency correction function,a difference electric charge pump, a linear double / single conversion circuit, a frequency divider, etc. The voltage-control oscillator possesses two gain channels, fast and slow. Its load transistor connects in serial into the voltage control channel to form a positive feedback. A selectable load array and a switch designed for technology and temperature compensation work in parallel with the original PMOS load. According to the conditions of technology and temperature, an auto-switch control module monitors the loop's lockup status and decides the number of parallel loads. Via self-accommodation feedback monitoring and compensation, it greatly reduces the dependency of the phase lock loop against the technology and temperature.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a high-frequency ring-vibration phase-locked loop circuit capable of self-adaptive frequency compensation under various processes and temperatures. Background technique [0002] As communication technology advances, the rate at which information is sent and received tends to be faster. This requires a stable clock circuit with higher frequency and higher precision to realize data transmission and recovery (reception). Deep submicron CMOS technology, low jitter (phase noise) PLL as an IP core, can be applied to many different occasions under the premise of compatible technology and performance, such as Gigabit / 10 Gigabit Ethernet, UWB, etc. Has high practical value. At the same time, the low-jitter on-chip adjustable clock can also be used as a powerful auxiliary tool for circuit testing, providing a good testing environment for circuits such as ADCs, and...

AI Technical Summary

Problems solved by technology

But this has caused the deterioration of loop performance

Most of the existing methods of switching capacitors and currents (generating multiple approximately parallel gain curves) are used to extend the coverage of the carrier, and the digital control signal related to the frequency division coefficient comes from the outside of the clock circuit [1], and cannot automatically adjust the Frequency adjustment of a certain center frequency relative to PVT fluctuations

Even if some technologies such as threshold voltage detection are applied, using a dynamic bias circuit to change the output value of the control voltage to adjust the deviation of the phase-locked loop frequency to the process and temperature [2] is only applicable to the lower frequency range, that is, the control The voltage range can still cover the center frequency

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