38 results about "Phase frequency detector" patented technology

According to an embodiment, a phased-locked loop (PLL) circuit, within a gyroscope system, generates demodulation signals. It includes a phase frequency detector receiving gyroscope output, which compares a reference signal with a feedback signal to produce an error signal. A charge pump then converts this error into a first analog control signal. A programmable clamp circuit refines this into a second analog control signal. A voltage-controlled oscillator uses the second signal to produce an output signal at a controlled frequency determined by the clamp circuit. A frequency divider sends a comparison frequency signal back to the detector, completing the loop.

The invention discloses a fractional frequency division frequency synthesizer with output signal phase synchronization and frequency modulation continuous wave functions, and the basic structure is a charge pump phase-locked loop. Comprising a phase frequency detector, a first charge pump, a second charge pump, a low-pass filter, a voltage-controlled oscillator, a first buffer, a second buffer, a two-frequency divider chain, an IQ undersampling circuit, a local oscillator generator, a programmable multimode frequency divider, a Delta-Sigma modulator (DSM), a first selector, a second selector, a third selector, a tracking phase accumulator, a numerical control oscillator, an accumulation phase difference register and an atan2 logic circuit. The device comprises a main phase control circuit, a phase adjusting circuit, an enabling control circuit, a waveform generator and a serial peripheral interface. The decimal frequency-division frequency synthesizer can be applied to a general-inductance integrated system, ensures that output signals provided by a plurality of decimal frequency-division frequency synthesizers are consistent in phase in a multi-channel radio frequency transceiving system adopting a multi-chip splicing mode, and can also be applied to the general-inductance integrated system as a sensing signal source; and the speed and the distance of an object can be quickly sensed by the high linearity and the quick chirp capability of an output signal. The decimal frequency division frequency synthesizer is applied to a linear frequency modulation continuous wave radar system, initial phase synchronization can be carried out firstly, then frequency continuous modulation is carried out, and measurement errors can be eliminated. In view of functional similarity of partial modules of the synchronous loop and the FMCW loop, such as a phase frequency detector, a charge pump, a voltage-controlled oscillator and the like, the modules can be shared, so that the power consumption and area cost of the system are remarkably reduced.

In an embodiment, a device includes: phase frequency detector (PFD) circuitry having an input and an output; an oscillator having an input and an output, the input of the oscillator coupled to the output of the PFD circuitry; clock divider circuitry having a first input, a second input, and an output, the first input of the clock divider circuitry coupled to the output of the oscillator, the output of the clock divider circuitry coupled to the input of the PFD circuitry; and a controller having an output coupled to the second input of the clock divider circuitry.

The utility model discloses a Ka wave band broadband transmit-receive front end comprising a local oscillator source module, an X frequency conversion module, a Ka wave band frequency conversion module and an antenna module, the local oscillator source module is respectively connected with the X frequency conversion module and the Ka wave band frequency conversion module, and the X frequency conversion module, the Ka wave band frequency conversion module and the antenna module are connected in sequence. The local oscillator source module comprises a crystal oscillator module, a phase frequency detector, a loop filter, a voltage-controlled oscillator, an N frequency divider and a frequency doubling processing module, the crystal oscillator module, the phase frequency detector, the loop filter, the voltage-controlled oscillator and the frequency doubling processing module are connected in sequence, and the N frequency divider is connected with the phase frequency detector and the voltage-controlled oscillator. The local oscillation source module can stably generate high-quality signals, the transmitting-receiving front end adopts a superheterodyne structure and uses two times of frequency conversion, the first time of frequency conversion is Ka-X wave band frequency conversion, the second time of frequency conversion is X wave band frequency conversion, and mirror image frequency interference is well inhibited by using the two times of frequency conversion.

A fractional-N phase-locked loop (PLL) and its charge pump control method are provided. The fractional-N PLL includes a first current source, a first phase frequency detector (PFD), a second current source, a second PFD, and a frequency divider clock controller. The first current source provides a first current. The first PFD generates a first detection signal based on a first frequency divider clock to control the first current source, wherein the first frequency divider clock is generated based on an oscillation clock with an oscillation period. The second current source provides a second current. The second PFD generates a second detection signal based on a second frequency divider clock to control the second current source. The frequency divider controller controls the second frequency divider clock based on a variable delay relative to the first frequency divider clock, wherein the variable delay is an integer multiple of the oscillation period. Using this method, phase noise can be reduced.

A phase-locked loop circuit includes a phase-frequency detector circuit, a time amplifier circuit, a control circuit, and a variable oscillator circuit, such as a voltage-controlled oscillator. The phase-frequency detector is configured to generate a phase error output indicating a phase difference between a reference signal and a feedback signal generated using an output signal. The time amplifier is configured to extend the phase difference to generate an extended phase error output. The variable oscillator is configured to use one or more control signals generated by the control circuit using the extended phase error to adjust a frequency of the output signal. The control circuit may generate a proportional control signal using a switched-resistor circuit that includes a pull-up resistor and a pull-down resistor. The control circuit may generate an integral control signal using a capacitive-shared-integration circuit that includes passive integrating components.

A phase-locked loop working system includes: a pre-frequency divider, a phase frequency detector, a charge pump, a filter, a voltage-controlled oscillator, a loop frequency divider and a circuit parameter regulator. The phase frequency detector, the charge pump, the filter, the voltage-controlled oscillator and the loop frequency divider are sequentially coupled end to end to form a phase-locked loop circuit. The circuit parameter regulator is coupled to the phase-locked loop circuit and is used to adjust a filtering resistor and a filter capacitor in the filter, to control loop parameters generated by the phase-locked loop circuit to be within a preset margin range. The circuit parameter regulator is coupled to the phase-locked loop circuit and is further used to adjust a frequency-division coefficient of the pre-frequency divider and / or a frequency of the signal to be processed inputted into the pre-frequency divider.

A phase frequency detector circuit, a method for generating a first output signal and a second output signal based on a reference signal and a feedback signal, and a phase-locked loop are provided. The phase frequency detector circuit includes a plurality of reference signals, a plurality of feedback signals, a first output signal, and a second output signal. The plurality of reference signals, including a primary reference signal having a reference triggering edge. The plurality of feedback signals, including a primary feedback signal having a feedback triggering edge. The first output signal and the second output signal indicating a phase difference between the primary reference signal and the primary feedback signal. The first output signal remains asserted after the primary feedback signal arrives, when the phase difference exceeds a max phase difference indicated by a difference between the primary reference signal and the reference signal.

A circuit (100) for a phase-locked loop is described herein. The circuit (100) includes a phase frequency detector (102) configured to determine a phase error; a loop filter (106) coupled to the phase frequency detector (102) and configured to provide a clocked signal based on the phase error; and a controller (116) coupled to the phase frequency detector (102) and the loop filter (106). The controller (116) is configured to receive the phase error, detect a behavior of the phase error, and in response to the behavior of the phase error, perform a response including causing the phase frequency detector (102) to adjust the phase error and causing the loop filter (106) to adjust the clocked signal. Thus, the circuit (100) may reduce setup time, overshoot, and / or undershoot in an output clock generated based on the clock control signal.

In one example, the system includes a phase-locked loop (100) comprising a charge pump (104) coupled to a phase frequency detector (102), a low-pass filter (106) coupled to the charge pump, and a VCO (108) coupled to the low-pass filter, wherein the charge pump is configured to provide a charge pump current (126) to the low-pass filter. The system also includes a current source (114) configured to provide a bias current (130) to the charge pump. The system includes a first bias compensation circuit (116) configured to increase the bias current (130) in response to a control voltage (128) supplied to the VCO being within a first range. The system also includes a second bias compensation circuit (116) configured to decrease the bias current (130) in response to a control voltage (128) supplied to the VCO being within a second range.

The invention relates to the technical field of microelectronics, and discloses a charge pump current mismatch compensation circuit and method and a phase-locked loop system, and the compensation circuit comprises a time-to-digital conversion module which is connected to a phase frequency detector of a phase-locked loop and is configured to detect the pulse width of an uplink signal and a downlink signal output by the phase frequency detector; the compensation current control module is connected with the time-to-digital conversion module and is configured to generate compensation current based on the uplink signal pulse width and the downlink signal pulse width; wherein the compensation current is configured to be input to a charge pump of the phase-locked loop so as to counteract current mismatch of the charge pump in real time. The problem that dynamic compensation cannot be achieved through static optimization in the prior art is solved, output voltage fluctuation of the loop filter is reduced, the stability and precision of the output frequency of the phase-locked loop system are improved, and meanwhile introduction of noise or limitation of the working range is avoided.

A method of measuring phase noise (PN). A PLL frequency synthesizer is provided including a first phase frequency detector (PFD) receiving a reference frequency signal coupled to a first charge pump (CP) coupled to a VCO having an output fedback to the first PFD through a feedback divider that provides a divided frequency signal to the first PFD which outputs an error signal, and PN measurement circuitry including a replica CP coupled to an output of a second PFD or the first PFD. The error signal is received at the replica CP or the divided and reference frequency signal are received at the second PFD, wherein the replica CP outputs a scaled phase error current which is current-to-voltage converted and amplified to provide an amplified phase error voltage, and digitized to provide a digital phase error signal. The digital phase error signal is frequency analyzed to generate a PN measurement.

The present invention constitutes a frequency synchronization loop of an oscillation circuit without using an amplifier for comparing voltages.　This oscillation circuit comprises: an oscillator; and a phase comparison unit that constitutes a feedback loop for the oscillator on the basis of the result of comparing phases obtained by converting the oscillation frequency of the oscillator. The phase comparison unit may include a first sub-oscillator that converts a reference voltage into a phase, and a second sub-oscillator that converts a control voltage obtained by converting the oscillation frequency of the oscillator into a phase. The phase comparison unit may include: a phase frequency detector (PFD) connected to subsequent stages of the first sub-oscillator and the second sub-oscillator; a charge pump circuit connected to a subsequent stage of the PFD; and a loop filter connected to a subsequent stage of the charge pump circuit.

A device may include: a reference divider circuit for dividing a reference clock; a phase-frequency detector circuit for detecting a detected phase difference and a detected frequency difference based on the reference divider output and a feedback clock; a loop filter circuit for filtering the detector output; a voltage-controlled oscillator (VCO) control output pin coupled to the loop filter output; a VCO clock divider control output pin for selecting the divisor of an external clock divider circuit; a divider VCO clock input pin coupled to the output of the external clock divider circuit; a pulse width modulation (PWM) circuit having a PWM clock input coupled to the divider VCO clock input pin; a period register for storing a period value; a duty cycle register for storing a duty cycle value; and a PWM output based on the period value and the duty cycle value.

The application discloses a frequency discriminator and phase detector and a phase-locked loop circuit. The frequency discriminator and phase detector comprises a first digital circuit and a second digital circuit. The signal input end of the first digital circuit receives a first signal and is connected with the configuration end of the second digital circuit. The signal input end of the second digital circuit receives a second signal and is connected with the configuration end of the first digital circuit. The first digital circuit outputs a first level signal when the second signal appears a clock active edge. The first digital circuit outputs a second level signal when the first signal appears a clock active edge twice in succession during the period that the second signal appears a clock active edge twice in succession. The second digital circuit outputs the first level signal when the first signal appears a clock active edge. The second digital circuit outputs the second level signal when the second signal appears a clock active edge twice in succession during the period that the first signal appears a clock active edge twice in succession. For a charge pump type phase-locked loop circuit, the frequency discriminator and phase detector can reduce the matching requirement of the current source for the subsequent charge pump circuit.

The present disclosure relates to a phase frequency detector with saturated output. A phase frequency detector circuit, a method for generating a first output signal and a second output signal based on a reference signal and a feedback signal, and a phase-locked loop are provided. The phase frequency detector circuit comprises a plurality of reference signals, a plurality of feedback signals, a first output signal and a second output signal. The plurality of reference signals comprises a main reference signal having a reference trigger edge. The plurality of feedback signals comprises a main feedback signal having a feedback trigger edge. The first output signal and the second output signal are indicative of a phase difference between the main reference signal and the main feedback signal. The first output signal remains asserted after arrival of the main feedback signal when the phase difference exceeds a maximum phase difference indicated by a difference between the main reference signal and the reference signal.

The invention discloses a high-stability radar flowmeter data acquisition method and a radar flowmeter, relates to the technical field of radar flowmeters, and solves the technical problem of unstable data acquisition results. The method comprises the steps that a radar flowmeter starts to collect an I-channel original signal and a Q-channel original signal, and frequency-selecting amplification of the signals is carried out respectively; the working temperature T of the radar flowmeter is measured, and the gain G of the programmable gain amplifier is determined; performing PGA amplification on the I channel original signal and the Q channel original signal after frequency selection amplification based on a gain selection range; the phase difference between the phase phi 1 and the phase phi 2 is converted into a voltage signal Vf through a phase frequency detector PFD, the voltage signal Vf is converted into a frequency signal F3 through a voltage-frequency converter VFC, and the phase difference delta phi = phi 1-phi 2 is obtained; and comparing the phase difference delta phi with a phase difference threshold value phi s, and judging whether phase compensation is carried out or not. The PGA amplification factor is adjusted based on the temperature, phase compensation can be carried out on the waveform, and the stability of collected data is improved.

The present disclosure relates to a frequency synthesizer capable of generating a full spectrum for ultra-wideband applications by utilizing a single voltage-controlled oscillator (VCO). The disclosed frequency synthesizer includes a phase-frequency detector (PFD), a charge pump (CP), a VCO, a feedback divider, and a divider bank. The PFD, the CP, the VCO, and the feedback divider are coupled in series in a closed loop, while the divider bank follows the VCO and is not included in the closed loop. Herein, the VCO has a tuning range less than 35%. The divider bank includes two or more divider branches parallel to each other, each of which is configured to provide a different division ratio. An oscillating spectrum of the VCO and division ratios of the two or more divider branches are selected such that the divider bank is capable of providing a continuous spectrum with at least a 64% frequency coverage.

Embodiments of the present disclosure relate to fractional N phase-locked loop (PLL) with noise cancellation. A PLL circuit includes a fractional N divider that generates a feedback signal, a first phase frequency detector that compares the feedback signal to a reference signal to generate first up / down control signals that control a charge pump to generate a charge pump output current. A noise cancellation circuit includes a synchronization circuit that generates first and second synchronized feedback signals from the PLL circuit output and the feedback signal, where the first and second synchronized feedback signals are offset by an integer number of cycles of the PLL circuit output. A second phase frequency detector circuit compares the first and second synchronized feedback clock signals to generate second up / down control signals that differ in pulse width by an integer number of PLL cycles. A current digital-to-analog converter circuit is controlled in response to the second up / down control signals to apply a noise cancellation source current and a sink current to the charge pump output current.

The invention relates to a fractional frequency division phase-locked loop for an FMCW radar. The fractional frequency division phase-locked loop comprises a phase frequency detector, a charge pump, a low-pass filter, a voltage-controlled oscillator, a multimode frequency divider, a delta-sigma modulator, a chirp signal generation module and a linearity calibration module, when the fractional frequency division phase-locked loop is in a closed-loop acquisition mode, the chirp signal generation module acquires control voltage time sequence data of the voltage-controlled oscillator in a complete chirp period; and when the fractional frequency division phase-locked loop is in an open-loop driving mode, the chirp signal generation module generates an analog voltage signal according to the control voltage time sequence data, and drives the voltage-controlled oscillator to output a chirp signal. The problems of poor VCO tuning linearity, performance drift at extreme temperature, quantization noise leakage, insufficient multi-target interference adaptation, slow frequency modulation response speed and the like in the prior art are solved, the distance measurement precision of the FMCW radar is improved, and particularly the close-range distance measurement performance and the high-speed target detection capability are improved.

The present disclosure provides a phase-locked loop, a frequency divider and a communication device that enable fast locking. The phase-locked loop comprises a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, a fast-locking control unit and a frequency divider, wherein the frequency divider comprises a plurality of cascaded frequency division units and a reset / set control circuit, the reset / set control circuit being configured to receive the reset signal outputted by the fast-locking control unit, and in response to transition of the reset signal from a low level to the high level, change a state code combination composed of respective state codes of the cascaded frequency division units from the first state to the second state, to cause transition of a feedback signal outputted by the frequency divider from the low level to the high level. With the frequency divider and phase-locked loop, fast locking can be achieved.

The utility model relates to a clock synchronization phase-locked loop based on a fractional order filter. The clock synchronization phase-locked loop comprises a phase frequency detector, a charge pump, a loop order filter and a voltage-controlled oscillator. The phase frequency detector comprises a main clock input end and a local clock input end; the charge pump is electrically connected between the output end of the phase frequency detector and the input end of the loop order filter; the loop order filter is a fractional order filter and comprises an equivalent fractional order capacitor filter circuit and an RC filter circuit which are arranged in parallel; the output end of the loop order filter is electrically connected to the input end of the voltage-controlled oscillator; the output end of the voltage-controlled oscillator outputs a local clock and is electrically connected to the local clock input end of the phase frequency detector. According to the utility model, the circuit realization problem of the fractional order filter is solved, and the performance and the stability of the phase-locked loop are improved based on the construction of the equivalent fractional order capacitor filter circuit.

A circuit includes a phase-frequency-detector generating first and second digital control signals indicative of phase differences between an input reference-signal and an output-signal, a charge-pump generating a control-signal based upon the first and second digital control signals, and an oscillator-circuit. The oscillator-circuit includes an active core coupled between first and second nodes, with a tunable resonant circuit a set of capacitances selectively connected between the first and second nodes, wherein a tap between the first and second variable capacitances receives the control-signal for tuning the tunable resonant circuit. A timer-circuit generates a timing-signal based upon the input reference-signal and a reset-signal. A calibration-circuit controls which capacitances of the set of capacitances are connected between the first and second nodes, in response to the timing-signal and a comparison between a threshold and a voltage-signal that is based upon auxiliary pulsed currents generated based upon the first and second digital control signals.

The invention discloses a high-speed low-noise charge pump phase-locked loop pre-stage circuit, which belongs to the field of integrated circuit radio frequency and comprises a high-speed phase frequency detector and a high-speed charge pump. The high-speed phase frequency detector performs phase frequency detection on the reference signal fREF and the feedback signal fVCO; and the high-speed charge pump performs charging and discharging according to UP and DN signals output by the high-speed phase frequency detector. According to the invention, frequency and phase detection and low-mismatch charging and discharging work can be carried out on an input signal with the highest frequency of 6.4 GHz, and meanwhile, the low-noise performance is considered. According to the high-speed low-noise high-speed phase frequency detector provided by the invention, on the basis of an existing mature SiGe process platform, phase frequency detection and low-mismatch charging and discharging work can be carried out under an input signal with the highest frequency of 6.4 GHz, and meanwhile, the low-noise performance is considered.

The invention relates to the technical field of integrated circuits, and discloses a phase-locked loop structure, system and method for preventing a reference clock signal from jittering and losing lock, and the structure comprises a phase frequency detector of which the first input end is used for receiving the reference clock signal and the second input end is connected to a feedback signal; the input end of the charge pump is connected to the output end of the phase frequency detector; the port of the loop filter is connected to the output end of the charge pump; the input end of the voltage-controlled oscillator is connected to the port of the loop filter, and the output end of the voltage-controlled oscillator provides an output clock signal of the phase-locked loop and forms a feedback signal; the voltage holding module is connected to a port of the loop filter; the control module is respectively connected with the phase frequency detector, the charge pump and the voltage holding module; after one-time locking, even if the reference clock signal is lost or violent jittering occurs, the output of the phase-locked loop cannot be greatly influenced, the stability of the phase-locked loop is enhanced, and the requirement of the phase-locked loop for the application environment is reduced.

Embodiments included herein are directed towards a subranging digital to time converter-based fractional phase locked loop circuit. The circuit may include a digital to time converter and a phase detector circuit configured to receive a reference frequency and an output of the digital to time converter. The circuit may further include a phase frequency detector / charge pump circuit configured to receive the reference frequency and the output of the digital to time converter. The circuit may also include a loop filter and voltage-controlled oscillator circuit configured to receive an output of the phase frequency detector / charge pump circuit. The circuit may further include a divider circuit configured to receive an output of the voltage-controlled oscillator circuit and to transmit a signal to the digital to time converter.

A circuit for reducing a time to switch between the redundant clock signals applied to a phase lock loop. The circuit includes a phase frequency detector of the phase lock loop that detects a shift in the phase of a reference clock signal relative to the phase of a feedback clock signal. The circuit further includes a coarse tuning mechanism configured to delay the feedback clock signal until the feedback clock signal is aligned with a backup reference clock signal. Furthermore, the circuit includes a fine tuning mechanism configured to align the edge of the feedback clock signal with the edge of the backup reference clock signal, such as by utilizing a series of delay elements to delay the backup reference clock signal at different points in time and selecting the appropriate delayed backup reference clock signal whose edge is aligned with the edge of the feedback clock signal.

The invention provides a charge pump phase-locked loop real-time calibration circuit, method and device based on phase detection, and the circuit comprises a time-to-digital conversion circuit, a thermometer code conversion circuit, and a logic state machine circuit. The time-to-digital conversion circuit converts two output signals of the phase frequency detector into time-to-digital signals based on phase-locked loop locking indication signals output by the locking detection circuit, the thermometer code conversion circuit converts the time-to-digital signals into binary codes, and the logic state machine circuit forms calibration feedback control signals based on the binary codes. And transmitting the calibration feedback control signal to a current steering type two-way switch charge pump of a charge pump phase-locked loop circuit so as to calibrate a voltage control signal output by the current steering type two-way switch charge pump in real time. According to the charge pump phase-locked loop real-time calibration circuit, the consistency of the circuit under different processes, temperatures and power voltages can be improved, and the reference stray level of the charge pump phase-locked loop circuit is improved.

A radio frequency (RF) transceiver includes a reference signal source to generate a reference signal, a local RF source to generate a local RF signal, and a mixed signal phase / frequency detector to compare the reference signal to the local RF signal and generate a difference signal from the comparison, wherein the difference signal includes a modulation component and an error component. The transceiver further includes a receiver front end to receive an angle modulated RF signal and downconvert the angle modulated RF signal to a baseband signal, and a quadrature modulator configured to angle modulate the reference signal source with the baseband signal.

In an example, a device includes; phase frequency detector (PFD) circuitry (220) having an input and an output; an oscillator (250) having an input and an output, the input of the oscillator (250) coupled to the output of the PFD circuitry (220); clock divider circuitry (260) having a first input, a second input, and an output, the first input of the clock divider circuitry (260) coupled to the output of the oscillator (250), the output of the clock divider circuitry (260) coupled to the input of the PFD circuitry (220); and a controller (280) having an output coupled to the second input of the clock divider circuitry (260).