71 results about "Phase frequency detector" patented technology

According to an embodiment, a phased-locked loop (PLL) circuit, within a gyroscope system, generates demodulation signals. It includes a phase frequency detector receiving gyroscope output, which compares a reference signal with a feedback signal to produce an error signal. A charge pump then converts this error into a first analog control signal. A programmable clamp circuit refines this into a second analog control signal. A voltage-controlled oscillator uses the second signal to produce an output signal at a controlled frequency determined by the clamp circuit. A frequency divider sends a comparison frequency signal back to the detector, completing the loop.

According to an embodiment, a phased-locked loop (PLL) circuit, within a gyroscope system, generates demodulation signals. It includes a phase frequency detector receiving gyroscope output, which compares a reference signal with a feedback signal to produce an error signal. A charge pump then converts this error into a first analog control signal. A programmable clamp circuit refines this into a second analog control signal. A voltage-controlled oscillator uses the second signal to produce an output signal at a controlled frequency determined by the clamp circuit. A frequency divider sends a comparison frequency signal back to the detector, completing the loop.

The invention discloses a fractional frequency division frequency synthesizer with output signal phase synchronization and frequency modulation continuous wave functions, and the basic structure is a charge pump phase-locked loop. Comprising a phase frequency detector, a first charge pump, a second charge pump, a low-pass filter, a voltage-controlled oscillator, a first buffer, a second buffer, a two-frequency divider chain, an IQ undersampling circuit, a local oscillator generator, a programmable multimode frequency divider, a Delta-Sigma modulator (DSM), a first selector, a second selector, a third selector, a tracking phase accumulator, a numerical control oscillator, an accumulation phase difference register and an atan2 logic circuit. The device comprises a main phase control circuit, a phase adjusting circuit, an enabling control circuit, a waveform generator and a serial peripheral interface. The decimal frequency-division frequency synthesizer can be applied to a general-inductance integrated system, ensures that output signals provided by a plurality of decimal frequency-division frequency synthesizers are consistent in phase in a multi-channel radio frequency transceiving system adopting a multi-chip splicing mode, and can also be applied to the general-inductance integrated system as a sensing signal source; and the speed and the distance of an object can be quickly sensed by the high linearity and the quick chirp capability of an output signal. The decimal frequency division frequency synthesizer is applied to a linear frequency modulation continuous wave radar system, initial phase synchronization can be carried out firstly, then frequency continuous modulation is carried out, and measurement errors can be eliminated. In view of functional similarity of partial modules of the synchronous loop and the FMCW loop, such as a phase frequency detector, a charge pump, a voltage-controlled oscillator and the like, the modules can be shared, so that the power consumption and area cost of the system are remarkably reduced.

In an embodiment, a device includes: phase frequency detector (PFD) circuitry having an input and an output; an oscillator having an input and an output, the input of the oscillator coupled to the output of the PFD circuitry; clock divider circuitry having a first input, a second input, and an output, the first input of the clock divider circuitry coupled to the output of the oscillator, the output of the clock divider circuitry coupled to the input of the PFD circuitry; and a controller having an output coupled to the second input of the clock divider circuitry.

The present invention discloses a primary-secondary delay-locked loop (DLL) with dual delay lines, comprising a power-on reset module (POR), a primary delay-locked loop (DLL1), a secondary delay-locked loop (DLL2), and a lock indication module (LI). The power-on reset module is connected to the reset control module of the primary delay-locked loop (DLL), the output voltage signal (V1) of the primary delay-locked loop (DLL) is connected to the short link of the secondary dual-chain voltage-controlled delay line, an external input clock signal (CLK) is connected to the primary and secondary delay-locked loops, a total reset signal generated by the primary delay-locked loop is connected to the secondary delay-locked loop filter module, and the output signals of the phase frequency detector (PFD) module (PFD1) and the phase frequency detector (PFD) module (PFD2) are respectively connected to the lock indication module. The DLL of the present invention has the advantages of accurate locking and small area overhead.

The utility model discloses a Ka wave band broadband transmit-receive front end comprising a local oscillator source module, an X frequency conversion module, a Ka wave band frequency conversion module and an antenna module, the local oscillator source module is respectively connected with the X frequency conversion module and the Ka wave band frequency conversion module, and the X frequency conversion module, the Ka wave band frequency conversion module and the antenna module are connected in sequence. The local oscillator source module comprises a crystal oscillator module, a phase frequency detector, a loop filter, a voltage-controlled oscillator, an N frequency divider and a frequency doubling processing module, the crystal oscillator module, the phase frequency detector, the loop filter, the voltage-controlled oscillator and the frequency doubling processing module are connected in sequence, and the N frequency divider is connected with the phase frequency detector and the voltage-controlled oscillator. The local oscillation source module can stably generate high-quality signals, the transmitting-receiving front end adopts a superheterodyne structure and uses two times of frequency conversion, the first time of frequency conversion is Ka-X wave band frequency conversion, the second time of frequency conversion is X wave band frequency conversion, and mirror image frequency interference is well inhibited by using the two times of frequency conversion.

A fractional-N phase-locked loop (PLL) and its charge pump control method are provided. The fractional-N PLL includes a first current source, a first phase frequency detector (PFD), a second current source, a second PFD, and a frequency divider clock controller. The first current source provides a first current. The first PFD generates a first detection signal based on a first frequency divider clock to control the first current source, wherein the first frequency divider clock is generated based on an oscillation clock with an oscillation period. The second current source provides a second current. The second PFD generates a second detection signal based on a second frequency divider clock to control the second current source. The frequency divider controller controls the second frequency divider clock based on a variable delay relative to the first frequency divider clock, wherein the variable delay is an integer multiple of the oscillation period. Using this method, phase noise can be reduced.

A phase-locked loop circuit includes a phase-frequency detector circuit, a time amplifier circuit, a control circuit, and a variable oscillator circuit, such as a voltage-controlled oscillator. The phase-frequency detector is configured to generate a phase error output indicating a phase difference between a reference signal and a feedback signal generated using an output signal. The time amplifier is configured to extend the phase difference to generate an extended phase error output. The variable oscillator is configured to use one or more control signals generated by the control circuit using the extended phase error to adjust a frequency of the output signal. The control circuit may generate a proportional control signal using a switched-resistor circuit that includes a pull-up resistor and a pull-down resistor. The control circuit may generate an integral control signal using a capacitive-shared-integration circuit that includes passive integrating components.

A phase-locked loop working system includes: a pre-frequency divider, a phase frequency detector, a charge pump, a filter, a voltage-controlled oscillator, a loop frequency divider and a circuit parameter regulator. The phase frequency detector, the charge pump, the filter, the voltage-controlled oscillator and the loop frequency divider are sequentially coupled end to end to form a phase-locked loop circuit. The circuit parameter regulator is coupled to the phase-locked loop circuit and is used to adjust a filtering resistor and a filter capacitor in the filter, to control loop parameters generated by the phase-locked loop circuit to be within a preset margin range. The circuit parameter regulator is coupled to the phase-locked loop circuit and is further used to adjust a frequency-division coefficient of the pre-frequency divider and / or a frequency of the signal to be processed inputted into the pre-frequency divider.

A phase frequency detector circuit, a method for generating a first output signal and a second output signal based on a reference signal and a feedback signal, and a phase-locked loop are provided. The phase frequency detector circuit includes a plurality of reference signals, a plurality of feedback signals, a first output signal, and a second output signal. The plurality of reference signals, including a primary reference signal having a reference triggering edge. The plurality of feedback signals, including a primary feedback signal having a feedback triggering edge. The first output signal and the second output signal indicating a phase difference between the primary reference signal and the primary feedback signal. The first output signal remains asserted after the primary feedback signal arrives, when the phase difference exceeds a max phase difference indicated by a difference between the primary reference signal and the reference signal.

A circuit (100) for a phase-locked loop is described herein. The circuit (100) includes a phase frequency detector (102) configured to determine a phase error; a loop filter (106) coupled to the phase frequency detector (102) and configured to provide a clocked signal based on the phase error; and a controller (116) coupled to the phase frequency detector (102) and the loop filter (106). The controller (116) is configured to receive the phase error, detect a behavior of the phase error, and in response to the behavior of the phase error, perform a response including causing the phase frequency detector (102) to adjust the phase error and causing the loop filter (106) to adjust the clocked signal. Thus, the circuit (100) may reduce setup time, overshoot, and / or undershoot in an output clock generated based on the clock control signal.

In one example, the system includes a phase-locked loop (100) comprising a charge pump (104) coupled to a phase frequency detector (102), a low-pass filter (106) coupled to the charge pump, and a VCO (108) coupled to the low-pass filter, wherein the charge pump is configured to provide a charge pump current (126) to the low-pass filter. The system also includes a current source (114) configured to provide a bias current (130) to the charge pump. The system includes a first bias compensation circuit (116) configured to increase the bias current (130) in response to a control voltage (128) supplied to the VCO being within a first range. The system also includes a second bias compensation circuit (116) configured to decrease the bias current (130) in response to a control voltage (128) supplied to the VCO being within a second range.

The invention relates to the technical field of frequency synthesizers, and discloses a controllable phase frequency detector, a phase-locked loop and communication equipment. The controllable phase frequency detector comprises a phase detection core circuit, a switching power supply circuit, a clock selection circuit and a control circuit. The clock selection circuit selects one of a reference clock signal and a feedback clock signal to output a gating clock signal according to an input clock selection signal. After the enable signal is valid, the control circuit responds to the first valid clock edge of the gating clock signal and controls the switching power supply circuit to be switched on so as to supply power to the phase detection core circuit. The circuit can be started under a controllable preset initial phase, and the initial output state of the circuit only depends on the setting of a clock selection signal and is irrelevant to the actual phase relation when an input clock is powered on. When the charge pump is used for a phase-locked loop, the locking time can be effectively shortened, the overvoltage risk caused by long-time charging of the charge pump is avoided, and the performance and reliability of the phase-locked loop are improved.

The invention relates to the technical field of microelectronics, and discloses a charge pump current mismatch compensation circuit and method and a phase-locked loop system, and the compensation circuit comprises a time-to-digital conversion module which is connected to a phase frequency detector of a phase-locked loop and is configured to detect the pulse width of an uplink signal and a downlink signal output by the phase frequency detector; the compensation current control module is connected with the time-to-digital conversion module and is configured to generate compensation current based on the uplink signal pulse width and the downlink signal pulse width; wherein the compensation current is configured to be input to a charge pump of the phase-locked loop so as to counteract current mismatch of the charge pump in real time. The problem that dynamic compensation cannot be achieved through static optimization in the prior art is solved, output voltage fluctuation of the loop filter is reduced, the stability and precision of the output frequency of the phase-locked loop system are improved, and meanwhile introduction of noise or limitation of the working range is avoided.

A method of measuring phase noise (PN). A PLL frequency synthesizer is provided including a first phase frequency detector (PFD) receiving a reference frequency signal coupled to a first charge pump (CP) coupled to a VCO having an output fedback to the first PFD through a feedback divider that provides a divided frequency signal to the first PFD which outputs an error signal, and PN measurement circuitry including a replica CP coupled to an output of a second PFD or the first PFD. The error signal is received at the replica CP or the divided and reference frequency signal are received at the second PFD, wherein the replica CP outputs a scaled phase error current which is current-to-voltage converted and amplified to provide an amplified phase error voltage, and digitized to provide a digital phase error signal. The digital phase error signal is frequency analyzed to generate a PN measurement.

An electronic device may include wireless circuitry having mixer circuitry configured to receive oscillator signals from a partial-fractional phase-locked loop (PLL). The partial-fractional PLL may include a phase frequency detector, a charge pump, a loop filter, and a frequency divider connected in a loop. To implement the partial-fractional capability of the PLL, the frequency divider may receive a bitstream from a first order sigma delta modulator and a finite impulse response filter. The first order sigma delta modulator may output a periodic non-randomized output. The finite impulse response filter may increase the frequency of toggling of the periodic non-randomized output. Configured and operated in this way, the partial-fractional PLL can exhibit reduced phase noise.

The present invention constitutes a frequency synchronization loop of an oscillation circuit without using an amplifier for comparing voltages.　This oscillation circuit comprises: an oscillator; and a phase comparison unit that constitutes a feedback loop for the oscillator on the basis of the result of comparing phases obtained by converting the oscillation frequency of the oscillator. The phase comparison unit may include a first sub-oscillator that converts a reference voltage into a phase, and a second sub-oscillator that converts a control voltage obtained by converting the oscillation frequency of the oscillator into a phase. The phase comparison unit may include: a phase frequency detector (PFD) connected to subsequent stages of the first sub-oscillator and the second sub-oscillator; a charge pump circuit connected to a subsequent stage of the PFD; and a loop filter connected to a subsequent stage of the charge pump circuit.

A device may include: a reference divider circuit for dividing a reference clock; a phase-frequency detector circuit for detecting a detected phase difference and a detected frequency difference based on the reference divider output and a feedback clock; a loop filter circuit for filtering the detector output; a voltage-controlled oscillator (VCO) control output pin coupled to the loop filter output; a VCO clock divider control output pin for selecting the divisor of an external clock divider circuit; a divider VCO clock input pin coupled to the output of the external clock divider circuit; a pulse width modulation (PWM) circuit having a PWM clock input coupled to the divider VCO clock input pin; a period register for storing a period value; a duty cycle register for storing a duty cycle value; and a PWM output based on the period value and the duty cycle value.

The invention provides a PLL (Phase Locked Loop) layout structure applied to an MCU (Microprogrammed Control Unit) chip, which is provided with a digital function layout area, an analog function layout area and a signal output layout area, and the digital function layout area comprises a first function area for placing a phase frequency detector; the simulation function layout area comprises a second functional area for placing a charge pump, a third functional area for placing a low-pass filter, a fourth functional area for placing a mirror current source and a fifth functional area for placing a voltage-controlled oscillator; the lower side of the second functional area and the lower side of the fourth functional area are respectively close to the upper side of the first functional area, the left side of the fourth functional area is close to the right side of the second functional area, and the lower side of the third functional area is respectively close to the upper side of the second functional area and the upper side of the fourth functional area. And the right side of the fifth functional area is respectively close to the left sides of the first functional area and the fourth functional area, so that the loop signal stability of the PLL is remarkably improved, and a plurality of PLLs are arranged in the MCU chip in parallel.

The present invention discloses a phase-locked loop (PLL) for adaptively adjusting the dead zone of a phase frequency detector, which relates to an integrated circuit. This solution is proposed to address the problem of difficulty in controlling the dead zone of a phase frequency detector in the prior art. A first capacitor is provided to sample and compare the charging current of the charge pump; a second capacitor is provided to sample and compare the discharge current of the charge pump; a digital algorithm module is provided to adjust the reset pulse width of the phase frequency detector according to the output results of the first comparator and the second comparator; a selection switch is provided to input a reference signal or a feedback signal to the feedback input terminal of the phase frequency detector according to the selection signal of the digital algorithm module. The advantage is that the reset pulse width of the phase frequency detector is controlled according to the results of the two comparators to achieve an optimal value. It can adapt to phase-locked loops under any process node and can ensure that the narrowest available reset pulse width is obtained.

An electronic device may include wireless circuitry having mixer circuitry configured to receive oscillator signals from a partial-fractional phase-locked loop (PLL). The partial-fractional PLL may include a phase frequency detector, a charge pump, a loop filter, and a frequency divider connected in a loop. To implement the partial-fractional capability of the PLL, the frequency divider may receive a bitstream from a first order sigma delta modulator and a finite impulse response filter. The first order sigma delta modulator may output a periodic non-randomized output. The finite impulse response filter may increase the frequency of toggling of the periodic non-randomized output. Configured and operated in this way, the partial-fractional PLL can exhibit reduced phase noise.

The invention discloses an ultra-short dead zone phase frequency detector, a high-speed ultra-low jitter charge pump circuit and a phase-locked loop. The circuit comprises a phase frequency detector, a high-speed level conversion circuit module and a high-speed low-noise charge pump circuit module, the output end of the phase frequency detector is connected with the input end of the high-speed level conversion circuit module, and the input end of the high-speed low-noise charge pump circuit module is connected with the output end of the high-speed level conversion circuit module; the phase frequency detector is used for generating a DN signal and a UP signal according to an input signal; the high-speed level conversion circuit module is used for converting the DN signal and the UP signal into signals adaptive to the high-speed low-noise charge pump circuit module to obtain the converted DN signal and the converted UP signal; and the high-speed low-noise charge pump circuit module is used for obtaining an output current according to the converted DN signal and the converted UP signal. The invention has the advantages of high speed, low noise, low stray, low power consumption and the like.

The application discloses a frequency discriminator and phase detector and a phase-locked loop circuit. The frequency discriminator and phase detector comprises a first digital circuit and a second digital circuit. The signal input end of the first digital circuit receives a first signal and is connected with the configuration end of the second digital circuit. The signal input end of the second digital circuit receives a second signal and is connected with the configuration end of the first digital circuit. The first digital circuit outputs a first level signal when the second signal appears a clock active edge. The first digital circuit outputs a second level signal when the first signal appears a clock active edge twice in succession during the period that the second signal appears a clock active edge twice in succession. The second digital circuit outputs the first level signal when the first signal appears a clock active edge. The second digital circuit outputs the second level signal when the second signal appears a clock active edge twice in succession during the period that the first signal appears a clock active edge twice in succession. For a charge pump type phase-locked loop circuit, the frequency discriminator and phase detector can reduce the matching requirement of the current source for the subsequent charge pump circuit.

The invention relates to the technical field of communication systems, in particular to a charge pump device for mode multiplexing in a CDR, which is judged by a phase frequency detector (PFD), charges UP or discharges DN for a loop filter (LPF), and comprises a current source current mirror module, a current source current mirror module and a mode multiplexing module, the current source and current mirror module comprises a CDR positive current source, a CDR negative current source, a PLL positive current source, a PLL negative current source, an operational amplifier module and a switch module, the CDR positive current source, the CDR negative current source, the PLL positive current source and the PLL negative current source are arranged in a mirror image mode, the switch module comprises a plurality of sets of switches TG and a logic control module, and the logic control module comprises a PLL-mode finite state machine FSM and a CDR-mode finite state machine FSM. The mode multiplexing charge pump device is used for a PLL mode multiplexing charge pump circuit and a CDR mode multiplexing charge pump circuit in a CDR, can rapidly switch between the two modes, keeps high stability, low mismatch and low power consumption at the same time, and reduces the arrangement of operational amplifiers and charge discharge switches, thereby reducing the circuit area.

The present disclosure relates to a phase frequency detector with saturated output. A phase frequency detector circuit, a method for generating a first output signal and a second output signal based on a reference signal and a feedback signal, and a phase-locked loop are provided. The phase frequency detector circuit comprises a plurality of reference signals, a plurality of feedback signals, a first output signal and a second output signal. The plurality of reference signals comprises a main reference signal having a reference trigger edge. The plurality of feedback signals comprises a main feedback signal having a feedback trigger edge. The first output signal and the second output signal are indicative of a phase difference between the main reference signal and the main feedback signal. The first output signal remains asserted after arrival of the main feedback signal when the phase difference exceeds a maximum phase difference indicated by a difference between the main reference signal and the reference signal.

A circuit for an edge-based Phase Frequency Detector (PFD) (200) comprising two edge detectors (103), two SR latches (104), one NAND gate (106), and one NOR gate (107). A reference (Ref) (101) and feedback signals (Fb) (102) are provided to the two edge detector (103) which generates a pulse of active low logic. The output of the edge detector (103) is provided to the two SR latches (104), which provide output signals of the phase frequency detectors. The output of two SR latch (104) is buffered though two invertors (201) and additionally connected to a pair of cross-coupled inverters (202) to generate complementary up (UP and UPb) and down (DN and DNb) signals (105). Phase Frequency Detector (PFD) circuit (200) minimize the number of gates, reducing noise and Random Jitter (RJ), enhance dead zone performance and also reduce the duty cycle of the reference (Ref) (101) and feedback (Fb) signal (102) to a minimal 10%.

The invention relates to the technical field of phase-locked loops, and particularly provides a high-reliability low-power-consumption lock detector which comprises a dead zone pulse processing unit and a lock detection maintaining unit. The dead zone pulse processing unit performs logical operation on the first signal and the second signal output by the phase frequency detector to obtain a first judgment signal; performing logical operation on the second signal and the first judgment signal to obtain a second judgment signal; the lock detection maintaining unit generates a lock decision signal for determining the locked state of the phase-locked loop on the basis of the second decision signal. According to the invention, logic operation is carried out on the signal output by the phase frequency detector, so that an effective pulse signal can be always generated according to the signal output by the phase frequency detector, the dead zone problem is eliminated, and the locking state of the phase-locked loop is judged according to the generated pulse signal; the judgment precision of the locking detection circuit on the locking state of the phase-locked loop is improved, and the overall circuit is low in power consumption.

The invention discloses a high-stability radar flowmeter data acquisition method and a radar flowmeter, relates to the technical field of radar flowmeters, and solves the technical problem of unstable data acquisition results. The method comprises the steps that a radar flowmeter starts to collect an I-channel original signal and a Q-channel original signal, and frequency-selecting amplification of the signals is carried out respectively; the working temperature T of the radar flowmeter is measured, and the gain G of the programmable gain amplifier is determined; performing PGA amplification on the I channel original signal and the Q channel original signal after frequency selection amplification based on a gain selection range; the phase difference between the phase phi 1 and the phase phi 2 is converted into a voltage signal Vf through a phase frequency detector PFD, the voltage signal Vf is converted into a frequency signal F3 through a voltage-frequency converter VFC, and the phase difference delta phi = phi 1-phi 2 is obtained; and comparing the phase difference delta phi with a phase difference threshold value phi s, and judging whether phase compensation is carried out or not. The PGA amplification factor is adjusted based on the temperature, phase compensation can be carried out on the waveform, and the stability of collected data is improved.

The invention provides a decimal-N phase-locked loop system and a control method thereof. In the decimal-N phase-locked loop system, a plurality of phase frequency detectors are arranged, a charge pump module directly coupled to the plurality of phase frequency detectors is arranged, the charge pump module comprises a current circuit with M bits, and the proportion of the magnitude of current generated by performing phase frequency detection on different phase frequency detectors corresponding to the charge pump module is controlled. The step length for realizing the fractional frequency division ratio is used for realizing frequency division; wherein Y represents an integer frequency division ratio, Z represents a decimal frequency division ratio, and Z is less than M. Fractional frequency division can be achieved without a complex circuit, phase noise can be reduced without arranging a calibration circuit, and the overall area and consumption of the circuit are reduced.

A circuit for reducing a time to switch between the redundant clock signals applied to a phase lock loop. The circuit includes a phase frequency detector of the phase lock loop that detects a shift in the phase of a reference clock signal relative to the phase of a feedback clock signal. The circuit further includes a coarse tuning mechanism configured to delay the feedback clock signal until the feedback clock signal is aligned with a backup reference clock signal. Furthermore, the circuit includes a fine tuning mechanism configured to align the edge of the feedback clock signal with the edge of the backup reference clock signal, such as by utilizing a series of delay elements to delay the backup reference clock signal at different points in time and selecting the appropriate delayed backup reference clock signal whose edge is aligned with the edge of the feedback clock signal.