116 results about "Phase frequency detector" patented technology

The invention relates to a phase-locked loop circuit, a clock generator, a chip and electronic equipment, and the phase-locked loop circuit mainly comprises a phase frequency detector which is used for generating a phase detection output signal according to the phase of a reference clock signal and the phase of a feedback clock signal; the proportional path module is used for generating a first control current according to the phase discrimination output signal; the integral path module is used for generating a second control current according to the phase discrimination output signal; the current control oscillation module is used for generating a clock output signal according to the first control current and the second control current; and the feedback frequency divider is used for obtaining a feedback clock signal through frequency division of the clock output signal. According to the phase-locked loop, the advantages of the analog charge pump phase-locked loop and the full-digital phase-locked loop are combined, the generation of a high-performance clock which is small in area, high in bandwidth, stable in loop and low in quantization noise is facilitated, the applicability of the phase-locked loop to the high bandwidth requirement is facilitated, the quantization noise is reduced, and the performance of the phase-locked loop is improved. And unconditional stability of the phase-locked loop is realized theoretically.

The invention belongs to the field of electronic devices, particularly relates to an anti-SET reinforced phase frequency detector, and aims to solve the problems that the existing SET injection can change the output logic state of a PFD (phase frequency detector), and a post-stage circuit obtains a wrong phase difference indication signal. According to the invention, an output UP signal and an output DOWN signal of a first-stage unit are used as the input of an input control logic, and the input control logic outputs four indication signals; the input of the first output control logic is four indication signals, and the output of the first output control logic is a first conduction control signal; the second-stage unit is used for carrying out rising edge sampling on the UP signal and the DOWN signal respectively and outputting two indication signals; the input of the phase selector is a reference clock signal, a feedback clock signal and two indication signals, the output of the phase selector is the input of the second output control logic, and the second output control logic outputs a second conduction control signal. According to the invention, the output logic state is not changed during SET injection, and a correct phase difference indication signal is obtained at a rear stage.

According to an embodiment, a phased-locked loop (PLL) circuit, within a gyroscope system, generates demodulation signals. It includes a phase frequency detector receiving gyroscope output, which compares a reference signal with a feedback signal to produce an error signal. A charge pump then converts this error into a first analog control signal. A programmable clamp circuit refines this into a second analog control signal. A voltage-controlled oscillator uses the second signal to produce an output signal at a controlled frequency determined by the clamp circuit. A frequency divider sends a comparison frequency signal back to the detector, completing the loop.

The invention discloses a phase-locked loop quantization noise calibration method and system, electronic equipment and a storage medium. The method comprises the following steps: a phase frequency detector performs correlation processing on a feedback signal output by a modulator and a reference signal output by a phase discriminator to generate a gain coefficient; multiplying the gain coefficient by a feedback signal output by the modulator to output a first gain signal; subtracting the first gain signal from a reference signal output by the phase discriminator to output a second gain signal; the second gain signal is filtered by the digital loop filter to obtain a filtered signal and the filtered signal is output to the digital time converter; and the digital time converter processes the filtering signal to obtain a pulse signal suitable for being processed by the phase discriminator and outputs the pulse signal to the phase discriminator. The LMS algorithm is adopted, and on the basis of the complementary digital time converter calibration technology, quantization noise is eliminated through a low-energy-consumption circuit.

According to an embodiment, a phased-locked loop (PLL) circuit, within a gyroscope system, generates demodulation signals. It includes a phase frequency detector receiving gyroscope output, which compares a reference signal with a feedback signal to produce an error signal. A charge pump then converts this error into a first analog control signal. A programmable clamp circuit refines this into a second analog control signal. A voltage-controlled oscillator uses the second signal to produce an output signal at a controlled frequency determined by the clamp circuit. A frequency divider sends a comparison frequency signal back to the detector, completing the loop.

The invention discloses a fractional frequency division frequency synthesizer with output signal phase synchronization and frequency modulation continuous wave functions, and the basic structure is a charge pump phase-locked loop. Comprising a phase frequency detector, a first charge pump, a second charge pump, a low-pass filter, a voltage-controlled oscillator, a first buffer, a second buffer, a two-frequency divider chain, an IQ undersampling circuit, a local oscillator generator, a programmable multimode frequency divider, a Delta-Sigma modulator (DSM), a first selector, a second selector, a third selector, a tracking phase accumulator, a numerical control oscillator, an accumulation phase difference register and an atan2 logic circuit. The device comprises a main phase control circuit, a phase adjusting circuit, an enabling control circuit, a waveform generator and a serial peripheral interface. The decimal frequency-division frequency synthesizer can be applied to a general-inductance integrated system, ensures that output signals provided by a plurality of decimal frequency-division frequency synthesizers are consistent in phase in a multi-channel radio frequency transceiving system adopting a multi-chip splicing mode, and can also be applied to the general-inductance integrated system as a sensing signal source; and the speed and the distance of an object can be quickly sensed by the high linearity and the quick chirp capability of an output signal. The decimal frequency division frequency synthesizer is applied to a linear frequency modulation continuous wave radar system, initial phase synchronization can be carried out firstly, then frequency continuous modulation is carried out, and measurement errors can be eliminated. In view of functional similarity of partial modules of the synchronous loop and the FMCW loop, such as a phase frequency detector, a charge pump, a voltage-controlled oscillator and the like, the modules can be shared, so that the power consumption and area cost of the system are remarkably reduced.

In an embodiment, a device includes: phase frequency detector (PFD) circuitry having an input and an output; an oscillator having an input and an output, the input of the oscillator coupled to the output of the PFD circuitry; clock divider circuitry having a first input, a second input, and an output, the first input of the clock divider circuitry coupled to the output of the oscillator, the output of the clock divider circuitry coupled to the input of the PFD circuitry; and a controller having an output coupled to the second input of the clock divider circuitry.

The present invention discloses a primary-secondary delay-locked loop (DLL) with dual delay lines, comprising a power-on reset module (POR), a primary delay-locked loop (DLL1), a secondary delay-locked loop (DLL2), and a lock indication module (LI). The power-on reset module is connected to the reset control module of the primary delay-locked loop (DLL), the output voltage signal (V1) of the primary delay-locked loop (DLL) is connected to the short link of the secondary dual-chain voltage-controlled delay line, an external input clock signal (CLK) is connected to the primary and secondary delay-locked loops, a total reset signal generated by the primary delay-locked loop is connected to the secondary delay-locked loop filter module, and the output signals of the phase frequency detector (PFD) module (PFD1) and the phase frequency detector (PFD) module (PFD2) are respectively connected to the lock indication module. The DLL of the present invention has the advantages of accurate locking and small area overhead.

Embodiments of a clock synchronization unit of an all-digital phase-locked loop (ADPLL), a successive approximation register (SAR) time-to-digital converter (TDC) of the ADPLL, and a clock synchronization method in the ADPLL are disclosed. In one embodiment, the clock synchronization unit of the ADPLL includes a dual flip-flop synchronizer, a phase frequency detector (PFD) connected to the dual flip-flop synchronizer, and a synchronization control circuit configured to control the dual flip-flop synchronizer and the PFD to perform clock synchronization between a reference clock input signal and a divided clock input signal, and to control the dual flip-flop synchronizer and the PFD to perform the clock synchronization between the reference clock input signal and the divided clock input signal with PFD operation instead. Other embodiments are also described.

The utility model discloses a Ka wave band broadband transmit-receive front end comprising a local oscillator source module, an X frequency conversion module, a Ka wave band frequency conversion module and an antenna module, the local oscillator source module is respectively connected with the X frequency conversion module and the Ka wave band frequency conversion module, and the X frequency conversion module, the Ka wave band frequency conversion module and the antenna module are connected in sequence. The local oscillator source module comprises a crystal oscillator module, a phase frequency detector, a loop filter, a voltage-controlled oscillator, an N frequency divider and a frequency doubling processing module, the crystal oscillator module, the phase frequency detector, the loop filter, the voltage-controlled oscillator and the frequency doubling processing module are connected in sequence, and the N frequency divider is connected with the phase frequency detector and the voltage-controlled oscillator. The local oscillation source module can stably generate high-quality signals, the transmitting-receiving front end adopts a superheterodyne structure and uses two times of frequency conversion, the first time of frequency conversion is Ka-X wave band frequency conversion, the second time of frequency conversion is X wave band frequency conversion, and mirror image frequency interference is well inhibited by using the two times of frequency conversion.

The invention belongs to the field of global navigation satellite systems, and discloses a PPP-B2b-based high-precision time service method, which mainly comprises a PPP resolving module, a loop filter and a constant-temperature crystal oscillator + DDS (Direct Digital Synthesizer) combined circuit. The PPP resolving module is equivalent to a phase frequency detector in a delay locking loop, realizes a real-time precise point single positioning function by adopting double-frequency observed quantity and precise correction of a Beidou satellite navigation system, and outputs a precise clock error; a loop filter is equivalent to a loop filter in a carrier ring, a second-order frequency-locked loop is adopted to assist a third-order phase-locked loop structure, and frequency ramp-up excitation can be stably tracked; the combination of the constant-temperature crystal oscillator and the DDS is equivalent to a numerical control oscillator (NCO), and the precise adjustment of the clock frequency can be realized. Compared with a traditional high-precision time service terminal, the high-precision time service terminal does not depend on GPS observed quantity and precise correction information of the internet, a relatively low constant-temperature crystal oscillator instead of an atomic clock is adopted as a clock source, and the quantization error problem of second pulse output is solved.

A fractional-N phase-locked loop (PLL) and its charge pump control method are provided. The fractional-N PLL includes a first current source, a first phase frequency detector (PFD), a second current source, a second PFD, and a frequency divider clock controller. The first current source provides a first current. The first PFD generates a first detection signal based on a first frequency divider clock to control the first current source, wherein the first frequency divider clock is generated based on an oscillation clock with an oscillation period. The second current source provides a second current. The second PFD generates a second detection signal based on a second frequency divider clock to control the second current source. The frequency divider controller controls the second frequency divider clock based on a variable delay relative to the first frequency divider clock, wherein the variable delay is an integer multiple of the oscillation period. Using this method, phase noise can be reduced.

A phase-locked loop circuit includes a phase-frequency detector circuit, a time amplifier circuit, a control circuit, and a variable oscillator circuit, such as a voltage-controlled oscillator. The phase-frequency detector is configured to generate a phase error output indicating a phase difference between a reference signal and a feedback signal generated using an output signal. The time amplifier is configured to extend the phase difference to generate an extended phase error output. The variable oscillator is configured to use one or more control signals generated by the control circuit using the extended phase error to adjust a frequency of the output signal. The control circuit may generate a proportional control signal using a switched-resistor circuit that includes a pull-up resistor and a pull-down resistor. The control circuit may generate an integral control signal using a capacitive-shared-integration circuit that includes passive integrating components.

A phase-locked loop working system includes: a pre-frequency divider, a phase frequency detector, a charge pump, a filter, a voltage-controlled oscillator, a loop frequency divider and a circuit parameter regulator. The phase frequency detector, the charge pump, the filter, the voltage-controlled oscillator and the loop frequency divider are sequentially coupled end to end to form a phase-locked loop circuit. The circuit parameter regulator is coupled to the phase-locked loop circuit and is used to adjust a filtering resistor and a filter capacitor in the filter, to control loop parameters generated by the phase-locked loop circuit to be within a preset margin range. The circuit parameter regulator is coupled to the phase-locked loop circuit and is further used to adjust a frequency-division coefficient of the pre-frequency divider and / or a frequency of the signal to be processed inputted into the pre-frequency divider.

A phase frequency detector circuit, a method for generating a first output signal and a second output signal based on a reference signal and a feedback signal, and a phase-locked loop are provided. The phase frequency detector circuit includes a plurality of reference signals, a plurality of feedback signals, a first output signal, and a second output signal. The plurality of reference signals, including a primary reference signal having a reference triggering edge. The plurality of feedback signals, including a primary feedback signal having a feedback triggering edge. The first output signal and the second output signal indicating a phase difference between the primary reference signal and the primary feedback signal. The first output signal remains asserted after the primary feedback signal arrives, when the phase difference exceeds a max phase difference indicated by a difference between the primary reference signal and the reference signal.

A circuit (100) for a phase-locked loop is described herein. The circuit (100) includes a phase frequency detector (102) configured to determine a phase error; a loop filter (106) coupled to the phase frequency detector (102) and configured to provide a clocked signal based on the phase error; and a controller (116) coupled to the phase frequency detector (102) and the loop filter (106). The controller (116) is configured to receive the phase error, detect a behavior of the phase error, and in response to the behavior of the phase error, perform a response including causing the phase frequency detector (102) to adjust the phase error and causing the loop filter (106) to adjust the clocked signal. Thus, the circuit (100) may reduce setup time, overshoot, and / or undershoot in an output clock generated based on the clock control signal.

In one example, the system includes a phase-locked loop (100) comprising a charge pump (104) coupled to a phase frequency detector (102), a low-pass filter (106) coupled to the charge pump, and a VCO (108) coupled to the low-pass filter, wherein the charge pump is configured to provide a charge pump current (126) to the low-pass filter. The system also includes a current source (114) configured to provide a bias current (130) to the charge pump. The system includes a first bias compensation circuit (116) configured to increase the bias current (130) in response to a control voltage (128) supplied to the VCO being within a first range. The system also includes a second bias compensation circuit (116) configured to decrease the bias current (130) in response to a control voltage (128) supplied to the VCO being within a second range.

The invention relates to the technical field of frequency synthesizers, and discloses a controllable phase frequency detector, a phase-locked loop and communication equipment. The controllable phase frequency detector comprises a phase detection core circuit, a switching power supply circuit, a clock selection circuit and a control circuit. The clock selection circuit selects one of a reference clock signal and a feedback clock signal to output a gating clock signal according to an input clock selection signal. After the enable signal is valid, the control circuit responds to the first valid clock edge of the gating clock signal and controls the switching power supply circuit to be switched on so as to supply power to the phase detection core circuit. The circuit can be started under a controllable preset initial phase, and the initial output state of the circuit only depends on the setting of a clock selection signal and is irrelevant to the actual phase relation when an input clock is powered on. When the charge pump is used for a phase-locked loop, the locking time can be effectively shortened, the overvoltage risk caused by long-time charging of the charge pump is avoided, and the performance and reliability of the phase-locked loop are improved.

The invention relates to the technical field of microelectronics, and discloses a charge pump current mismatch compensation circuit and method and a phase-locked loop system, and the compensation circuit comprises a time-to-digital conversion module which is connected to a phase frequency detector of a phase-locked loop and is configured to detect the pulse width of an uplink signal and a downlink signal output by the phase frequency detector; the compensation current control module is connected with the time-to-digital conversion module and is configured to generate compensation current based on the uplink signal pulse width and the downlink signal pulse width; wherein the compensation current is configured to be input to a charge pump of the phase-locked loop so as to counteract current mismatch of the charge pump in real time. The problem that dynamic compensation cannot be achieved through static optimization in the prior art is solved, output voltage fluctuation of the loop filter is reduced, the stability and precision of the output frequency of the phase-locked loop system are improved, and meanwhile introduction of noise or limitation of the working range is avoided.

The invention belongs to the technical field of integrated circuits, and particularly relates to a phase frequency detector applied to a satellite-borne wireless communication system. The circuit structure of the phase frequency detector comprises an anti-radiation phase frequency detector core circuit, a power detection circuit, an analog-to-digital converter and a control module circuit, an input signal is input to the anti-radiation phase frequency detector core circuit, and an output signal is generated and output to the power detection circuit. The power detection circuit processes the received signal, outputs a processing result to the analog-to-digital converter, receives an instruction of the control module circuit and generates an output signal of the whole circuit; the analog-to-digital converter converts a processing result output by the power detection circuit into a digital signal and outputs the digital signal to the control module circuit; the control module circuit performs judgment according to the input digital signal, generates a control signal for controlling the working mode of the anti-radiation phase frequency detector core circuit, and generates a control signal for controlling the power detection circuit and the analog-to-digital converter; the radiation-proof phase frequency detector core circuit is composed of four identical phase frequency detector branches, a logic gate circuit and six numerical control single-pole double-throw switches. The two paths of phase frequency detector branches connected with the same input signal can be switched under the control of the numerical control switch, and by applying the structure, the circuit failure probability caused by space irradiation can be remarkably reduced, and the anti-irradiation performance and the stability of the circuit are improved.

A phase-locked loop circuit includes a phase frequency detector (PFD) circuit, a digital code generator circuit, a frequency divider and an oscillator circuit. The PFD circuit is configured to detect a difference in phase and frequency between a reference clock and a feedback clock to generate a first control signal and a second control signal. The digital code generator circuit is configured to process the second control signal to generate a digital code. The frequency divider is configured to receive an output clock to generate the feedback clock. The oscillator circuit is configured to generate the output clock according to the first control signal and the digital code. A frequency of the output clock is determined according to a first control parameter and a second control parameter of different types. The first and second control parameters are adjusted in response to the first control signal and the digital code respectively.

The embodiment of the invention provides a clock circuit phase drift compensation circuit, a clock chip, an array and a system, and the clock circuit phase drift compensation circuit comprises a phase frequency detector which obtains a reference clock signal and a feedback clock signal, and determines an error voltage signal based on the reference clock signal and the feedback clock signal; the filter is used for filtering the transmitted error voltage signal; the voltage-controlled oscillator receives the filtered error voltage signal and adjusts the frequency of the current clock signal according to the error voltage signal; the buffer is connected with the output end of the voltage-controlled oscillator; feedback branches connected with the multiplexer are respectively arranged behind the multiplexer, the voltage-controlled oscillator and the buffer; and the frequency divider is connected between the multiplexers and the phase frequency detectors, carries out frequency division on the signals of the feedback branches selected by the multiplexers to obtain feedback clock signals, and sends the feedback clock signals to the phase frequency detectors.

A method of measuring phase noise (PN). A PLL frequency synthesizer is provided including a first phase frequency detector (PFD) receiving a reference frequency signal coupled to a first charge pump (CP) coupled to a VCO having an output fedback to the first PFD through a feedback divider that provides a divided frequency signal to the first PFD which outputs an error signal, and PN measurement circuitry including a replica CP coupled to an output of a second PFD or the first PFD. The error signal is received at the replica CP or the divided and reference frequency signal are received at the second PFD, wherein the replica CP outputs a scaled phase error current which is current-to-voltage converted and amplified to provide an amplified phase error voltage, and digitized to provide a digital phase error signal. The digital phase error signal is frequency analyzed to generate a PN measurement.

An electronic device may include wireless circuitry having mixer circuitry configured to receive oscillator signals from a partial-fractional phase-locked loop (PLL). The partial-fractional PLL may include a phase frequency detector, a charge pump, a loop filter, and a frequency divider connected in a loop. To implement the partial-fractional capability of the PLL, the frequency divider may receive a bitstream from a first order sigma delta modulator and a finite impulse response filter. The first order sigma delta modulator may output a periodic non-randomized output. The finite impulse response filter may increase the frequency of toggling of the periodic non-randomized output. Configured and operated in this way, the partial-fractional PLL can exhibit reduced phase noise.

The present invention constitutes a frequency synchronization loop of an oscillation circuit without using an amplifier for comparing voltages.　This oscillation circuit comprises: an oscillator; and a phase comparison unit that constitutes a feedback loop for the oscillator on the basis of the result of comparing phases obtained by converting the oscillation frequency of the oscillator. The phase comparison unit may include a first sub-oscillator that converts a reference voltage into a phase, and a second sub-oscillator that converts a control voltage obtained by converting the oscillation frequency of the oscillator into a phase. The phase comparison unit may include: a phase frequency detector (PFD) connected to subsequent stages of the first sub-oscillator and the second sub-oscillator; a charge pump circuit connected to a subsequent stage of the PFD; and a loop filter connected to a subsequent stage of the charge pump circuit.

A device may include: a reference divider circuit for dividing a reference clock; a phase-frequency detector circuit for detecting a detected phase difference and a detected frequency difference based on the reference divider output and a feedback clock; a loop filter circuit for filtering the detector output; a voltage-controlled oscillator (VCO) control output pin coupled to the loop filter output; a VCO clock divider control output pin for selecting the divisor of an external clock divider circuit; a divider VCO clock input pin coupled to the output of the external clock divider circuit; a pulse width modulation (PWM) circuit having a PWM clock input coupled to the divider VCO clock input pin; a period register for storing a period value; a duty cycle register for storing a duty cycle value; and a PWM output based on the period value and the duty cycle value.

A pulse limiter circuit of a phase-locked loop (PLL) receives, from a phase frequency detector of the PLL, first second input pulses, where pulse widths of the first and second input pulses indicate whether a reference clock signal leads or lags a feedback clock signal. The pulse limiter circuit determines whether a pulse width of the first or second input pulse is greater than a selected duration indicative of transient phase jitter. Based on determining the pulse width of the first or second input pulse is greater than the selected duration, the pulse limiter circuit sets a pulse width of a first output pulse equal to a pulse width of a second output pulse width and outputs the first and second output pulses to a charge pump of the PLL, such that no phase adjustment to the feedback clock signal is made based on the first and second input pulses.

The invention relates to a phase frequency detector circuit with radiation hardening. The phase frequency detector circuit comprises a first D flip-flop circuit, a second D flip-flop circuit, a C unit circuit and a frequency locking indication unit circuit, the first D flip-flop circuit and the second D flip-flop circuit are the same in structure, each of the first D flip-flop circuit and the second D flip-flop circuit comprises a first DICE latch circuit and a second DICE latch circuit which are connected in sequence, and the DICE latch circuits are controlled by zero setting signals and clock signals; two input ends of the C unit circuit are respectively connected with output ends of the first D flip-flop circuit and the second D flip-flop circuit, and an output signal of the C unit circuit is fed back to the first D flip-flop circuit and the second D flip-flop circuit as a zero setting signal; the input end of the frequency locking indication unit circuit is connected with the output ends of the first D flip-flop circuit and the second D flip-flop circuit, and the output end of the frequency locking indication unit circuit outputs a frequency locking indication signal. According to the invention, the anti-radiation reinforcement design of the phase frequency detector circuit is realized.

The invention discloses a phase-locked loop circuit based on PID control, and relates to the technical field of integrated circuits, and the main points of the technical scheme are that the phase-locked loop circuit comprises a phase frequency detector, a PID gain module, an oscillator, a self-adaptive PID controller and a frequency divider; the PID gain module comprises three gain paths, and the three gain paths respectively carry out proportional, integral and differential control on the received clock error signals and superpose and output the signals to the oscillator; the oscillator generates an oscillation signal, the frequency divider outputs a feedback clock signal after carrying out frequency division on the oscillation signal, and the adaptive PID controller is provided with a plurality of gain control ends corresponding to gain paths; in the self-adaptive PID controller, phase detection is carried out on a feedback clock signal, a feedback phase signal is generated, combinational logic processing is carried out on the feedback phase signal, a gain control signal corresponding to the gain path is generated, and therefore the oscillation signal is adjusted. The method has the characteristics of reducing overshoot, improving the stability of the system and being flexible in control.

The invention provides a PLL (Phase Locked Loop) layout structure applied to an MCU (Microprogrammed Control Unit) chip, which is provided with a digital function layout area, an analog function layout area and a signal output layout area, and the digital function layout area comprises a first function area for placing a phase frequency detector; the simulation function layout area comprises a second functional area for placing a charge pump, a third functional area for placing a low-pass filter, a fourth functional area for placing a mirror current source and a fifth functional area for placing a voltage-controlled oscillator; the lower side of the second functional area and the lower side of the fourth functional area are respectively close to the upper side of the first functional area, the left side of the fourth functional area is close to the right side of the second functional area, and the lower side of the third functional area is respectively close to the upper side of the second functional area and the upper side of the fourth functional area. And the right side of the fifth functional area is respectively close to the left sides of the first functional area and the fourth functional area, so that the loop signal stability of the PLL is remarkably improved, and a plurality of PLLs are arranged in the MCU chip in parallel.