115 results about "Analogue electronics" patented technology

A multi-input low-dropout (LDO) linear voltage stabilizing circuit and a control method therefor. The multi-input LDO linear voltage stabilizing circuit comprises a LDO unit, comprising a first LDO linear regulator (LDO1) and a second LDO linear regulator (LDO2) connected to a same output node, wherein the first LDO linear regulator (LDO1) comprises a first operational amplifier (AMP1) and a first power device (201), the input voltage of the first LDO linear regulator (LDO1) is a first input voltage (VIN), the second LDO linear regulator (LDO2) comprises a second operational amplifier (AMP2) and a second power device (202), and the input voltage of the second LDO linear regulator (LDO2) is a second input voltage (BIAS); and a reference voltage selection unit (10), used for selecting, when the first LDO linear regulator (LDO1) is switched to the second LDO linear regulator (LDO2), the reference voltage of the first operational amplifier (AMP1) as a second reference voltage (VREFb), and the reference voltage of the second operational amplifier (AMP2) as a first reference voltage (VREFa), wherein the first reference voltage (VREFa) is higher than the second reference voltage (VREFb). By optimizing the structure and the working time sequence of a multi-input LDO circuit, stable switching among different LDOs can be achieved, the power supply fluctuation amplitude of an internal analog circuit is greatly reduced, the output voltage of the LDOs during different switching does not trigger UVLO by mistake, and the normal working state and good performance of the circuit are guaranteed.

The invention provides a wind turbine generator grid-connected broadband oscillation power grid simulation method, system and device and a medium, and belongs to the technical field of power system new energy grid connection, and the method comprises the steps: carrying out the frequency sweeping of a network side part of a physical wind turbine generator grid-connected system, and obtaining a full-band dq impedance characteristic curve; performing segmentation processing on the full-band dq impedance characteristic curve according to frequency; performing rational function fitting on the dq impedance characteristic curve of each frequency band by using a least square method, and enabling the network side part of the physical wind turbine generator grid-connected system to be equivalent to an RLC branch; constructing an impedance circuit, a main circuit and a signal processing module for each frequency band, and completing the construction of a broadband oscillation working condition simulation circuit; and the broadband impedance dynamic characteristics of the physical wind turbine generator grid-connected system are reproduced through the broadband oscillation working condition simulation circuit, so that the grid-connected stability of the physical wind turbine generator is detected. According to the invention, the simulation precision of the power grid simulator based on the power electronic converter topology is prevented from being limited by switching frequency and control precision.

The device may include a housing assembly. Also, the device may include analog circuitry electrically connected to a power source. Furthermore, the device may include the analog circuitry configured to detect the presence of voltage. In addition, the device may include the analog circuitry configured to test connectivity to the power source. Moreover, the device may include means for a user to initiate a test for the absence of voltage. Also, the device may include a supervisory test circuit within the analog circuitry to verify that the AVT is functioning properly. Furthermore, the device may include a visual indicator within the analog circuitry to confirm the absence of voltage after an absence of voltage test has been performed. In addition, the device may include a secondary power source operatively connected to the supervisory test circuit for powering the supervisory test circuit.

The invention provides a joint simulation method, system and equipment for power supply integrity and signal integrity. The joint simulation method comprises the following steps: acquiring a first excitation signal; the first excitation signal is obtained by a first simulation result obtained by performing power supply integrity simulation on the to-be-tested system according to the second excitation signal; and performing signal integrity simulation on the to-be-tested system according to the first excitation signal and the second excitation signal to generate a second simulation result. According to the invention, by using the result of the power supply integrity simulation as the input of the signal integrity simulation, the power supply dynamic state of the circuit in the actual working environment can be simulated more accurately, and the influence of the power supply noise on the signal quality can be revealed, so that the potential problem can be avoided in the design stage. In addition, the problem of excessive design caused by separate simulation of SI simulation and PI simulation can be avoided, so that a better solution is provided for PPA and cost of a high-speed interface system.

Provided in the present invention are a temperature effect calibration circuit and method for voltage measurement, and a battery management system and a vehicle. The temperature effect calibration circuit for voltage measurement comprises: a temperature measurement module, which performs measurement and outputs a temperature measurement signal; a sampling module, which samples a voltage to be measured; a reference voltage generation module, which generates a reference voltage; a quantization module, which converts into a digital signal an analog signal output by the sampling module; a compensation parameter calculation module, which performs quadratic fitting and calculation to obtain compensation parameters; and a temperature effect correction module, which corrects an output signal of the quantization module at a current temperature to obtain a corrected voltage measurement signal. In the present invention, there is no need to add a complex circuit design to an analog circuit domain, and thus the design is easier to implement; the requirement for a temperature coefficient of a device in the process is reduced, and thus the technical solution can be applied to various different process nodes; and calibration is performed at a digital backend, and only one instance of full-temperature-range scanning is required during the factory testing of a chip, without spending a large amount of time on a high / low-temperature test, thereby effectively reducing costs.

A signal predistortion circuit configuration includes a digital predistortion (DPD) circuit, a first transceiver, and a second transceiver, and can reduce the influence of poor signal path insulation when performing a DPD training. During the DPD training, the DPD circuit transmits a training signal through a first signal path to adjust first predistortion parameters, and transmits a training signal through a second signal path to adjust second predistortion parameters. The first signal path includes: a transmitting circuit and an analog-front-end circuit of the first transceiver, a receiving analog circuit and a switch circuit of the second transceiver, and a switch circuit and an analog-to-digital converter (ADC) of the first transceiver. The second signal path includes: a transmitting circuit and an analog-front-end circuit of the second transceiver, a receiving analog circuit and the switch circuit of the first transceiver, and the switch circuit and an ADC of the second transceiver.

The application discloses a kind of anti-radiation reinforcement circuits of fast radiation charge, it is related to the field of semiconductor integrated circuit design.The present application is to solve the problem of large area, large power consumption of existing circuit level anti-radiation reinforcement mode, and cannot be applied in the anti-radiation reinforcement design of analog circuit.The voltage generating circuit of the present application is used to provide voltage for charge discharge circuit to trigger charge discharge circuit, so that the charge radiated to the output node of charge discharge circuit is discharged.When the positive voltage pulse of output end appears due to the positive charge pulse generated by radiation particle, the gate of positive charge discharge tube appears positive voltage pulse, the positive charge discharge tube is turned on, and the negative charge discharge tube is closed, so that the positive charge radiated to the output end is discharged;When the negative voltage pulse of output end appears due to the negative charge pulse generated by radiation particle, the gate of negative charge discharge tube appears negative voltage pulse, the negative charge discharge tube is turned on, and the positive charge discharge tube is closed, so that the negative charge radiated to the output end is discharged.

The present application relates to the technical field of analog circuit, and discloses a charge pump.The charge pump comprises a first voltage boosting control circuit, a second voltage boosting control circuit, a first voltage lifting circuit and a second voltage lifting circuit.The first voltage boosting control circuit can generate a first multiplex signal at a first node and a second multiplex signal at a second node in response to an input voltage and a control signal.The second voltage boosting control circuit comprises a third node and a fourth node.The first voltage lifting circuit is connected between the first node and the third node, and the second voltage lifting circuit is connected between the second node and the fourth node.When the control signal is a first level signal, the first voltage lifting circuit lifts the voltage of the third node to a first multiplex voltage according to the first multiplex signal, and the second voltage boosting control circuit outputs a target voltage in response to the first multiplex voltage of the third node and the input voltage.The same is true when the control signal is a second level signal.Therefore, the embodiment does not need to increase an additional circuit to drive the charge pump.

Methods, systems, and devices for techniques for coupled host and memory dies are described. As part of a low-speed testing phase of a memory system, a low-speed tester may measure the change in phase of a set of clock signals in response to a change in a configuration of the memory system. For example, the low-speed tester may communicate with a mimic circuit of the memory system to determine a first frequency of a first clock signal of the multi-phase clock associated with a first configuration of the memory system and determine a second frequency of the first clock signal associated with a second configuration of the memory system. The low-speed tester may store an indication of the difference between the first frequency and the second frequency, and a high-speed tester may use the difference as part of selecting a set of trim parameters for the multi-phase clock signal.

The utility model provides a load simulation circuit and a rack-mounted load box, and belongs to the field of load boxes, the load simulation circuit comprises a rectification circuit, a diverter, a power module, a fan module and a control and drive circuit, the power module comprises at least one heating tube and at least one transistor, the control and drive circuit comprises a main control circuit, a voltage signal processing circuit, a current signal processing circuit, a power setting and display module and at least one IGBT drive circuit, the base electrode of the transistor is connected to the main control circuit through the IGBT drive circuit, and the power setting and display module is connected to the main control circuit; the transistor is connected to the main control circuit through the IGBT driving circuit, the duty ratio adjusting range of the transistor is from 0 to 1, with the rated power of the heating tubes being 2kW as an example, the output power adjusting range of the heating tubes is from 0 to 2kW, and when the three heating tubes are connected in parallel and the rated power of each heating tube is 2kW, the power of the load simulation circuit can be adjusted within the range of 0-6kW. The problem that an existing load box is large in power span is solved, and high-precision power adjustment of the load box is achieved.

The application provides an adaptive ambient light compensation circuit, aiming at the ambient light interference problem in a photoelectric measurement system, and realizes high-precision ambient light compensation through an integrated analog circuit. The circuit adopts PMOS, NMOS transistors and various amplifiers, resistors, capacitors and switch elements, and builds a system capable of self-adaptive adjustment and elimination of the influence of ambient light current. Compared with the prior art, the application utilizes adaptive current sinking and replication current technology, effectively expands the ambient light compensation range to 0-5mA, reduces the circuit area and improves the integration. In addition, by optimizing the design of the filter capacitor and resistor, the settling time is further shortened, and the trade-off problem between the filter bandwidth and the settling time is avoided. The adaptive ambient light compensation circuit of the application has a wide application prospect in the photoelectric measurement system, and can significantly improve the measurement dynamic range and accuracy.

The present disclosure relates to a wafer test circuit unit and method, a wafer test circuit, and a wafer. The wafer test circuit unit is used for wafer testing. The wafer includes a grain area and a scribe line. The grain area includes at least one grain. The wafer test circuit unit includes a test pad, a control pad, and a parasitic resistance simulation circuit. The test pad is arranged on the scribe line for inputting a test signal. The control pad is arranged on the scribe line for inputting a control signal. The parasitic resistance simulation circuit is respectively connected to the test pad, the control pad, and the grain for simulating the external parasitic resistance of the grain, and transmitting the test signal to the grain in response to the control signal.

The present disclosure describes a system with an antenna, a signal generator, data converters, and an aggregator circuit. The antenna is configured to provide an input signal to the data converters. The signal generator is configured to generate a random binary sequence received by the data converters. The data converters include an analog circuit and a digital circuit configured to sample positive and negative polarities of the input signal based on the random binary sequence, reducing an offset tone in an output spectrum produced by the aggregator circuit.

The application discloses a CAN frame double-edge resynchronization decoding method and device, equipment and a storage medium, and relates to the field of signal processing. The scheme obtains the CAN frame signal of the sending end through the CAN simulation circuit, converts the digital waveform, and performs edge detection; based on the clock frequencies of the receiving end and the sending end, the rising edge delay and the falling edge delay of the sending end edge signal relative to the receiving end when the receiving end captures the edge signal are determined; the delay correction configuration is performed based on the rising edge delay and the falling edge delay, and the level timing and signal sampling are performed based on the edge signal after the delay correction; and the CAN frame information is decoded and output based on the bit value output by the signal sampling. The technology accurately calculates and corrects the edge delay difference caused by the clock deviation through the double-edge resynchronization mechanism, effectively corrects the timing deviation in combination with the dynamically adjusted sampling point position, has the advantages of effectively coping with the risk of synchronization failure and improving the decoding stability.

1. Name of the product in this design: Discharge Detection Device. 2. Purpose of this design: This design is used to simulate electrical contact discharge on a circuit board, detect the critical distance during discharge, and present the test results via an oscilloscope. 3. The key design feature of this product is its shape. 4. The image or photograph that best illustrates the design's key points: 3D view 1. 5. Other situations requiring explanation: Part A is made of transparent material.

The invention relates to a PCB circuit of a three-degree-of-freedom Duffing type MEMS resonator and an event-triggered fuzzy neural network inversion control method, and belongs to the technical field of MEMS resonator control, and the method comprises the steps: constructing an electrostatic coupling three-degree-of-freedom Duffing type MEMS resonator based on a series mode, and building a mathematical model; the method comprises the following steps: designing an analog circuit of a three-degree-of-freedom Duffing type MEMS resonator, and constructing a PCB experiment platform; designing an inversion controller based on a logarithmic obstacle Lyapunov function, an acceleration function, an acceleration exponential integral tracking differentiator and a type-2 fuzzy wavelet neural network; and a switching threshold event triggering mechanism is introduced into the inversion controller.

The invention discloses an incremental scaling analog-to-digital converter signal-to-noise ratio improving method based on a jitter technology, which comprises two parts of operations of jitter voltage injection and high-order decimation filtering. According to the jitter voltage injection, Gaussian distribution jitter voltage injection is carried out on coarse quantization SAR ADC input of the scaling type analog-to-digital converter through a capacitor array controlled by a random sequence, and the randomness of quantization errors is enhanced; the high-order decimation filtering performs summation and re-averaging on randomly distributed quantization noise, the obtained final quantization error is smaller than the quantization error of a traditional incremental scaling type analog-to-digital converter, and the signal-to-noise ratio of the incremental scaling type analog-to-digital converter is effectively improved. The overhead of an analog circuit part brought by the signal-to-noise ratio improving method is only used for a capacitor array for jitter voltage injection, and compared with other signal-to-noise ratio improving technologies, the signal-to-noise ratio improving method has higher area and energy efficiency.

This invention discloses a full-angle control system and method for a hemispherical gyroscope based on a dual-frequency carrier scheme, employing a dual-frequency carrier excitation / readout scheme. In this scheme, two high-frequency carriers of different frequencies are used to excite / read out the hemispherical gyroscope. x, y The electrostatic driving force signal in the directional direction is modulated and applied to the circumferential excitation electrodes of the gyroscope, causing the vibration signals in the two axes to propagate in mutually independent frequency bands. At this time, the resonator's spherical shell acts as a common capacitor plate; therefore, a front-end amplifier is used to read the modulation signals of the two axes from the resonator, which are then fed into subsequent circuits for filtering and demodulation to obtain the displacement information for each axis. Since the signal originates from... x, y The detection signals from both axes are read out through the same circuit, thereby suppressing the asymmetry of the anisotropic electrodes and x, y This system detects errors caused by asymmetry in analog circuit parameters. It achieves full-angle output functionality for a hemispherical resonant gyroscope and possesses high practical value.

The present invention discloses a cumulative probability density distribution statistical loop circuit, belonging to the field of wireless communications. The circuit extracts the envelope signal of a radio frequency signal through a peak detection module; compares the feedback output voltage and the envelope signal through a cumulative probability density comparison module to obtain a probability density signal; then, in a cumulative probability density quantization module, obtains a cumulative probability density quantized voltage signal; finally, in a cumulative probability density voltage generation module, the output voltage of the circuit is regulated based on the cumulative probability density quantized voltage signal; furthermore, a lock detection module outputs a lock signal to stabilize the output voltage; and a control signal generation module generates a control signal throughout the entire operation process. The present invention is implemented using an analog circuit and has the advantages of a simple structure, low power consumption, and a wide applicable frequency band, making it suitable for amplitude alignment of various signals.

This application provides a compensation circuit, an amplification circuit, and an analog circuit. The compensation circuit includes: a compensation capacitor, with its first terminal coupled to the node to be compensated in the feedback loop; a resistor generating circuit, coupled to the second terminal of the compensation capacitor, for providing a compensation resistor with a first resistance value; and a first current mirror, including a first transistor and a second transistor. The control electrode of the first transistor is coupled to the second terminal of the compensation capacitor, the first current electrode of the first transistor is coupled to the node to be compensated, the second current electrode of the first transistor is coupled to a reference voltage, and the control electrode of the second transistor is coupled to the control electrode of the first transistor via the resistor generating circuit, for providing a first bias voltage to the control electrode of the first transistor according to a first bias current. This application can provide better compensation for the feedback loop with a smaller area, significantly reducing the chip area and cost, and has a wide range of applications.

An adaptable, multistage, multi-rate digital predistortion system that can increase the accuracy of the distortion applied to a power amplifier input signal is disclosed. Further, the digital predistortion system can be implemented using a reduced circuit area by reducing a number of coefficients used by the models applied to generate the distortion compensation signal. Further, the system can implement an improved digital predistortion adaptation engine that improves an adjacent channel leakage ratio of the digital predistortion system. Moreover, the system can compensate for non-linear impairments due to analog / RF circuits and systems and improve at least the following metrics: Error vector magnitude (EVM), adjacent channel leakage ratio (ACLR), spectrum emission mask (SEM), and power consumption of the circuits and systems. An example of circuits and systems is radio frequency power amplifier (RF PA).

The invention discloses an automobile electronic circuit board test fixture which comprises a support, a fluorescent lamp is installed on a sliding block, and the fluorescent lamp irradiates a circuit board at a variable angle to detect the processing capacity of the circuit board on data of an optical sensor. The spraying pipe is provided with spraying holes for spraying air with different temperatures to the circuit board, and the working states of the circuit board in different environments are simulated. According to the invention, multiple detection functions are integrated, and the appearance of the circuit board, the data processing capability of the optical sensor and the performance and stability in different temperature environments can be comprehensively detected at the same time; the automation and intelligence of the detection process are realized, the detection efficiency is greatly improved, and the interference of human factors is reduced; meanwhile, by simulating a real working environment, the performance of the circuit board in actual use can be evaluated more accurately, and powerful support is provided for quality assurance of the automobile electronic circuit board.

A control method and a control system of a lithium niobate based Mach-Zehnder interferometer modulator are disclosed. The system includes a laser, a Mach-Zehnder interferometer, a photoelectric detection module and an analog circuit bias control module. The method includes: converting, by the photoelectric detection module, two optical signals into two photocurrent signals after obtaining the two optical signals generated by the Mach-Zehnder interferometer; comparing the two photocurrent signals by a judgement unit to obtain a comparison voltage; in response to the comparison voltage being zero, keeping a bias voltage constant by a bias control unit; and in response to the comparison voltage not being zero, adjusting the bias voltage by a bias control unit according to the comparison voltage until the comparison voltage is zero.

A non-contact voltage sensor device is provided with: a probe electrode (10) for observing an AC voltage generated in a cable having a cable conductor and a coating material for coating the cable conductor, without performing electrode connection; an impedance circuit (14) that is connected to the probe electrode and has a first resistance element (142) that simulates the insulation resistance of the coating material, a first capacitor element (141) that simulates the coupling capacitance generated between the cable conductor and the probe electrode, and a dielectric relaxation simulation circuit (143) that simulates the dielectric relaxation generated in the coating material, the first resistance element, the first capacitor element, and the dielectric relaxation simulation circuit being connected in parallel to each other; and an operational amplifier (15), the positive electrode input terminal of which is connected to the reference potential point, the negative electrode input terminal of which is connected to the input point of the impedance circuit, and the output terminal of which is connected to the output point of the impedance circuit, the dielectric relaxation analog circuit having at least one snubber circuit (SC, SC1-SC3) having a series connection of second resistive elements (1431, 51-53) and second capacitor elements (1432, 61-63).

The utility model provides an analog signal acquisition device based on three-dimensional packaging. The device comprises a shell, a three-dimensional packaging structure is arranged in the shell, a signal circuit board, a power supply circuit board and an analog circuit board are sequentially stacked on the three-dimensional packaging structure from bottom to top, and resin is filled among the signal circuit board, the power supply circuit board and the analog circuit board. The side end face of the three-dimensional packaging structure is provided with laser etching lines, the signal circuit board, the power supply circuit board and the analog circuit board are electrically connected through the laser etching lines, and one end of the three-dimensional packaging structure is further provided with a connecting port. The utility model relates to the field of analog signal acquisition devices.

Provided herein are various enhancements for skew balancing in semiconductor circuits, such as during the synthesis, timing, routing, and phases of circuit design. In one example implementation, a method includes simulating a circuit to determine initial path delay values for a set of paths in the circuit, and determining a reference value for the set of paths based on the initial path delay values. The method also includes generating constraints using the reference value and a skew target for the set of paths, and performing a timing analysis to redesign the circuit using the constraints.

The present invention discloses a multi-channel device for measuring the magnetic field of a ship, which includes a magnetic field measurement probe unit and a magnetic field measurement host unit; a magnetic field measurement sensor device is arranged in the magnetic field measurement probe unit, and the magnetic field measurement sensor device includes an exciting coil, a measuring coil and an iron core; the exciting coil and the measuring coil are wound around the iron core at the same time; the magnetic field measurement host unit includes an analog circuit part, a band-pass filter circuit, an AC amplification circuit, a phase-sensitive detection circuit, a low-pass filter circuit, an integration amplification circuit, a limiting device, a phase shifter and a phase-locked loop; the present invention can measure the magnetic fields at different positions at different depths of the ship (including the starboard, port and keel) at one time, can display the magnetic field at a certain depth point, and the depth can be displayed through a depth sensor.

The application discloses a low-power digital LDO circuit applied to a radio frequency identification label chip, comprising a bias circuit, a voltage comparator, a ring oscillator, a charge pump circuit, a clamping circuit composed of diode strings D1-DN, a voltage stabilizing capacitor C1, an NMOS transistor N1, voltage dividing resistors R1 and R2; wherein the transistor N1 is a power transistor; the digital LDO load current is set to be the total opening voltage of the diode strings D1-DN when the power transistor gate voltage VG is light load. The application controls the gate of the power transistor through the charge pump circuit, the voltage comparator compares the resistance voltage division VFB of the reference voltage and the output voltage of the digital LDO circuit in real time, when the comparison result is low, the ring oscillator and the charge pump circuit are started to boost the voltage of the power transistor gate, which greatly reduces the overall power consumption of the system compared with the traditional analog LDO circuit; the voltage stabilizing capacitor and the clamping diode discharge path are added to the power transistor gate, thereby reducing the overshoot output voltage ripple of the digital LDO.

The invention discloses a method and system for displaying circuit logic through a self-simulation function and a medium, and belongs to the technical field of circuit principle teaching. The method comprises the following steps: a special electrical primitive library construction stage: editing characteristic logic for each electrical primitive; in the dynamic simulation circuit drawing stage, the electrical primitives are spatially arranged according to a standard circuit diagram layout to form a complete circuit topology; in the circuit simulation stage, a self-simulation engine is started for visual operation; in the real-time rendering stage, circuit logic is rendered in real time, different colors are used for displaying the cable with electricity or without electricity, a current flowing animation is added to the cable with electricity, and an electrical primitive switches a visual state according to an electricity-obtaining / electricity-losing state; in the fault injection stage, a fault injection instruction which is manually or randomly input is responded, a circuit fault event is simulated in the circuit, and a corresponding fault phenomenon, an influence range and a visual prompt are generated. The teaching efficiency can be improved, the training cost is reduced, potential safety hazards are eliminated, and the talent training period is shortened.

The application provides a kind of intelligent arc fault diagnosis method and system based on the cooperation of electric energy meter and circuit breaker, it is related to electrical safety technical field. Including: intelligent circuit breaker real-time monitoring obtains the loop current of the distribution loop;If intelligent circuit breaker determines that current anomaly event is detected according to loop current, then send abnormal early warning information to intelligent electric meter through local communication link;Intelligent electric meter according to the time information corresponding to current anomaly event, call the current characteristic information in the preset time range;Intelligent electric meter determines whether there is arc fault according to the current characteristic information in the preset time range. This method realizes the double determination of arc fault diagnosis through the cooperative processing of intelligent electric meter and intelligent circuit breaker, improves the accuracy of fault diagnosis result. And through the digital twin model built, the running state of the circuit can be simulated, the potential abnormal trend can be predicted, and predictive judgment of arc fault is realized.