414results about "Analog circuit testing" patented technology

Disclosed are techniques for efficiently inspecting defects on voltage contrast test. In one embodiment, methodologies and test structures allow inspection to occur entirely within a charged particle system. In a specific embodiment, a method of localizing and imaging defects in a semiconductor test structure suitable for voltage contrast inspection is disclosed. A charged particle beam based tool is used to determine whether there are any defects present within a voltage contrast test structure. The same charged particle beam based tool is then used to locate defects determined to be present within the voltage contrast test structure. Far each localized defect, the same charged particle beam based tool may then be used to generate a high resolution image of the localized defect whereby the high resolution image can later be used to classify the each defect. In one embodiment, the defect's presence and location are determined without rotating the test structure relative to the charged particle beam.

A cleaner of this invention is a cleaner for inspecting projections and removes any substance, e.g., aluminum oxide, which attaches to needle points of probe needles, when the probe needles pierce into the cleaner. The cleaner has a cleaner layer and a substrate. The cleaner layer is constituted by an elastic material layer, and a filler having a surface state improving function of the inspecting projections and dispersed in the elastic material layer. As the filler having a surface state improving function, a powder including at least one of ceramic materials, e.g., sand, glass, alumina, Carborundum (trade name), and the like, or a fiber layer made of an inorganic fiber or organic fiber can be employed.

The invention discloses an analog circuit dynamic online failure diagnosing method based on GSD-SVDD, belonging to the technical field of analog circuit failure diagnosis. In an offline test process, a KFCM algorithm is adopted to calculate a failure resolution value of each testable node and an optimal test node set is selected according to the failure resolution value. In an online diagnosis process, a failure diagnosis model is established by adopting an SVDD single classification approach based on a map spatial distance positive and negative sample weighting, test samples are diagnosed by a layered diagnosis method, and a failure class library and the diagnosis model are renewed dynamically. The method effectively reduces the drill and online diagnosis time of the diagnosis model, guarantees the real-time property of the online diagnosis and improves the precision of the failure diagnosis and can dynamically renew parameters of the diagnosis model so as to enable the a diagnosis system to have the self-adaption capability.

A Deep Belief Network (DBN) feature extraction-based analogue circuit fault diagnosis method comprises the following steps: a time-domain response signal of a tested analogue circuit is acquired, where the acquired time-domain response signal is an output voltage signal of the tested analogue circuit; DBN-based feature extraction is performed on the acquired voltage signal, wherein learning rates of restricted Boltzmann machines in a DBN are optimized and acquired by virtue of a quantum-behaved particle swarm optimization (QPSO); a support vector machine (SVM)-based fault diagnosis model is constructed, wherein a penalty factor and a width factor of an SVM are optimized and acquired by virtue of the QPSO; and feature data of test data are input into the SVM-based fault diagnosis model, and a fault diagnosis result is output, where the feature data of the test data is generated by performing the DBN-based feature extraction on the test data.

Final testing of an LCD panel or the like is performed after preliminary testing for short circuit defects. During final testing, the panel is exposed to signals at the shorting bars and the resulting display pattern is imaged. The resulting image data then is processed at a computer system to determine whether the resulting display pattern differs from an expected display pattern. If differences are present then an open circuit or pixel defect is present. The applied test signals and the pattern or differences determine the type of defect present. For an open circuit defect along a gate line, a partial row (column) of the resulting display pattern does not activate. For an open circuit along a drive line, a partial column (row) of the resulting display does not activate. Pixel shorts are identified by applying test signals to the shorting bars during a first test cycle, then imaging the display during a second test cycle after at least one of the test signals is removed. Pixels which remain active that should be inactive have short circuit defects.

A general purpose integrated circuit (IC) tester includes a set of channels, one for each input or output pin of an IC device under test (DUT). Each channel is programmed by a host computer to either supply a test signal to a DUT I/O pin or sample a DUT output signal appearing at the I/O pin and produce sample data representing its magnitude or logic state. The tester also includes an amorphous logic circuit (ALC) having a set of input and output terminals and a programmable logic circuit interconnecting the input and output terminals. Some of the ALC input and output terminals receive the sample data produced by each channel and other ALC terminals send control signals directly to each channel. Other ALC terminals transmit data to the host computer. When it programs the channels to perform a test, the host computer also programs the ALC to control various operations of the channels during the test, to perform a real-time analysis of the test data produced by the channels, and to communicate results of the analysis to the host.

A semiconductor device analyzer has a substrate model reading module, a Y-matrix entry module, a discriminating module, a matrix reduction module, and an output format discriminating module. The substrate model reading module reads a substrate network model of three-dimensional meshes representing the substrate of a semiconductor device. The substrate network model is a network of resistive and capacitive elements and is used for the simulation and analysis of the semiconductor substrate. The Y-matrix entry module prepares a Y-matrix from the substrate network model, each element of the Y-matrix being expressed with a polynomial of differential operator "s". The discriminating module discriminates internal nodes to be eliminated from external nodes to be left among the nodes of the substrate network model. The matrix reduction module eliminates the internal nodes, thereby reducing the Y-matrix. The output format determining module determines an output format for an operation result.

An integrated circuit (IC) tester includes a set of dual-purpose digital/analog channels. Each tester channel includes a driver capable of supplying either a digital or analog test signal input to an IC terminal and a receiver for digitizing and processing either an analog or digital IC output signal appearing at the DUT terminal to produce results data representing the behavior of that IC output signal during a test. A test is organized into a succession of test cycles, and before each test cycle a pattern generator within each channel produces data for controlling the behavior of the driver and receiver during the test cycle. The control data controls whether the driver is to produce an analog or a digital test signal, controls a magnitude or logic level to which the test signal is to be driven during the test cycle, and controls a time during the test cycle of any test signal state or magnitude changes. The control data also indicates how and when the receiver digitizes and processes an IC output signal during the test cycle.

A technique for characterizing a communications interface includes determining a voltage margin and a timing margin of the interface based on data sampled by a sampling device of a receiver of the interface. In at least one embodiment of the invention, a method for determining margin associated with a receiver circuit of an integrated circuit includes periodically sampling a signal over a time period by a receiver sampling circuit of the receiver circuit to generate a sampled version of the signal. The method includes incrementally varying a value of the parameter associated with the signal. The varying of the parameter is through a range of values of the parameter over the time period. The method includes determining a margin value of the receiver circuit associated with the parameter based, at least in part, on the sampled version of the signal.

The invention discloses a simulating PCB intelligent test system which is based on nerve network, which includes main control PC machine, processor, storage, communication circuit, function signal generator, multi-channel sampling switch matrix, sequential circuit, decoding circuit, A/D converter, sampling retainer, differential amplifier, function signal generator under the control of processor outputs stimulating signal to the stimulating node of the tested circuit, the responding signal of the tested circuit is transmited to the processor by multi-channel sampling circuit, then is transmitted to the main control PC machine by communication circuit, the main control PC machine treats the sampling signal with wavelet packet transform de-noising treatment, and with principal component analysis and normalization processing for obtaining fault feature vector; the fault feature vector is inputted into the trained BP nerve network, the output of the BP nerve network is fault type. The invention can position the PCB test fault to the component level effectively, and improve the scalability of system greatly with the simple and effective test method of CMOS switch array.

The invention discloses an analog-circuit fault diagnosis method based on DAGSVC. The method comprises the following steps: applying certain test excitation to a analog circuit to be tested; acquiring circuit output response signals to be tested in a testable node of the circuit; performing multi-order fractional order wavelet packet (FRWPT) transformation on the acquired circuit output response signals and extracting fault characteristics so as to form a test sample; and performing calculation by utilizing fault-dictionary prestored information together with the DAGSVC to classify and position faults. The method has the advantages of global training optimality, fewer needed training samples, high fault-information resolution and the like, and can improve the precision and efficiency of diagnosing the faults of analog circuits.

The invention discloses an analog circuit fault diagnosis method based on an improved RBF neural network. The analog circuit fault diagnosis method includes the following steps that excitation is exerted on a circuit to be detected, and response signals are processed through improved wavelet packet transformation to extract fault characteristic signals; the extracted candidate characteristic signals are normalized to obtain fault characteristic vectors; the fault characteristic vectors serving as samples are input into the neural network and classified to obtain a result of fault diagnosis. Extraction of the fault characteristic vectors based on wavelet packet transformation is adopted, so that the distinguishability is improved; through normalization and other preprocessing, influences caused by different dimensions and too large numerical value difference on original variables are effectively eliminated; an LMS method in an RBF algorithm is replaced by a genetic optimization algorithm to train parameters of the neural network, so that the performance of the RBF algorithm is improved, an optimizing starting point of a genetic algorithm is set through a K average clustering learning algorithm, the iterations of the algorithm is effectively reduced, errors are reduced, diagnosis speed is increased, and the fault recognition rate is improved.

The invention discloses a method for diagnosing fault of an analog circuit based on a nerve network. The method is characterized in that the method comprises the following steps: (1) an electrical signal of the analog circuit is acquired; the electrical signal is testable node voltage of the analog circuit or a current signal of a branch circuit; (2) the acquired electrical signal is subjected to centralized processing; (3) signal entropy value and signal kurtosis of the electrical signal are calculated; and (4) the signal entropy value and the signal kurtosis are sent to a BP nerve network separator, and a fault diagnosis result is output by the BP nerve network separator. The method can be used for a real-time system and a nonreal-time system and can be also used for diagnosing hard fault and soft fault.

The invention discloses an analogue circuit failure prediction method which comprises the following steps: performing Monte Carlo analysis on various elements of an analogue circuit in a failure-free section and extracting various frequency band signal energy, normalizing the extracted frequency band signal energy to obtain a feature vector; training a BP neural network; judging failure modes with occurrence trends, extracting a failure prediction feature vector when the element is at the initial value, extracting the failure prediction feature vector when a detected circuit is in work, computing the cosine angle distance to represent the health degree of the element, computing the health degree threshold value when the element is in failure, and optimally selecting a kernel function width factor of a relevance vector machine algorithm, and performing the failure prediction on the analogue circuit. The method can be used for a real-time system, and can be further used for a non-real-time system, a failure of the linear analogue circuit can be predicted, and a failure of the non-linear analogue circuit can be predicted, and failures of main elements such as resistor, inductor and the capacitor in the analogue circuit can be predicted.

The invention discloses a probabilistic neural network-based tolerance-circuit fault diagnosis method, which comprises the following steps of: selecting a pulse signal source as the energization of a fault circuit to be detected; carrying out Monte Carlo analysis on the fault circuit so as to obtain an amplitude-frequency response signal of the fault circuit to be detected; carrying out three-layer wavelet packet decomposition on the amplitude-frequency response signal of the fault circuit so as to obtain low and high frequency coefficients of the amplitude-frequency response signal, carryingout threshold quantification on the wavelet packet decomposition coefficients, then carrying out wavelet packet reconstruction according to the lowest-layer low frequency wavelet packet decompositioncoefficients and the high frequency wavelet packet decomposition coefficients subjected to threshold quantification so as to complete the de-noising processing of the wavelet packet; calculating the band-gap energy of the response signal according to the low and high coefficients obtained after wavelet packet reconstruction, and constituting a fault characteristic vector by using the band-gap energy; and inputting the fault characteristic vector in a fault grader of the probabilistic neural network to realize circuit fault diagnosis. The method has the advantages of high right fault diagnosisrate, simple structure, short training time, high fault tolerance and strong extrapolation ability.

The invention provides an analog circuit fault diagnosis method based on wavelet packet analysis and the Hopfield network. The method includes data obtaining, feature extraction and fault classification, wherein data obtaining includes performing data sampling for output response of an analog circuit respectively through simulation program with integrated circuit emphasis (SPICE) simulation and a data collection plate connected at a practical circuit terminal so as to obtain an ideal output response data set and an actually-measured output response data set; feature extraction includes performing wavelet packet decomposition with ideal circuit output response and actually-measured output response respectively serving as a training data set and a test data set, and leading energy values obtained by decomposed wavelet coefficient through energy calculating to form feature vectors of corresponding faults; and fault classification includes leading the feature vectors of all samples to be subjected to Hopfield coding and then submitting the coded feature vectors to the Hopfield network to achieve accurate and fast fault classification. The analog circuit fault diagnosis method is good in fault feature pretreatment effect aiming at hard faults with weak amplitude response and soft faults with large amplitude response, and the newly defined energy function and the newly defined coding rule are remarkable in influence on fault diagnosis accuracy of the analog circuit.

The invention discloses an artificial circuit fault diagnosis pattern sorting algorithm based on signal characteristic space modeling. According to the method, signals collected by test nodes are utilized, optimal fractional Fourier transform (FrFT) and R type cluster analysis are performed on the signals on the basis of the maximum entropy principle (MEP) to describe the characteristics of fault samples, and different spatial distribution modeling of faults are conducted; according to the sort separability criterion of the characteristic evaluation of minimum-in-cluster-distance and maximum-between-cluster-distance, objective optimization functions of nuclear parameters are constructed, and on the basis of a self-adaption genetic algorithm, the objective functions are optimally solved, and the nuclear parameters are adjusted; in combination with Q type cluster analysis, a hierarchical support vector machine classifier (SVC) is constructed to find and separate the faults; and through the algorithm, sensitivity reflecting fault characteristics can be extracted from measurement signals, and higher fault diagnosis speed and higher fault diagnosis accuracy are achieved. The fault diagnosis examples of a Continuous-Time State-Variable Filter circuit and an ML-8 radar prove the speediness and effectiveness of the algorithm.

An artificial circuit fault diagnosis system based on a random forest of the present invention belongs to the fault diagnosis field, and comprises a fault simulation subsystem, a fault diagnosis subsystem and a man-machine interaction interface. The fault simulation subsystem is used to realize a simulation fault simulation circuit and a semi-physical fault simulation circuit, and output circuit data to the fault diagnosis subsystem. The fault diagnosis subsystem removes redundancy on the circuit data and then constructs an RF classifier and an RF rule base to diagnose faults. The semi-physical fault simulation circuit is characterized in that a programmable resistor card is added in a real circuit by a fault injection module to realize a resistor fault. When the RF classifier is used to diagnose faults, the reconstruction is carried out by the stored RF node data information, and the time of retraining the RF classifier is saved. According to the present invention, a plurality of fault mode simulation and fault diagnosis can be carried out on any resistor in any real circuit, the faults are diagnosed by completely using the circuit data, and the simulation circuit fault information is transparent.

The invention relates to a random sampling analog circuit compressed sensing measurement and signal reconstruction method, which belongs to the field of electronic system test and fault diagnosis. Aiming at a fault signal having a sparsity distribution characteristic per se or in an orthogonal space in an output response of an analog circuit, a test node is selected according to a circuit topology structure, circuit output responses are randomly sampled under a distributed sensor test network, response signals are expressed in a sparse way on a transform domain by utilizing discrete orthonormal basis, compressed sensing measurement of the sparse signals is completed under observability matrix projection, and when the recovery rate of signal reconstruction by randomly compressed sampling points reaches more than 80 percent, the compressed measurement values of the circuit output responses are effective, can form a characteristic set and can be used for analog circuit fault diagnosis. The method solves the problems that the traditional analog signal sampling occupies a large number of hardware resources, large signal reconstruction calculated amount and the like; and the random sampling compressed sensing measurement method is utilized to improve the efficiency of electronic system testing.

The present disclosure relates to a method for testing a circuit having analog components. The method comprises performing a low-cost optimized test on the circuit by applying an optimized input stimulus to the circuit, capturing the circuit response to the input stimulus applied to the circuit, evaluating the circuit response to predict whether the performance parameters of the circuit satisfies predetermined specifications for the circuit, and making a pass/fail determination for the circuit based upon the evaluation of the circuit response.