134results about "Analog circuit testing" patented technology

A chip tester, comprising: a support frame movable in the vertical direction and a movable plate movable in the horizontal direction. An upper test base is mounted on the support frame; a lower test base capable of moving to a position directly below the upper test base along with the movable plate is mounted on the movable plate; a recess is formed in a lower surface of the upper test base and / or an upper surface of the lower test base; when the chip tester is in a test state, the lower surface of the upper test base is tightly attached to the upper surface of the lower test base to form at the recess region a sealing cavity used for accommodating a chip to be tested; and a PCB and a partition plate are sequentially stacked above the upper test base. Flat attachment is ensured while realizing standard conversion after the upper test base and the lower test seat are subjected to mold closing, thereby improving the consistency of test data, and improving the safety of the chip in a high-current and high-voltage test state.

The invention discloses an analog IC synchronization test optimization method and system based on crosstalk simulation. The method comprises the following steps: firstly, acquiring position layout data and test signal data of each analog IC in a synchronous test process of the analog ICs, determining electromagnetic crosstalk information by combining test signals, and constructing a crosstalk schematic diagram according to the electromagnetic crosstalk information and the position layout data; clustering the schematic diagrams by using a spectral clustering algorithm, and identifying a crosstalk path in the synchronization test; designing an electromagnetic crosstalk signal isolation barrier based on the schematic diagram and the crosstalk path, deploying the electromagnetic crosstalk signal isolation barrier in a test environment, performing simulation evaluation on an independently tested analog IC by constructing and injecting a crosstalk simulation signal, and judging an isolation effect; and optimizing the isolation barrier according to an evaluation result to obtain an optimization scheme. According to the method, the electromagnetic crosstalk path in the synchronous test process can be effectively identified and isolated, and the accuracy and reliability of the simulation IC test are improved.

The invention relates to a programmable delay test circuit. An integrated circuit includes a test circuit, an analog delay circuit, and a sampler register, each configured to receive a signal. The delay circuit includes a configuration input and a phase having a final phase. The sampler register includes a result output and delayed inputs, each coupled to a respective delayed output of the phase. The sampler register is configured to output a sampled signal indicative of a relationship between the signal and at least a final one of the phases. The integrated circuit also includes a test circuit including a configuration output coupled to the configuration input of the delay circuit and including a result input coupled to the result output of the sampler register. The test circuit is configured to iterate the selected values to test the delay circuit and determine that the delay circuit passes the test when the relationship matches a predetermined criterion.

The invention discloses an analog integrated circuit test method based on edge calculation, the method is executed by an edge node, and the method comprises the following steps: obtaining a step response waveform of an analog integrated circuit; extracting screening features from the step response waveform; determining an abnormal level and a test type of the screening feature; determining the demand level of the server for the original waveform data based on the abnormal level of the screening feature and the test type; and determining a sending strategy for sending the screening feature and the original waveform data to the server based on the demand level. According to the invention, waiting and repeated interaction of the server can be reduced, and test judgment efficiency and test throughput are improved.

The invention discloses an analog circuit fault diagnosis method and system for optimizing an SVM (Support Vector Machine) and a storage medium. An SVM algorithm is optimized by adopting a fused particle swarm algorithm and an improved grey wolf algorithm. Comprising the following steps: extracting time domain features and wavelet packet features of various fault sample signals of an analog circuit, and fusing the two features as a final fault feature sample set; dividing the fault feature sample set into a training set and a test set according to a certain proportion; optimizing a kernel function and a penalty factor of the SVM by using a fusion particle swarm algorithm and an improved grey wolf algorithm, and constructing a PSO-IGWO-SVM model; and training and testing the PSO-IGWO-SVM model by using the test set, and outputting a fault diagnosis result of the analog circuit. By combining the advantages of the two algorithms, the classification effect and diagnosis precision of the SVM are improved. Meanwhile, by introducing a nonlinear convergence factor and a proportional weight dynamic adjustment strategy, the search efficiency and convergence speed of the algorithm are further improved.

The density and power consumption of modern integrated circuits, such as Graphic Processing Units (GPUs), Central Processing Units (CPUs), and Network Processing Units (NPUs) is growing rapidly, which necessitates designing advanced cooling systems. Existing solutions for characterizing and validating these cooling system are inadequate. A flexible, scalable Thermal Test Vehicle (TTV) is disclosed which is based on an array of power transistors, measurement / control circuitry, and onboard computer. The TTV is configured for characterizing the performance of electronic cooling solutions under a variety of operating conditions.

The invention discloses an analog circuit fault detection method and device based on CNN-LSTM, readable storage equipment and a program product, and relates to the technical field of deep learning for circuit fault diagnosis. The problems that an existing fault diagnosis method based on deep learning is difficult to effectively deal with complex characteristics of high-dimensional data and cannot fully capture key characteristic information related to faults, so that the diagnosis effect is poor, and the comprehensiveness and reliability of diagnosis results are poor are solved. By constructing the CNN-LSTM fault detection model, spatial features and time sequence features in circuit fault signals can be processed at the same time, and accurate detection and classification of faults can be realized without depending on an accurate mathematical model. The method is mainly used for fault diagnosis of the analog circuit.

The invention belongs to the technical field of circuit fault prediction, and discloses a PCB analog circuit component fault prediction method based on an improved large language model. Excitation is applied to the PCB analog circuit, and output voltages of a to-be-predicted component in the PCB analog circuit under different frequencies are extracted; performing data preprocessing according to a Pearson's correlation coefficient method; the improved large language model takes a general large language model as a base model, a linear layer, a cross attention layer and a full connection layer are added, and feature vectors after cross-modal alignment are obtained; and improving cue words of the general large language model, and adding and connecting the cue word vectorization of the general large language model and the feature vector after cross-modal alignment to serve as an input feature vector of the large model. According to the method provided by the invention, the loss of the features is reduced during feature extraction, so that the prediction result has generalization and reliability.

Apparatuses, systems, and methods for, and more particularly to apparatuses, systems, and methods for a high-speed composite amplifier driving circuit to generate and output analog signals. The high-speed composite amplifier driving circuit can combine a voltage-controlled pulser and waveform generator with high-accuracy current-voltage (I-V) measurement functions. The voltage-controlled pulser and waveform generator, for example, can provide a ±5 volt, 10 milliamp waveform at up to 50 megahertz with 5 nanosecond rise / fall timing and 8 ns minimum pulse widths. In addition, the high-accuracy I-V measurements can measure a ±10 volts, 10 milliamp waveform at up to 30 MHz with 7-10 nanosecond rise / fall timing and 8 to 12 nanosecond minimum pulse widths.

The application discloses a kind of analog circuit fault diagnosis method based on wavelet scattering and ensemble learning, to solve the problem that analog circuit fault response aliasing leads to difficult fault diagnosis.First, the circuit response is divided into multiple frequency band subsets by wavelet scattering transform, and the fault features of the subsets are enhanced using Fisher discriminant analysis.Second, each frequency band subset is sent to different extreme learning machines under Bagging integration, and the classification accuracy of each fault mode in the frequency band subset is used as the class weight of the extreme learning machine.Then, the output values of each extreme learning machine are weighted to obtain the fused output result, and the fault class is determined accordingly.Finally, two example circuits are simulated, and the simulation results show that the diagnostic accuracy is 100%, indicating that the method is feasible and effective, and can realize fault classification and positioning.

The invention discloses a chip testing machine which comprises a supporting frame capable of moving in the vertical direction and a movable plate capable of moving in the horizontal direction, an upper testing seat is installed on the supporting frame, and a lower testing seat capable of moving to the position under the upper testing seat along with the movable plate is installed on the movable plate. A groove is formed in the lower surface of the upper testing seat and / or the upper surface of the lower testing seat, and when the chip testing machine is in a testing state, the lower surface of the upper testing seat is tightly attached to the upper surface of the lower testing seat, and a sealing cavity used for placing a chip to be tested is formed in the groove area; and a PCB and a partition plate are sequentially stacked above the upper test seat. According to the invention, while reference conversion after die assembly of the upper and lower test bases is realized, smooth lamination is ensured, the consistency of test data is improved, and the safety of a chip in a high-current and high-voltage test state is also improved.

The present invention discloses a long-distance circuit parameter monitoring system based on RS485 communication, the system includes a temperature monitoring module, a humidity monitoring module, a current and voltage monitoring module, a main control module and a communication module, wherein the temperature monitoring module and the humidity monitoring module are respectively used to detect the temperature data and humidity data of the environment in which the analog front-end circuit is located; the current and voltage monitoring module is used to detect the current and voltage data of the analog front-end circuit; the main control module is used to receive the temperature data, the humidity data and the current and voltage data, and process the received data, and transmit the processed data to the upper level processing unit through the communication module, so as to realize long-distance circuit parameter monitoring. The present invention can be applied to low temperature and harsh environment, and by monitoring the temperature and humidity data of the analog front-end cavity, and the current and voltage data of the analog front-end circuit, it can realize the abnormal judgment of the analog front-end circuit and the monitoring of the operating environment, thereby providing an important reference for the operation and maintenance of the equipment.

Provided is a test apparatus comprising an input unit that is connected to a device under test and receives a signal to be tested from the device under test, and a function test unit that tests a function of the device under test on the basis of the signal to be tested, the function test unit having a timing measurement unit that measures the timing of an edge of the input signal, the input unit having a current measurement unit that outputs a current measurement signal corresponding to the current value of the signal to be tested, and a first input switching unit that switches whether or not to input the current measurement signal to the function test unit, and the timing measurement unit measuring the pulse width of the current measurement signal on the basis of the timing of the edge of the current measurement signal that is input to the function test unit.

The invention discloses an analog circuit switch control method with a fault self-checking function, and relates to the technical field of electric switches, and the method comprises the steps: dynamically monitoring and obtaining circuit state information through a built-in circuit monitor in an analog circuit. And calling a circuit feature extraction strategy, performing feature extraction analysis on the circuit state information, and generating a circuit feature vector. And reading a predetermined feature vector, comparing the circuit feature vector with the predetermined feature vector, and calculating a triangular distance value. And performing normalization processing on the triangular distance value to obtain a degradation state index, and sending a first fault early warning signal when the degradation state index does not meet a predetermined index threshold. And executing action control on a circuit switch of the analog circuit based on the first fault early warning signal so as to realize early warning and response of the circuit fault. Therefore, the technical effects of reducing the calculation amount, reducing the data dependence and providing a clear and explainable diagnosis result are achieved.

A temperature measurement circuit includes a band-gap reference circuit configured to generate a band-gap reference voltage that is fixed regardless of an operation temperature, a reference voltage generator circuit configured to generate a measurement reference voltage by adjusting the band-gap reference voltage, a sensing circuit configured to generate a temperature-variant voltage based on a bias current, where the temperature-variant voltage is varied depending on the operation temperature, an analog-digital converter circuit configured to generate a first digital code indicating the operation temperature based on the measurement reference voltage and the temperature-variant voltage, and an analog built-in self-test (BIST) circuit configured to generate a plurality of flag signals indicating whether each of the band-gap reference voltage, the measurement reference voltage, and a bias voltage corresponding to the bias current is included in a predetermined range.

The application provides a chip analog quantity gear value determination method and device and a controller. In the application, an initial gear value is first obtained, then a gear value of a measured chip is set to the initial gear value, an analog quantity output value of the measured chip is obtained, in a case where the analog quantity output value is not located in a preset analog quantity interval, an output difference value between a center value of the preset analog quantity interval and the analog quantity output value is determined, in a case where a difference value between adjacent gear values is a fixed difference value, a gear difference value corresponding to the output difference value is determined, and an actual gear value of the measured chip is determined according to the initial gear value and the gear difference value. That is, in the application, the final actual gear value can be directly determined according to the initial gear value, the output difference value between the center value of the preset analog quantity interval and the analog quantity output value corresponding to the initial gear value, compared with a traversal mode, the number of adjustment times can be reduced, and the adjustment efficiency is improved.

To provide a semiconductor device capable of performing a highly accurate test about a D / A converter.SOLUTION: A semiconductor device comprises a digital-to-analog converter provided with a plurality of current cells, and a test circuit electrically connected to the digital-to-analog converter and testing the digital-to-analog converter. The test circuit includes an electric charge information holding circuit which holds a difference value between a first electric charge conforming to a first current by at least one or more current cells among the plurality of current cells and a second electric charge conforming to a second current as differential electric charge information, and a comparison circuit which compares a determination voltage conforming to the differential electric charge information with a reference voltage, and outputs the comparison results.SELECTED DRAWING: Figure 6

The application discloses a kind of analog signal calibration method, controller and system suitable for semiconductor equipment, method includes: control analog signal output module exports first preset electric signal;Through analog signal input module, first preset electric signal is collected, and first electric parameter acquisition value is obtained;First preset electric signal is measured by analog electric parameter measuring device, and first electric parameter measurement value is obtained;According to first electric parameter acquisition value and first electric parameter measurement value, analog signal input module is calibrated;Control analog signal output module exports second preset electric signal corresponding to first preset electric parameter value;Second preset electric signal is collected by calibrated analog signal input module, and second electric parameter acquisition value is obtained;According to first preset electric parameter value and second electric parameter acquisition value, the signal output by analog signal output module is calibrated.By the above-mentioned mode, analog input signal and analog output signal can be calibrated to improve precision.

The analog circuit fault diagnosis method, electronic device and storage medium based on BV-CNN belong to the technical field of analog circuit fault diagnosis. In order to efficiently perform analog circuit fault diagnosis of BV-CNN, the present invention defines an optimization objective function, sets the modal number K and the penalty parameter α as the Bayesian optimization parameter search space, and uses the Bayesian optimization method to search for the optimal combination of the modal number K and the penalty parameter α of the VMD algorithm to obtain the parameters of the optimized VMD algorithm. The Bayesian optimization automatically selects the VMD parameters, avoiding the problem of modal aliasing or excessive signal decomposition when the parameters are not properly selected, improving the signal decomposition effect, and combining the CNN automatic feature extraction and classification capabilities, greatly improving the accuracy and robustness of fault diagnosis, and can also achieve better processing of nonlinear and non-stationary signals, adapting to complex signals and multiple working conditions, and realizing efficient parameter optimization and model training.

Embodiments described herein provide for high frequency transmission spectroscopy (HFTS) system and methods. The HFTS system and methods provided herein allow for identification or classification of materials of interest in a wide range of industries. The HFTS system and methods are capable of identifying unknown particles, characterizing particle size / charge, or monitoring solutions for specific materials in semiconductor, biomedical, and environmental applications. The HFTS system includes an ENA operable to generate an AC as an excitation signal and sweep a frequency of the AC from an initial frequency to a final frequency. A test cell operable to retain a MOI is positioned between an input antenna and an output antenna. The ENA is configured to calculate parameters at each frequency step to plot magnitude response and / or phase response for identification or classification.

A device may perform impedance spectroscopy on a component under test. The frequency response analyzer circuity may be coupled to the component under test outside of a current loop supplying an operational current to the component under test. The frequency response analyzer circuity may drive a variable impedance circuit to generate an oscillating current component within the current loop. The frequency response analyzer circuity may monitor a frequency response of the component under test to the oscillating current component.

Provided is a test apparatus comprising an input unit that is connected to a device under test and receives a signal to be tested from the device under test, and a function test unit that tests a function of the device under test on the basis of the signal to be tested, the function test unit having a timing measurement unit that measures the timing of an edge of the input signal, the input unit having a current measurement unit that outputs a current measurement signal corresponding to the current value of the signal to be tested, and a first input switching unit that switches whether or not to input the current measurement signal to the function test unit, and the timing measurement unit measuring the pulse width of the current measurement signal on the basis of the timing of the edge of the current measurement signal that is input to the function test unit.

An integrated circuit includes a test circuit, and an analog delay circuit and a sampler register, each configured to receive a signal. The delay circuit includes a configuration input and phases with a final phase. The sampler register includes result outputs and delay inputs that are each coupled to a respective delay output of the phases. The sampler register is configured to output a sample signal indicating a relationship between the signal and at least the final phase of the phases. The integrated circuit further includes a test circuit that includes a configuration output coupled to the configuration input of the delay circuit, and result inputs coupled to the result outputs of the sampler register. The test circuit is configured to iterate through selected values to test the delay circuit and determine that the delay circuit passes the test when the relationship matches a predetermined criterion.

The invention discloses an airborne radio frequency system filter circuit fault diagnosis method based on confidence fusion, and belongs to the technical field of analog circuit fault diagnosis. The method comprises the following steps: firstly, acquiring an output end voltage data set in a circuit health state and each fault state, converting time domain data into frequency domain data by using FFT (Fast Fourier Transform), then carrying out logarithmic compression, and normalizing the time domain data; constructing a 1D-CNN model, and performing fault diagnosis by using the time domain data to obtain a time domain probability vector; constructing a Transform model, and performing fault diagnosis by using the frequency domain data to obtain a frequency domain probability vector; a fusion probability vector is obtained through weighted fusion, and a fault category corresponding to the maximum probability in the fusion probability vector is selected as a diagnosis result; training by using the training set, and verifying validity by using the test set. According to the method, time-frequency double-domain feature extraction is adopted to capture multi-dimensional representation of a circuit state; in combination with 1D-CNN local feature extraction and Transform global association, computing resource consumption is reduced, and the accuracy and robustness of a diagnosis result are greatly improved.

The invention provides a full-channel measurement system based on analog chip test equipment, and relates to the technical field of chip test equipment. The full-channel measurement system based on the analog chip test equipment comprises a full-channel measurement device, a nitrogen purging device, a heat supply device, a cold supply device, an air draft device, an analyzer, the chip test equipment and a resistance load board. Through a multi-chamber independent temperature control structure of the variable temperature box, stable testing of the resistive load board in an extreme temperature environment in a wide temperature range is realized, the matching degree of a testing environment and a terminal application scene is remarkably improved, and through a combined transmission scheme of the cabin-penetrating connector and the temperature-resistant wire, the mobility of the resistive load board is ensured, and the test efficiency is improved. The transmission fidelity of a high-frequency test signal under the condition of a wide temperature range is ensured, the problem of signal distortion caused by temperature change in a traditional test is solved, and the analysis result of a full-channel measurement system can truly reflect the signal output quality of each channel of a test machine.

An integrated circuit, IC, (100) includes: a first functional analog pin or pad (152); a first analog test bus (162) coupled to the first functional analog pin or pad; first and second analog circuits (124, 134, 144) coupled to the first analog test bus (162); and a test controller (110) configured to: when the IC is in a functional operating mode, connect an input or output of the first analog circuit to the first analog test bus (162) so that the input or output of the first analog circuit is accessible by the first functional analog pin or pad (152), and keep disconnected an input or output of the second analog circuit from the first analog test bus (162), and when the IC is in a test mode, selectively connect the input or output of the first and second analog circuits (124, 134, 144) to the first analog test bus (162) to test the first and second analog circuits using the first analog test bus (162).

The invention relates to the field of nuclear power station protection systems, in particular to a test method for a protection system card. The test method comprises the following steps: carrying out indicator light test and logic function test on all protection system cards in sequence; the logic function test specifically comprises the step of testing each non-triggering condition and the lowest triggering condition in sequence; confirming the type of the protection system card; performing delay unit testing, self-holding unit testing and anti-interference testing on the logic card in sequence; response time testing is carried out on the signal cards in sequence; and carrying out self-holding unit testing and response time testing on the output card in sequence. The performance of the card is comprehensively tested, and the reliability is high.

SOLUTION: A computation apparatus comprises a plurality of memory banks and a computation processing unit that generates a result data sequence obtained by computation of a plurality of data sequences by repeating processes of reading the data sequence from a source memory bank among the plurality of memory banks, performing computation between the read data sequence and the next data sequence, and writing the data sequence obtained as a result of the computation into a destination memory bank among the plurality of memory banks while alternately switching the source memory bank and the destination memory bank.SELECTED DRAWING: Figure 4

The invention provides a fault detection method and system for an analog circuit, and the method comprises the steps: obtaining a one-dimensional time sequence voltage signal outputted by a to-be-detected analog circuit in a plurality of preset fault modes, and converting the one-dimensional time sequence voltage signal into a two-dimensional detection image through employing a Grubm angle difference field; obtaining a preset fault detection model based on a double-attention residual shrinkage network, the preset fault detection model comprising a double-attention residual shrinkage block, the double-attention residual contraction block comprises a channel attention module used for adaptively calibrating the weight of a feature channel, a space attention module used for enhancing the response of a key space region in a feature map, and a soft thresholding module used for suppressing noise and retaining effective features; and inputting the two-dimensional detection image into the preset fault detection model to obtain a fault classification result of the analog circuit to be detected. According to the technical scheme, the working efficiency of analog circuit fault detection and the accuracy of a detection result can be improved.

A communication link operating characteristic testing system includes: a relay combination circuit board, a simulation assembly and an interface assembly. The simulation assembly is arranged on the relay combination circuit board. The interface assembly is arranged on the relay combination circuit board, and the interface assembly is configured to connect with a DUT. The relays on the combination circuit board are turned on / off to connect the DUT to the required devices in the simulation assembly, so that the DUT can be tested under the working environment simulated by the simulation assembly. The system can cope with different working conditions, test and verify the various signal characteristics of the DUT and the operating characteristics of the DUT under various working conditions, which is applicable to various differential communication technologies and avoids negligence caused by manual testing.