79results about "Analog circuit testing" patented technology

The invention discloses an analog IC synchronization test optimization method and system based on crosstalk simulation. The method comprises the following steps: firstly, acquiring position layout data and test signal data of each analog IC in a synchronous test process of the analog ICs, determining electromagnetic crosstalk information by combining test signals, and constructing a crosstalk schematic diagram according to the electromagnetic crosstalk information and the position layout data; clustering the schematic diagrams by using a spectral clustering algorithm, and identifying a crosstalk path in the synchronization test; designing an electromagnetic crosstalk signal isolation barrier based on the schematic diagram and the crosstalk path, deploying the electromagnetic crosstalk signal isolation barrier in a test environment, performing simulation evaluation on an independently tested analog IC by constructing and injecting a crosstalk simulation signal, and judging an isolation effect; and optimizing the isolation barrier according to an evaluation result to obtain an optimization scheme. According to the method, the electromagnetic crosstalk path in the synchronous test process can be effectively identified and isolated, and the accuracy and reliability of the simulation IC test are improved.

The invention discloses an analog integrated circuit test method based on edge calculation, the method is executed by an edge node, and the method comprises the following steps: obtaining a step response waveform of an analog integrated circuit; extracting screening features from the step response waveform; determining an abnormal level and a test type of the screening feature; determining the demand level of the server for the original waveform data based on the abnormal level of the screening feature and the test type; and determining a sending strategy for sending the screening feature and the original waveform data to the server based on the demand level. According to the invention, waiting and repeated interaction of the server can be reduced, and test judgment efficiency and test throughput are improved.

The density and power consumption of modern integrated circuits, such as Graphic Processing Units (GPUs), Central Processing Units (CPUs), and Network Processing Units (NPUs) is growing rapidly, which necessitates designing advanced cooling systems. Existing solutions for characterizing and validating these cooling system are inadequate. A flexible, scalable Thermal Test Vehicle (TTV) is disclosed which is based on an array of power transistors, measurement / control circuitry, and onboard computer. The TTV is configured for characterizing the performance of electronic cooling solutions under a variety of operating conditions.

Apparatuses, systems, and methods for, and more particularly to apparatuses, systems, and methods for a high-speed composite amplifier driving circuit to generate and output analog signals. The high-speed composite amplifier driving circuit can combine a voltage-controlled pulser and waveform generator with high-accuracy current-voltage (I-V) measurement functions. The voltage-controlled pulser and waveform generator, for example, can provide a ±5 volt, 10 milliamp waveform at up to 50 megahertz with 5 nanosecond rise / fall timing and 8 ns minimum pulse widths. In addition, the high-accuracy I-V measurements can measure a ±10 volts, 10 milliamp waveform at up to 30 MHz with 7-10 nanosecond rise / fall timing and 8 to 12 nanosecond minimum pulse widths.

The application discloses a kind of analog circuit fault diagnosis method based on wavelet scattering and ensemble learning, to solve the problem that analog circuit fault response aliasing leads to difficult fault diagnosis.First, the circuit response is divided into multiple frequency band subsets by wavelet scattering transform, and the fault features of the subsets are enhanced using Fisher discriminant analysis.Second, each frequency band subset is sent to different extreme learning machines under Bagging integration, and the classification accuracy of each fault mode in the frequency band subset is used as the class weight of the extreme learning machine.Then, the output values of each extreme learning machine are weighted to obtain the fused output result, and the fault class is determined accordingly.Finally, two example circuits are simulated, and the simulation results show that the diagnostic accuracy is 100%, indicating that the method is feasible and effective, and can realize fault classification and positioning.

Provided is a test apparatus comprising an input unit that is connected to a device under test and receives a signal to be tested from the device under test, and a function test unit that tests a function of the device under test on the basis of the signal to be tested, the function test unit having a timing measurement unit that measures the timing of an edge of the input signal, the input unit having a current measurement unit that outputs a current measurement signal corresponding to the current value of the signal to be tested, and a first input switching unit that switches whether or not to input the current measurement signal to the function test unit, and the timing measurement unit measuring the pulse width of the current measurement signal on the basis of the timing of the edge of the current measurement signal that is input to the function test unit.

The invention discloses an analog circuit switch control method with a fault self-checking function, and relates to the technical field of electric switches, and the method comprises the steps: dynamically monitoring and obtaining circuit state information through a built-in circuit monitor in an analog circuit. And calling a circuit feature extraction strategy, performing feature extraction analysis on the circuit state information, and generating a circuit feature vector. And reading a predetermined feature vector, comparing the circuit feature vector with the predetermined feature vector, and calculating a triangular distance value. And performing normalization processing on the triangular distance value to obtain a degradation state index, and sending a first fault early warning signal when the degradation state index does not meet a predetermined index threshold. And executing action control on a circuit switch of the analog circuit based on the first fault early warning signal so as to realize early warning and response of the circuit fault. Therefore, the technical effects of reducing the calculation amount, reducing the data dependence and providing a clear and explainable diagnosis result are achieved.

The application provides a chip analog quantity gear value determination method and device and a controller. In the application, an initial gear value is first obtained, then a gear value of a measured chip is set to the initial gear value, an analog quantity output value of the measured chip is obtained, in a case where the analog quantity output value is not located in a preset analog quantity interval, an output difference value between a center value of the preset analog quantity interval and the analog quantity output value is determined, in a case where a difference value between adjacent gear values is a fixed difference value, a gear difference value corresponding to the output difference value is determined, and an actual gear value of the measured chip is determined according to the initial gear value and the gear difference value. That is, in the application, the final actual gear value can be directly determined according to the initial gear value, the output difference value between the center value of the preset analog quantity interval and the analog quantity output value corresponding to the initial gear value, compared with a traversal mode, the number of adjustment times can be reduced, and the adjustment efficiency is improved.

The application discloses a kind of analog signal calibration method, controller and system suitable for semiconductor equipment, method includes: control analog signal output module exports first preset electric signal;Through analog signal input module, first preset electric signal is collected, and first electric parameter acquisition value is obtained;First preset electric signal is measured by analog electric parameter measuring device, and first electric parameter measurement value is obtained;According to first electric parameter acquisition value and first electric parameter measurement value, analog signal input module is calibrated;Control analog signal output module exports second preset electric signal corresponding to first preset electric parameter value;Second preset electric signal is collected by calibrated analog signal input module, and second electric parameter acquisition value is obtained;According to first preset electric parameter value and second electric parameter acquisition value, the signal output by analog signal output module is calibrated.By the above-mentioned mode, analog input signal and analog output signal can be calibrated to improve precision.

Embodiments described herein provide for high frequency transmission spectroscopy (HFTS) system and methods. The HFTS system and methods provided herein allow for identification or classification of materials of interest in a wide range of industries. The HFTS system and methods are capable of identifying unknown particles, characterizing particle size / charge, or monitoring solutions for specific materials in semiconductor, biomedical, and environmental applications. The HFTS system includes an ENA operable to generate an AC as an excitation signal and sweep a frequency of the AC from an initial frequency to a final frequency. A test cell operable to retain a MOI is positioned between an input antenna and an output antenna. The ENA is configured to calculate parameters at each frequency step to plot magnitude response and / or phase response for identification or classification.

A device may perform impedance spectroscopy on a component under test. The frequency response analyzer circuity may be coupled to the component under test outside of a current loop supplying an operational current to the component under test. The frequency response analyzer circuity may drive a variable impedance circuit to generate an oscillating current component within the current loop. The frequency response analyzer circuity may monitor a frequency response of the component under test to the oscillating current component.

Provided is a test apparatus comprising an input unit that is connected to a device under test and receives a signal to be tested from the device under test, and a function test unit that tests a function of the device under test on the basis of the signal to be tested, the function test unit having a timing measurement unit that measures the timing of an edge of the input signal, the input unit having a current measurement unit that outputs a current measurement signal corresponding to the current value of the signal to be tested, and a first input switching unit that switches whether or not to input the current measurement signal to the function test unit, and the timing measurement unit measuring the pulse width of the current measurement signal on the basis of the timing of the edge of the current measurement signal that is input to the function test unit.

The invention discloses an airborne radio frequency system filter circuit fault diagnosis method based on confidence fusion, and belongs to the technical field of analog circuit fault diagnosis. The method comprises the following steps: firstly, acquiring an output end voltage data set in a circuit health state and each fault state, converting time domain data into frequency domain data by using FFT (Fast Fourier Transform), then carrying out logarithmic compression, and normalizing the time domain data; constructing a 1D-CNN model, and performing fault diagnosis by using the time domain data to obtain a time domain probability vector; constructing a Transform model, and performing fault diagnosis by using the frequency domain data to obtain a frequency domain probability vector; a fusion probability vector is obtained through weighted fusion, and a fault category corresponding to the maximum probability in the fusion probability vector is selected as a diagnosis result; training by using the training set, and verifying validity by using the test set. According to the method, time-frequency double-domain feature extraction is adopted to capture multi-dimensional representation of a circuit state; in combination with 1D-CNN local feature extraction and Transform global association, computing resource consumption is reduced, and the accuracy and robustness of a diagnosis result are greatly improved.

The invention provides a full-channel measurement system based on analog chip test equipment, and relates to the technical field of chip test equipment. The full-channel measurement system based on the analog chip test equipment comprises a full-channel measurement device, a nitrogen purging device, a heat supply device, a cold supply device, an air draft device, an analyzer, the chip test equipment and a resistance load board. Through a multi-chamber independent temperature control structure of the variable temperature box, stable testing of the resistive load board in an extreme temperature environment in a wide temperature range is realized, the matching degree of a testing environment and a terminal application scene is remarkably improved, and through a combined transmission scheme of the cabin-penetrating connector and the temperature-resistant wire, the mobility of the resistive load board is ensured, and the test efficiency is improved. The transmission fidelity of a high-frequency test signal under the condition of a wide temperature range is ensured, the problem of signal distortion caused by temperature change in a traditional test is solved, and the analysis result of a full-channel measurement system can truly reflect the signal output quality of each channel of a test machine.

An integrated circuit, IC, (100) includes: a first functional analog pin or pad (152); a first analog test bus (162) coupled to the first functional analog pin or pad; first and second analog circuits (124, 134, 144) coupled to the first analog test bus (162); and a test controller (110) configured to: when the IC is in a functional operating mode, connect an input or output of the first analog circuit to the first analog test bus (162) so that the input or output of the first analog circuit is accessible by the first functional analog pin or pad (152), and keep disconnected an input or output of the second analog circuit from the first analog test bus (162), and when the IC is in a test mode, selectively connect the input or output of the first and second analog circuits (124, 134, 144) to the first analog test bus (162) to test the first and second analog circuits using the first analog test bus (162).

The invention relates to the field of nuclear power station protection systems, in particular to a test method for a protection system card. The test method comprises the following steps: carrying out indicator light test and logic function test on all protection system cards in sequence; the logic function test specifically comprises the step of testing each non-triggering condition and the lowest triggering condition in sequence; confirming the type of the protection system card; performing delay unit testing, self-holding unit testing and anti-interference testing on the logic card in sequence; response time testing is carried out on the signal cards in sequence; and carrying out self-holding unit testing and response time testing on the output card in sequence. The performance of the card is comprehensively tested, and the reliability is high.

SOLUTION: A computation apparatus comprises a plurality of memory banks and a computation processing unit that generates a result data sequence obtained by computation of a plurality of data sequences by repeating processes of reading the data sequence from a source memory bank among the plurality of memory banks, performing computation between the read data sequence and the next data sequence, and writing the data sequence obtained as a result of the computation into a destination memory bank among the plurality of memory banks while alternately switching the source memory bank and the destination memory bank.SELECTED DRAWING: Figure 4

The invention provides a fault detection method and system for an analog circuit, and the method comprises the steps: obtaining a one-dimensional time sequence voltage signal outputted by a to-be-detected analog circuit in a plurality of preset fault modes, and converting the one-dimensional time sequence voltage signal into a two-dimensional detection image through employing a Grubm angle difference field; obtaining a preset fault detection model based on a double-attention residual shrinkage network, the preset fault detection model comprising a double-attention residual shrinkage block, the double-attention residual contraction block comprises a channel attention module used for adaptively calibrating the weight of a feature channel, a space attention module used for enhancing the response of a key space region in a feature map, and a soft thresholding module used for suppressing noise and retaining effective features; and inputting the two-dimensional detection image into the preset fault detection model to obtain a fault classification result of the analog circuit to be detected. According to the technical scheme, the working efficiency of analog circuit fault detection and the accuracy of a detection result can be improved.

A communication link operating characteristic testing system includes: a relay combination circuit board, a simulation assembly and an interface assembly. The simulation assembly is arranged on the relay combination circuit board. The interface assembly is arranged on the relay combination circuit board, and the interface assembly is configured to connect with a DUT. The relays on the combination circuit board are turned on / off to connect the DUT to the required devices in the simulation assembly, so that the DUT can be tested under the working environment simulated by the simulation assembly. The system can cope with different working conditions, test and verify the various signal characteristics of the DUT and the operating characteristics of the DUT under various working conditions, which is applicable to various differential communication technologies and avoids negligence caused by manual testing.

A system for generating and measuring electrical signals is disclosed. The system includes a digital-to-analog converter module configured to generate one or more analog signals based on a control signal and one or more channels. Each channel includes an output terminal configured to be electrically connected to an electrical device and a buffer circuit. The buffer circuit is configured to receive one of the one or more analog signals and provide a voltage at the output terminal based on a voltage of the received analog signal. The buffer circuit is further configured to be electrically connected to a current source and to allow a current to flow between the current source and the output terminal. The system further includes a voltage measurement system and a current measurement system. The voltage measurement system is configured to measure, for each channel, a voltage indicative of a voltage at the output terminal of the channel. The current measurement system is configured to measure, for each channel, a current flowing through the output terminal of the channel. A method for generating and measuring electrical signals is also disclosed.

The invention discloses a method for carrying out fault detection on an analog board and a related product thereof. The analog board comprises a plurality of functional modules and a plurality of detection switches. The method comprises the following steps: controlling the detection switch to execute preset switching so as to access a to-be-detected functional module to a corresponding transmission path; inputting associated test data to the functional module accessed to the corresponding transmission path to obtain a test result of the to-be-detected functional module, the test result being used for determining whether the to-be-detected functional module has a fault; and outputting the test result through the corresponding transmission path so as to determine whether the to-be-detected function module has a fault or not based on the test result. According to the scheme, the fault point of the analog board can be quickly and accurately positioned, so that the fault point of the acquisition system can be quickly and accurately positioned.

The application discloses a confidence fusion-based fault diagnosis method for a filter circuit of an airborne radio frequency system, and belongs to the technical field of analog circuit fault diagnosis. Firstly, output end voltage data sets in a healthy state and in each fault state are collected, time domain data is converted into frequency domain data through FFT, and then logarithmic compression is performed on the frequency domain data, so that the time domain data is normalized; a 1D-CNN model is constructed, time domain data is used for fault diagnosis to obtain a time domain probability vector; a Transformer model is constructed, frequency domain data is used for fault diagnosis to obtain a frequency domain probability vector; a fusion probability vector is obtained through weighted fusion, a fault category corresponding to the maximum probability in the fusion probability vector is selected as a diagnosis result; and a training set is used for training, and a test set is used for verifying effectiveness. The application adopts time-frequency dual domain feature extraction to capture multi-dimensional representation of the circuit state, combines 1D-CNN local feature extraction with Transformer global correlation, reduces the consumption of computing resources, and greatly improves the accuracy and robustness of the diagnosis result.

The invention provides an analog chip test system, which comprises a signal input module, a test module, a signal processing module, a signal acquisition module and an upper computer which are connected in sequence, and is characterized in that the signal acquisition module is connected with one end, connected with the signal input module, of the test module; the test module is used for connecting an analog chip to be tested, the signal input module is used for inputting a signal to the analog chip to be tested through the test module, and the signal processing module is used for receiving an output signal of the analog chip to be tested through the test module, processing the received output signal and outputting the processed output signal to the analog chip to be tested. The signal acquisition module is used for acquiring a signal processed by the signal processing module and a signal input to the analog chip to be tested by the signal input module, and the upper computer is used for receiving the signal acquired by the signal acquisition module and analyzing the signal to obtain a test result of the analog chip to be tested. The practicability of the test system can be improved.

The present invention belongs to the field of communication testing technology, and specifically relates to a communication link operating characteristic testing system and a testing method thereof, wherein the communication link operating characteristic testing system includes: a relay combination circuit board, a simulation assembly and an interface assembly. The simulation assembly is arranged on the relay combination circuit board. The interface assembly is arranged on the relay combination circuit board, and the interface assembly is configured to connect with a DUT. The relays on the relay combination circuit board are turned on / off to connect the DUT to the required devices in the simulation assembly, so that the DUT can be tested under the working environment simulated by the simulation assembly. The present invention can cope with different working conditions, test and verify the various signal characteristics of the DUT and the operating characteristics of the DUT under various working conditions, which is applicable to various differential communication technologies and avoids negligence caused by manual testing.

Method for functional testing of a filter (2), preferably a high-frequency filter or an EMC filter, in particular a common-mode filter and / or a differential-mode filter, and wherein the filter (2) comprises an active filter and / or a passive filter and / or a digital filter, and wherein the filter (2) is arranged in or on a power supply line, preferably installed in a DC network and / or a traction network of a motor vehicle, in order to filter out disturbances, characterized by that a functional detector (3) is arranged at the input and / or output of the filter (2), and that an averaging is carried out with the function detector (3), and that a voltage value is determined by averaging and the determined voltage value is used to assess the functionality of the filter (2) by comparing the voltage value with a threshold value.

The invention discloses an analog circuit fault diagnosis method based on GOA and SVM, and belongs to the technical field of fault diagnosis, the analog circuit in different fault states is simulated, and the output end of the circuit is used as a test point to obtain circuit pulse response; multiple groups of sample data are obtained for each circuit fault state through Monte Carlo, singular values obtained by decomposing the sample data through combination of wavelet packets and singular values serve as feature vectors to construct a sample set, and the sample set is randomly divided into a training set and a test set; based on the training set, GOA is adopted to find an optimal penalty factor and kernel function parameters of an SVM, and a GOA-SVM fault diagnosis model is established; and performing diagnosis classification on the test set data by using the GOA-SVM fault diagnosis model, and obtaining a diagnosis result of the analog circuit fault. When the method is used for carrying out analog circuit fault diagnosis, the resolution ratio of a fault mode is high, the diagnosis performance is good, and therefore the diagnosis performance and efficiency of the tested analog circuit are improved.

Device (1, 1') with a signal amplifier (2, 2') integrated into a semiconductor chip, the signal amplifier having an amplifier input (E) for an input signal and an amplifier output (A) for an output signal, the signal amplifier (2, 2') having at least two amplifier stages (6, 6', 7, 7', 8, 9) connected in series between the amplifier input (E) and the amplifier output (A) and a feedback network arranged between the amplifier input (E) and the amplifier output (A), and with an error detection circuit (3) integrated into the semiconductor chip for detecting a faulty modulation of the output signal caused by a fault in the circuitry of the integrated circuit, the error detection circuit having a comparator (16),which is designed to compare a comparator input signal applied to a comparator input (17) of the comparator (16) with a predetermined tolerance value or tolerance range, characterized in that a comparator input (17) of the comparator (16) is connected to a node (14, 14') of the signal amplifier (2, 2') arranged between two amplifier stages (6, 6', 7, 7', 8, 9), and that the signal amplifier (2, 2') is designed such that a signal can be output at the node (14, 14') which is more strongly modulated than the input signal.

The invention relates to a test method for checking the operating state of an efuse (1) which can be switched between at least one conducting and one non-conducting state and via which an electrical load (3) is electrically connected to a supply voltage source (2), wherein the electrical load (3) tolerates a supply interruption for a predetermined maximum interruption duration. An actual residual current value is determined by an actual value of a discharge time duration, T, of the discharge of a capacitor (103) supplied by the switchable efuse (1) in parallel with the electrical load (3) via a resistor (102) and is compared with at least one desired value of the discharge time duration, T, determined for the switchable efuse (1) for each operating state and associated with a desired residual current value. The invention further relates to a test system (100) for carrying out the test method.

The invention discloses a method for generating training data for fault diagnosis of an analog circuit, and the method comprises the steps: firstly building a Condition-DDPM model employing a self-adaptive strategy, then collecting the real output data of a target analog circuit in a normal state and different fault states, carrying out the modal decomposition processing, and then training the built Condition-DDPM model, and finally, a training data set is generated through the trained Conditional-DDPM model.