28results about "Analog circuit testing" patented technology

The invention discloses an analog integrated circuit test method based on edge calculation, the method is executed by an edge node, and the method comprises the following steps: obtaining a step response waveform of an analog integrated circuit; extracting screening features from the step response waveform; determining an abnormal level and a test type of the screening feature; determining the demand level of the server for the original waveform data based on the abnormal level of the screening feature and the test type; and determining a sending strategy for sending the screening feature and the original waveform data to the server based on the demand level. According to the invention, waiting and repeated interaction of the server can be reduced, and test judgment efficiency and test throughput are improved.

The density and power consumption of modern integrated circuits, such as Graphic Processing Units (GPUs), Central Processing Units (CPUs), and Network Processing Units (NPUs) is growing rapidly, which necessitates designing advanced cooling systems. Existing solutions for characterizing and validating these cooling system are inadequate. A flexible, scalable Thermal Test Vehicle (TTV) is disclosed which is based on an array of power transistors, measurement / control circuitry, and onboard computer. The TTV is configured for characterizing the performance of electronic cooling solutions under a variety of operating conditions.

Apparatuses, systems, and methods for, and more particularly to apparatuses, systems, and methods for a high-speed composite amplifier driving circuit to generate and output analog signals. The high-speed composite amplifier driving circuit can combine a voltage-controlled pulser and waveform generator with high-accuracy current-voltage (I-V) measurement functions. The voltage-controlled pulser and waveform generator, for example, can provide a ±5 volt, 10 milliamp waveform at up to 50 megahertz with 5 nanosecond rise / fall timing and 8 ns minimum pulse widths. In addition, the high-accuracy I-V measurements can measure a ±10 volts, 10 milliamp waveform at up to 30 MHz with 7-10 nanosecond rise / fall timing and 8 to 12 nanosecond minimum pulse widths.

The application provides a chip analog quantity gear value determination method and device and a controller. In the application, an initial gear value is first obtained, then a gear value of a measured chip is set to the initial gear value, an analog quantity output value of the measured chip is obtained, in a case where the analog quantity output value is not located in a preset analog quantity interval, an output difference value between a center value of the preset analog quantity interval and the analog quantity output value is determined, in a case where a difference value between adjacent gear values is a fixed difference value, a gear difference value corresponding to the output difference value is determined, and an actual gear value of the measured chip is determined according to the initial gear value and the gear difference value. That is, in the application, the final actual gear value can be directly determined according to the initial gear value, the output difference value between the center value of the preset analog quantity interval and the analog quantity output value corresponding to the initial gear value, compared with a traversal mode, the number of adjustment times can be reduced, and the adjustment efficiency is improved.

The application discloses a kind of analog signal calibration method, controller and system suitable for semiconductor equipment, method includes: control analog signal output module exports first preset electric signal;Through analog signal input module, first preset electric signal is collected, and first electric parameter acquisition value is obtained;First preset electric signal is measured by analog electric parameter measuring device, and first electric parameter measurement value is obtained;According to first electric parameter acquisition value and first electric parameter measurement value, analog signal input module is calibrated;Control analog signal output module exports second preset electric signal corresponding to first preset electric parameter value;Second preset electric signal is collected by calibrated analog signal input module, and second electric parameter acquisition value is obtained;According to first preset electric parameter value and second electric parameter acquisition value, the signal output by analog signal output module is calibrated.By the above-mentioned mode, analog input signal and analog output signal can be calibrated to improve precision.

A device may perform impedance spectroscopy on a component under test. The frequency response analyzer circuity may be coupled to the component under test outside of a current loop supplying an operational current to the component under test. The frequency response analyzer circuity may drive a variable impedance circuit to generate an oscillating current component within the current loop. The frequency response analyzer circuity may monitor a frequency response of the component under test to the oscillating current component.

The invention provides a fault detection method and system for an analog circuit, and the method comprises the steps: obtaining a one-dimensional time sequence voltage signal outputted by a to-be-detected analog circuit in a plurality of preset fault modes, and converting the one-dimensional time sequence voltage signal into a two-dimensional detection image through employing a Grubm angle difference field; obtaining a preset fault detection model based on a double-attention residual shrinkage network, the preset fault detection model comprising a double-attention residual shrinkage block, the double-attention residual contraction block comprises a channel attention module used for adaptively calibrating the weight of a feature channel, a space attention module used for enhancing the response of a key space region in a feature map, and a soft thresholding module used for suppressing noise and retaining effective features; and inputting the two-dimensional detection image into the preset fault detection model to obtain a fault classification result of the analog circuit to be detected. According to the technical scheme, the working efficiency of analog circuit fault detection and the accuracy of a detection result can be improved.

A system for generating and measuring electrical signals is disclosed. The system includes a digital-to-analog converter module configured to generate one or more analog signals based on a control signal and one or more channels. Each channel includes an output terminal configured to be electrically connected to an electrical device and a buffer circuit. The buffer circuit is configured to receive one of the one or more analog signals and provide a voltage at the output terminal based on a voltage of the received analog signal. The buffer circuit is further configured to be electrically connected to a current source and to allow a current to flow between the current source and the output terminal. The system further includes a voltage measurement system and a current measurement system. The voltage measurement system is configured to measure, for each channel, a voltage indicative of a voltage at the output terminal of the channel. The current measurement system is configured to measure, for each channel, a current flowing through the output terminal of the channel. A method for generating and measuring electrical signals is also disclosed.

Method for functional testing of a filter (2), preferably a high-frequency filter or an EMC filter, in particular a common-mode filter and / or a differential-mode filter, and wherein the filter (2) comprises an active filter and / or a passive filter and / or a digital filter, and wherein the filter (2) is arranged in or on a power supply line, preferably installed in a DC network and / or a traction network of a motor vehicle, in order to filter out disturbances, characterized by that a functional detector (3) is arranged at the input and / or output of the filter (2), and that an averaging is carried out with the function detector (3), and that a voltage value is determined by averaging and the determined voltage value is used to assess the functionality of the filter (2) by comparing the voltage value with a threshold value.

The invention discloses an analog circuit fault diagnosis method based on GOA and SVM, and belongs to the technical field of fault diagnosis, the analog circuit in different fault states is simulated, and the output end of the circuit is used as a test point to obtain circuit pulse response; multiple groups of sample data are obtained for each circuit fault state through Monte Carlo, singular values obtained by decomposing the sample data through combination of wavelet packets and singular values serve as feature vectors to construct a sample set, and the sample set is randomly divided into a training set and a test set; based on the training set, GOA is adopted to find an optimal penalty factor and kernel function parameters of an SVM, and a GOA-SVM fault diagnosis model is established; and performing diagnosis classification on the test set data by using the GOA-SVM fault diagnosis model, and obtaining a diagnosis result of the analog circuit fault. When the method is used for carrying out analog circuit fault diagnosis, the resolution ratio of a fault mode is high, the diagnosis performance is good, and therefore the diagnosis performance and efficiency of the tested analog circuit are improved.

Device (1, 1') with a signal amplifier (2, 2') integrated into a semiconductor chip, the signal amplifier having an amplifier input (E) for an input signal and an amplifier output (A) for an output signal, the signal amplifier (2, 2') having at least two amplifier stages (6, 6', 7, 7', 8, 9) connected in series between the amplifier input (E) and the amplifier output (A) and a feedback network arranged between the amplifier input (E) and the amplifier output (A), and with an error detection circuit (3) integrated into the semiconductor chip for detecting a faulty modulation of the output signal caused by a fault in the circuitry of the integrated circuit, the error detection circuit having a comparator (16),which is designed to compare a comparator input signal applied to a comparator input (17) of the comparator (16) with a predetermined tolerance value or tolerance range, characterized in that a comparator input (17) of the comparator (16) is connected to a node (14, 14') of the signal amplifier (2, 2') arranged between two amplifier stages (6, 6', 7, 7', 8, 9), and that the signal amplifier (2, 2') is designed such that a signal can be output at the node (14, 14') which is more strongly modulated than the input signal.

The invention discloses a voltage reference evaluation board and method with electromagnetic compatibility, the evaluation board comprises a core board and a bottom board which are split, the core board is integrated with a high-speed digital circuit, and the bottom board is provided with high-precision analog chips in a centralized manner; an inter-board ground loop is formed between the core board and the bottom board through a connector which vertically penetrates through the core board and the bottom board; the bottom plate comprises a four-layer plate laminated structure, namely a top signal layer, a ground layer, a power supply layer and a bottom signal layer in sequence from top to bottom; the bottom signal layer is provided with a reference voltage source, an ADC, an operational amplifier, a voltage dividing module and a test connecting hole of the reference voltage source to be tested, which are far away from the main control area of the core board. An annular heat insulation groove is formed in the periphery of the reference voltage source to form an air heat insulation layer, high-density grounding via hole arrays are arranged on the two sides of the heat insulation groove, and bridging capacitors are laid on the high-density grounding via hole arrays in a cross-groove mode. The electromagnetic compatibility of the voltage reference evaluation board can be improved, and thermal interference can be suppressed.

The application discloses a kind of multi-channel detection circuit, method, equipment and computer program product, it is related to analog circuit detection technical field, the circuit includes integrated with multiple analog channel unit Channel module, control module and reference signal generation module;Through control module is set to obtain current channel identification, determine the analog channel unit corresponding to current channel identification from all analog channel units as target channel unit, and reference signal detection is carried out according to target channel unit, and the detection reference signal of target channel unit is obtained;Reference signal generation module generates the standard reference signal of target channel unit under the driving of control module, and the standard reference signal is sent to control module, so that control module determines the channel operating state of target channel unit according to detection reference signal and standard reference signal.The application aims at realizing the reliability detection of multi-channel analog circuit.

The present invention provides a device and method for monitoring high-speed signals using low-bandwidth probe signals. [Solution] The device includes a first clock signal generator, a second clock signal generator, an input signal generation circuit, and an input signal sampling circuit. The first clock signal generator generates a first clock signal. The second clock signal generator generates a second clock signal delayed relative to the first clock signal. The input signal generation circuit includes a voltage signal generator and a function circuit. The voltage signal generator generates a voltage signal. The function circuit receives the voltage signal and performs one or more circuit functions. The input signal sampling circuit samples the value of the voltage signal at the rising or falling edge of the second clock signal and provides the sampled value as an output signal, thereby analyzing one or more characteristics of the voltage signal based on the output signal.

The invention discloses a nuclear power plant test data acquisition method, a nuclear power plant test data acquisition system and a computer program product. The method comprises the steps that S1, a signal distribution unit is arranged in a cabinet of a main cabinet group, the signal distribution unit obtains initial signals of to-be-tested equipment, each initial signal is distributed, a plurality of corresponding identical signals are output, and the identical signals comprise a control signal and at least one test signal; s2, the cabinets in the main cabinet group are connected with a test processing cabinet through a plurality of first normal state cables, and the test signals output by the main cabinet group are transmitted to the test processing cabinet; and S3, the test processing cabinet collects test signals and carries out calculation processing. By implementing the technical scheme of the invention, temporary connection and disconnection are not needed, the operation safety of the nuclear power unit is improved, the risk of key path delay of overhaul caused by test rework due to connection looseness, low insulation or short-circuit grounding is reduced, the test reliability is improved, and the labor cost input is reduced.

The invention provides a switch device and a test device. A switching device electrically connects or disconnects a first terminal and a second terminal, the switching device including: a plurality of main switches connected in series between the first terminal and the second terminal; a first detection buffer section to which a first voltage at the first terminal is input and which outputs a first detection voltage corresponding to the first voltage; and a bias circuit that divides a potential difference between a voltage corresponding to a second voltage at the second terminal and the first detection voltage in accordance with the number of main switches, and applies each of the divided voltages to the corresponding main switch.

The application discloses a kind of based on network centrality simulation / mixed signal circuit measuring point set compression method, and the node dictionary set and component dictionary set are extracted from the netlist file of analog / mixed signal circuit, the connection between node and the current direction relationship of extraction according to component dictionary set and node dictionary set establish the directed network graph of node, the centrality index of each measuring point is calculated, based on weighted Borda number method is comprehensively sorted to measuring point, and from measuring point sequence, the measuring point of early sorting is selected as alternative measuring point, and finally the measuring point set is further preferred based on criticality to alternative measuring point and obtained.The centrality of the application is combined with the sensitivity of defect to carry out measuring point screening, so that the measuring point set screened is more accurate and effective.

Various embodiments relate to a method of testing a plurality of devices of the same type wherein each of the plurality of devices of the same type include a built-in self-test device, including: randomly generating, by a processor, stimulus parameters; applying, by the built-in self-test devices, the generated stimulus parameters N times to the plurality of devices of the same type; measuring, by the plurality of devices of the same type, a response of the plurality of devices of the same type to the generated stimulus parameters to produce M×N response outputs, where M is a number of the plurality of devices of the same type; calculating, by the processor, a defect likelihood for a test set of the plurality of identical devices based upon a mean of a reference set of the plurality of identical devices response outputs, a mean of the test set response outputs, a standard deviation of reference set response outputs, and a standard deviation of the test set response outputs; determining, by the processor, that the defect likelihood for the test set is greater than a first threshold value; applying, by the processor, an initial step of a directed random search algorithm to update stimulus parameters in response to determining that the defect likelihood is greater than the first threshold; applying, by the built-in self-test devices, the updated stimulus parameters N times to the plurality of devices of the same type; measuring, by the plurality of devices of the same type, a response of the plurality of devices of the same type to the updated stimulus parameters to produce M×N updated response outputs; calculating, by the processor, a defect likelihood for the test set based upon a mean of the reference set updated response outputs, a mean of the test set updated response outputs, a standard deviation of reference set updated response outputs, and a standard deviation of the test set updated response outputs; and determining, by the processor, that the defect likelihood for the test set is greater than a second threshold, wherein the second threshold is greater than the first threshold.

The invention relates to a monitoring module (16) for monitoring a surge protection module (21). The monitoring module (16) has a first connection (18) and a second connection (20) for the surge protection module (21). The monitoring module (16) has an overload protection device (22) which is connected to the first connection (18) via a line (26) and can be connected in series with the surge protection module (21) via the first connection (18). The monitoring module (16) includes a bridge circuit (28) for voltage detection. The monitoring module (16) has an evaluation unit (30) which is connected to the line (26) via a tap (29) of the bridge circuit (28) in order to detect and evaluate a voltage drop across the overload protection device (22) and / or a voltage drop between the first connection (18) and the second connection (20). A surge protection system (10) is also described.

The invention relates to a MOS, BiCMOS or CMOS-based analog circuit (1). The analog circuit (1) is designed to implement a predetermined circuit function in a normal state of the analog circuit (1). The analog circuit (1) has an analog input or output signal, or has an analog signal inside the analog circuit (1). The analog circuit (1) is connected to test logic (38). The test logic (38) is designed to bring the analog circuit (1) into the normal state and into at least a first test state. The analog circuit (1) comprises a first component (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) which is designed to perform a function of the analog circuit (1) in accordance with the predetermined circuit function during normal operation. According to the invention, the analog circuit (1) further comprises a second component (S1 to S9; G1 to G9) which is designed to enable the test logic (38) to set a switching state of the first component (7, 9, 10, 11, 12, 13, 15, 16, 20, 21, 22, 23, 30) in at least the first test state of the analog circuit (1).

The invention discloses an analog signal calibration method, controller and system suitable for semiconductor equipment. The method comprises the following steps: controlling an analog signal output module to output a first preset electric signal; acquiring a first preset electric signal through an analog signal input module to obtain a first electric parameter acquisition value; measuring the first preset electric signal through an analog electric parameter measurement device to obtain a first electric parameter measurement value; calibrating the analog signal input module according to the first electrical parameter acquisition value and the first electrical parameter measurement value; controlling the analog signal output module to output a second preset electric signal corresponding to the first preset electric parameter value; acquiring a second preset electric signal through the calibrated analog signal input module to obtain a second electric parameter acquisition value; and calibrating the signal output by the analog signal output module according to the first preset electrical parameter value and the second electrical parameter acquisition value. Through the mode, the analog input signal and the analog output signal can be calibrated, so that the precision is improved.

The invention relates to a test device (100) for investigating an electrical isolation process of a DC source (20) from a DC sink (30) in a high-voltage network, comprising at least a circuit arrangement (10) with the DC source (20) and the DC sink (30) as well as a network with a plurality of adjustable passive components, in particular different components, especially adjustable resistors (40), adjustable capacitors (42) and adjustable inductors (44). The circuit arrangement (10) includes at least one isolation element (46, 48) between the DC source (20) and the DC sink (30). The invention further relates to a method for investigating an electrical separation process of a DC source (20) from a DC sink (30) in a high-voltage network using a test device (100).

The invention provides a test method of an integrated circuit and an integrated circuit using the same, a check bit generation circuit is arranged in a simulation block, and check bits are generated from a plurality of test points. The automatic layout and winding block comprises a test pattern generating circuit which generates a test signal from the control signal output end. The system generates check bits according to the test signals and compares the check bits with the check bits. And if not, judging that the integrated circuit is damaged. According to the method, tests of different blocks are effectively integrated, and the detection efficiency and accuracy of the integrated circuit are improved.

The application discloses a kind of based on crosstalk simulation analog IC synchronous test optimization method and system.The method first obtains the position layout data in analog IC synchronous test process and the test signal data of each analog IC, determines electromagnetic crosstalk information in combination with test signal, and accordingly constructs crosstalk schematic diagram with position layout data;Spectral clustering algorithm is used to cluster the schematic diagram, and the crosstalk path in synchronous test is identified;Based on the schematic diagram and the crosstalk path, an electromagnetic crosstalk signal isolation barrier is designed and deployed in the test environment, the analog IC is simulated and evaluated by constructing and injecting crosstalk simulation signals for independent testing, and the isolation effect is judged;According to the evaluation result, the isolation barrier is optimized to obtain an optimization scheme.The method can effectively identify and isolate the electromagnetic crosstalk path in the synchronous test process, and improve the accuracy and reliability of analog IC testing.

The invention provides a failure determination circuit and method, a detection device, an electronic apparatus, and a moving object. The failure determination circuit can perform failure determination of an analog-to-digital converter without stopping operation of the analog-to-digital converter which continuously receives analog voltage signals and converts the analog voltage signals into digital voltage signals. The failure determination circuit includes: a first conversion unit that continuously performs A / D conversion on a first analog signal based on a first physical quantity detection signal; a switching unit into which a plurality of signals including a first reference voltage and a second analog signal based on the first physical quantity detection signal are input, and which outputs the signals in a time division manner; a second conversion unit for A / D converting the output of the switching unit; and a comparison determination unit that performs a failure determination of the first conversion unit on the basis of a signal based on a first digital signal obtained by A / D converting the first analog signal by the first conversion unit and a signal based on a second digital signal obtained by A / D converting the second analog signal by the second conversion unit.

The invention discloses an automatic test method of an isolation amplifier. The automatic test method comprises the following steps: step 1) building a peripheral test circuit of the isolation amplifier; the method for testing the linearity of the isolation amplifier based on the peripheral test circuit can greatly improve efficiency and data stability. The method for testing the linearity of the isolation amplifier based on the peripheral test circuit can be used for testing the linearity of the isolation amplifier based on the peripheral test circuit.

The invention discloses a multi-channel detection circuit, method and device and a computer program product, and relates to the technical field of analog circuit detection, the circuit comprises a channel module integrated with a plurality of analog channel units, a control module and a reference signal generation module; a control module is set to obtain a current channel identifier, determine an analog channel unit corresponding to the current channel identifier from all analog channel units as a target channel unit, and perform reference signal detection according to the target channel unit to obtain a detection reference signal of the target channel unit; and the reference signal generation module generates a standard reference signal of the target channel unit under the driving of the control module, and sends the standard reference signal to the control module, so that the control module determines the channel operation state of the target channel unit according to the detection reference signal and the standard reference signal. The invention aims to realize the reliability detection of the multi-channel analog circuit.