139 results about "Subtractor" patented technology

The present application relates to the technical field of integrated circuits and relates to a matrix operation apparatus based on a flexible RRAM memory-computing array, and solves the problem in the prior art of the inability to reduce the area of the memory-computing array without affecting the precision. The apparatus comprises: the flexible RRAM memory-computing array for outputting cumulative currents of columns of memory-computing units to a multiplexer (MUX) on the basis of multiple rows of inputs; the MUX for selecting the cumulative current of one column of memory-computing units from among the columns of memory-computing units and sending said cumulative current to an analog-to-digital converter (ADC); the ADC for converting the received cumulative current into a digital signal and sending said digital signal to a subtractor; a popcount module for receiving the multiple rows of inputs, obtaining the number of 1 in the multiple rows of inputs, and outputting the number of 1 to a multiplier; the multiplier for multiplying the number of 1 by a fixed value β and sending a product result to the subtractor; and the subtractor for subtracting the product result from the digital signal to obtain a multiply-accumulate result of the matrix. The present application realizes high-precision memory-computing based on a small-area memory-computing array, further enhances energy efficiency, and can be applied to flexible computing chips to create electronic skin.

The invention relates to a multi-modal control-based multi-target unified optimization modulation method for a Semi-DAB converter, and the method comprises the following steps: dividing the working mode of the Semi-DAB converter into a low-power mode and a high-power mode, combining with a cost function, optimizing the backflow power and the current stress, and carrying out the optimization of the backflow power and the current stress. And through a closed-loop control system based on multi-mode control, the converter can automatically switch working modes according to working states. After the input voltage Vin and the output voltage Vo of the Semi-DAB converter are sampled, the output reference voltage and the output voltage are input into a subtractor for subtraction, the obtained error amount is input into a PI controller, p is obtained through corresponding operation, the current working state of the Semi-DAB converter is judged according to the range of the obtained p, seamless switching between the two modes is automatically achieved, and therefore the semi-DAB converter can be switched automatically. And corresponding PWM signals are generated through D0 and D1 given in each mode, and the corresponding switching tubes are driven to be switched on and switched off, so that the converter always operates in the optimal efficiency state in different power intervals.

Devices, systems, and methods for reconfigurable butterfly architectures are provided. A reconfigurable butterfly operator circuit includes a single multiplier configured to receive a first variable and a twiddle factor and produce a product, first and second modular subtractors coupled to the multiplier, the first modular subtractor coupled to receive input coefficients and provide a modular difference, and the second modular subtractor coupled to receive the product, a modular adder coupled to receive the input coefficients and provide a modular sum, and multiplexers coupled to (i) provide the input coefficients to the modular adder, (ii) provide the first variable and the twiddle factor to the multiplier, (iii) and receive the modular difference from the first modular subtractor, respectively, each of the multiplexers coupled to receive a control signal that selects whether the circuit is configured as a Gentleman-Sande butterfly operator circuit or a Cooley-Tukey butterfly operator circuit.

The invention discloses a method and a device for calculating Gamma correction in an RISC-V processor, which can improve the execution efficiency and the calculation precision of a Gamma correction algorithm on the RISC-V processor. Gamma correction is divided into six levels of pipeline structures, wherein the first level is composed of a floating point adder and a floating point shifter, and input pixel values in an integer range from 0 to 255 are mapped to a real number range from 0 to 1; the second stage is used for carrying out reciprocal operation on the Gamma value; in the third stage, logarithm operation is carried out on input pixel values, and a lookup table and piecewise linear approximation method is adopted; the fourth stage uses a floating point multiplier to perform product operation on the result of reciprocal operation and the result of logarithm operation; the fifth stage is used for performing exponential operation on the result output by the fourth stage; and the sixth level is composed of a floating point shifter and a floating point subtractor, and image pixel values after Gamma correction are remapped to an integer range of 0-255.

Aspects of the subject disclosure may include, for example, a digital timing skew compensator, including: a first polyphase adaptive filter bank having a first input and a first output; a first input matrix coupled to the first input of the first polyphase adaptive filter bank; a first subtractor coupled to the first output of the first polyphase adaptive filter bank, wherein the first subtractor removes a first signal generated by the first polyphase adaptive filter bank from digital outputs of sub analog-to-digital converters (ADCs) of a time-interleaved ADC to create a desired signal, wherein the desired signal is coupled to the first input matrix; a modulation matrix that modulates the digital outputs of the sub-ADCs to create a modulated signal vector; a second polyphase adaptive filter bank having a second input and a second output; a second input matrix coupled to the second input of the second polyphase adaptive filter bank; and a second subtractor coupled to the second output of the second polyphase adaptive filter bank, wherein the second subtractor removes a second signal generated by the second polyphase adaptive filter bank from the modulated signal vector to create an error signal, wherein the error signal is coupled to the second input matrix. Other embodiments are disclosed.

The invention relates to a matrix operation device based on a flexible RRAM storage and calculation array, belongs to the technical field of integrated circuits, and solves the problem that the area of the storage and calculation array cannot be reduced under the condition that the precision is not influenced in the prior art. According to the device, a flexible RRAM memory array outputs accumulated current of each column of memory units to a multiplexer MUX according to multi-row input; the multiplexer MUX selects one column of accumulated current from each column of storage and calculation unit and sends the accumulated current to the analog-to-digital converter ADC; the analog-to-digital converter ADC converts the received accumulated current into a digital signal and sends the digital signal to the subtractor; the popcount module receives the multi-line input, obtains the number of 1 in the multi-line input, and outputs the number to the multiplier; the multiplier multiplies the number of 1 by a fixed value beta and sends a product result to the subtracter; and the subtracter subtracts the product result from the digital signal to obtain a multiplication and addition result of the matrix. A small-area storage and calculation array high-precision storage and calculation function is realized, the energy efficiency is further improved, and the method is applied to a flexible calculation chip to make electronic skin.

Devices, systems, and methods for secure modular addition and subtraction are provided. A modular adder and subtractor circuit with masking circuit includes an arithmetic to Boolean (A2B) conversion operator configured to convert (i) a second sum and (ii) a value determined based on a first sum, to Boolean resulting in first and second Boolean values, a shifter configured to (i) make a most significant bit of the first Boolean value a least significant bit resulting in a shifted first Boolean value and (ii) make the most significant bit of the second Boolean value a least significant bit resulting in a shifted second Boolean value, and a Boolean to arithmetic (B2A) conversion operator, configured to convert a representation of the shifted first Boolean value and a representation of the shifted second Boolean value to arithmetic representation resulting in first and second arithmetic values, respectively.

The embodiment of the invention provides a modular reduction circuit, a modular reduction method and a method for determining circuit design parameters. The modular reduction circuit is used for calculating a modular result of an operand with a 2n-bit width on a preset modulus M with an n-bit width, and specifically comprises a lookup table circuit which comprises d lookup tables realized by a storage unit and d first sub-results for lookup of data corresponding to d fragments to perform modular operation on M, and the d fragments are obtained by dividing high (n-m)-bit data of the operand; the adding circuit comprises a plurality of adders and is used for accumulating the d first sub-results to obtain a second sub-result; the iteration circuit comprises a first subtracter and is used for calculating to obtain a third sub-result of the low n + m-bit data of the operand for modulo M through an iteration subtraction mode; the fusion circuit is used for fusing the second sub-result and the third sub-result to obtain a fourth sub-result; and the adjusting circuit is used for performing subtraction-based adjustment on the fourth sub-result to obtain a modulo result.

Devices, systems, and methods for modular multiplication are provided. A circuit for modular multiplication can include a single multiplier configured to receive two variables and produce a product of the two variables, first adders configured to receive one or more subsets of contiguous bits of the product and generate sums based on received subsets of contiguous bits, second adders configured to receive at least a portion of the sums from the first adders and generate intermediate sums, a customized adder configured to receive another, different subset of contiguous bits of the product and an intermediate sum of the intermediate sums and generate a sum based on the received subset of contiguous bits and the intermediate sum, and a subtractor configured to receive the sum from the customized adder and another intermediate result of the intermediate results and generate a result that is the product modulo a prime number, q=8,380,417.

The application discloses a kind of anti-rising sine tracking differential devices and methods, by first subtracter to input signal and the output signal of second integrator carry out subtraction operation, the output result of subtracter is input to first integrator and is integrated, and the output result of first integrator is input to second integrator and is integrated;By delay ware to the output result of second integrator is delayed, the output result of first integrator and input signal are input to second subtracter and carry out subtraction operation, and the output result of second subtracter and the output result of second integrator after time delay are transmitted to third subtracter and carry out subtraction operation, obtain anti-rising sine tracking differential signal.The application subtracts the sum of first integration result and second integration result after time delay from input signal, can improve the cut-off speed of output differential signal, improves the tracking efficiency of differentiator.

The present invention discloses an electronic device, including a substrate and a timing control module. The timing control module transmits a plurality of timing control signals to the substrate, and includes an overcurrent protection circuit for detecting the timing control signals. The overcurrent protection circuit includes a subtractor and a comparator electrically connected to the subtractor. The timing control signal includes a first timing control signal and a second timing control signal, the subtractor calculates a first current difference between the draw current values ​​of the first timing control signal and the second timing control signal, the comparator compares the first current difference with a first threshold value, and when the first current difference is greater than or equal to the first threshold value, the overcurrent protection circuit executes an overcurrent protection mechanism.

Provided are feedforward amplifier circuit, audio amplifier and audio playing device, including: a main amplifier circuit, an adder circuit, a sub-amplifier circuit and a subtractor circuit, wherein the main amplifier circuit adds distortion to a first input signal to output a distorted signal, and inputs the distorted signal to the adder circuit and the subtractor circuit for performing feedforward correction; the sub-amplifier circuit amplifies a second input signal and serves as a positive input of the subtractor, so that a signal gain output by the subtractor is equal to a signal gain of the main amplifier; the subtractor circuit, with the distorted signal as a negative input, reversely amplifies the distorted signal and afterwards performs feedforward; and the adder circuit superimposes the distorted signal output by the main amplifier circuit and the reversely amplified distorted signal output by the subtractor, so as to output a distortion-free signal.

The application discloses a kind of secondary steam temperature process signal differential control method and system, utilize first subtracter to carry out subtraction operation to secondary steam temperature process signal and the second integrator output second integral signal, obtain feedback output signal;Utilize first integrator to integrate feedback output signal, obtain first integral signal;Utilize second integrator to integrate first integral signal, obtain second integral signal;Utilize first addition module to process first integral signal, obtain first superimposed signal;Second superimposed signal is obtained by using second addition module to process second integral signal;Utilize second subtracter to subtract first superimposed signal and second superimposed signal, obtain first subtraction signal, utilize fixed proportion controller to obtain fixed proportion control signal;Utilize third adder to superimpose secondary steam temperature process signal and fixed proportion control signal, obtain fixed proportion fastest tracking differential signal.The embodiment of the application provides a kind of secondary steam temperature process signal differential control method and system, improve the output tracking input differential tracking efficiency of secondary steam temperature process signal.

The invention discloses a lightweight embedded serial input conversion unit, which is used for designing an in-memory calculation circuit supporting lower-overhead floating-point number reference shift. The invention provides a lightweight input counter-pointing shift architecture, which comprises the following steps: firstly, calculating the exponent sum of a group of inputs and weights in parallel, finding out the maximum value, subtracting 1 from the maximum value per cycle, observing whether the maximum value is equal to other exponent sum values or not, and generating mantissa serial shift control signals of corresponding inputs, thereby realizing global counter-pointing shift. Compared with a traditional floating point alignment shifting scheme, the floating point alignment shifting method has the advantages that a barrel-shaped shifter, a subtracter and a parallel-to-serial circuit which are large in area are prevented from being used, and the floating point calculation function is achieved with smaller hardware expenditure.

The invention relates to a superspiral sliding mode active disturbance rejection control strategy based on a four-active bridge converter, and the method comprises the following steps: employing an extended state observer to estimate uncertain factors, unmodeled dynamics and coupling terms in a system, putting the disturbance estimation into superspiral sliding mode closed-loop control for elimination, and independent control of voltages of all ports is realized. After voltage and phase shift of each port of the four-active bridge converter are input into an extended state observer to estimate total disturbance of a system, given voltage is input into a differential tracker to eliminate influence of sudden change of the given voltage on a control effect, and obtained tracking voltage and observed voltage of the observer are input into a subtractor for subtraction; the method comprises the following steps of: inputting the obtained error quantity into a sliding mode controller, obtaining a phase shift ratio di through corresponding operation, giving phase shift ratios d2, d3 and d4 between primary and secondary side ports, generating corresponding PWM (Pulse-Width Modulation) signals, driving corresponding switching tubes to be switched on and switched off, and realizing independent voltage control and more efficient and reliable control operation of each port.

A calculator for calculating a plurality of square roots includes a memory array, at least two registers, a bit subtractor, and a controller. The memory array is organized into columns and rows. The registers store a fixed value. The controller, operatively coupled to the other components, allocates a first set of rows to test variables and a second set to result variables, and initially stores each of a plurality of radicands in a separate column. For multiple iterations, the controller concurrently activates selections of rows to form current operands and current guesses for each column. The controller then instructs the bit subtractor to perform subtraction operations. For each column with a positive subtraction result, the controller selectively writes a new bit of the square root and selectively overwrites values with a new remainder derived from the subtraction result, without performing an explicit data-shifting operation.

This invention discloses a differential control method and system for the main steam pressure process signal. The method involves acquiring the main steam pressure process signal of a thermal power unit, subtracting the main steam pressure process signal from a second integral signal output by a second integrator using a first subtractor to generate a feedback output signal, integrating the feedback output signal using the first integrator to obtain a first integral signal, integrating the first integral signal using a second integrator to obtain a second integral signal, processing the second integral signal using an adjustable proportional control module to obtain an adjustable proportional control signal, and processing the main steam pressure process signal and the adjustable proportional control signal using a second subtractor to obtain a cosine-type tracking differential signal. This invention improves the differential tracking efficiency of the main steam pressure process signal by subtracting the main steam pressure process signal from the corresponding adjustable proportional control signal.

The present application relates to a device and method for multiplying signals. A multiplication circuit (100) has a first time-coded modulator (103a) and a second time-coded modulator (103b), wherein the first time-coded modulator (103a) and the second time-coded modulator (103b) are configured to receive a first combined signal (S C1 ) and the second combined signal (S C2 ) and generate respective first PWM signals (S) each having a cycle frequency that substantially depends on the square of the value of the input combined signal PWM1 ) and the second PWM signal (S PWM2 ). The first combined signal (S C1 ) corresponds to the sum of the first input signal (S1) and the second input signal (S2), and the second combined signal (S C2 ) corresponds to the difference between the first input signal (S1) and the second input signal (S2). The first time decoding converter (104a) and the second time decoding converter (104b) receive the first PWM signal and the second PWM signal and provide a corresponding first count value (D1) and a second count value (D2) based on a parameter related to the frequency of the corresponding first PWM signal or the second PWM signal. The subtractor (105) determines the difference between the first count value (D1) and the second count value (D2) and provides an output signal (D1) based on the difference. OUT ).

The invention discloses an inverter output control system and control method based on a reconstruction controller, relates to the technical field of power electronics, and can measure a network access current and subtract the network access current from a reference current through a first subtractor to generate a current deviation signal; inputting the current deviation signal to a current loop proportional resonance controller, selecting a switching differential controller and a lead correction controller according to a system short circuit ratio, and generating a first control signal; inputting the network access current to an active damping module, generating a damping signal, superposing the damping signal with the first control signal, and inputting the superposed damping signal to a second subtractor; a common coupling point voltage is collected, a feed-forward signal is generated through a feed-forward module, and the feed-forward signal is superposed with an output signal of the second subtractor to generate a modulation signal; the modulation signal is converted into a driving signal through the pulse width modulation module, the inverter is controlled to output current, and the system stability and the harmonic suppression capability under the weak power grid are improved by dynamically adjusting a controller combination mode.

Fully homomorphic encryption integrated circuit (IC) chips, systems and associated methods are disclosed. In one embodiment, a method of operation for a number theoretic transform (NTT) butterfly circuit is disclosed. The (NTT) butterfly circuit includes a high input word path cross-coupled with a low word path. The high input word path includes a first adder / subtractor, and a first multiplier. The low input word path includes a second adder / subtractor, and a second multiplier. The method includes selectively bypassing the second adder / subtractor and the second multiplier, and reconfiguring the low and high input word paths into different logic processing units in response to different mode control signals.

A device, system and method for cancelling echo at electronic devices are provided. The device comprises: a send path comprising a send input and output; a receive path comprising a receive input and output; an echo estimator engine that determines an estimate of echo, on the send path; a subtractor engine subtracts the estimated echo from a send signal received at the send input; a delay buffer engine; and an adder. The delay buffer engine provides, to the adder engine, a delayed-attenuated portion of a receive signal, received at the receive input, delayed by a given delay period corresponding to at least a delay of the echo between the receive path and the send input. The adder engine adds the delayed-attenuated portion to the send signal. The echo estimator engine determines the estimated echo using at least the delayed-attenuated portion of the receive signal added to the send signal.

The present invention discloses a digital control system for a three-level DC converter. The digital control system includes a first subtractor, a second subtractor, a third subtractor, a fourth subtractor, a fifth subtractor, a sixth subtractor, a first adder, a first multiplier, a first PI controller, a second PI controller, a third PI controller, a fourth PI controller, a fifth PI controller, a sixth PI controller, a reverse given absolute value calculation module, a minimum value calculation module, a maximum value calculation module, a PWM generator, and a driver. The present invention implements bidirectional automatic switching control in any constant voltage, constant current, or constant power mode; utilizes the high-speed characteristics and parallel computing advantages of FPGAs to achieve rapid dynamic response; the switching time from positive 90% to negative 90% is shorter than that of conventional control methods, and the forward and reverse switching speeds are fast.

This invention claims protection for an adaptive background calibration system for pipelined ADCs, comprising: a sample-and-hold module, a first conversion unit, a second conversion unit, a low-speed, high-precision ADC, a pipelined ADC to be calibrated, an LMS adaptive filter, and a subtractor; capable of calibrating linear errors in the pipelined ADC caused by non-ideal factors such as capacitor mismatch, finite op-amp gain, and op-amp offset. By using a low-speed, high-precision ADC as a reference, connected in parallel with the pipelined ADC to be calibrated, and sending the difference between their digital outputs to a digital adaptive filter for processing, the output of the pipelined ADC continuously approximates the output of the low-speed, high-precision ADC, thereby achieving digital calibration. During this process, the normal conversion process remains unaffected and the conversion speed of the original ADC is not reduced, offering advantages such as high calibration accuracy, fast convergence speed, and strong tracking capability.

According to various embodiments, a security device is provided comprising a modular reducer configured to perform a modulo reduction by a modulus of each binary number of a sequence of binary numbers forming a data word, wherein each binary number consists of n bits by one or more first iterations comprising, in reaction to a first detector of the security device detecting that the most significant bit (MSB) of the binary number is set, changing the binary number by deleting its MSB and adding the difference between 2n−1 and the modulus to the binary number, followed by one or more second iterations comprising, in reaction to a second detector of the security device detecting that the MSB of the sum of the binary number with the difference between 2n−1 and the modulus is set, setting the binary number to that sum, wherein the MSB of the sum is deleted.

The present invention discloses a fractional all-digital phase-locked loop with adaptive adjustment of algorithm step size and loop bandwidth. The fractional all-digital phase-locked loop includes a frequency and phase detector, a time-to-digital converter, a first subtractor, a second subtractor, a first adder, a first register, a first multiplier, an adaptive step size / bandwidth control algorithm module, an LMS algorithm module, a digital loop filter, a numerically controlled oscillator, a multi-mode frequency divider, and a ΣΔ modulator. The present invention improves the existing circuit structure, and optimizes the performance and innovates the structure of the circuit modules. The adaptive step size / bandwidth control algorithm of the present invention simultaneously adjusts the convergence step size of the LMS algorithm and the bandwidth of the phase-locked loop according to the state of the phase-locked loop, thereby achieving the characteristics of short LMS algorithm convergence time, good fractional spurious performance, short phase-locked loop locking time, and good in-band phase noise of the phase-locked loop.

Provided in the embodiments of the present application are an operation component and method based on a Cordic algorithm. The component comprises: a first shifter, which is configured to shift an addition iteration result obtained in the previous iteration, so as to obtain first shift data; a second shifter, which is configured to shift a subtraction iteration result obtained in the previous iteration, so to obtain second shift data; an addition selector, which is configured to select, from the addition iteration result, the subtraction iteration result, the first shift data and the second shift data, two pieces of data as addition input data; a subtraction selector, which is configured to select, from the above four pieces of data, two pieces of data as subtraction input data; an adder, which is configured to obtain an addition iteration result on the basis of the addition input data; and a subtractor, which is configured to obtain a subtraction iteration result on the basis of the subtraction input data. The present application solves the problem in the related art whereby resource consumption is relatively large during angle rotation calculation, so that the effect of reducing the resource consumption of angle rotation calculation is achieved.

A feedforward amplifier circuit, an audio amplifier, and an audio playback device relate to the field of feedforward amplifier circuits. The amplifier circuit comprises: a main amplifier circuit, an adder circuit, an auxiliary amplifier circuit, and a subtractor circuit. The main amplifier circuit adds distortion to an input signal to output a distorted signal, and inputs the distorted signal into the adder circuit and the subtractor circuit for feedforward correction. The auxiliary amplifier circuit amplifies the input signal and uses it as the positive input of the subtractor, so that the signal gain output by the subtractor equals the signal gain of the main amplifier. The subtractor circuit uses the distorted signal as a negative input, reversely amplifies the distorted signal, and then performs feedforward. The adder circuit superimposes the distorted signal output by the main amplifier circuit with the reversely amplified distorted signal output by the subtractor, and outputs a distortion-free signal. By eliminating the reliance on the open-loop frequency-amplitude characteristics and feedback loop of the main amplifier, the circuit structure and component parameter selection are simplified, and costs are saved.

Aspects of the subject disclosure may include, for example, a digital timing skew compensator, including: a first polyphase adaptive filter bank having a first input and a first output; a first input matrix coupled to the first input of the first polyphase adaptive filter bank; a first subtractor coupled to the first output of the first polyphase adaptive filter bank, wherein the first subtractor removes a first signal generated by the first polyphase adaptive filter bank from digital outputs of sub analog-to-digital converters (ADCs) of a time-interleaved ADC to create a desired signal, wherein the desired signal is coupled to the first input matrix; a modulation matrix that modulates the digital outputs of the sub-ADCs to create a modulated signal vector; a second polyphase adaptive filter bank having a second input and a second output; a second input matrix coupled to the second input of the second polyphase adaptive filter bank; and a second subtractor coupled to the second output of the second polyphase adaptive filter bank, wherein the second subtractor removes a second signal generated by the second polyphase adaptive filter bank from the modulated signal vector to create an error signal, wherein the error signal is coupled to the second input matrix. Other embodiments are disclosed.

The application relates to a programmable frequency divider and a phase-locked loop, the programmable frequency divider comprising a plurality of cascaded subtractors, a period end detection module and a delay reset circuit, wherein the plurality of cascaded subtractors are connected to corresponding initial value signals, under the triggering of a clock signal to be divided, the signals output by the plurality of cascaded subtractors correspond to the output results of decrement, and under the condition that the signals output by the plurality of cascaded subtractors reach a period end condition, the period end detection module outputs a period end signal to the delay reset circuit based on the signals output by the plurality of cascaded subtractors and the period end condition. Under the condition that the delay reset circuit receives the period end signal, a reset trigger signal is output to each subtractor so as to reset each subtractor. After a preset delay time length of the delay reset circuit after the reset trigger signal, a work trigger signal is output to each subtractor so as to make each subtractor work and enter the next round of decrement cycle operation.

The application discloses a control circuit and a control method of a power factor correction circuit, and relates to the field of power converters.The control circuit comprises a current reference signal generating circuit, a current sampling circuit, a first subtractor, a first calculation unit, a current loop and a control signal generating circuit.The current reference signal generating circuit generates a current reference signal, the current sampling circuit outputs a current sampling signal, the first subtractor generates a first error signal according to the current sampling signal and the current reference signal, the first calculation unit generates a first parameter and a second parameter according to the current reference signal, the current loop generates a current loop control signal according to the first error signal, the first parameter and the second parameter, and the control signal generating circuit generates a driving control signal according to the current loop control signal.The gradual control of the first parameter and the second parameter of the control circuit can overcome the contradiction between ITHD and input current peak oscillation, improve ITHD and avoid the problem of peak oscillation.