172 results about "Arithmetic circuits" patented technology

The invention discloses a large model generation content traceability technology based on model copyright ID watermark embedding, which comprises the following steps that: firstly, a large model content generator compiles a dynamic watermark embedding process into an arithmetic circuit, and generates a watermark text and a proof by using a zero-knowledge proof algorithm; then the large model content generator publishes the text with the watermark and the proof together, and hides the copyright ID and the secret key; a large model content user verifies the proof and the watermarked text through a smart contract by adopting a zero-knowledge verification algorithm; after verification is passed, an adversarial sample corresponding to the text with the watermark is generated, an adversarial training method is used for optimizing the text with the watermark, and parameters of the Viterbi balance algorithm are dynamically adjusted and improved. According to the method, the concealment and the generation quality are balanced, high-capacity watermark embedding is realized, the tamper resistance and the accurate traceability of multi-model copyright disputes are improved, and the privacy protection intensity is improved.

Systems and methods for performing hardware approximation of functions are provided. In one example, a system comprises a controller, a plurality of multiplexors, configurable arithmetic circuits, and a mapping table that stores a set of function parameters. According to a mode of operations, the controller may configure the plurality of multiplexors to forward the set of function parameters or a subset of the function parameters to the arithmetic circuits to compute an approximation result. In a case where the subset of the function parameters is forwarded to the arithmetic circuits, the controller may configure the arithmetic circuits to perform post-processing, such as quantization, of the approximation result.

The invention relates to the technical field of medical marketing data sharing, in particular to a medical marketing data sharing method and system based on a block chain, and the method comprises the steps: compiling a plaintext description of a medical marketing business rule into an arithmetic circuit with a multi-port structure, generating a verification key, and deploying the verification key in a block chain smart contract in the block chain; the verification node initiates a verification request containing a data type, a service rule identifier and a time period identifier; the medicine enterprise node and the medical institution node respectively load the local privacy data to the input port and generate a corresponding first zero-knowledge proof and a corresponding second zero-knowledge proof; and the verification smart contract loads a verification key according to the time period identifier to carry out cooperative verification on the two zero-knowledge certificates and generates a conclusion for uplink storage. According to the method, cross-subject association verification is realized on the premise of not converging original data, and the accuracy and auditing performance of compliance judgment are improved through a time period self-adaptive threshold value.

Provided are a manufacturing planning system, a manufacturing planning method, and a program that make it possible to improve production efficiency and reduce the load of off-line setup. A manufacturing planning system (1) is for determining a manufacturing plan for producing a plurality of types of products by one or more production lines, and comprises an arithmetic circuit (15) capable of accessing changeover time data (D1) indicating a changeover time for one or more production lines due to a changeover between a plurality of types of products, and workload data (D2) indicating a workload of off-line setup due to a changeover. The arithmetic circuit (15) outputs a manufacturing plan (D5) for optimizing the sum of changeover times and the sum of workloads, on the basis of the changeover time data (D1) and the workload data (D2), in response to an input of production requirement data (D4) including target quantities of a plurality of types of products.

To provide a controller in which total harmonic distortion (THD) can be improved.SOLUTION: A controller (700) includes: a first external terminal receiving a first voltage (Vmult) with a full-wave rectified waveform; a second external terminal receiving a first detection voltage (Vis), as a negative voltage, generated by a current flowing through a sense resistor (Ris) connected to a ground potential application terminal; an error amplifier circuit (710) generating a second voltage (V2) by amplifying an error between a second detection voltage (Vs) corresponding to an output voltage (Vdc) and a reference voltage (Vref1); an arithmetic circuit (733) generating a third voltage (V4) by multiplying the first and second voltages; an inverting amplifier (734) generating a fourth voltage (V5) by inverting and amplifying the first detection voltage; and a comparator (735) comparing the third voltage and the fourth voltage.SELECTED DRAWING: Figure 11

An example apparatus includes a hardware platform having arithmetic circuits and a memory, the memory configured to store, at a first precision, first compressed parameters of a machine learning (ML) model; a network interface controller; and a controller, supported by the hardware platform, configured to: decompress, from the memory through an increase in precision to a second precision, the first compressed parameters to obtain decompressed parameters; control the arithmetic circuits to train, using arithmetic operations, the ML model and update the decompressed parameters; compress, using quantization and reduction in precision to the first precision, the decompressed parameters as updated to obtain second compressed parameters; send, using the network interface controller, the second compressed parameters over a network to a server; and update the first compressed parameters in the memory in response to data received, through the network interface controller, from the server over the network.

The present invention relates to a method for homomorphically encrypting general plaintext spaces with controlled noise growth, comprising: a general plaintext space by selecting a polynomial of degree greater than 1, and defining the plaintext space as formula (I), where f(x) and t(x) are polynomials; applying an encoding method on a message and producing a corresponding element in the plaintext space Rt; applying a homomorphic encryption method that takes the encoded message as input and returns a ciphertext that encrypts the message; providing a decryption method that takes the ciphertext as input and returns the decoded plaintext; applying a method to homomorphically process encrypted messages by evaluating an arithmetic circuit representing the function to be evaluated, wherein the noise growth during homomorphic operations is determined by the size of; and applying a method to refresh ciphertexts via bootstrapping, which consists of homomorphically processing the decryption circuit.

A multiply-accumulate unit comprises a first input configured to receive a first operand encoded using a two-bit encoding scheme in which a ternary value is represented by two bits, wherein identical bits indicate a non-computable value and different bits indicate a computable value. The unit further comprises a second input for receiving a second operand, a zero detection circuit with a logic gate that compares the two bits and generates a skip signal when they are identical, an arithmetic circuit for performing accumulation based on both operands, an accumulator register for storing the result, and a gating circuit that selectively enables writing to the accumulator register based on the skip signal, preventing writing when the first operand is non-computable.

Provided are an image processing device, a display device, and a control method whereby the luminance of an overlapping region in a projection image can be suppressed from decreasing non-linearly according to the position in the overlapping region by edge blending. This image processing device comprises an arithmetic circuit and a storage device, and transmits an output video signal to a display device. The arithmetic circuit performs gamma correction on a received input video signal using a first gamma characteristic and a second gamma characteristic, performs edge blending for adjusting the luminance of a predetermined region in an image according to the position in the predetermined region using the second gamma characteristic, and generates an output video signal. The second gamma characteristic is the inverse function of a third gamma characteristic of the display device. The third gamma characteristic has a gamma curve expressed by an exponential function. The predetermined region is a region in which the image displayed by the display device and another image displayed by another display device overlap.

A processing unit includes a redundant remainder generation circuit that converts first operand data and second operand data into a plurality of first operand redundant remainder sets and a plurality of second operand redundant remainder sets based on a redundant remainder system (RRNS) using first to Tth moduli. T is a natural number equal to or greater than 4. The processing unit includes a plurality of arithmetic circuits that perform operations using the plurality of first operand redundant remainder sets and the plurality of second operand redundant remainder sets, and a reconstruction circuit that restores the RRNS-based result data to the weighted coefficient-based result data. An in-memory processing (PIM) apparatus and an in-memory processing (PIM) system are also provided.

A neural processing unit for performing inference operations of a large-scale language model based on an artificial neural network is disclosed. The neural processing unit according to the present disclosure includes a processing element core configured to perform an attention mechanism-based operation based on input data in vector format to output an operation result, a special function unit comprising a plurality of arithmetic circuits including at least one vector-dedicated arithmetic circuit that exclusively performs vector operations and at least one mixed arithmetic circuit capable of performing both vector and scalar operations, and configured to perform a special function operation on the operation result, and a controller configured to, upon receiving an RMS normalization operation execution command, activate at least one of the plurality of arithmetic circuits to control the special function unit to perform an operation of converting at least one of the operation result or the input data into a normalized vector whose magnitude is adjusted based on a root mean square (RMS), wherein the operation result may include an attention score for the input data.

A neural network device, a computing system, and a method of processing a feature map are provided. The neural network device includes at least one processor configured to implement: an arithmetic circuit configured to generate third data including a plurality of pixels based on a neural network performing an arithmetic operation on first data and second data; and a compressor configured to generate compressed data by compressing the third data, wherein the compressor is further configured to generate bitmap data as the compressed data based on a quadtree structure, the bitmap data including position information of non-zero pixels having non-zero data values among the plurality of pixels.

An in-memory computing (IMC) accelerator using a high-density operation circuit and a low-power sense amplifier as a peripheral circuit includes a plurality of dynamic random-access memory (DRAM) banks each including a pair of cell arrays, a data supply logic, a memory, and a controller for IMC, a global SRAM, and a top-level controller, wherein the cell array includes a plurality of subarrays, each of the subarrays includes a DRAM array including a big array and a little array, and an arithmetic circuit configured to perform an operation, and the arithmetic circuit includes a sense amplifier configured to amplify a bit line voltage difference, and a compact multiply-accumulate (MAC)-single instruction multiple data (SIMD) unit (CMSU) for an MAC operation and an SIMD operation, so that functionality of an in-memory operation is diversified.

The invention belongs to the technical field of information security, relates to zero-knowledge proof and block chain technologies, and particularly provides a public verifiable data service method for an instrument control system, so as to solve the technical problem of huge calculation overhead caused by the fact that commitment consistency check of large-scale data needs to be executed in a circuit in an existing zk-SNARK-based scheme. According to the invention, a hybrid proving system based on a cryptographic protocol Plonk and Groth16 is designed, the promise adaptive to the system is designed, and the consistency check of the promise of the database is transferred from the inside of an arithmetic circuit to the outside of the circuit, so that the huge calculation overhead introduced into a zk-SNARK circuit by the promise consistency check of a large-scale database is avoided; and finally, the verifiable execution of safe calling and operation on the data subset from the third-party cloud storage is realized, the accuracy and integrity of industrial data are ensured, and the problem of trust missing in a cross-domain scene is solved.

The invention relates to a method for applying zero-knowledge proof to block chain agriculture, and relates to the technical field of block chain agriculture, a low-power-consumption edge computing gateway is deployed to collect farmland environment and farming data, and growth stages such as a seedling stage and a vegetative growth stage are dynamically divided based on a crop growth date (GDD) model; business rules of all stages are compiled into an arithmetic circuit, and a lightweight zero-knowledge proof is generated in a trusted execution environment (TEE) by taking sensitive data as private input; after validity is verified and proved through the block chain smart contract, a content identifier (CID) is associated with a certificate and written into the chain; a consumer can inquire a series of verification results of the whole growth cycle through the agricultural product traceability code. According to the scheme, agricultural production data can be verified and invisible, triple contradictions of weak privacy protection, dynamic adaptation deficiency and field deployment obstacle in a traditional agricultural block chain are solved in a breakthrough mode, safe and efficient credible traceability infrastructure is provided for high-value agricultural products such as organic authentication, and the risk of commercial secret leakage is reduced through actual measurement.

A system and method are provided for converting high-level source code into arithmetic circuitry representing functions expressed in the source code. The invention includes a translation / interpretation component for performing the conversion. In a preferred embodiment, the source code is a smart contract, such as a contract used in connection with a blockchain platform. A method according to an embodiment includes the steps of processing a portion of a high-level source code (e.g., a smart contract) to generate an arithmetic circuit. The arithmetic circuit includes one or more arithmetic gates arranged to represent at least some of the functions expressed in the source code. The processing involves evaluating one or more constants provided in the source code to generate one or more expressions containing Boolean and / or arithmetic operators. The arithmetic circuit includes an n-bit line connected to the arithmetic gate; it may be used to provide hardware and / or software circuitry. The arithmetic circuitry may be used to generate quadratic plans that may be executed on the processor.

Integrated circuit devices and circuitry for digital filtering are provided. An integrated circuit device may include a first digital signal processing (DSP) block with first hardened arithmetic circuitry and an output register to store an output of the first DSP block and a second DSP block with second hardened arithmetic circuitry and an input register to receive the output of the first DSP block. An input signal chain may include a first set of registers to provide first input data signals to the first DSP block, a second set of registers to provide second input data signals to the second DSP block, and a third set of registers connected between the first set of registers and the second set of registers to provide delay equal to that of the output register of the first DSP block and the input register of the second DSP block.

Method and device for generating a Gaussian error. This description relates to a device configured to generate an approximate value by adding noise to an output of a balanced arithmetic circuit, comprising: - the balanced arithmetic circuit configured to generate a first value; - an approximation circuit configured to generate a k-bit mask based on a first distribution; and - a logic circuit configured to generate a second value based on the first value, the k least significant bits of the second value being generated by applying the mask to the k least significant bits of the first value, the most significant bits of the second values ​​being equal to the most significant bits of the first value, the first distribution being such that the second value corresponds to the first value with an added error value having a Gaussian distribution of standard deviation.Figure for the abridged version: Fig. 1.

Electronic control device, comprising: a logic circuit (255) capable of reconfiguring a plurality of arithmetic circuits, including a first circuit and a second circuit; a reconfiguration controller (204) that reconfigures the arithmetic circuits based on reconfiguration commands and verifies the reconfigured arithmetic circuits; and a process controller (202) that sends the reconfiguration commands to the reconfiguration controller (204) and commands the arithmetic circuits to perform operations, wherein the reconfiguration controller (204) reconfigures and verifies the first circuit when a first reconfiguration command is received, The process controller (202) of the first circuit commands to perform an operation when the verification of the first circuit by the reconfiguration controller (204) is complete. After the first circuit has been reconfigured, the process controller (202) sends a second reconfiguration command to the reconfiguration controller (204) and orders the reconfiguration controller (204) to start the reconfiguration of the second circuit until the first circuit has completed its operation.

A homomorphic encryption apparatus and a ciphertext arithmetic method thereof are disclosed. The homomorphic encryption apparatus includes a re-encryption parameter generation circuit, a re-encryption circuit, and an arithmetic circuit. The re-encryption parameter generation circuit is configured to generate re-encryption parameters including a plurality of re-encryption levels for a plurality of ciphertexts, respectively, based on an arithmetic scenario including information on an arithmetic schedule between the plurality of ciphertexts. The re-encryption circuit is configured to generate a plurality of re-encrypted ciphertexts by re-encrypting each of the plurality of ciphertexts to a corresponding re-encryption level based on the re-encryption parameters. The arithmetic circuit is configured to output an arithmetic result by performing an operation using the plurality of re-encrypted ciphertexts according to the arithmetic scenario.

Provided are a video data processing system, a video data processing method, and a program that make it possible to improve the efficiency of analysis of video data. This video data processing system comprises a computation circuit (45) that is capable of accessing one or more pieces of video data (D1) in which are shown one or more tasks that one or more objects are involved in. The computation circuit (45) is configured so as to: detect the state of one or more objects in first video data (D4) which is a portion of the one or more pieces of video data (D1); determine second video data (D5) which is another portion of the one or more pieces of video data (D1) on the basis of the state of the one or more objects in the first video data (D4); output a display screen that includes a reproduction window in which the first video data (D4) is reproduced and a button for reproducing the second video data (D5); and reproduce the second video data (D5) in response to the button being selected.

A region extraction method of the present disclosure is executed by an information processing device including an arithmetic circuit to extract a desired region corresponding a moving object from three-dimensional point cloud information. The method includes: by the arithmetic circuit, receiving three-dimensional point cloud information acquired by a three-dimensional point cloud acquisition device; receiving reference information that includes at least a part of a range of the three-dimensional point cloud information and is acquired under a condition different from the acquisition of the three-dimensional point cloud information; and comparing the three-dimensional point cloud information with the reference information, detecting the moving object, and extracting a region of the moving object from the three-dimensional point cloud information.

Provided is a control input generation device for generating a control input for controlling a pneumatic actuator with high precision. A device for generating a control input for controlling a pneumatic actuator is provided with: a first control input generation function for generating a first control input when there is a deviation of a control amount from a target value; a second control input generation function that generates, when there is a temporal change in the control amount, a second control input in which the deviation of the control amount from the target value becomes larger as the deviation becomes smaller; and an output generation function that generates the control input based on the first control input and the second control input. When the generated control input is used for controlling the pneumatic actuator, the responsiveness of the pneumatic actuator near the target value can be improved, and overshoot with respect to the target value can be suppressed, so that the accuracy of operating the pneumatic actuator to the target value can be improved. In addition, overshoot with respect to the target value can be prevented.

A battery module failure is reliably determined. A power supply device is provided with: a plurality of battery modules (2) including a failure determination section (21) that determines failure and normality and outputs failure and normality using signals of "high" and "low"; a failure transmission line (3) connected to the failure determination section (21) of each battery module (2); and a module failure determination circuit (1) connected to the failure transmission line (3) and determining failure and normality of the battery modules (2). The module failure determination circuit (1) is provided with: a voltage determination circuit (4) that determines "high" and "low" of the failure transmission line (3); an impedance detection circuit (5) that detects impedance with respect to a ground line (23); and an arithmetic circuit (6) that determines failure and normality of the battery modules (2) and abnormality of the failure transmission line (3) based on outputs of the voltage determination circuit (4) and the impedance detection circuit (5).

Methods and systems, including computational instructions / programs encoded on computer-readable media, are described for exploiting input and output sparsity for in-memory machine-learning computations. A Processing-in-Memory ("PiM") architecture for an integrated memory device includes compute units, a shared queue coupled to each compute unit, reduction circuitry, and a shared datapath. The queue stores (i) inputs that are routed along the shared datapath for processing by the compute units and (ii) outputs that are generated after the compute units process the inputs. Each compute unit includes arithmetic circuitry for computing accumulated values from the inputs. The reduction circuitry generates the outputs based on reduction operations performed on accumulated values received from the compute units. The outputs are routed to the queue for storage using a portion of the shared datapath that couples the reduction circuitry to the shared queue.

To provide a semiconductor device that can perform multiply-accumulate operations with low power consumption. [Solution] An arithmetic circuit having circuits MC and MCr, wherein circuit MC has a holding node nd1, and circuit MCr has a holding node nd1r. Circuits MC and MCr are electrically connected to input wirings X1L and X2L and wirings OL and OLB, respectively, and each of circuits MC and MCr holds first and second potentials corresponding to first data in its respective holding node. When a potential corresponding to second data is input to input wirings X1L and X2L, circuit MC outputs a current to one of wirings OL or OLB, and circuit MCr outputs a current to the other of wirings OL or OLB. The current that circuits MC and MCr output to wirings OL or OLB is determined according to the first and second potentials held in the holding nodes nd1 and nd1r.

Techniques described herein may be utilised to implement methods and systems for lossless compression and serialisation of arithmetic circuits to a bit stream using compression techniques such as the arithmetic coding. An arithmetic circuit representing a smart contract may be compressed using arithmetic coding, thereby generating a compressed arithmetic circuit that can be stored or broadcast to a blockchain network using less computational resources (e.g., data storage resources) than would otherwise be needed to store the arithmetic circuit. The arithmetic circuit can be efficiently compressed using entropy coding based on the frequency of elements in the data structure, such as the arithmetic operator types. Instructions for de-serialisation and de-compression can also be embedded in the bit stream, and can be used (e.g., by another computer system) to reconstruct the original circuit in a lossless manner.

A hardware-anchored Liquidity Containment and Capital Reserve Enforcement Engine executes real-time reserve validation, liquidity sufficiency computation, and deterministic settlement gating entirely within trusted execution environments (TEEs) comprising Intel SGX enclaves, AMD SEV-SNP protected VMs, or ARM TrustZone secure worlds, materially altering processor states to isolate all reserve computation. Liquidity Integrity Vectors are computed using the reserve adequacy function h(alpha, beta, gamma) from hardware-attested inputs anchored to TEE-resident hardware mechanisms comprising enclave-sealed monitoring registers, memory encryption engine integrity states, or attestation-based recalibration triggers. A Liquidity Containment Gate enforces a non-bypassable hardware execution barrier requiring all LIV computation, Capital Reserve Monitor validation, and ZKP proof generation to complete within a single attested TEE execution instance before settlement authorization is released. A ZKP Verification Engine generates Groth16 arithmetic-circuit proofs of approximately 192 bytes verifiable in under 10 milliseconds, enabling External Counterparty verification of reserve sufficiency without disclosure of proprietary balance sheet data. A Provenance Ledger stores append-only cryptographic hash chains with each entry bound to a TEE attestation report. A Settlement Attestation Binder cryptographically binds settlement authorizations to specific TEE attestation report identifiers, enabling independent verification of both settlement outcomes and the hardware environments that authorized them.

A designation method makes adjustment of a display system that combines images displayed by a plurality of display devices into one image easy. The designation method uses a sampling region in adjustment of display of images by a plurality of display devices when the plurality of display devices display one image content in an adjustment device. The adjustment device has an arithmetic circuit, and can access a storage device and a display. The adjustment device causes the plurality of display devices to display an adjustment image that is stored in the storage device in advance by the arithmetic circuit, acquires a captured image obtained by capturing the adjustment image displayed by the plurality of display devices from a capturing device, causes the display to display the acquired captured image, presents a candidate of the sampling region to a user superimposed on the captured image displayed in the display, and accepts designation of the sampling region determined based on the candidate of the sampling region according to an operation from the user via an input device.

A service privacy data verification method and apparatus, and a device and a storage medium. The method comprises: acquiring initial public parameters generated by a blockchain system (S110); on the basis of service privacy data to be verified, generating a data relationship equation to be verified (S120); on the basis of said data relationship equation, generating an equivalent arithmetic circuit and a multi-party data joint vector set (S130); generating a first privacy data commitment value on the basis of a verification demander's own service privacy data, acquiring a second privacy data commitment value generated by a verification participant on the basis of associated service privacy data, and generating a target privacy data commitment value (S140); on the basis of the verification demander's own service privacy data, the initial public parameters, arithmetic circuit parameters of the equivalent arithmetic circuit, and the multi-party data joint vector set, in combination with the associated service privacy data, determining a proof field value (S150); on the basis of the proof field value, generating transaction proof data (S160); and uploading the transaction proof data and the target privacy data commitment value to a blockchain, such that on-chain nodes verify the service privacy data to be verified (S170).