606 results about "Arithmetic circuits" patented technology

The arithmetic processing apparatus of the present invention is an arithmetic processing apparatus that can be reconfigured in accordance with a processing mode and has a plurality of arranged unit arithmetic circuits. Each unit arithmetic circuit includes at least one input terminal, at least one output terminal, a first register which holds data, an adder which calculates a sum of two pieces of data, a second register which holds data, a bit shifter which shifts data left or right, a subtractor which calculates a difference between two pieces of data, an absolute value calculating unit which calculates an absolute value of data, and a path setting unit which sets a path according to the processing mode connecting among these circuit elements.

An arithmetic apparatus for performing a long product-sum operation includes an integer unit arithmetic circuit, a finite field GF(2^m) based unit arithmetic circuit logically adjacent to the integer unit arithmetic circuit, a selector for selecting the integer unit arithmetic circuit or the finite field GF(2^m) based unit arithmetic circuit, and an adder circuit which has a buffer for storing interim result data, adds the interim result data to the result data obtained by one of the integer unit arithmetic circuit and the finite field GF(2^m) based unit arithmetic circuit which is selected by the selector, propagates a carry in an integer unit arithmetic operation, and propagates no carry in a finite field GF(2^m) based unit arithmetic operation.

The present invention provides a scattered pilot (SP) location detector capable of detecting patterns of SP symbols promptly without using a TMCC signal. The SP location detector comprises a multiplier which multiplies received signals generated by demodulating OFDM modulation signals in which pilot symbols are dispersively disposed in accordance with four types of patterns and which are transmitted periodically, by a pseudo-random number bit sequence, four arithmetic circuits which are respectively provided corresponding to the four types of patterns and which respectively extract pilot symbols corresponding to respective patterns from results of multiplication by the multiplier and calculate sums of phase differences between the extracted pilot symbols, followed by outputting absolute values thereof, and a pattern detection circuit which detects the corresponding arithmetic circuit maximum in the calculated absolute value from within the four arithmetic circuits.

A display device which incorporates a touch panel function therein can reduce the number of elements which constitute a photo sensor circuit and can accurately detect an input coordinate position without requiring a particular coordinate arithmetic circuit. In a display device which includes: a display part on which a plurality of pixels are arranged in a matrix array; and a plurality of photo detection circuits which are arranged in a matrix array in the inside of the display part, each photo detection circuit of the plurality of photo detection circuits includes: a photo sensor which converts an incident light into a optical current corresponding to intensity of the incident light; an integral capacitance which integrates the optical current converted by the photo sensor; and a comparator to which a voltage of the integral capacitance is inputted; and the comparator includes a transistor of an open drain output type with a grounded source.

To eliminate an amplitude difference between luminance signals from pixels included in horizontal lines of color filters, caused by a sensitivity difference from one photosensor to another in a CCD, and reduce a horizontal stripe-like noise appearing in a monitoring image and captured image, there is provided an arithmetic circuit to calculate an amplitude difference in Gr and Gb signals based on an output from a four-channel detector to set gains multiplied by compensation factors, respectively, with which the white balance-processed Gr and Gb signals are equal in amplitude to each other, thereby controlling the gain of a while balance amplifier.

An arithmetic circuit having a high versatility, with which such a circuit as a compact and high-speed logic-in-memory is obtained and various operations is performed, is provided. The arithmetic circuit includes a memory element having a variable resistance element R in which the state of resistance changes reversibly between the state of high resistance and the state of low resistance by applying voltages with different polarities between one electrode and the other electrode, and at least one transistor of MRD, MRS, MW1 and MW2 connected respectively to both ends of the memory element; wherein data is stored in the memory element, the operation for the external data X, W, Y1 and Y2 input through any of the transistors is performed by applying potential to each of the ends of the memory element through the transistors MRD, MRS, MW1, and MW2, and a result of the operation is output from the memory element.

A non-volatile memory device includes a memory cell array including memory cells, each having a resistance value reversibly transitioning among resistance value ranges in a variable state in accordance with application of different electrical signals, a control circuit that, in operation, receives a control signal, a read circuit that, in operation, obtains pieces of resistance value information each relating to the resistance value of one of the memory cells in accordance with the control signal, and an arithmetic circuit that, in operation, calculates a binary reference value based on at least a part of the pieces of resistance value information. In operation, the read circuit selectively assigns, based on the binary reference value, one of two values to each of the pieces of resistance value information.

A power amplifying apparatus which is of a switching type and capable of efficiently amplifying a power of an input AC signal such as an acoustic signal, includes a first switch circuit (11) and a second switch circuit (12) to which a power supply voltage Vc is applied, an inductor (13) and a load (14) which are connected between the switch circuits, and a control circuit (15) which receives an input AC signal Vi, sets a predetermined ratio of ON/OFF periods, and drives the switch circuits. The control circuit (15) includes an arithmetic circuit (20) which multiplies a modulation sensitivity (for example, an amplitude of a triangular wave voltage used for generation of a pulse signal for driving a switch circuit) by a ratio (Vc/Ec) of the power supply voltage Vc and a DC component Ec thereof. This configuration can compensate for distortion caused by a ripple variation of the power supply voltage due to regenerated power or the like, and enable a gain control by the power supply voltage.

In a semiconductor device having a large-scale arithmetic circuit, when there is delay in clock signals, a malfunction occurs in a circuit. In particular, in an environment where supply voltage varies as in a wireless chip, it is very difficult to precisely estimate delays in clock signals in designing. Further, in order to keep supply voltage stable, a large-scale power supply circuit is required, which increases the area of a chip, and the cost thereof. A semiconductor device provided with a power control circuit and a clock generation circuit is used to detect variation in supply voltage using the power control circuit and changing frequency and duty ratio of a clock circuit using the clock generation circuit, thereby operating an arithmetic circuit stably. A high performance semiconductor device provided with such a large-scale arithmetic circuit can be provided at low cost.

A focus detection apparatus includes an image sensor including pixels for focus detection for receiving a pair of respective light beams transmitted through different pupil areas of a photographing lens to output a pair of signals; an acquisition unit for acquiring exit window information on the photographing lens; an arithmetic circuit for calculating a tilt for detection area in the detecting position, depending on an image height for a detecting position in which a focus state is detected and on the exit window information; and a calculation unit for calculating the shape of the detection area depending on the calculated tilt, in which the defocus amount is detected on the basis of a phase difference between the pair of signals obtained from pixels for focus detection included in the calculated detection area.

A power supply circuit drives circuits having different numbers of series-connected LEDs without changing a circuit constant or a component. An LED series circuit is connected to a power converter circuit of a power supply circuit. The power converter circuit is controlled by a control arithmetic circuit, and supplies a constant current to the LED series circuit. A voltage detection circuit detects a voltage applied to the LED series circuit. The control arithmetic circuit checks whether the LED series circuit has 40 LEDs or 20 LEDs, based on the voltage detected by the voltage detection circuit. The control arithmetic circuit holds a constant-current value table for 40 LEDs and a constant-current value table for 20 LEDs. In accordance with the detected voltage, the control arithmetic circuit selects one constant-current value table, and controls the power converter circuit based on the constant-current value table selected.

The integrated circuit device includes a CPU having an arithmetic circuit and a PMU implementing power control of the CPU through a power IC. The PMU has no arithmetic circuit. The PMU includes RAM storing a plurality of commands and a control section implementing power control of the CPU according to the commands stored in the RAM.

An arithmetic circuit, which is retained by each pixel in a conventional image sensor, is shared by each column. Signal processing circuits of different configurations are provided on signal transmission paths in an upward direction and a downward direction of a vertical signal line for extracting an image signal from each pixel, whereby image output processing and arithmetic processing are performed completely separately by the different circuit blocks. Thus, image quality of an actual image is improved and optimum design for arithmetic processing is made possible. Specifically, an I-V converter circuit unit, a CDS circuit unit and the like are provided on the image output side. A current mirror circuit unit, an analog memory array unit, a comparator unit, a bias circuit unit, a data latch unit, an output data bus unit and the like are provided on the arithmetic processing side.

A signal current corresponding to an incident light intensity is output from a photodiode PD, the signal current is converted into a signal voltage by an integration circuit 10, and the amount of a change in signal voltage in a predetermined time is output from a CDS circuit 20. The difference between two voltage values output from the CDS circuit 20 is obtained by a difference arithmetic circuit 30 and held by a S-H circuit 40. In addition, the maximum value of voltage values obtained by the difference arithmetic circuits 30 of respective units 100_n is obtained by comparison circuits 50 of the respective units 100_n, a reference signal voltage generation circuit 500, a final coincidence determination circuit 200, and a reference voltage hold circuit 300, and on the basis of the maximum value, the A/D conversion range of an A/D conversion circuit 400 is set.

A non-volatile memory device includes a memory cell array including memory cells, each having a resistance value reversibly transitioning among resistance value ranges, a read circuit that, in operation, obtains pieces of resistance value information each relating to the resistance value of one of the memory cells, an arithmetic circuit that, in operation, calculates a binary reference value based on at least a part of the pieces of resistance value information, and a write circuit. In operation, the read circuit selectively assigns, based on the binary reference value, one of two values to each of the pieces of resistance value information. In operation, the write circuit performs a first write operation on a memory cell corresponding to one of the two values among the memory cells.

The present invention relates to a method for detecting a rotation speed and a rotation direction of a rotating apparatus with the digital detection of a single sensor. In the method, a turnable which is connected with a rotation axis with a same axial center is provided on the rotating apparatus. Different directions of the circumference of the turnable are provided with a plurality of inducing pieces of a same sensor. The position angles formed by adjacent inducing pieces are not equal. The inducing pieces are arranged in the sequence of the magnitude of the position angle. When the turnable rotates, a sensor detects the pulse output generated by the inducing pieces. The pulse signal is obtained through a shaping circuit and is outputted to an arithmetic circuit and is connected to a display circuit. A time period S for rotating the turnable for a circle is the summation of a plurality of adjacent pulse interval lengths of a plurality of inducing piece compositions. The rotation speed of the turnable is digitally displayed. The arrival sequence of spacing interval of random adjacent pulse is obtained for determining that the rotation direction of the turnable is clockwise direction or counter-clockwise direction. The invention requires only one sensor for completing the digital detection to the rotation speed and rotation direction of the rotating apparatus. The installation position of the inducing piece of the sensor has no high requirement and the structure is simple. The cost for digital detection and the cost for installing the sensor are reduced.

To make it difficult to obtain a secret key from a power change or EM emission intercepted when an IC card encounters a power analysis attack or an electromagnetic wave analysis attack. An arithmetic circuit and a circuit for transmitting/receiving a signal to/from outside are included. The arithmetic circuit includes a central processing unit, an auxiliary arithmetic unit, a random number generator, and a read only memory. The read only memory stores a program for processing of blocking a side-channel attack in signal transmission/reception to/from outside. By additionally providing the random number generator and the auxiliary arithmetic unit, time change of physical data which leaks from an IC chip can be made more complex. This operation is executed by the program. Therefore, it takes time to obtain inside data from physical data intercepted by the third party, thereby security can be improved.

A memory circuit includes a transistor having a channel in an oxide semiconductor layer, a capacitor, a first arithmetic circuit, a second arithmetic circuit, a third arithmetic circuit, and a switch. An output terminal of the first arithmetic circuit is electrically connected to an input terminal of the second arithmetic circuit. The input terminal of the second arithmetic circuit is electrically connected to an output terminal of the third arithmetic circuit via the switch. An output terminal of the second arithmetic circuit is electrically connected to an input terminal of the first arithmetic circuit. An input terminal of the first arithmetic circuit is electrically connected to one of a source and a drain of the transistor. The other of the source and the drain of the transistor is electrically connected to one of a pair of electrodes of the capacitor and to an input terminal of the third arithmetic circuit.

A compact BCH parallel decoding circuit which supports preview search works on a finite field GF(2<13>). The parallel decoding circuit comprises a syndrome arithmetic circuit(1), a realizing circuit(2)with multiple shoots in one round for IBM wrong position multinomial iterative computation in the finite field GF(2<13>), a wrong address search circuit(3) provided with a totally combined logic pre-search module and a multifunctional configurable data interface(27)of an encoder. Compared with prior art, the decoding circuit has the advantages that the hardware is of low degree of complexity, the circuit area is compact and the decoding circuit is low in cost; data throughput is high and wrong address research is quick; the interface is simple in design and is practical and multi-functional; correcting performance can be flexibly configured according to the length of the check element and is free from the change of the code length.

A biological information detection device includes a light source, an image capturing device, and one or more arithmetic circuits. The light source projects dots formed by light onto a target including a living body. The image capturing device includes photodetector cells and generates an image signal representing an image of the target onto which the dots are projected. The one or more arithmetic circuits detect a portion corresponding to at least a part of the living body in the image by using the image signal and calculate biological information of the living body by using image signal of the portion.