379 results about "Arithmetic circuits" patented technology

The invention discloses a large model generation content traceability technology based on model copyright ID watermark embedding, which comprises the following steps that: firstly, a large model content generator compiles a dynamic watermark embedding process into an arithmetic circuit, and generates a watermark text and a proof by using a zero-knowledge proof algorithm; then the large model content generator publishes the text with the watermark and the proof together, and hides the copyright ID and the secret key; a large model content user verifies the proof and the watermarked text through a smart contract by adopting a zero-knowledge verification algorithm; after verification is passed, an adversarial sample corresponding to the text with the watermark is generated, an adversarial training method is used for optimizing the text with the watermark, and parameters of the Viterbi balance algorithm are dynamically adjusted and improved. According to the method, the concealment and the generation quality are balanced, high-capacity watermark embedding is realized, the tamper resistance and the accurate traceability of multi-model copyright disputes are improved, and the privacy protection intensity is improved.

Systems and methods for performing hardware approximation of functions are provided. In one example, a system comprises a controller, a plurality of multiplexors, configurable arithmetic circuits, and a mapping table that stores a set of function parameters. According to a mode of operations, the controller may configure the plurality of multiplexors to forward the set of function parameters or a subset of the function parameters to the arithmetic circuits to compute an approximation result. In a case where the subset of the function parameters is forwarded to the arithmetic circuits, the controller may configure the arithmetic circuits to perform post-processing, such as quantization, of the approximation result.

The invention discloses a path prediction circuit, method and device for a multi-path group connection cache and a processor, and belongs to the field of processors. The circuit prediction circuit comprises an operational circuit unit, a read logic circuit unit, a plurality of counting lookup tables and a judgment circuit unit, the multi-path group connection cache comprises a plurality of cache groups, each cache group comprises a plurality of cache paths, the plurality of cache paths are in one-to-one correspondence with the plurality of counting lookup tables, and each counting lookup table in the plurality of counting lookup tables has a plurality of entries; the operational circuit unit is used for generating an index value corresponding to the memory access address based on the memory access address; the read logic circuit unit is used for accessing an entry corresponding to the index value in each counting lookup table to obtain a plurality of count values, and the ith count value of the plurality of count values indicates the number of cache lines matched with the index value in the ith cache path; and the judgment circuit unit is used for respectively judging the relationship between the plurality of count values and zero. The path prediction circuit reduces the power consumption of the access cache.

A laser displacement sensor acquisition circuit disclosed by the present invention comprises a detection circuit, a sampling circuit, an operational circuit and an MCU controller, the sampling circuit is connected with the operational circuit and the detection circuit, the operational circuit is connected with the MCU controller, and the detection circuit is used for detecting the amplitude and state of a displacement signal of a sensor. When in non-static work, a sampling control signal Tag1 and a sampling signal Tag2 are fed back to the sampling circuit, the precision of the sampling circuit is controlled by a plurality of sampling units, and when the Tag1 signal is input, each sampling unit samples the sampling signal Tag2 in sequence and feeds back the signal to the operational circuit. After sampling is completed, the sampling unit feeds back an operation reset signal Tag5 to the operation circuit to carry out equalization calculation on a sampling point, or the MCU controller inputs the operation reset signal Tag5 to the operation circuit, and the operation circuit feeds back an operation result to the MCU controller to carry out waveform drawing and imaging. When the laser is in a static state, the detection circuit feeds back an interrupt signal Tag6 to the sampling unit.

This work classification device comprises: a storage unit that stores image data in which a work area has been imaged; and an arithmetic circuit that classifies the behavior of a worker on the basis of the image data. The classification includes a first class, a second class different from the first class, a first subclass included in the first class, and a second subclass different from the first subclass in the first class. The arithmetic circuit switches the granularity of the first class when assigning the behavior of the worker to the classification, on the basis of information in the work area in an image indicated by the image data.

The invention relates to the technical field of medical marketing data sharing, in particular to a medical marketing data sharing method and system based on a block chain, and the method comprises the steps: compiling a plaintext description of a medical marketing business rule into an arithmetic circuit with a multi-port structure, generating a verification key, and deploying the verification key in a block chain smart contract in the block chain; the verification node initiates a verification request containing a data type, a service rule identifier and a time period identifier; the medicine enterprise node and the medical institution node respectively load the local privacy data to the input port and generate a corresponding first zero-knowledge proof and a corresponding second zero-knowledge proof; and the verification smart contract loads a verification key according to the time period identifier to carry out cooperative verification on the two zero-knowledge certificates and generates a conclusion for uplink storage. According to the method, cross-subject association verification is realized on the premise of not converging original data, and the accuracy and auditing performance of compliance judgment are improved through a time period self-adaptive threshold value.

To reduce the load of data processing when displaying an image using three-dimensional spatial information.SOLUTION: An information extraction method is executed by an information processing device including an arithmetic circuit that can access a storage device, information is linked to each of a plurality of subspaces, and the method extracts the information linked to at least one subspace accompanying movement of a moving object. The storage device stores three-dimensional spatial information including the information linked to each of the plurality of subspaces obtained by virtually and regularly dividing a three-dimensional space around the center of a sphere. Each subspace is associated with at least one first element that specifies three-dimensional coordinates indicating the three-dimensional space. The moving object is associated with a second element indicating at least one point of the moving object. The arithmetic circuit selects the subspace based on the three-dimensional spatial information according to a positional relation between the first element and the second element when virtually moving the moving object in the three-dimensional space, and extracts the information linked to the selected subspace.SELECTED DRAWING: Figure 1

To enable focus detection signals having parallax in multiple different directions to be processed using a single arithmetic circuit for focus detection.SOLUTION: A focus detection device includes: acquisition means that acquires, for each pixel, a pair of focus detection signals having parallax in one of multiple different directions from signals of multiple pixels output by imaging means; separation means that separates the focus detection signals for each direction of the parallax; detection means that detects a focus state on the basis of a first focus detection signal which is separated by the separation means and in which the direction of the parallax is a predetermined first direction; and rearrangement means that rearranges a sequence of second focus detection signals which are separated by the separation means and in which the direction of the parallax is a second direction different from the first direction so that the direction of the parallax becomes the first direction. The detection means further detects the focus state on the basis of the second focus detection signals rearranged by the rearrangement means.SELECTED DRAWING: Figure 7

An arithmetic apparatus includes a first operand holding circuit configured to output a first operand according to a clock signal, generate an indicator signal based on bit values of high-order bit data including a most significant bit of the first operand, and gate the clock signal based on the indicator signal, the clock signal being applied to a flip-flop latching the high-order bit data of the first operand; a second operand holding circuit configured to output a second operand according to the clock signal; and an arithmetic circuit configured to perform data gating on the high-order bit data of the first operand based on the indicator signal and output an operation result by performing an operation using a modified first operand resulting from the data gating and the second operand.

Provided are a manufacturing planning system, a manufacturing planning method, and a program that make it possible to improve production efficiency and reduce the load of off-line setup. A manufacturing planning system (1) is for determining a manufacturing plan for producing a plurality of types of products by one or more production lines, and comprises an arithmetic circuit (15) capable of accessing changeover time data (D1) indicating a changeover time for one or more production lines due to a changeover between a plurality of types of products, and workload data (D2) indicating a workload of off-line setup due to a changeover. The arithmetic circuit (15) outputs a manufacturing plan (D5) for optimizing the sum of changeover times and the sum of workloads, on the basis of the changeover time data (D1) and the workload data (D2), in response to an input of production requirement data (D4) including target quantities of a plurality of types of products.

To provide a controller in which total harmonic distortion (THD) can be improved.SOLUTION: A controller (700) includes: a first external terminal receiving a first voltage (Vmult) with a full-wave rectified waveform; a second external terminal receiving a first detection voltage (Vis), as a negative voltage, generated by a current flowing through a sense resistor (Ris) connected to a ground potential application terminal; an error amplifier circuit (710) generating a second voltage (V2) by amplifying an error between a second detection voltage (Vs) corresponding to an output voltage (Vdc) and a reference voltage (Vref1); an arithmetic circuit (733) generating a third voltage (V4) by multiplying the first and second voltages; an inverting amplifier (734) generating a fourth voltage (V5) by inverting and amplifying the first detection voltage; and a comparator (735) comparing the third voltage and the fourth voltage.SELECTED DRAWING: Figure 11

The utility model discloses an arc discharge detection system, and belongs to the technical field of circuit detection. The system comprises a current sampling device, a band-pass filter circuit, a signal generation circuit and an operational circuit, the sampling end of the current sampling device is connected with a line to be detected, and the output end of the current sampling device is connected with the input end of the band-pass filter circuit; the output end of the band-pass filter circuit is connected with the first input end of the operational circuit; the output end of the signal generation circuit is connected with the second input end of the operational circuit, and the signal generation circuit is used for outputting a reference AC component signal; the operational circuit is used for subtracting the AC component signal input by the first input end from the reference AC component signal input by the second input end, a subtraction result is output through the output end of the operational circuit, and the subtraction result is used for indicating whether arc discharge exists in the line to be detected or not. And arc discharge detection of the circuit can be realized.

The embodiment of the invention relates to the technical field of information security, and discloses a task proving method and device, a task execution method and equipment and a storage medium, and the task proving method comprises the steps: segmenting a to-be-executed calculation task into a plurality of sub-tasks; selecting at least one sub-target task from the plurality of sub-tasks based on a task selection rule; based on the at least one sub-target task, generating at least one arithmetic circuit, at least one proof key and at least one verification key corresponding to the at least one sub-target task; sending the to-be-executed calculation task, the at least one proof key and the at least one arithmetic circuit to a second server, and receiving a calculation result and a proof result of the second server; and proving the validity of the calculation task to be executed based on the at least one verification key, the at least one arithmetic circuit, the proving result and the calculation result. According to the task certification method disclosed by the invention, the problem that a lot of time needs to be consumed in the certification generation and verification process is solved, so that the efficiency of verifying the calculation task is relatively high.

An example apparatus includes a hardware platform having arithmetic circuits and a memory, the memory configured to store, at a first precision, first compressed parameters of a machine learning (ML) model; a network interface controller; and a controller, supported by the hardware platform, configured to: decompress, from the memory through an increase in precision to a second precision, the first compressed parameters to obtain decompressed parameters; control the arithmetic circuits to train, using arithmetic operations, the ML model and update the decompressed parameters; compress, using quantization and reduction in precision to the first precision, the decompressed parameters as updated to obtain second compressed parameters; send, using the network interface controller, the second compressed parameters over a network to a server; and update the first compressed parameters in the memory in response to data received, through the network interface controller, from the server over the network.

The present invention relates to a method for homomorphically encrypting general plaintext spaces with controlled noise growth, comprising: a general plaintext space by selecting a polynomial of degree greater than 1, and defining the plaintext space as formula (I), where f(x) and t(x) are polynomials; applying an encoding method on a message and producing a corresponding element in the plaintext space Rt; applying a homomorphic encryption method that takes the encoded message as input and returns a ciphertext that encrypts the message; providing a decryption method that takes the ciphertext as input and returns the decoded plaintext; applying a method to homomorphically process encrypted messages by evaluating an arithmetic circuit representing the function to be evaluated, wherein the noise growth during homomorphic operations is determined by the size of; and applying a method to refresh ciphertexts via bootstrapping, which consists of homomorphically processing the decryption circuit.

The invention relates to distributed ledger technologies such as consensus-based blockchains. Computer-implemented methods for reducing arithmetic circuits derived from smart contracts are described. The invention is implemented using a blockchain network, which may be, for example, a Bitcoin blockchain. A set of conditions encoded in a first programming language is obtained. The set of conditions is converted into a programmatic set of conditions encoded in a second programming language. The programmatic set of conditions is precompiled into precompiled program code. The precompiled program code is transformed into an arithmetic circuit. The arithmetic circuit is reduced to form a reduced arithmetic circuit, and the reduced arithmetic circuit is stored.

A multiply-accumulate unit comprises a first input configured to receive a first operand encoded using a two-bit encoding scheme in which a ternary value is represented by two bits, wherein identical bits indicate a non-computable value and different bits indicate a computable value. The unit further comprises a second input for receiving a second operand, a zero detection circuit with a logic gate that compares the two bits and generates a skip signal when they are identical, an arithmetic circuit for performing accumulation based on both operands, an accumulator register for storing the result, and a gating circuit that selectively enables writing to the accumulator register based on the skip signal, preventing writing when the first operand is non-computable.

Provided are an image processing device, a display device, and a control method whereby the luminance of an overlapping region in a projection image can be suppressed from decreasing non-linearly according to the position in the overlapping region by edge blending. This image processing device comprises an arithmetic circuit and a storage device, and transmits an output video signal to a display device. The arithmetic circuit performs gamma correction on a received input video signal using a first gamma characteristic and a second gamma characteristic, performs edge blending for adjusting the luminance of a predetermined region in an image according to the position in the predetermined region using the second gamma characteristic, and generates an output video signal. The second gamma characteristic is the inverse function of a third gamma characteristic of the display device. The third gamma characteristic has a gamma curve expressed by an exponential function. The predetermined region is a region in which the image displayed by the display device and another image displayed by another display device overlap.

A processing unit includes a redundant remainder generation circuit that converts first operand data and second operand data into a plurality of first operand redundant remainder sets and a plurality of second operand redundant remainder sets based on a redundant remainder system (RRNS) using first to Tth moduli. T is a natural number equal to or greater than 4. The processing unit includes a plurality of arithmetic circuits that perform operations using the plurality of first operand redundant remainder sets and the plurality of second operand redundant remainder sets, and a reconstruction circuit that restores the RRNS-based result data to the weighted coefficient-based result data. An in-memory processing (PIM) apparatus and an in-memory processing (PIM) system are also provided.

A neural processing unit for performing inference operations of a large-scale language model based on an artificial neural network is disclosed. The neural processing unit according to the present disclosure includes a processing element core configured to perform an attention mechanism-based operation based on input data in vector format to output an operation result, a special function unit comprising a plurality of arithmetic circuits including at least one vector-dedicated arithmetic circuit that exclusively performs vector operations and at least one mixed arithmetic circuit capable of performing both vector and scalar operations, and configured to perform a special function operation on the operation result, and a controller configured to, upon receiving an RMS normalization operation execution command, activate at least one of the plurality of arithmetic circuits to control the special function unit to perform an operation of converting at least one of the operation result or the input data into a normalized vector whose magnitude is adjusted based on a root mean square (RMS), wherein the operation result may include an attention score for the input data.

A neural network device, a computing system, and a method of processing a feature map are provided. The neural network device includes at least one processor configured to implement: an arithmetic circuit configured to generate third data including a plurality of pixels based on a neural network performing an arithmetic operation on first data and second data; and a compressor configured to generate compressed data by compressing the third data, wherein the compressor is further configured to generate bitmap data as the compressed data based on a quadtree structure, the bitmap data including position information of non-zero pixels having non-zero data values among the plurality of pixels.

The present application provides a storage operation circuit, which includes a first chip, a second chip, and multiple data pins. Among them, the first chip and the second chip are three-dimensionally stacked, and the multiple data pins are the data pins of the first chip, which are arranged in a two-dimensional array form. The first chip includes multiple memory blocks, and each memory block includes multiple memory cells. The second chip includes multiple operation blocks corresponding to the memory blocks one by one, and each operation block includes a read / write circuit and an in-block operation circuit connected to the read / write circuit. In the storage operation circuit of the present application, the first chip and the second chip are three-dimensionally stacked, so that the data pins can be arranged in a two-dimensional array form, and the number is no longer limited by the side length of the memory. Therefore, within one read / write cycle, more data than one row in the existing memory can be read, written, and transmitted for operation, improving the bandwidth and thus the operation speed.

To provide arithmetic unit and method capable of performing a multiplication operation on input data with different data types.SOLUTION: An arithmetic unit in an embodiment can include a controller that receives first input data of a first data type and second input data of a second data type different from the first data type, and outputs a first signal expressing the first data type, a second signal expressing the second data type, and a clock signal based on the number of bits of the first input data and the second input data, and an arithmetic circuit that generates output data by performing a multiplication operation on the first input data and the second input data on the basis of the first signal, the second signal, and the clock signal.SELECTED DRAWING: Figure 6

A semiconductor device with a novel structure is provided. The semiconductor device includes a plurality of arithmetic blocks each including an arithmetic circuit portion and a memory circuit portion. The arithmetic circuit portion and the memory circuit portion are electrically connected to each other. The arithmetic circuit portion and the memory circuit portion have an overlap region. The arithmetic circuit portion includes, for example, a Si transistor, and the memory circuit portion includes, for example, an OS transistor. The arithmetic circuit portion has a function of performing product-sum operation. The memory circuit portion has a function of retaining weight data. A first driver circuit has a function of writing the weight data to the memory circuit portion. The weight data is written to all the memory circuit portions included in the same column with the use of the first driver circuit.

An in-memory computing (IMC) accelerator using a high-density operation circuit and a low-power sense amplifier as a peripheral circuit includes a plurality of dynamic random-access memory (DRAM) banks each including a pair of cell arrays, a data supply logic, a memory, and a controller for IMC, a global SRAM, and a top-level controller, wherein the cell array includes a plurality of subarrays, each of the subarrays includes a DRAM array including a big array and a little array, and an arithmetic circuit configured to perform an operation, and the arithmetic circuit includes a sense amplifier configured to amplify a bit line voltage difference, and a compact multiply-accumulate (MAC)-single instruction multiple data (SIMD) unit (CMSU) for an MAC operation and an SIMD operation, so that functionality of an in-memory operation is diversified.

The invention belongs to the technical field of information security, relates to zero-knowledge proof and block chain technologies, and particularly provides a public verifiable data service method for an instrument control system, so as to solve the technical problem of huge calculation overhead caused by the fact that commitment consistency check of large-scale data needs to be executed in a circuit in an existing zk-SNARK-based scheme. According to the invention, a hybrid proving system based on a cryptographic protocol Plonk and Groth16 is designed, the promise adaptive to the system is designed, and the consistency check of the promise of the database is transferred from the inside of an arithmetic circuit to the outside of the circuit, so that the huge calculation overhead introduced into a zk-SNARK circuit by the promise consistency check of a large-scale database is avoided; and finally, the verifiable execution of safe calling and operation on the data subset from the third-party cloud storage is realized, the accuracy and integrity of industrial data are ensured, and the problem of trust missing in a cross-domain scene is solved.

The present invention provides a neuron logic gate metal oxide semiconductor νLGMOS circuit, which can simulate the "integration and firing" behavior of neurons in a biological neural network system, and can be fabricated together with multiple digital arithmetic circuits by using industrial CMOS logic process technology. The processing system of the present invention includes an analog νLGMOS circuit, a converter circuit, and a digital processing circuit, which can optimize the power and cost of various applications and can be fabricated into an integrated circuit chip by using the same CMOS logic process technology. At the same time, the above-mentioned analog νLGMOS circuit is inspired by the biological neural network system and can be simulated, designed, and fabricated into an integrated circuit chip for applications in the biomedical field.

An example system includes a processor to partition an arithmetic circuit representing a homomorphically encrypted (HE) code into a number of execution blocks. The processor can generate, for each of the number of execution blocks, manifests describing access patterns for a number of different machine environments. The processor can then dynamically execute the HE code by selecting successive blocks to execute based on an access pattern calculated for the execution block corresponding to a detected current machine environment.

The invention relates to a method for applying zero-knowledge proof to block chain agriculture, and relates to the technical field of block chain agriculture, a low-power-consumption edge computing gateway is deployed to collect farmland environment and farming data, and growth stages such as a seedling stage and a vegetative growth stage are dynamically divided based on a crop growth date (GDD) model; business rules of all stages are compiled into an arithmetic circuit, and a lightweight zero-knowledge proof is generated in a trusted execution environment (TEE) by taking sensitive data as private input; after validity is verified and proved through the block chain smart contract, a content identifier (CID) is associated with a certificate and written into the chain; a consumer can inquire a series of verification results of the whole growth cycle through the agricultural product traceability code. According to the scheme, agricultural production data can be verified and invisible, triple contradictions of weak privacy protection, dynamic adaptation deficiency and field deployment obstacle in a traditional agricultural block chain are solved in a breakthrough mode, safe and efficient credible traceability infrastructure is provided for high-value agricultural products such as organic authentication, and the risk of commercial secret leakage is reduced through actual measurement.

A system and method are provided for converting high-level source code into arithmetic circuitry representing functions expressed in the source code. The invention includes a translation / interpretation component for performing the conversion. In a preferred embodiment, the source code is a smart contract, such as a contract used in connection with a blockchain platform. A method according to an embodiment includes the steps of processing a portion of a high-level source code (e.g., a smart contract) to generate an arithmetic circuit. The arithmetic circuit includes one or more arithmetic gates arranged to represent at least some of the functions expressed in the source code. The processing involves evaluating one or more constants provided in the source code to generate one or more expressions containing Boolean and / or arithmetic operators. The arithmetic circuit includes an n-bit line connected to the arithmetic gate; it may be used to provide hardware and / or software circuitry. The arithmetic circuitry may be used to generate quadratic plans that may be executed on the processor.