39 results about "Arithmetic circuits" patented technology

A neural processing unit for performing inference operations of a large-scale language model based on an artificial neural network is disclosed. The neural processing unit according to the present disclosure includes a processing element core configured to perform an attention mechanism-based operation based on input data in vector format to output an operation result, a special function unit comprising a plurality of arithmetic circuits including at least one vector-dedicated arithmetic circuit that exclusively performs vector operations and at least one mixed arithmetic circuit capable of performing both vector and scalar operations, and configured to perform a special function operation on the operation result, and a controller configured to, upon receiving an RMS normalization operation execution command, activate at least one of the plurality of arithmetic circuits to control the special function unit to perform an operation of converting at least one of the operation result or the input data into a normalized vector whose magnitude is adjusted based on a root mean square (RMS), wherein the operation result may include an attention score for the input data.

Integrated circuit devices and circuitry for digital filtering are provided. An integrated circuit device may include a first digital signal processing (DSP) block with first hardened arithmetic circuitry and an output register to store an output of the first DSP block and a second DSP block with second hardened arithmetic circuitry and an input register to receive the output of the first DSP block. An input signal chain may include a first set of registers to provide first input data signals to the first DSP block, a second set of registers to provide second input data signals to the second DSP block, and a third set of registers connected between the first set of registers and the second set of registers to provide delay equal to that of the output register of the first DSP block and the input register of the second DSP block.

Method and device for generating a Gaussian error. This description relates to a device configured to generate an approximate value by adding noise to an output of a balanced arithmetic circuit, comprising: - the balanced arithmetic circuit configured to generate a first value; - an approximation circuit configured to generate a k-bit mask based on a first distribution; and - a logic circuit configured to generate a second value based on the first value, the k least significant bits of the second value being generated by applying the mask to the k least significant bits of the first value, the most significant bits of the second values ​​being equal to the most significant bits of the first value, the first distribution being such that the second value corresponds to the first value with an added error value having a Gaussian distribution of standard deviation.Figure for the abridged version: Fig. 1.

A battery module failure is reliably determined. A power supply device is provided with: a plurality of battery modules (2) including a failure determination section (21) that determines failure and normality and outputs failure and normality using signals of "high" and "low"; a failure transmission line (3) connected to the failure determination section (21) of each battery module (2); and a module failure determination circuit (1) connected to the failure transmission line (3) and determining failure and normality of the battery modules (2). The module failure determination circuit (1) is provided with: a voltage determination circuit (4) that determines "high" and "low" of the failure transmission line (3); an impedance detection circuit (5) that detects impedance with respect to a ground line (23); and an arithmetic circuit (6) that determines failure and normality of the battery modules (2) and abnormality of the failure transmission line (3) based on outputs of the voltage determination circuit (4) and the impedance detection circuit (5).

Techniques described herein may be utilised to implement methods and systems for lossless compression and serialisation of arithmetic circuits to a bit stream using compression techniques such as the arithmetic coding. An arithmetic circuit representing a smart contract may be compressed using arithmetic coding, thereby generating a compressed arithmetic circuit that can be stored or broadcast to a blockchain network using less computational resources (e.g., data storage resources) than would otherwise be needed to store the arithmetic circuit. The arithmetic circuit can be efficiently compressed using entropy coding based on the frequency of elements in the data structure, such as the arithmetic operator types. Instructions for de-serialisation and de-compression can also be embedded in the bit stream, and can be used (e.g., by another computer system) to reconstruct the original circuit in a lossless manner.

A hardware-anchored Liquidity Containment and Capital Reserve Enforcement Engine executes real-time reserve validation, liquidity sufficiency computation, and deterministic settlement gating entirely within trusted execution environments (TEEs) comprising Intel SGX enclaves, AMD SEV-SNP protected VMs, or ARM TrustZone secure worlds, materially altering processor states to isolate all reserve computation. Liquidity Integrity Vectors are computed using the reserve adequacy function h(alpha, beta, gamma) from hardware-attested inputs anchored to TEE-resident hardware mechanisms comprising enclave-sealed monitoring registers, memory encryption engine integrity states, or attestation-based recalibration triggers. A Liquidity Containment Gate enforces a non-bypassable hardware execution barrier requiring all LIV computation, Capital Reserve Monitor validation, and ZKP proof generation to complete within a single attested TEE execution instance before settlement authorization is released. A ZKP Verification Engine generates Groth16 arithmetic-circuit proofs of approximately 192 bytes verifiable in under 10 milliseconds, enabling External Counterparty verification of reserve sufficiency without disclosure of proprietary balance sheet data. A Provenance Ledger stores append-only cryptographic hash chains with each entry bound to a TEE attestation report. A Settlement Attestation Binder cryptographically binds settlement authorizations to specific TEE attestation report identifiers, enabling independent verification of both settlement outcomes and the hardware environments that authorized them.

A designation method makes adjustment of a display system that combines images displayed by a plurality of display devices into one image easy. The designation method uses a sampling region in adjustment of display of images by a plurality of display devices when the plurality of display devices display one image content in an adjustment device. The adjustment device has an arithmetic circuit, and can access a storage device and a display. The adjustment device causes the plurality of display devices to display an adjustment image that is stored in the storage device in advance by the arithmetic circuit, acquires a captured image obtained by capturing the adjustment image displayed by the plurality of display devices from a capturing device, causes the display to display the acquired captured image, presents a candidate of the sampling region to a user superimposed on the captured image displayed in the display, and accepts designation of the sampling region determined based on the candidate of the sampling region according to an operation from the user via an input device.

An arithmetic device (10) includes multiple PEs (12) arranged in two-dimensional manner. Each PE (12) has a selector (24) that outputs input data in a set direction. The PE (12) performs data movement via the selector (24) with another non-adjacent PE (12) located diagonally, or performs data movement via the selector (24) in own PE (12) by moving data from a register (22) to an arithmetic circuit (20), by processing a selector setting command and an input output command in a single operation.

A neural network processor and method include a fetch controller configured to receive input feature information, indicating whether each of a plurality of input features of an input feature map includes a non-zero value, and weight information, indicating whether each of a plurality of weights of a weight map includes a non-zero value, and configured to determine input features and weights to be convoluted, from among the plurality of input features and the plurality of weights, based on the input feature information and the weight information. The neural network processor and method also include a data arithmetic circuit configured to convolute the determined weights and input features to generate an output feature map.

An induction heating cooking appliance has a top plate, a heating coil, a drive circuit that drives the heating coil, an arithmetic circuit that controls the drive circuit, and an input device that accepts an instruction to the arithmetic circuit. The input device accepts a setting of an automatic cooking procedure and a pot type selection that selects a pot type. The arithmetic circuit controls the drive circuit based on one heating sequence among a plurality of heating sequences corresponding to the automatic cooking procedure. In a case where the input device accepts the setting of the automatic cooking procedure, the arithmetic circuit selects one heating sequence from the plurality of heating sequences in accordance with a pot type selected at a time of a last execution of the automatic cooking procedure.

The application discloses a graph neural network node forgetting method based on differential privacy and zero-knowledge proof and belongs to the field of artificial intelligence and data privacy protection.The method comprises three stages: firstly, the multi-hop semantic influence area of the target node is accurately positioned by combining gradient, curvature and topological distance, the node and the associated edge are removed, and local topological disturbance is carried out; secondly, the node embedding is reconstructed in the affected area, and privacy budget is allocated according to the influence degree of the node, and adaptive differential privacy noise is added to the embedding; finally, the whole forgetting process is coded into an arithmetic circuit, and a publicly verifiable proof is generated by using a zero-knowledge proof system, so that a third party can verify the deletion integrity, reconstruction independence and privacy compliance without contacting the original data.The application solves the problems of completeness, anti-inference and auditability of graph data deletion and is suitable for high-sensitive scenes.

The application discloses a privacy protection verifiable joint analysis method based on semi-trusted hardware, which comprises n computing nodes P1,..., P n The local data analysis model is converted into an arithmetic circuit respectively, the arithmetic circuit comprising a plurality of addition gates and a plurality of multiplication gates; a polynomial secret share of to-be-analyzed data distributed by a data holder through a (t, n) threshold Shamir secret sharing scheme is acquired; the polynomial secret share of the to-be-analyzed data is taken as input of the arithmetic circuit, analysis is performed through the arithmetic circuit, and thus an analysis result secret share is obtained, wherein the addition gate is realized by directly adding the polynomial secret share, the multiplication gate is realized by multiplying the polynomial secret share and jointly computing nodes, and the product is reduced in order by using a random secret share generation algorithm; and the analysis result secret share is sent to the data holder, so that the data holder restores the clear analysis result.

A hardware-anchored Systemic Contagion Detection and Exposure Containment Engine executes real-time cross-institution exposure graph modeling, cascade propagation detection, and deterministic settlement path interruption entirely within trusted execution environments (TEEs) comprising Intel SGX enclaves, AMD SEV-SNP protected VMs, or ARM TrustZone secure worlds, materially altering processor states to isolate all contagion risk computation. Contagion Risk Tensors are computed using the cascade propagation function c(epsilon, phi, psi, tau) from hardware-attested exposure inputs anchored to TEE-resident hardware mechanisms comprising enclave-sealed monitoring registers, memory encryption engine integrity states, or attestation-based recalibration triggers. A Cascade Interruption Gate enforces a non-bypassable hardware execution barrier requiring CRT computation, Exposure Drift Monitor validation, and ZKP proof generation to complete within a single attested TEE execution instance before settlement path authorization is released. A ZKP Contagion Verification Engine generates Groth16 arithmetic-circuit proofs of approximately 192 bytes verifiable in under 10 milliseconds, enabling External Supervisory Authority verification of systemic containment compliance without disclosure of institution-proprietary exposure data. An Attestation-Bound Provenance Ledger binds all cascade detection and interruption events to specific TEE attestation report identifiers, enabling independent verification of both cascade containment outcomes and the hardware environments that authorized them.

An evaluation method is performed by an arithmetic circuit and includes obtainment processing (S1), evaluation processing (S2), and presentation processing (S3). The obtainment processing (S1) obtains: image information on a sectional image representing an interested section of an organism including a target section of a testis of the organism generated by use of magnetic resonance of hydrogen atoms; and concentration information on a creatine concentration in the interested section measured by use of magnetic resonance based on chemical exchange saturation transfer. The evaluation processing (S2) generates an evaluation image representing a distribution of evaluation results of a testicular function in the target section based on the concentration information. The presentation processing (S3) presents the sectional image and the evaluation image.

The embodiments of the present specification provide a data verification method and device. According to the method, a computing device first acquires function information of a target function group of a target arithmetic circuit, wherein the target arithmetic circuit is used to perform a target computing task instructed by a verification device, and the target function group is used to describe a circuit structure of the target arithmetic circuit. The computing device determines a first function according to a current computing process of the target computing task, wherein the first function is used to describe input and output values of each gate in the target arithmetic circuit in the current computing process. Then, the computing device proves that the first function satisfies a plurality of preset constraint relationships by performing an interactive argument protocol with the verification device, thereby proving the correctness of the current computing process, wherein the plurality of constraint relationships include a constraint relationship between the first function and the function information of the target function group.

An electronic device with a novel structure is provided. The electronic device includes a semiconductor device, and the semiconductor device has a structure where a first element layer, a second element layer, and a third element layer are stacked. The first element layer includes a first transistor that includes a semiconductor layer containing silicon in a channel formation region. The second element layer includes a second transistor that includes a semiconductor layer containing a metal oxide in a channel formation region. The third element layer includes a light-emitting device. The first element layer includes an arithmetic circuit including a scan flip-flop. The second element layer includes a backup circuit electrically connected to the scan flip-flop and a pixel circuit electrically connected to the light-emitting device.

This invention discloses a grid-connected data management system and method for network security, relating to the field of data security technology. In a power system, when different participants need to negotiate and manage grid-connected data using a task function, the different participants determine unified security parameters and establish secure communication channels between each other. Each data point in the time-series data stream is divided into data fragments, which are then sent to all participants through the secure communication channels. All data fragments of the same data point received by all participants constitute a secret share. The task function is transformed into an arithmetic circuit, which inputs the secret share and triplet of the grid-connected data held by each participant. Based on the optimized real-time grid topology, addition gates, multiplication gates, and constant gates are calculated one by one, and the secret share after gate operations is finally output.

An arithmetic circuit includes a resistance change element having three terminals of a first terminal, a second terminal, and a third terminal, capable of changing a resistance value; an input line connected to the first terminal; a capacitor connected to the second terminal, between the second terminal and a reference potential; a first switching element connected to the third terminal; a wiring connected to the third terminal via the first switching element; a second switching element connected to a first end of the wiring; and a third switching element connected to a second end of the wiring.

In a communication device according to an embodiment of the present invention, a signal reception unit receives an OFDM signal and converts the signal into a time-axis waveform signal of a baseband. A time waveform arithmetic unit extracts a part of the time-axis waveform signal output from the signal reception unit and calculates a correlation value between the extracted signal and a known signal. In a series of arithmetic stages for performing a Fourier transform, a FFT unit repeatedly uses a single arithmetic circuit and a data storage circuit through time multiplexing and performs FFT on the time-axis waveform signal output from the signal reception unit. A frequency waveform arithmetic unit extracts a part of a frequency-axis waveform signal through the FFT and calculates a degree of similarity between the extracted signal and a known signal. A switching timing estimation unit estimates a switching timing between uplink communication and downlink communication in a host device on the basis of the calculation result for the degree of similarity.

This application provides a method, apparatus, device, storage medium, and program product for transmitting business request data, which can be applied to the field of big data technology. The method includes: parsing a business request from a business requester to obtain data to be encrypted and a set of key feature indicators, wherein the set of key feature indicators is a set of fields extracted from the business request and characterizing the attributes of the business request; obtaining a set of applicable rules matching the set of key feature indicators from a pre-set compliance logic rule base constructed based on regulatory rules; determining a target encryption algorithm based on a business risk assessment value calculated from the set of key feature indicators and the set of applicable rules; generating a zero-knowledge proof based on a compliance circuit determined by the set of applicable rules, wherein the compliance circuit is an arithmetic circuit usable for the zero-knowledge proof; and sending the ciphertext, the zero-knowledge proof, and auxiliary information for verifying the zero-knowledge proof and decrypting the ciphertext to a receiver, enabling the receiver to verify the zero-knowledge proof based on the auxiliary information, and decrypting the ciphertext upon successful verification.

The application provides a data processing method and device, computer equipment, computer readable storage medium, computer program product, and belongs to the technical field of computers. The data processing method is used for a computing node in a secure multi-party computing system, and the method comprises: obtaining target parameters and an arithmetic circuit corresponding to a target task, and data shards provided by a plurality of clients for the target task; generating an operation result shard based on the target parameters, the arithmetic circuit and the data shards, and sending the operation result shard to other computing nodes in the secure multi-party computing system; obtaining operation result shards generated by the other computing nodes, and generating a target operation result corresponding to the target task based on the locally generated operation result shard and the operation result shards generated by the other computing nodes. The technical scheme of the embodiment of the application jointly completes a computing task through a plurality of computing nodes, and takes into account computing accuracy and data privacy.

A hardware-enforced AI liability containment system binds autonomous AI agent decisions to predefined liability envelopes retrieved from TEE-sealed policy stores within trusted execution environments (TEEs) comprising Intel SGX enclaves, AMD SEV-SNP protected VMs, or ARM TrustZone secure worlds, materially altering processor states to isolate all liability computations. Real-time risk exposure is computed using trust-state signals derived from TEE-resident hardware mechanisms comprising enclave-sealed monitoring registers, memory encryption engines, or attestation-based recalibration triggers, incorporating the exposure function f(d, delta, r, cap). Excess exposure is routed to insurance pools via zk-SNARK zero-knowledge proofs with arithmetic circuit structures generating constant-size cryptographic proofs verifiable within real-time operational latency constraints, replacing manual audit review with constant-size cryptographic verification operations executed in hardware-isolated environments. An ethical supervisor enforces behavioral guardrails, with symbiotic rollback circuits reverting agent state on cap breach. A provenance ledger uses append-only cryptographic hash chains bound to TEE attestation reports for non-repudiable verification of liability binding events and hardware environments, enabling per-decision insurable autonomous AI deployment at commercial scale.

An arithmetic device includes multiple PEs arranged in two-dimensional manner. Each PE has a selector that outputs input data in a set direction. The PE performs data movement via the selector with another non-adjacent PE located diagonally, or performs data movement via the selector in own PE by moving data from a register to an arithmetic circuit, by processing a selector setting command and an input output command in a single operation.

The present disclosure relates to Booth multipliers, arithmetic circuits, processors, and computing devices. A Booth multiplier includes one or more partial product generation circuits, each partial product generation circuit including: a negation circuit configured to selectively negate a second number based on a highest bit of three adjacent bits of a first number; an encoding circuit configured to generate a selection signal for selecting an operation to perform on an output of the negation circuit based on the three adjacent bits of the first number; a selection circuit configured to apply the selection signal received from the encoding circuit to the output of the negation circuit received from the negation circuit to generate a partial product; a carry compensation circuit configured to generate a carry compensation corresponding to a sign of the Booth encoding of the three adjacent bits. The Booth multiplier further includes a partial product summation circuit configured to sum outputs of the selection circuits and the carry compensation circuits of the one or more partial product generation circuits to generate a product of the first number and the second number.

A data bus toggle circuit includes: a DBI calculation circuit, used to calculate the data toggle signal corresponding to the current input data, comprising a register, a comparator, and an arithmetic circuit; a DBI mask generation circuit, comprising an accumulator circuit and a comparator circuit, the input of the accumulator circuit being connected to the output of the DBI calculation circuit, and the output of the accumulator circuit being connected to the input of the comparator circuit; and a data processing circuit, including a DBI processing circuit and a data toggle circuit, the DBI processing circuit being connected to the output of the comparator circuit and the output of the DBI calculation circuit. This application controls whether data bus toggle is enabled by a mask signal when continuously transmitting large amounts of data, reducing unnecessary toggles and thus reducing power loss during data transmission.

A multiplication circuit with reduced power consumption is provided. The multiplication circuit includes a first unit and a second unit. Both the first and second units are used as current source circuits. The first unit generates a first current based on the gate-source voltage of a first transistor, and the second unit generates a reference current based on the gate-source voltage of a second transistor. Furthermore, the multiplication circuit functions to change the reference current of the second unit to a second current, thereby amplifying the first current to a third current according to the ratio of the reference current to the second current. Additionally, to maintain the gate-source voltage of each of the first and second transistors, both the first and second units include switching sections. Each switching section includes a transistor connected in series and a capacitor connected between them.

A kind of proxy body cooperation logic closed loop verification system based on zero-knowledge proof, the output end of contract conversion module is connected to the instruction input end of task execution module and the circuit parameter input end of closed loop verification module respectively through data bus, for converting the cooperation rule in the received multi-proxy body cooperation task protocol into arithmetic circuit, and the generated arithmetic circuit parameters are distributed to downstream module, the signal output end of task execution module is connected to the data input end of proof generation module, for responding the cooperation task of requester proxy body.The present application cooperates with the work of rule disassembly, logic mapping and circuit assembly unit in the inside of contract conversion module, solidifies business logic into topological structure that can be deduced in mathematics, so that all subsequent execution and verification have unique and explicit mathematical scale, and circuit parameter package generated by module is synchronously distributed to execution and verification end, to ensure the absolute consistency of "test paper" and "test paper standard".

A Trust-State Credit and Capital Markets Infrastructure Layer executes credit scoring, risk weighting, issuance authorization, and settlement verification entirely within trusted execution environments (TEEs) comprising Intel SGX enclaves, AMD SEV-SNP protected VMs, or ARM TrustZone secure worlds, materially altering processor states to isolate all credit computation. Trust-State Scores are computed using the scoring function g(sigma, delta, rho, kappa) with hardware-anchored integrity signals derived from TEE-resident hardware mechanisms comprising enclave-sealed monitoring registers, memory encryption engine integrity states, or attestation-based recalibration triggers, with Drift Detection Anchor monitoring preventing silent model degradation. A Credit Issuance Gate enforces a hardware-validated execution barrier requiring all scoring, drift validation, and risk weighting to complete within a single attested TEE execution instance before any issuance authorization is released. A ZKP Verification Engine generates Groth16 arithmetic-circuit proofs of approximately 192 bytes verifiable in under 10 milliseconds, enabling External Counterparty verification without exposure of proprietary scoring data, replacing multi-party rating reconciliation with constant-size cryptographic verification in hardware-isolated environments. A Provenance Ledger stores append-only cryptographic hash chains wherein each entry is cryptographically bound to a TEE attestation report. A Settlement Attestation Binder cryptographically binds settlement confirmations to specific TEE attestation report identifiers, enabling independent verification of both settlement outcomes and the hardware execution environments that authorized them, delivering verifiable AI-generated credit ratings and attestation-bound settlement finality at market scale.