767 results about "Binary multiplier" patented technology

The invention discloses a high-energy-efficiency logarithm floating point multiplier based on truncation error compensation. The system comprises a compensation parameter modeling unit and a floating point multiplier module. The compensation parameter modeling unit obtains an optimal compensation value k through linear fitting and parameter optimization, and realizes regional self-adaptive compensation in combination with block modeling so as to reduce truncation errors; the floating point multiplier module comprises a special value detection module, a symbol exclusive or module, an exponential addition module and a mantissa truncation compensation module. In a logarithm domain, multiplication is replaced by addition, and compensation logic is introduced to correct errors. The multiplier supports various floating point precisions and configurable truncation bit widths, provides three representative structures to give consideration to both the precision and the energy efficiency, and is suitable for high-energy-efficiency calculation scenes such as neural networks and image processing.

A logarithmic amplifier system is disclosed. The system includes first and second amplifiers respectively having first and second gains; a first multiplier having an input connected to an output of the first amplifier, and being configured to output a first multiplied signal based on an output signal of the first amplifier and based on a received first multiplication factor equal to a value K; a second multiplier having an input connected to an output of the second amplifier, and being configured to output a second multiplied signal based on an output signal of the second amplifier and based on a received second multiplication factor equal to 1 minus the value K; a transition shaping circuit configured to change the value K from 0 to 1 with a filtered transfer function; and a summing circuit having inputs coupled to outputs of the first multiplier and the second multiplier.

An even harmonic multiplier employing complementary current reuse is disclosed. The even harmonic multiplier employs supply voltage and current density scaling to reduce power consumption. Further, by using complimentary NMOS and PMOS transistors, the even harmonic multiplier achieves high areal efficiency. Current reuse causes a reduction in noise at the first harmonic, as the corresponding first harmonic currents from the NMOS and PMOS transistors are in opposite, i.e., canceling, directions. Complementary current reuse is now feasible, as the performance of PMOS transistors at current process nodes is similar to those of NMOS transistors, with appropriate sizing leading to approximately equivalent transconductances. Multiple even harmonic multiplier configurations are possible, with many using transformer circuits at the input and / or the output. The resultant even harmonic multipliers find ready application in millimeter wave radio frequency receivers. The most common even harmonic multiplier is a frequency doubler, which produces a strong second harmonic signal.

The embodiment of the invention discloses an internal memory, a chip and related electronic equipment. A target computing unit of the internal memory comprises a plurality of groups of primary multipliers, a plurality of adder trees and a plurality of secondary multipliers, one group of first-level multipliers is connected with one second-level multiplier through one adder tree; the group of first-level multipliers comprises a plurality of pairs of first multipliers, and each adder tree comprises a first adder, a second adder and a third adder; each pair of first multipliers respectively receive data to perform multiplication operation, and respectively input output results into the first adder to perform addition operation; each second adder receives the output results of the plurality of first adders or the second adder at the upper level to carry out addition operation, and respectively inputs the output results to the second adder at the lower level or the third adder; and each third adder receives the output results of the plurality of second adders to carry out addition operation, and inputs the output results to the secondary multiplier to carry out multiplication operation. By implementing the embodiment of the invention, the memory computing capability can be improved.

The invention discloses a high-precision face recognition method and system which are suitable for complex illumination and unconstrained position scenes. The method is realized through cooperation of a multi-modal acquisition guide strategy driven by a state machine and a self-adaptive fusion mechanism based on a physical multiplier array: the state machine controls logic to generate a position-attitude sequence instruction, and drives a user to synchronously provide RGB-NIR image pairs in upper, middle and lower screen areas and left and right side face attitudes; the double-flow convolutional neural network extracts an aligned bimodal feature map through shared weight constraint; the attention fusion module dynamically generates a space-channel joint attention weight based on a local signal-to-noise ratio difference through a multiplier array and a weight register realized by hardware, and performs pixel-by-pixel weighted fusion on the bimodal features. And a physical mapping relation between state machine position change and modal weight distribution is established through coupling training. According to the invention, through algorithm hardening and hardware cooperation, the accuracy and real-time performance of cross-illumination and cross-position unconstrained face recognition are significantly improved.

A mixed analog / digital in-memory computing device implements matrix vector multiplication with reduced noise for use by a deep neural network (DNN). For each row of a cross-bar array a digital multiplier is split into a least significant (LS) portion and a most significant (MS) portion of different sizes that are preloaded into two cells on one row and two different columns of the cross-bar array. An input activation (IA) value is driven onto input conductors of each row and an analog-to-digital converter (ADC) converts output signals from the two columns as a MS partial sum and a LS partial sum. A gain is applied to the MS partial sum and added to the LS partial sum to form a resulting value for one node of the DNN.

The invention relates to a reconfigurable multi-channel polynomial multiplier architecture and an implementation method thereof, and belongs to the technical field of post-quantum cryptography hardware acceleration. The architecture comprises a scheduler, a twiddle factor memory bank, a bank address routing module, a bank array and a reconfigurable butterfly unit array. According to the architecture, a cyclic decoupling multi-channel NTT / INTT / PWM algorithm is used, flexible configuration of the degree of parallelism and the flow line depth can be supported, and the adaptability of a memory access control strategy is improved; a conflict-free memory mapping scheme based on interleaved storage is adopted, so that storage and read-write of polynomial coefficients are irrelevant to polynomial length and a calculation stage, NTT / INTT / PWM access modes are unified, and hardware resource overhead is greatly reduced; and a conflict-free detection algorithm oriented to multi-channel assembly line design is adopted, so that the utilization rate of hardware resources is remarkably improved.

A system includes a substrate on which a first memory, a neural processing unit (NPU) including a plurality of processing elements (PEs) with multiplier-accumulator circuits, a controller, and a second memory, and a central processing unit (CPU) are disposed. The CPU may be configured to execute a universal compiler to perform a conversion for a particular neural network model into a machine code executable by the NPU and store the machine code in the first memory or the second memory. When the particular neural network model, generated by one among a plurality of machine learning frameworks that are incompatible with each other, is received and stored in the first memory, the universal compiler may perform the conversion based on mapping information indicating mapping between elements of machine learning frameworks and functions or operations executable by the CPU or NPU.

The invention relates to the technical field of artificial intelligence, in particular to an approximate multiplication method based on Point data and an arithmetic unit, and the method comprises the steps: carrying out the analysis processing of the obtained Point data, carrying out the splicing operation of the exponential expansion bit and the exponent of each piece of Point data, and determining a mantissa truncation bit width control signal according to the equivalent exponent bit of the Point data; two mantissa bits obtained through analysis are converted into logarithm domain tail values, truncation errors are compensated for the truncated logarithm domain tail values, error compensation is carried out on a logarithm domain mantissa product according to a numerical value interval where the logarithm domain tail values are located, and a linear domain equivalent index is processed and split to obtain an exponential expansion bit and an exponential bit of the product; through the design of the novel error compensation circuit, the calculation error is effectively reduced by using relatively low extra overhead, and the energy efficiency and the calculation precision of the Point multiplier are considered.

The invention discloses a parameter serial and parallel mixed input complex multiplication implementation method, which is implemented by adopting a complex multiplier circuit, and the complex multiplier circuit comprises a serial input cache unit, a parallel input cache unit, a real number multiplication unit and a real number addition / subtraction unit. The method comprises the specific implementation steps that S1, serial input complex number parameters and parallel input complex number parameters are sequentially input from a serial input cache unit and a parallel input cache unit respectively; s2, the serial input complex parameters and the parallel input complex parameters are subjected to combined calculation through a real number multiplication unit and a real number addition / subtraction unit; and S3, outputting a real part and an imaginary part of a complex multiplication result in sequence in a serial mode. Compared with a traditional and optimized triple multiplier version complex multiplication operation circuit, only a small number of registers are additionally arranged, latch resources are conditionally selected, and the complex multiplication operation circuit has obvious advantages in hardware resource consumption.

A unit for accumulating multiplied bit values includes an array of bit-line processors. The unit is implemented in an in-memory associative processor, and each bit-line processor includes multiple memory cells coupled to a bit-line. The array of processors is arranged in rows and columns. The array passes bits of a first multiplicand vertically down a column and provides bits of a second multiplicand horizontally across a row. The array generates carry bits and passes them vertically to a subsequent processor in the same column. The array also generates sum bits and passes them diagonally to a subsequent processor in an adjacent column. The array includes multiplying processors, summing processors, and accumulator processors. Multiplying processors perform an XOR operation by simultaneously activating two memory cells and then perform a full adder operation. Summing processors perform a full adder operation. Accumulator processors perform a full adder operation that includes a feedback sum bit from a previous cycle.

A matrix multiplier includes an input vector scaler configured to generate a scaled input matrix based on a first input matrix and a plurality of scaling factors; a first data type converter configured to convert a data type of the scaled input matrix into a fixed point and generate a fixed point input matrix; a multiply-accumulate operator array configured to receive the fixed-point input matrix and the plurality of binary vectors, generate a fixed-point output matrix based on the fixed-point input matrix and the plurality of binary vectors, generate a first input matrix and a second input matrix, and generate a first output matrix based on the first input matrix and the second input matrix; and a second data type converter configured to convert a data type of the fixed point output matrix into a floating point and generate a second output matrix.

The invention provides a phase error correction method for an inductive position sensor. The device is characterized by consisting of a first group of multipliers (1), a sliding window integrator (2) for solving a signal average value in a period of time, a second group of multipliers (3) and an adder group (4). The method can be used for correcting and eliminating the phase error in the inductive position sensor chip circuit, and can be widely applied to the fields of industrial robots, automobile manufacturing, industrial automation and the like.

The invention provides a multi-precision floating point fusion multiply-add structure and a microprocessor architecture, and the structure is characterized in that in a first-stage assembly line, an input preprocessing module decomposes an input operand to obtain a sign bit, an index bit and a mantissa bit; the Booth encoder generates partial products through a radix-4 Booth encoding algorithm, and the tree array multiplier compresses the partial products into three groups; in the second-stage assembly line, the CSA4-2 compression adder compresses the mantissa bits after the three groups of partial products and shift alignment into two groups; the summator module sums the two groups of partial products to obtain a mantissa summation result; in the third-stage assembly line package, a leading zero detection module performs leading zero detection on the mantissa summation result, and performs index adjustment and mantissa adjustment to obtain a normalized result; and in the fourth-stage assembly line, rounding of floating point data is carried out. According to the application, the operation performance, the energy efficiency ratio and the adaptability of the floating point fusion multiply-add structure are improved, so that the high performance and the high energy efficiency of the microprocessor are balanced.

The invention provides a low-power-consumption feed-forward equalizer circuit which comprises a grouping processing module which divides tap values of tap coefficients of the feed-forward equalizer circuit into a plurality of groups, each group comprises a plurality of tap values, and a tap combination value needing to be processed by each lookup table module is calculated; the lookup table module is used for storing the tap combination value which is calculated in advance and performing lookup operation according to the bit combination of the input data to generate an intermediate result; the clock gating trigger module is used for enabling a signal tapdata to be equal to 1 when a tap value is updated, completing updating of the tap value output by a register DFF, and closing an input clock of the DFF when the tap value is kept unchanged and the tapdata is equal to 0; the shift accumulation module performs weight shift operation on the intermediate results output by the lookup table module and then accumulates the intermediate results to generate a plurality of groups of tap value processing results; and the result output module outputs a final equalization signal of the feed-forward equalizer circuit. The FFE circuit is realized by converting the multiplier into the LUT table and the adder, and the power consumption of the FFE circuit is greatly reduced while the signal processing performance of the FFE circuit is ensured.

Here is postprocessing calibration of class probabilities inferred by a machine learning (ML) model, and this calibration is improved by generation of novel initial points that accelerate a genetic algorithm that optimizes fairness and accuracy of the ML model. Tri-objective optimization for multiplier tuning is enhanced by adding a “warm start” mechanism. Innovative designed points are high performance as follows. An identity point has all group multipliers set to 1.0, corresponding to the original model. By definition, this solution will have high accuracy scores and no outcome regression. A parity point has multipliers that have near-perfect disparity and outcome regression. This entails finding multipliers that provide every subgroup approximately the outcome rate of the subgroup with the highest outcome rate. An opportunity point has multipliers that give an approximation of the outcome rate given by an Equality of Opportunity algorithm. This solution provides near-optimal values for accuracy and disparity.

The invention relates to a convolution calculation unit and a sensor internal processing circuit, and the convolution calculation unit comprises a Gilbert multiplication circuit which is used for carrying out the voltage multiplication of a differential voltage of a processed image pixel value and a differential voltage of a weight of a convolution kernel; and the switched capacitor circuit is used for carrying out weighted calculation on the voltage multiplication result. The output bandwidth of the Gilbert multiplier is optimized on the basis of the Gilbert multiplier, the stability and the accuracy of the system are improved, the power consumption of the system can be further reduced by adopting the switched capacitor circuit to carry out weighting operation on the signal, the work and the turn-off of the system can be controlled by utilizing a time signal, and the power consumption of the system is reduced. And the system hardly consumes energy in a static state.

Devices, systems, and methods for reconfigurable butterfly architectures are provided. A reconfigurable butterfly operator circuit includes a single multiplier configured to receive a first variable and a twiddle factor and produce a product, first and second modular subtractors coupled to the multiplier, the first modular subtractor coupled to receive input coefficients and provide a modular difference, and the second modular subtractor coupled to receive the product, a modular adder coupled to receive the input coefficients and provide a modular sum, and multiplexers coupled to (i) provide the input coefficients to the modular adder, (ii) provide the first variable and the twiddle factor to the multiplier, (iii) and receive the modular difference from the first modular subtractor, respectively, each of the multiplexers coupled to receive a control signal that selects whether the circuit is configured as a Gentleman-Sande butterfly operator circuit or a Cooley-Tukey butterfly operator circuit.

The invention discloses a matrix multiplier, a chip, electronic equipment, a data processing method, a computer readable storage medium and a computer program product, and belongs to the field of artificial intelligence. The matrix multiplier comprises a multiplier array, a data preprocessing module and an accumulator; the multiplier array is configured to perform multiplication operation on an input first matrix and a second matrix; the data preprocessing module is configured to preprocess the third matrix to obtain a mask matrix; the accumulator is configured to add the multiplication result of the first matrix and the second matrix and the mask matrix; wherein the first matrix is an M * K matrix, the second matrix is a K * N matrix, the third matrix is an M * N matrix, and M, N and K are all integers greater than or equal to 1. According to the method, the mask process is fused into the matrix multiplication operation, so that the matrix multiplication operation and the mask adding operation can be synchronously carried out, and the calculation rate of the Attention (attention) operation is effectively improved.

According to the technical scheme, the large-scale logic optimization multiplier verification method is characterized in that a four-stage pipeline processing mode is adopted, the first stage is a partial adder tree recovery stage, and the second stage is a partial adder tree recovery stage; the second stage is an architecture generation stage; the third stage is a function verification stage; and the fourth stage is an equivalence checking stage. The verification capability is improved in a breakthrough manner and is far better than that of an existing method; the innovative three-stage decomposition strategy significantly reduces the calculation complexity, the ILP algorithm optimizes resource allocation, the multi-stage scheduling balances the calculation load, and the QACO algorithm efficiently explores the design space, so that the RefSCAT-2.0 framework provided by the invention becomes the most effective solution for verifying a large-scale logic optimization multiplier at present. From the perspective of practice, the technical blank of large-scale logic optimization multiplier verification is filled up, and important tool support is provided for reliability guarantee of key computing systems such as artificial intelligence chips, high-performance CPUs and GPUs.

The invention discloses a Tranformer network-oriented hybrid precision multiplier, which is applied to an FPGA (Field Programmable Gate Array), and is used for allocating a target high-resolution image according to the weight precision of the weight data of the current layer of the target Tranformer network, the feature map precision of the feature map data of the target high-resolution image and a preset data allocation rule. Determining a first quantity of weight data and a second quantity of feature map data of a single calculation cycle; according to the first quantity of weight data and the second quantity of feature map data, recoding the weight data and the feature map data after determining a target recoding algorithm to obtain weight coded data and feature map coded data; performing multiplication calculation on the weight coding data and the feature map coding data in a single calculation period to obtain an initial product result of the single calculation period; and decoding the initial product result, and merging the multiple sub-feature map data of all the calculation periods corresponding to the current layer of the target Transform network to obtain target feature map data. According to the method, the resource utilization rate is improved on the basis of ensuring the model precision.

The invention relates to the technical field of video coding, and discloses a low-frequency inseparable quadratic transformation multiplier efficient hardware architecture system, which comprises a control module, a selection module, a core module, an accumulation module and a rounding module, and is characterized in that the control module generates a sub-region index and a constant selection signal; the selection module extracts corresponding transformation constant input; the core module executes matrix multiplication operation on one 8 * 16 sub-region in each processing period, and each column of multipliers share the same group of input data; the accumulation module accumulates the multiplication result in the row direction; and the rounding module carries out rounding processing on the accumulation result and outputs a final conversion result. Through the measures of balancing the utilization rate of the multiplier under different transformation unit sizes, reducing invalid multiplication operation, introducing a coefficient approximation scheme to optimize a hardware circuit structure and the like, the calculation efficiency is improved, the hardware area and power consumption are reduced, and the high-resolution real-time coding requirement is met.

An analog multiplier accumulator array comprises analog multipliers organized in a matrix of rows and columns, each of the multiplier comprising one or more than one analog input signal line coupled to the analog multipliers in a row of the array; an analog level sensing circuit; a set of bit lines, each bit line electrically connected to the analog multiplier in each column of the row; and an analog accumulator configured to connect the set of the bit lines to an analog level sensing circuit for generating digital output signals, wherein an access transistor connected to the analog input line and a variable resistor form the analog multiplier.

To reduce the area requirements for sensing circuits of 3D NAND-based vector-matrix multiplication circuitry where weight values for a neural network are stored differentially as current levels on pairs of memory cells, techniques are presented for reducing the common mode current levels during sensing operations. When discharging a first capacitor through a first of a memory cell of a pair of memory cells storing a weight value by a first bit line and discharging second capacitor through a second memory cell of the pair by a second bit line, a reference current is applied to the bit lines. The product of a weight value with an input vector values is then determined by comparing the voltage levels on the two capacitors. The use of the reference current reduces the amount of voltage swing in the two capacitors, reducing the size requirements for the capacitors.

The invention discloses an FPGA (Field Programmable Gate Array) coprocessor for accelerated execution of an intelligent contract, which belongs to the field of hardware acceleration and comprises a controller module, an operation module, a memory module and a stack module, the controller module is used for receiving a byte code instruction of an external smart contract and generating a control signal to control the operation module to carry out corresponding operation and / or the stack module to carry out corresponding operation; the memory module is used for receiving and storing to-be-operated data output by the smart contract and outputting corresponding operation data to the stack module, and then the stack module inputs the data to the operation module; the operation module comprises a calculator module, a multiplier module, a divider module and a hash operation module; and the stack module is used for storing the data obtained by the calculation of the operation module, and can also execute the operations of in-stack, out-stack, copying and exchange according to the control of the control signal, and outputting the data stored in the stack module to the memory module. The method is suitable for block chains and other high-performance computing applications.

The invention relates to a phased-array antenna phase resolving method and device based on a programmable logic gate array. A trigonometric function value is calculated through a Cordic algorithm, fixed parameters in a unit phase difference formula are preset as constants to reduce real-time multiplication and division operation, array element phase difference is calculated in a cyclic accumulation or multiplier grouping mode, efficiency is improved by means of FPGA parallel capacity, phase quantization is achieved through divider parallel fixed-point operation or dichotomy table look-up, and phase quantization is achieved. The problems that in a traditional scheme, FPGA resource consumption is large, and calculation efficiency is low are effectively solved, efficient and low-power-consumption phase calculation can be achieved under a resource sensitive framework, and the requirements of a large-scale phased-array antenna for real-time performance and low cost are met.

Technologies for a jitter injection generator and a spectrum hardware engine for measuring and assessing phase noise and a jitter transfer function are described. One communication device includes a timing and synchronization circuit that generates a signal with time-domain data, and a spectrum hardware engine that converts this data into frequency-domain data. The spectrum hardware engine has registers storing past outputs, multipliers for computing products using these values and a pre-computed coefficient, and a summation block for combining the current input with these products to get the current output. This output is sent to a computing device to estimate phase noise.

The invention discloses an approximate multiplier, an operation method thereof, a processor and a chip, and belongs to the field of integrated circuits. The approximate multiplier comprises a high-order processing circuit, a low-order processing circuit, a high-low-order fusion circuit and an error compensation circuit, and the high-order processing circuit adopts a plurality of negative deviation approximate addition units, performs approximate addition on a high-order area of a partial product step by step and outputs an error signal; the low-order processing circuit adopts a positive deviation addition unit to process the low-order area to generate an intermediate result of positive deviation; the fusion circuit merges the high and low position results and outputs an initial multiplication result; the error compensation circuit compensates the result high order according to the error signal to offset the deviation. According to the approximate multiplier provided by the invention, the comprehensive performance of the multiplication unit in the aspects of area, power consumption and speed can be improved while the basic calculation precision is ensured.