459 results about "Binary multiplier" patented technology

The invention discloses a high-energy-efficiency logarithm floating point multiplier based on truncation error compensation. The system comprises a compensation parameter modeling unit and a floating point multiplier module. The compensation parameter modeling unit obtains an optimal compensation value k through linear fitting and parameter optimization, and realizes regional self-adaptive compensation in combination with block modeling so as to reduce truncation errors; the floating point multiplier module comprises a special value detection module, a symbol exclusive or module, an exponential addition module and a mantissa truncation compensation module. In a logarithm domain, multiplication is replaced by addition, and compensation logic is introduced to correct errors. The multiplier supports various floating point precisions and configurable truncation bit widths, provides three representative structures to give consideration to both the precision and the energy efficiency, and is suitable for high-energy-efficiency calculation scenes such as neural networks and image processing.

The embodiment of the invention discloses an internal memory, a chip and related electronic equipment. A target computing unit of the internal memory comprises a plurality of groups of primary multipliers, a plurality of adder trees and a plurality of secondary multipliers, one group of first-level multipliers is connected with one second-level multiplier through one adder tree; the group of first-level multipliers comprises a plurality of pairs of first multipliers, and each adder tree comprises a first adder, a second adder and a third adder; each pair of first multipliers respectively receive data to perform multiplication operation, and respectively input output results into the first adder to perform addition operation; each second adder receives the output results of the plurality of first adders or the second adder at the upper level to carry out addition operation, and respectively inputs the output results to the second adder at the lower level or the third adder; and each third adder receives the output results of the plurality of second adders to carry out addition operation, and inputs the output results to the secondary multiplier to carry out multiplication operation. By implementing the embodiment of the invention, the memory computing capability can be improved.

The invention discloses a high-precision face recognition method and system which are suitable for complex illumination and unconstrained position scenes. The method is realized through cooperation of a multi-modal acquisition guide strategy driven by a state machine and a self-adaptive fusion mechanism based on a physical multiplier array: the state machine controls logic to generate a position-attitude sequence instruction, and drives a user to synchronously provide RGB-NIR image pairs in upper, middle and lower screen areas and left and right side face attitudes; the double-flow convolutional neural network extracts an aligned bimodal feature map through shared weight constraint; the attention fusion module dynamically generates a space-channel joint attention weight based on a local signal-to-noise ratio difference through a multiplier array and a weight register realized by hardware, and performs pixel-by-pixel weighted fusion on the bimodal features. And a physical mapping relation between state machine position change and modal weight distribution is established through coupling training. According to the invention, through algorithm hardening and hardware cooperation, the accuracy and real-time performance of cross-illumination and cross-position unconstrained face recognition are significantly improved.

The invention relates to a reconfigurable multi-channel polynomial multiplier architecture and an implementation method thereof, and belongs to the technical field of post-quantum cryptography hardware acceleration. The architecture comprises a scheduler, a twiddle factor memory bank, a bank address routing module, a bank array and a reconfigurable butterfly unit array. According to the architecture, a cyclic decoupling multi-channel NTT / INTT / PWM algorithm is used, flexible configuration of the degree of parallelism and the flow line depth can be supported, and the adaptability of a memory access control strategy is improved; a conflict-free memory mapping scheme based on interleaved storage is adopted, so that storage and read-write of polynomial coefficients are irrelevant to polynomial length and a calculation stage, NTT / INTT / PWM access modes are unified, and hardware resource overhead is greatly reduced; and a conflict-free detection algorithm oriented to multi-channel assembly line design is adopted, so that the utilization rate of hardware resources is remarkably improved.

A unit for accumulating multiplied bit values includes an array of bit-line processors. The unit is implemented in an in-memory associative processor, and each bit-line processor includes multiple memory cells coupled to a bit-line. The array of processors is arranged in rows and columns. The array passes bits of a first multiplicand vertically down a column and provides bits of a second multiplicand horizontally across a row. The array generates carry bits and passes them vertically to a subsequent processor in the same column. The array also generates sum bits and passes them diagonally to a subsequent processor in an adjacent column. The array includes multiplying processors, summing processors, and accumulator processors. Multiplying processors perform an XOR operation by simultaneously activating two memory cells and then perform a full adder operation. Summing processors perform a full adder operation. Accumulator processors perform a full adder operation that includes a feedback sum bit from a previous cycle.

The invention provides a phase error correction method for an inductive position sensor. The device is characterized by consisting of a first group of multipliers (1), a sliding window integrator (2) for solving a signal average value in a period of time, a second group of multipliers (3) and an adder group (4). The method can be used for correcting and eliminating the phase error in the inductive position sensor chip circuit, and can be widely applied to the fields of industrial robots, automobile manufacturing, industrial automation and the like.

Devices, systems, and methods for reconfigurable butterfly architectures are provided. A reconfigurable butterfly operator circuit includes a single multiplier configured to receive a first variable and a twiddle factor and produce a product, first and second modular subtractors coupled to the multiplier, the first modular subtractor coupled to receive input coefficients and provide a modular difference, and the second modular subtractor coupled to receive the product, a modular adder coupled to receive the input coefficients and provide a modular sum, and multiplexers coupled to (i) provide the input coefficients to the modular adder, (ii) provide the first variable and the twiddle factor to the multiplier, (iii) and receive the modular difference from the first modular subtractor, respectively, each of the multiplexers coupled to receive a control signal that selects whether the circuit is configured as a Gentleman-Sande butterfly operator circuit or a Cooley-Tukey butterfly operator circuit.

According to the technical scheme, the large-scale logic optimization multiplier verification method is characterized in that a four-stage pipeline processing mode is adopted, the first stage is a partial adder tree recovery stage, and the second stage is a partial adder tree recovery stage; the second stage is an architecture generation stage; the third stage is a function verification stage; and the fourth stage is an equivalence checking stage. The verification capability is improved in a breakthrough manner and is far better than that of an existing method; the innovative three-stage decomposition strategy significantly reduces the calculation complexity, the ILP algorithm optimizes resource allocation, the multi-stage scheduling balances the calculation load, and the QACO algorithm efficiently explores the design space, so that the RefSCAT-2.0 framework provided by the invention becomes the most effective solution for verifying a large-scale logic optimization multiplier at present. From the perspective of practice, the technical blank of large-scale logic optimization multiplier verification is filled up, and important tool support is provided for reliability guarantee of key computing systems such as artificial intelligence chips, high-performance CPUs and GPUs.

To reduce the area requirements for sensing circuits of 3D NAND-based vector-matrix multiplication circuitry where weight values for a neural network are stored differentially as current levels on pairs of memory cells, techniques are presented for reducing the common mode current levels during sensing operations. When discharging a first capacitor through a first of a memory cell of a pair of memory cells storing a weight value by a first bit line and discharging second capacitor through a second memory cell of the pair by a second bit line, a reference current is applied to the bit lines. The product of a weight value with an input vector values is then determined by comparing the voltage levels on the two capacitors. The use of the reference current reduces the amount of voltage swing in the two capacitors, reducing the size requirements for the capacitors.

Technologies for a jitter injection generator and a spectrum hardware engine for measuring and assessing phase noise and a jitter transfer function are described. One communication device includes a timing and synchronization circuit that generates a signal with time-domain data, and a spectrum hardware engine that converts this data into frequency-domain data. The spectrum hardware engine has registers storing past outputs, multipliers for computing products using these values and a pre-computed coefficient, and a summation block for combining the current input with these products to get the current output. This output is sent to a computing device to estimate phase noise.

The invention discloses an approximate multiplier, an operation method thereof, a processor and a chip, and belongs to the field of integrated circuits. The approximate multiplier comprises a high-order processing circuit, a low-order processing circuit, a high-low-order fusion circuit and an error compensation circuit, and the high-order processing circuit adopts a plurality of negative deviation approximate addition units, performs approximate addition on a high-order area of a partial product step by step and outputs an error signal; the low-order processing circuit adopts a positive deviation addition unit to process the low-order area to generate an intermediate result of positive deviation; the fusion circuit merges the high and low position results and outputs an initial multiplication result; the error compensation circuit compensates the result high order according to the error signal to offset the deviation. According to the approximate multiplier provided by the invention, the comprehensive performance of the multiplication unit in the aspects of area, power consumption and speed can be improved while the basic calculation precision is ensured.

An apparatus to facilitate supporting 8-bit floating point format operands in a computing architecture is disclosed. The apparatus includes a processor comprising: a decoder to decode an instruction fetched for execution into a decoded instruction, wherein the decoded instruction is a matrix instruction that operates on 8-bit floating point operands to cause the processor to perform a parallel dot product operation; a controller to schedule the decoded instruction and provide input data for the 8-bit floating point operands in accordance with an 8-bit floating data format indicated by the decoded instruction; and systolic dot product circuitry to execute the decoded instruction using systolic layers, each systolic layer comprises one or more sets of interconnected multipliers, shifters, and adder, each set of multipliers, shifters, and adders to generate a dot product of the 8-bit floating point operands.

Systems and methods for a new field programmable gate array (FPGA) architecture that is optimized for machine learning (ML) applications are provided. Such ML applications can specifically include, for example, artificial neural networks and deep neural networks. Various embodiments enable the design of faster and more power efficient hardware accelerators for machine learning algorithms, compared to existing FPGAs in the market. This is made possible by hard systolic matrix multiplier blocks, hard activation blocks and soft ML-centric configurable logic blocks. The matrix multiplier blocks are connected to field programmable interconnect resources to enable creation of larger matrix multipliers. The hard matrix multipliers and the hard activation blocks have programmable interconnects between them and neighboring memory or compute blocks on the device.

The application provides a kind of approximate precoding convolution operation method and system based on booth algorithm, comprising: step S1: multiplier and multiplicand input multiplier are separated by approximate precoding module to partial product, and the partial product related to the multiplicand after separation is input to addition tree module to complete compression, and the partial product related to the multiplicand after compression and the partial product related to the multiplier are added to obtain multiplier result;Step S2: the multiplier result is extended to sign bit, and the extended multiplier result is input into accumulation module to carry out shift and addition operation, and the shift addition operation result is carried out carry compensation.

Provided are a hardware implementation method and a hardware implementation device of a Montgomery algorithm. A REDC operation of the Montgomery algorithm includes a first multiplication operation, a second multiplication operation, a third multiplication operation, a fourth multiplication operation, and a subtraction operation, the third multiplication operation depends on a result of the second multiplication operation, a clock cycle for the REDC operation includes a first clock cycle for multiplication operation and a second clock cycle for subtraction operation, the hardware implementation method includes: replacing the second clock cycle with an additional clock cycle for multiplication operation by adjusting a calculation flow of the REDC operation; performing the first multiplication operation, the second multiplication operation, and the third multiplication operation by a first multiplier, wherein the first multiplication operation includes a first multiplier and a second multiplier; and performing the fourth multiplication operation by a second multiplier. The hardware implementation method can save multiplier resources without reducing hardware performance.

The precision capacitance micrometer system comprises a modulation signal source, a sensitive probe, a differential transformer bridge circuit, a signal amplification link, a multiplier and a low-pass filter circuit which are electrically connected in sequence, a double-limit comparator is arranged between the signal amplification link and the multiplier; the input end of the double-limit comparator is connected with the output end of the signal amplification link, the output end of the double-limit comparator is connected to one input end of the multiplier, and the double-limit comparator is used for shaping the amplified modulation signal and taking the shaped signal as the demodulation input signal. The invention also provides a precise capacitance micrometer method. The precise capacitance micrometer system provided by the embodiment of the invention ensures that the system output is insensitive to phase difference fluctuation within a certain demodulation phase difference range, and finally realizes high-precision measurement of micro displacement. All the modules complete full-link conversion from physical quantity to measurable voltage signals through step-by-step signal transmission and function complementation.

The application discloses a CS101 testing device and method suitable for GJB151 standards, and relates to the technical field of testing devices, and specifically discloses a testing device, which comprises a control module, a waveform generating module, an analog-digital conversion module and a high-speed multiplier module, wherein the control module is connected to the waveform generating module, the analog-digital conversion module and the high-speed multiplier module; the waveform generating module and the analog-digital conversion module are respectively connected to the high-speed multiplier module, and the high-speed multiplier module is used for outputting ripple. The testing device and the testing method of the application replace the complicated manual control of the measuring range and other parameters of an oscilloscope or a receiver by a tester, save a large amount of manpower and time cost, do not need to replace different filters according to different testing frequencies, reduce cost and save time, avoid measurement errors caused by replacement of different filters, reduce the cost of purchasing a signal source, and do not need manual operation, so that complete automatic control of signals is realized.

Systems, devices, methods, and circuits for managing failures of in-memory computing (IMC) devices. An example memory device includes: a plurality of memory units and a circuitry configured for execution of a computing instruction in one or more memory units. A memory unit includes: a memory cell array and a peripheral circuit including a plurality of subcircuits coupled to the memory cell array. Each subcircuit includes: one or more internal sense amplifiers, one or more latches, and one or more multipliers. The circuitry is configured to: determine whether a subcircuit is defective by determining whether at least one of an internal sense amplifier, a latch, or a multiplier in the subcircuit is defective using an external sense amplifier external to the memory unit, and in response to determining that the subcircuit is defective, perform one or more corresponding actions including replacing the subcircuit with a redundant subcircuit in the peripheral circuit.

Systems, apparatus, articles of manufacture, and methods are disclosed. An example apparatus includes a Vector Processor Unit (VPU) comprising: first vector lane circuitry including first matrix multiplier circuitry; second vector lane circuitry including second matrix multiplier circuitry; and interconnect circuitry to connect the first vector lane circuitry and the second vector lane circuitry in a ring structure.

Disclosed in the embodiments of the present application are an internal memory, a chip and a related electronic device. A target processing unit (202) of an internal memory (102) comprises a plurality of groups of primary multipliers, a plurality of adder trees and a plurality of secondary multipliers, wherein one group of primary multipliers is connected to one secondary multiplier by means of one adder tree; one group of primary multipliers comprises a plurality of pairs of first multipliers; each adder tree comprises a first adder, a second adder and a third adder; each pair of first multipliers separately receives data to perform multiplication operations, and separately inputs output results into one first adder for addition operations; each second adder receives output results of a plurality of first adders or the upper-level second adder, so as to perform addition operations, and separately inputs the output results into the lower-level second adder or one third adder; and each third adder receives output results of a plurality of second adders to perform addition operations, and inputs the output results into one secondary multiplier for multiplication operations. Implementing the embodiments of the present application can improve the processing capability of the internal memory.

An apparatus and method for in-memory computation with weight update circuitry. The apparatus includes a memory array for storing a plurality of weight sets and a read circuit for reading the plurality of weight sets. The first weight buffer is used for storing a first weight set in a plurality of weight sets, and the write driver circuit is used for writing the first weight set into the first weight buffer during a single write clock pulse period. A plurality of first multiplier circuits receive a first set of weights from the first weight buffer and a first set of data inputs from the data input channels 0-N. Each of the first multiplier circuits receives a corresponding first weight of the first set of weights and a first data input of the first set of data inputs, and multiplies the first weight with the first data input to provide a partial product. The adder tree is used for summing the partial products and providing an accumulation result.

The present disclosure relates to a processing device, comprising: a storage part for storing data, the data comprising to-be-operated data of a neural network; an operation part for operating the to-be-operated data, comprising accelerating the to-be-operated data by using an adder and / or a multi-type multiplier; and a control part for controlling the storage part and the operation part, comprising accelerating operation according to the to-be-operated data. The device of the present disclosure has the advantages of high flexibility, high configurability, fast operation speed, low power consumption, etc.

The invention discloses a structured sparse matrix multiplier realized based on FPGA primitives, and belongs to the technical field of FPGA hardware acceleration and deep learning computing architecture. The multiplier is composed of a register area and a multiplication and addition area, and the core design thought is that a circuit is built in a customized mode by directly calling bottom layer physical resources based on FPGA primitives; the register area stores a dense matrix B and supports parallel reading of elements by utilizing the characteristic that LUT in an SLICEM can be configured to be double SRL16E; the multiplication and addition area refers to a partial product generation unit based on the 4-Booth algorithm and an improved GPC (4: 2) compressor structure, and efficient generation and rapid accumulation of partial products are achieved. According to the method, redundant loss caused by high-level HDL logic synthesis is avoided through precise physical resource binding of primitives, fine wiring constraint and structured sparse data characteristic adaptation.

Aspects relate to photonic computing systems and methods of optically performing matrix vector multiplication. A photonic computing system includes a light source configured to generate a plurality of input optical signals having mutually different wavelengths, a plurality of optical encoders configured to encode the plurality of input optical signals with respective input values, a first wavelength division multiplexer (WDM) configured to spatially combine the encoded plurality of input optical signals into an input waveguide, a photonic multiplier coupled to the input waveguide and configured to generate a plurality of output optical signals each encoded with a respective output value representing a product of the respective input value and a common weight value, and a second WDM coupled to the photonic multiplier and configured to spatially separate the plurality of output optical signals.

The application discloses a quantum image multiplication operation method and device and electronic equipment, and relates to the field of quantum operation, and solves the problem of low performance of a quantum image multiplication operation algorithm in the prior art, and the technical solution points are as follows: a plurality of quantum images with shared position information and in a superposition state are prepared based on a NEQR quantum image representation model; any two quantum images in the plurality of quantum images are subjected to multiplication operation processing based on a quantum multiplier, and a matrix of pixel values of the quantum image is obtained; information of each pixel point in the matrix of pixel values of the quantum image is extracted, and the information is converted into classical image information; wherein, the operation steps of quantum multiplication are improved according to binary multiplication, the quantum multiplication improved based on binary multiplication is designed by using a Toffoli gate and a quantum full adder, and a quantum multiplier is obtained. The application improves the performance of a quantum image expression algorithm, and makes it easier to simulate under a classical computer.

The invention relates to a floating-point number multiplier, a computing chip and a floating-point number multiplication operation method, and belongs to the technical field of computers. According to the floating-point number multiplier, floating-point multiplication of a target floating-point number type is performed on input data by utilizing multiplication mode indication, the floating-point number type is specified as the floating-point number type of floating-point numbers in the input data, the floating-point numbers in the input data are divided into data groups by preprocessing the input data, and the floating-point numbers in the input data are divided into the data groups based on a target multiplication mode. According to the invention, the floating point data in the same data set is subjected to floating point number type floating point number multiplication operation, so that the floating point number multiplier can perform floating point number multiplication operation of various floating point number types by specifying different multiplication modes for input data of different floating point number types; therefore, the operation requirements of floating-point number multiplication of various floating-point number types can be met.

The invention discloses a two-channel biorthogonal filter bank FPGA (Field Programmable Gate Array) implementation method based on matrix decomposition. The method comprises the following steps: for a two-channel biorthogonal filter bank, firstly determining an initial coefficient of a filter, then decomposing the initial coefficient into a coefficient retention sequence and a coefficient matrix, and further decomposing the coefficient matrix into a common matrix, a low-pass branch matrix and a high-pass branch matrix through common-base N-dimensional intercepted LU decomposition; the FPGA implementation scheme is designed by combining the structural characteristics of the two-channel biorthogonal filter bank and adopting the time division multiplexing technology, the number of multipliers is effectively reduced through efficient multiplexing of a multi-phase structure and the multipliers, and the hardware resource overhead in FPGA implementation is remarkably reduced. On the premise that orthogonality and reconstruction precision of the filter bank are guaranteed, operation efficiency and data throughput capacity of the system are improved, and a feasible and efficient solution is provided for FPGA implementation of a high-performance and real-time signal processing system.

Neuromorphic integrated circuit, including: a multi-layered neural network that exists in an analog A multiplier array of a plurality of two-quadrant multipliers is arranged in a memory sector of the neuromorphic integrated circuit, wherein at least one or more of the plurality of two-quadrant multipliers is a bias-free two-quadrant multiplier. wherein each multiplier of the multipliers is connected to ground and draws a small amount of current when input signal values ​​for input signals to transistors of the multiplier are approximately zero, weighting values ​​of the transistors of the multiplier are approximately zero, or a combination thereof is true, and where the efficiency in the neural network, in combination with the number of multipliers wired to ground, minimizes the energy consumption of the neuromorphic integrated circuit.

The invention discloses a dynamic scene-oriented beam former dimensionality reduction sparse design method, which adopts a polynomial structure to flexibly realize continuous beam pointing through simple online parameter adjustment, and according to the rule that even-order filter coefficients are the same and odd-order filter coefficients are opposite in the polynomial structure, the continuous beam pointing is realized. The dimensionality of sparse design is reduced by simplifying a polynomial structure, so that the optimization efficiency is improved, the sparse symmetry of a weight coefficient of the beam former is derived by utilizing a symmetry theory of an array, a dimensionality reduction sparse optimization model of the polynomial structure beam former is constructed on the basis, and a corresponding optimization algorithm is provided for the dimensionality reduction sparse optimization model. Compared with an original sparse design and a dimensionality reduction design, under the condition that the beam performance is almost unchanged, only half of weight coefficients need to be optimized, meanwhile, the number of adders and multipliers needed for achieving the polynomial structure beam former is reduced by nearly half, and the achieving complexity of the polynomial structure beam former is effectively reduced.