1037 results about "Binary multiplier" patented technology

An apparatus for facilitating support of 8-bit floating point format operands in a computing architecture is disclosed. In one embodiment, the apparatus includes a processor comprising: a decoder to decode an instruction fetched for execution into a decoded instruction, where the decoded instruction is a matrix instruction that operates on an 8-bit floating point operand to cause the processor to perform a parallel dot product operation; a controller to schedule the decoded instruction and provide input data for an 8-bit floating point operand according to an 8-bit floating point data format indicated by the decoded instruction; and a pulsation dot product circuit to execute the decoded instruction using pulsation layers, each pulsation layer comprising one or more sets of interconnected multipliers, shifters and adders, each set of multipliers, shifters and adders to generate a dot product of 8-bit floating point operands.

The invention discloses a demodulation device, a rotary digital converter and a storage medium, relates to the technical field of rotary digital converters, and discloses the demodulation device, the rotary digital converter and the storage medium. Comprising an input processing module, a primary multiplier module and an output processing module which are sequentially connected in series, wherein the input processing module is used for searching and combining according to accessed phase information; the primary multiplier module is used for multiplying according to an accessed excitation signal and a modulation signal to obtain a signal to be output; the output processing module is used for adding the accessed signal to be output to output a demodulation signal; the input processing module is used for searching and combining, the excitation signal is generated under the condition that a multiplier is not needed, the demodulation signal can be generated only through the first-stage multiplier module and the output processing module, the hardware cost of part of multipliers is reduced, one-time quantization errors are avoided, and the decoding efficiency is improved. Therefore, the error of the demodulated signal is reduced, and the accuracy of the demodulated signal is improved to a certain extent.

The invention discloses a high-energy-efficiency logarithm floating point multiplier based on truncation error compensation. The system comprises a compensation parameter modeling unit and a floating point multiplier module. The compensation parameter modeling unit obtains an optimal compensation value k through linear fitting and parameter optimization, and realizes regional self-adaptive compensation in combination with block modeling so as to reduce truncation errors; the floating point multiplier module comprises a special value detection module, a symbol exclusive or module, an exponential addition module and a mantissa truncation compensation module. In a logarithm domain, multiplication is replaced by addition, and compensation logic is introduced to correct errors. The multiplier supports various floating point precisions and configurable truncation bit widths, provides three representative structures to give consideration to both the precision and the energy efficiency, and is suitable for high-energy-efficiency calculation scenes such as neural networks and image processing.

The present application relates to the technical field of integrated circuits and relates to a matrix operation apparatus based on a flexible RRAM memory-computing array, and solves the problem in the prior art of the inability to reduce the area of the memory-computing array without affecting the precision. The apparatus comprises: the flexible RRAM memory-computing array for outputting cumulative currents of columns of memory-computing units to a multiplexer (MUX) on the basis of multiple rows of inputs; the MUX for selecting the cumulative current of one column of memory-computing units from among the columns of memory-computing units and sending said cumulative current to an analog-to-digital converter (ADC); the ADC for converting the received cumulative current into a digital signal and sending said digital signal to a subtractor; a popcount module for receiving the multiple rows of inputs, obtaining the number of 1 in the multiple rows of inputs, and outputting the number of 1 to a multiplier; the multiplier for multiplying the number of 1 by a fixed value β and sending a product result to the subtractor; and the subtractor for subtracting the product result from the digital signal to obtain a multiply-accumulate result of the matrix. The present application realizes high-precision memory-computing based on a small-area memory-computing array, further enhances energy efficiency, and can be applied to flexible computing chips to create electronic skin.

A logarithmic amplifier system is disclosed. The system includes first and second amplifiers respectively having first and second gains; a first multiplier having an input connected to an output of the first amplifier, and being configured to output a first multiplied signal based on an output signal of the first amplifier and based on a received first multiplication factor equal to a value K; a second multiplier having an input connected to an output of the second amplifier, and being configured to output a second multiplied signal based on an output signal of the second amplifier and based on a received second multiplication factor equal to 1 minus the value K; a transition shaping circuit configured to change the value K from 0 to 1 with a filtered transfer function; and a summing circuit having inputs coupled to outputs of the first multiplier and the second multiplier.

The invention provides a bit slice accelerator for efficient convolutional neural network reasoning, and belongs to the field of neural network reasoning hardware. The bit slice accelerator comprises a lookup table (LUT)-based multiplier which comprises a bit operation analysis unit (BMAU) and a bit level multiplier unit; and the BMAU manages bit-level multiplication operation by utilizing an LUT mechanism and performs bit field division on input data, and the bit-level multiplier unit processes groups of continuous multiplier bits after bit field division so as to realize bit-level data processing. According to the bit slice accelerator provided by the invention, through the multiplier based on the lookup table LUT, the BMAU of the integrated bit level and the bit level multiplier unit are included, and operation of different bit widths is supported; data sparsity can be effectively utilized in DNN reasoning, and reasoning efficiency and energy efficiency in a limited environment are remarkably improved.

An even harmonic multiplier employing complementary current reuse is disclosed. The even harmonic multiplier employs supply voltage and current density scaling to reduce power consumption. Further, by using complimentary NMOS and PMOS transistors, the even harmonic multiplier achieves high areal efficiency. Current reuse causes a reduction in noise at the first harmonic, as the corresponding first harmonic currents from the NMOS and PMOS transistors are in opposite, i.e., canceling, directions. Complementary current reuse is now feasible, as the performance of PMOS transistors at current process nodes is similar to those of NMOS transistors, with appropriate sizing leading to approximately equivalent transconductances. Multiple even harmonic multiplier configurations are possible, with many using transformer circuits at the input and / or the output. The resultant even harmonic multipliers find ready application in millimeter wave radio frequency receivers. The most common even harmonic multiplier is a frequency doubler, which produces a strong second harmonic signal.

The embodiment of the invention discloses an internal memory, a chip and related electronic equipment. A target computing unit of the internal memory comprises a plurality of groups of primary multipliers, a plurality of adder trees and a plurality of secondary multipliers, one group of first-level multipliers is connected with one second-level multiplier through one adder tree; the group of first-level multipliers comprises a plurality of pairs of first multipliers, and each adder tree comprises a first adder, a second adder and a third adder; each pair of first multipliers respectively receive data to perform multiplication operation, and respectively input output results into the first adder to perform addition operation; each second adder receives the output results of the plurality of first adders or the second adder at the upper level to carry out addition operation, and respectively inputs the output results to the second adder at the lower level or the third adder; and each third adder receives the output results of the plurality of second adders to carry out addition operation, and inputs the output results to the secondary multiplier to carry out multiplication operation. By implementing the embodiment of the invention, the memory computing capability can be improved.

The invention discloses a high-precision face recognition method and system which are suitable for complex illumination and unconstrained position scenes. The method is realized through cooperation of a multi-modal acquisition guide strategy driven by a state machine and a self-adaptive fusion mechanism based on a physical multiplier array: the state machine controls logic to generate a position-attitude sequence instruction, and drives a user to synchronously provide RGB-NIR image pairs in upper, middle and lower screen areas and left and right side face attitudes; the double-flow convolutional neural network extracts an aligned bimodal feature map through shared weight constraint; the attention fusion module dynamically generates a space-channel joint attention weight based on a local signal-to-noise ratio difference through a multiplier array and a weight register realized by hardware, and performs pixel-by-pixel weighted fusion on the bimodal features. And a physical mapping relation between state machine position change and modal weight distribution is established through coupling training. According to the invention, through algorithm hardening and hardware cooperation, the accuracy and real-time performance of cross-illumination and cross-position unconstrained face recognition are significantly improved.

The invention provides a universal Transform acceleration method and system based on floating point instruction set extension, and the method comprises the steps: constructing a multiplier which comprises a plurality of stages of adders and a 4-Booth coding algorithm which are connected in sequence, and coding data; the coded data is operated through a plurality of stages of adders in sequence to obtain the output of a multiplier; the construction of the floating-point number register comprises the following specific steps: adding a floating-point number register group, generating the floating-point number register group, enabling input result register indexes to correspond to respective register numbers by writing port logic of the floating-point number register group, generating a writing enable signal, writing data into the register by an enabled general register, and writing the data into the floating-point number register group. The read port is realized by using a multi-path parallel selector, and a selection signal of the multi-path parallel selector is an index of a read operand register; and the RISC-V processor accelerates the operation of the Transform neural network based on the constructed multiplier and the floating-point number register.

The invention discloses a logic design system for controller hardware acceleration, which relates to the technical field of controllers and comprises a target column extractor, a long-bit-width parallel comparator, a matrix multiplier and a truth table lookup device. The target column extractor is used for extracting target column data information from a preset page and sending the target column data information to the long-bit-width parallel comparator; the target column extractor does not need to read the column data information one by one, but directly reads the target column data information, so that the reading speed can be increased. Further, the long-bit-width parallel comparator is used for copying the target column data information to the corresponding long-bit-width register according to the data type, obtaining a comparison result according to the comparison operation instruction code and the target column data information, and sending the comparison result to the matrix multiplier; as the long-bit-width parallel comparator can compare the target column data information in parallel, the throughput rate of database calculation can be effectively improved, and the delay rate is reduced.

The invention relates to transcendental function calculation, in particular to a resource reuse type transcendental function calculation device and method, and the device comprises a selector which receives input data, a data type and a control signal, and transmits the input data and the data type to a corresponding processing unit PE according to the control signal; the processing unit PE can process all types of transcendental functions and perform transcendental function calculation on input data according to data types; the result output unit is used for splicing the calculation results of the plurality of processing units PE in sequence to obtain output data; when all the processing units PE perform transcendental function calculation, the lookup table, the fixed-point multiplier, the floating-point multiplier and the floating-point adder are multiplexed; according to the technical scheme provided by the invention, the defect that the transcendental function is difficult to accurately calculate by using fewer hardware resources in the prior art can be effectively overcome.

The invention discloses an approximate floating point multiplier, a chip and computing equipment, an approximate mantissa multiplier of the approximate floating point multiplier comprises an AND logic unit and a compressor unit, and the AND logic unit is used for performing AND operation on two input operands bit by bit to generate a partial product array with the size of 11 rows and 21 columns; the compressor unit is used for compressing the 11th column to the 21st column by column to obtain a final approximate mantissa, the compressor unit comprises two novel approximate 4-2 compressors ignoring carry design, and the error rate of the approximate 4-2 compressors is within an acceptable range by utilizing mutual compensation inside the compressors. The invention aims to excavate and use the characteristics of floating point multiplication to further improve the energy efficiency of floating point multiplication, realize the optimization of the approximate floating point multiplier in the overhead aspects of precision, power consumption, area and the like, and solve the problems of relatively complex circuit and low compression efficiency of the traditional approximate 4-2 compressor.

A mixed analog / digital in-memory computing device implements matrix vector multiplication with reduced noise for use by a deep neural network (DNN). For each row of a cross-bar array a digital multiplier is split into a least significant (LS) portion and a most significant (MS) portion of different sizes that are preloaded into two cells on one row and two different columns of the cross-bar array. An input activation (IA) value is driven onto input conductors of each row and an analog-to-digital converter (ADC) converts output signals from the two columns as a MS partial sum and a LS partial sum. A gain is applied to the MS partial sum and added to the LS partial sum to form a resulting value for one node of the DNN.

The invention relates to a multiplier based on radix-4Booth coding and an improved Wallace compression tree, and the multiplier comprises a partial product generation module which recodes an input multiplier into a plurality of partial products through employing a Radix-4Booth algorithm, and forms a compact partial product array; the partial product compression module is used for quickly compressing the partial product through two compressors by utilizing an improved Wallace tree compression structure, and reducing the calculation path delay; and the final summation module is used for summing the compressed partial product by using a high-speed summator to obtain a final multiplication result. According to the invention, a radix-4Booth coding algorithm is adopted, so that a partial product array is regularly arranged, the circuit area is reduced, a new tree type compression structure in which a 3-2 compressor and a 4-2 compressor are mixed is adopted to realize a Wallace tree, the compression efficiency is improved, and the key delay is reduced.

The invention relates to a reconfigurable multi-channel polynomial multiplier architecture and an implementation method thereof, and belongs to the technical field of post-quantum cryptography hardware acceleration. The architecture comprises a scheduler, a twiddle factor memory bank, a bank address routing module, a bank array and a reconfigurable butterfly unit array. According to the architecture, a cyclic decoupling multi-channel NTT / INTT / PWM algorithm is used, flexible configuration of the degree of parallelism and the flow line depth can be supported, and the adaptability of a memory access control strategy is improved; a conflict-free memory mapping scheme based on interleaved storage is adopted, so that storage and read-write of polynomial coefficients are irrelevant to polynomial length and a calculation stage, NTT / INTT / PWM access modes are unified, and hardware resource overhead is greatly reduced; and a conflict-free detection algorithm oriented to multi-channel assembly line design is adopted, so that the utilization rate of hardware resources is remarkably improved.

The invention discloses a lattice cryptographic modular multiplication method and a modular multiplier based on an improved plantard algorithm, which eliminate the post-processing overhead of the traditional modular multiplication method by preprocessing twiddle factors in the level of the modular multiplication method. In hardware implementation, shift-addition is adopted to replace a complex multiplier, a dynamic bit width truncation technology is combined, the bit width of intermediate data is compressed from 39 bits to 21 bits, and logic resource consumption is greatly reduced, so that modular multiplication operation in a lattice password digital signature scheme can be quickly and efficiently completed.

The embodiment of the invention discloses a power distribution network load recovery method and device, electronic equipment and a storage medium. The method comprises the following steps: constructing a power distribution network centralized optimization model based on a load recovery amount, a distributed energy utilization rate and a voltage drop; the centralized optimization model comprises connectivity and radial constraint, capacity constraint and power balance and voltage constraint; decomposing the power distribution network into at least two subsystems, and establishing an objective function for each subsystem; the connectivity, the radial performance and the coordination among the subsystems are optimized and adjusted; and calculating the distributed optimization problem of each subsystem by adopting a penalty driving distributed alternating direction multiplier algorithm so as to recover the load of the power distribution network. By adopting the scheme, the power distribution network is decomposed into at least two subsystems, the distributed optimization model is established, and the penalty-driven distributed alternating direction multiplier algorithm is combined, so that the load can be quickly recovered after the fault occurs, and the recovery efficiency of the power distribution network is improved.

A system includes a substrate on which a first memory, a neural processing unit (NPU) including a plurality of processing elements (PEs) with multiplier-accumulator circuits, a controller, and a second memory, and a central processing unit (CPU) are disposed. The CPU may be configured to execute a universal compiler to perform a conversion for a particular neural network model into a machine code executable by the NPU and store the machine code in the first memory or the second memory. When the particular neural network model, generated by one among a plurality of machine learning frameworks that are incompatible with each other, is received and stored in the first memory, the universal compiler may perform the conversion based on mapping information indicating mapping between elements of machine learning frameworks and functions or operations executable by the CPU or NPU.

The embodiment of the invention provides a butterfly computing unit, a butterfly computing unit array, a reconfigurable array and a chip. The butterfly computing unit comprises a first-in first-out cache unit, a butterfly computing module, a multiplier module, a twiddle factor storage module, a first external interface and a second external interface. The first external interface inputs radix-2 or radix-3 FFT data. And the first-in first-out cache unit caches the input data or the data output by the butterfly computing module or the data output by the multiplier module. And the butterfly calculation module receives the data output by the first-in first-out cache unit, and performs butterfly calculation to obtain butterfly calculation result data. And the multiplier module obtains the twiddle factor from the twiddle factor storage module and performs multiplication calculation on the data output by the first-in first-out cache unit or the data output by the butterfly calculation module according to the twiddle factor to obtain multiplication calculation result data. And the second external interface sends out multiplication calculation result data. According to the invention, the structure of the butterfly computing unit is simplified, and the hardware resource consumption is reduced.

The invention relates to the technical field of artificial intelligence, in particular to an approximate multiplication method based on Point data and an arithmetic unit, and the method comprises the steps: carrying out the analysis processing of the obtained Point data, carrying out the splicing operation of the exponential expansion bit and the exponent of each piece of Point data, and determining a mantissa truncation bit width control signal according to the equivalent exponent bit of the Point data; two mantissa bits obtained through analysis are converted into logarithm domain tail values, truncation errors are compensated for the truncated logarithm domain tail values, error compensation is carried out on a logarithm domain mantissa product according to a numerical value interval where the logarithm domain tail values are located, and a linear domain equivalent index is processed and split to obtain an exponential expansion bit and an exponential bit of the product; through the design of the novel error compensation circuit, the calculation error is effectively reduced by using relatively low extra overhead, and the energy efficiency and the calculation precision of the Point multiplier are considered.

The invention discloses a parameter serial and parallel mixed input complex multiplication implementation method, which is implemented by adopting a complex multiplier circuit, and the complex multiplier circuit comprises a serial input cache unit, a parallel input cache unit, a real number multiplication unit and a real number addition / subtraction unit. The method comprises the specific implementation steps that S1, serial input complex number parameters and parallel input complex number parameters are sequentially input from a serial input cache unit and a parallel input cache unit respectively; s2, the serial input complex parameters and the parallel input complex parameters are subjected to combined calculation through a real number multiplication unit and a real number addition / subtraction unit; and S3, outputting a real part and an imaginary part of a complex multiplication result in sequence in a serial mode. Compared with a traditional and optimized triple multiplier version complex multiplication operation circuit, only a small number of registers are additionally arranged, latch resources are conditionally selected, and the complex multiplication operation circuit has obvious advantages in hardware resource consumption.

A unit for accumulating multiplied bit values includes an array of bit-line processors. The unit is implemented in an in-memory associative processor, and each bit-line processor includes multiple memory cells coupled to a bit-line. The array of processors is arranged in rows and columns. The array passes bits of a first multiplicand vertically down a column and provides bits of a second multiplicand horizontally across a row. The array generates carry bits and passes them vertically to a subsequent processor in the same column. The array also generates sum bits and passes them diagonally to a subsequent processor in an adjacent column. The array includes multiplying processors, summing processors, and accumulator processors. Multiplying processors perform an XOR operation by simultaneously activating two memory cells and then perform a full adder operation. Summing processors perform a full adder operation. Accumulator processors perform a full adder operation that includes a feedback sum bit from a previous cycle.

To provide a speech recognition system with higher inference accuracy by using a large-scale language model.SOLUTION: A speech recognition system includes: a first pre-trained inference model (SSL model 20) that can output tokens corresponding to words contained in speech signals on a token-by-token basis, a second pre-trained inference model (large-scale language model 30) that outputs one or more corresponding tokens on the basis of inference based on one or more token inputs, and a multiplier 26 that multiplies a first inference output 22 of the first pre-trained inference model, and a second inference output 32 corresponding to the first inference output, which is an output of the second pre-trained inference model, on a word-by-word basis. Then, the word selected based on the new probability distribution, which is an output of the multiplier, is input to the second pre-trained inference model.SELECTED DRAWING: Figure 3

A matrix multiplier includes an input vector scaler configured to generate a scaled input matrix based on a first input matrix and a plurality of scaling factors; a first data type converter configured to convert a data type of the scaled input matrix into a fixed point and generate a fixed point input matrix; a multiply-accumulate operator array configured to receive the fixed-point input matrix and the plurality of binary vectors, generate a fixed-point output matrix based on the fixed-point input matrix and the plurality of binary vectors, generate a first input matrix and a second input matrix, and generate a first output matrix based on the first input matrix and the second input matrix; and a second data type converter configured to convert a data type of the fixed point output matrix into a floating point and generate a second output matrix.

The invention provides a phase error correction method for an inductive position sensor. The device is characterized by consisting of a first group of multipliers (1), a sliding window integrator (2) for solving a signal average value in a period of time, a second group of multipliers (3) and an adder group (4). The method can be used for correcting and eliminating the phase error in the inductive position sensor chip circuit, and can be widely applied to the fields of industrial robots, automobile manufacturing, industrial automation and the like.

The invention relates to the technical field of artificial intelligence chips, in particular to a runtime reconfigurable artificial intelligence chip, processing units, a calculation task execution method and electronic equipment, the chip comprises a controller and a plurality of processing units, the controller obtains a calculation task, analyzes the calculation task, and sends the calculation task to the processing units; obtaining a plurality of sub-calculation tasks and quantization bits corresponding to the sub-calculation tasks; the processing unit comprises an interception register, a first multiplier, a second multiplier, a shifter, an adder, a splicing register and a multiplexer and is used for processing a specified sub-calculation task, a quantization bit corresponding to the specified sub-calculation task is a specified quantization bit, the controller configures the quantization bit of the processing unit according to the specified quantization bit, and the processing unit is used for processing the specified sub-calculation task according to the quantization bit. Therefore, the runtime reconstruction of the artificial intelligence chip is realized.

Described herein is a graphics processor comprising an instruction cache and a plurality of processing elements coupled with the instruction cache. The plurality of processing elements include functional units configured to provide an integer pipeline to execute instructions to perform operations on integer data elements. The integer pipeline including a first multiplier and a second multiplier, the first multiplier and the second multiplier configured to execute operations for a single instruction.

The invention provides a multi-precision floating point fusion multiply-add structure and a microprocessor architecture, and the structure is characterized in that in a first-stage assembly line, an input preprocessing module decomposes an input operand to obtain a sign bit, an index bit and a mantissa bit; the Booth encoder generates partial products through a radix-4 Booth encoding algorithm, and the tree array multiplier compresses the partial products into three groups; in the second-stage assembly line, the CSA4-2 compression adder compresses the mantissa bits after the three groups of partial products and shift alignment into two groups; the summator module sums the two groups of partial products to obtain a mantissa summation result; in the third-stage assembly line package, a leading zero detection module performs leading zero detection on the mantissa summation result, and performs index adjustment and mantissa adjustment to obtain a normalized result; and in the fourth-stage assembly line, rounding of floating point data is carried out. According to the application, the operation performance, the energy efficiency ratio and the adaptability of the floating point fusion multiply-add structure are improved, so that the high performance and the high energy efficiency of the microprocessor are balanced.