15 results about "Rounding" patented technology

One or more embodiments of the specification provide a data processing method and device applied to a database system. After triggering a data type conversion task, the data processing method obtains a to-be-converted floating point number of the data type conversion task, converts the to-be-converted floating point number into a first floating point number represented by an extended precision, and then calculates a second floating point number scaled to a preset numerical interval through multiple loop integer calculations to perform accurate rounding. According to whether the decimal part of the intermediate value of the last loop integer calculation and the distance between the upper interval and the lower interval of the last loop integer calculation are both greater than the error value of the last loop integer calculation, in the case of satisfying the error value of the last loop integer calculation, the second floating point number is converted into a fixed point number according to the integer part of the intermediate value of each loop integer calculation and the rounding result of the last loop integer calculation, to serve as the execution result of the data type conversion task.

This invention discloses a floating-point-fractional hybrid anchoring method and computational system for suppressing iteration errors, belonging to the field of high-precision numerical computation technology. It solves the technical problems of pseudo-chaos caused by the accumulation of iteration errors in pure floating-point calculations, the computational power explosion in pure high-precision fractional calculations, and the inability to simultaneously achieve both computational power and precision. This invention completes high-speed iterative computations of nonlinear systems using a general floating-point format. After each floating-point calculation, an optimal rational number approximation algorithm is used to convert the calculation result into a simplified rational number with a denominator not exceeding a preset threshold, eliminating the original errors introduced by floating-point truncation and rounding. The purified rational number is then converted back to floating-point format to participate in the next iteration, relying on a bounded rational number anchoring mechanism to progressively block the error amplification chain. The denominator threshold is set to 10¹²~10¹ based on the effective number of bits of the floating-point number. 5 This invention can adaptively adjust to various scenarios such as embedded terminals, supercomputing, and industrial control, and optimizes the continued fraction algorithm to achieve the globally optimal rational approximation under a given upper limit of the denominator. It requires no dedicated large number hardware and combines the advantages of high-speed, low-load floating-point operations with zero approximation error in rational numbers. It can be stably used in nonlinear computing scenarios that are sensitive to initial values ​​and require long-term stable iterations, such as chaotic simulation, vehicle trajectory prediction, industrial PID closed-loop control, 5G / 6G communication channel simulation, microscale meteorological simulation, and large-scale number theory zero-point verification. It effectively eliminates numerical trajectory drift, reduces equipment computing power consumption, and minimizes the workload of manual calibration and data screening, possessing extremely high engineering and academic application value.

An AI-accelerating processor system may include memory that stores a value at a first precision level. The system may include a systolic array configured to perform computation. The systolic array may include rounding circuits. Each rounding circuit may round the value at the first precision level to a second precision level that is lower than the first precision level. At least a first rounding circuit and a second rounding circuit are configured to round the same value differently to respectively generate at least a first rounded value and a second rounded value. The systolic array may also include processing elements that are configured to receive a version of the value in one or more collective operations. At least a first processing element and a second processing element are configured to perform computations involving the value by respectively using the first rounded value and the second rounded value.

An adaptive learning compression method and system for floating-point data, incorporating outlier handling, is disclosed. The method includes: 1. Dividing the input floating-point number sequence into blocks and converting the floating-point values ​​in each block to integers through adaptive rounding; for high-precision floating-point numbers or outliers that cannot be effectively converted, a masquerading mechanism is employed to replace them with approximate values ​​close to the context precision; 2. Analyzing the distribution and variation patterns of the converted integer sequence and segmenting the sequence accordingly, fitting a lightweight prediction model to each segment; 3. Compactly encoding and storing the model parameters, segment boundary information, and residuals between predicted and actual values ​​for each data segment. This invention can efficiently and intelligently compress floating-point numbers, significantly reducing storage space while ensuring that the compressed data supports efficient random access and range queries, and possesses the ability to handle high-precision values ​​and outliers.

The application provides a multiply-accumulate operation method and device for extremely low precision training, which comprises the following steps: obtaining an operated part and to-be-operated data, the to-be-operated data comprising one or more of floating point, fixed point and logarithmic data formats; if there is a high-precision floating point number in the to-be-operated data, the high-precision floating point number is decomposed into the sum of two low-precision floating point numbers; decoding the floating point, fixed point and logarithmic data formats in the to-be-operated data into a unified format of sign, exponent and mantissa to generate input data in the unified format; performing multiple point products on the input data in the unified format to realize combined calculation of different precision data formats; and using an early random rounding method to add the combined calculation result to the operated part. The application can support combined calculation among multiple formats, uses the early random rounding method to reduce the accumulator bit width under the premise of maintaining the precision requirement, and reduces the operation cost compared with the existing operation hardware, thereby improving the training efficiency under extremely low precision.

The application discloses a kind of MMC-BESS low-computing amount extended level model predictive control methods, adopt hierarchical architecture: output current control layer is determined theoretical optimal level by minimizing current envelope area, and take its adjacent two integer levels as candidate, only evaluate 2 candidates can obtain optimal output level, constant 2 with the number of sub-modules, irrelevant;Based on the result, the circulating current control layer obtains the optimal bridge arm input combination by direct calculation and rounding, without exhaustive search, the amount of calculation is zero.Simultaneously set bridge arm input combination boundary constraint mechanism to ensure physical realizability.This method completely eliminates the tuning problem of weight factor in traditional model predictive control, the total amount of calculation is extremely low and does not increase with the number of sub-modules, with excellent output current quality, circulating current suppression ability and sub-module state of charge balancing performance, especially suitable for large-scale modular multilevel energy storage system.

The invention relates to a repeatable random rounding for intra-network computing. A system includes at least one processing node to execute one or more computing processes as part of a distributed workload to generate an output. The at least one processing node is configured with a derived seed value generated from the base seed value. The system also includes rounding circuitry to perform a rounding operation on the at least one processing node according to the derived seed value.

Systems and techniques are described herein for adjusting weights of a machine learning (ML) model. For instance, a process can include generating a first matrix of quantized weight values by rounding values of an input matrix of weight values for the ML model; applying an activation function to a second matrix, the second matrix generated based on a third matrix and a fourth matrix of a first matrix pair; applying the activation function to a fifth matrix, the fifth matrix based on a sixth matrix and seventh matrix of a second matrix pair; generating a positive second matrix by applying a positive factor to the second matrix; generating a negative fifth matrix by applying a negative factor to the fifth matrix; and summing the first matrix of quantized weight values with the positive second matrix and the negative fifth matrix to generate an output matrix of quantized weight values.

The application provides a turbine disc mortise and tenon groove side rounding model construction method, which comprises the following steps: constructing a part mortise and tenon groove structure model; completing the model establishment of the mortise and tenon groove structure according to design requirements; constructing the rounding of the mortise and tenon groove according to the middle difference; establishing the rounding of the mortise and tenon groove on a computer and constructing according to the middle difference; extracting the rounding surface in the form of a slice to form a plurality of slices; extracting the rounding center virtual line of the linear segment along the groove type in sequence; constructing the rounding linear of the linear segment and other related lines; forming the pruned rounding surface; constructing the envelope swept surface and the curve pruning between adjacent linear segments; using the stitching function to stitch the newly constructed swept surface to form a complete transition envelope surface; stitching the middle difference rounding slice; stitching the rounding surface along the groove type once to form a new rounding surface; program generation; and completing the numerical control machining of the part. The application has the advantages that the processing risk of overcutting and undercutting in processing can be solved from the source, the high surface integrity of the mortise and tenon groove side rounding is improved, 100% of the mortise and tenon groove side rounding is qualified, and higher value is created.

One or more embodiments of the invention provide a data processing method and device applied to a database system, and the method comprises the steps: obtaining a to-be-converted floating-point number of a data type conversion task after triggering the data type conversion task, converting the to-be-converted floating-point number into a first floating-point number represented by extended precision, and transmitting the first floating-point number to the database system; performing accurate rounding on the second floating-point number scaled into the preset numerical value interval through multiple times of circular rounding calculation; according to whether the distances between the decimal part of the intermediate value of the last cycle rounding calculation and the upper interval and the lower interval of the last cycle rounding calculation are both greater than the error value of the last cycle rounding calculation or not, the error value of the last cycle rounding calculation is satisfied; and converting the second floating-point number into a fixed-point number as an execution result of the data type conversion task according to an integer part of an intermediate value of each cycle rounding calculation and a rounding result of the last cycle rounding calculation.

The application provides a floating-point multiplication method and a floating-point multiplication circuit, and relates to the technical field of processors. The method comprises the following steps: obtaining a shift result of the product of a first floating-point number and a second floating-point number; the shift result is the result of a shift operation on the decimal part of the product; performing a mantissa rounding operation on the shift result to obtain a mantissa rounding result of the shift result; obtaining a first judgment result of whether the mantissa satisfies a first preset rounding condition in the process of the mantissa rounding operation; if the first judgment result is that the mantissa satisfies the first preset rounding condition, obtaining a target mantissa of the multiplication result of the first floating-point number and the second floating-point number according to the mantissa rounding result. The floating-point multiplication method has the advantage of short operation period.

The invention provides a floating-point multiplication and addition fusion operation unit and a floating-point multiplication and addition fusion processor. The floating-point multiplication and addition fusion operation unit comprises a precision keeping multiplication subunit, an index bit extraction subunit, a carry addition tree keeping subunit and a floating-point number merging output subunit. According to the arithmetic unit provided by the invention, multiplication and addition are fused into an efficient data path, the mantissa arithmetic structure in the multiplication unit is optimized, the rounding and normalization times are reduced, the problems of precision loss and delay caused by two-stage independent rounding in the prior art are solved, the hardware complexity of the multiplication unit is reduced, and the calculation efficiency is improved. The method is beneficial for realizing high working frequency, and realizes higher operation speed and precision on the premise of conforming to the existing calculation standard.

Systems and techniques are described herein for adjusting weights of a machine learning (ML) model. For instance, a process can include generating a first matrix of quantized weight values by rounding values of an input matrix of weight values for the ML model; applying an activation function to a second matrix, the second matrix generated based on a third matrix and a fourth matrix of a first matrix pair; applying the activation function to a fifth matrix, the fifth matrix based on a sixth matrix and seventh matrix of a second matrix pair; generating a positive second matrix by applying a positive factor to the second matrix; generating a negative fifth matrix by applying a negative factor to the fifth matrix; and summing the first matrix of quantized weight values with the positive second matrix and the negative fifth matrix to generate an output matrix of quantized weight values.

A method and hardware for performing hardware efficient unbiased rounding of a number includes receiving the number in a binary format having a first portion and a second portion. The first portion comprises bits of the number above a rounding point and the second portion comprises bits of the number after the rounding point. The method includes adding a first amount to the number to obtain a first value. Further the method comprises determining if the bit above the rounding point for a controlling value is ‘0’ bit or a ‘1’ bit. The controlling value is either the received number in the binary format or the first value. The method further includes adding a second amount to ‘b+1’ LSBs of the first value to obtain a second value if the bit above the rounding point for the controlling value is a ‘0’ bit and rounding the number by truncating the last b bits of the second value or the last b bits of the first value based on the determination.